ANALOG DEVICES AD5429 Service Manual

Dual 8-/10-/12-Bit, High Bandwidth,

FEATURES

10 MHz multiplying bandwidth INL of ±0.25 LSB @ 8 bits 16-lead TSSOP package

2.5 V to 5.5 V supply operation ±10 V reference input 50 MHz serial interface

2.47 MSPS update rate Extended temperature range: −40°C to +125°C 4-quadrant multiplication Power-on reset

0.5 μA typical current consumption Guaranteed monotonic Daisy-chain mode Readback function

APPLICATIONS

Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming

Multiplying DACs with Serial Interface

AD5429/AD5439/AD5449

GENERAL DESCRIPTION

The AD5429/AD5439/AD54491 are CMOS, 8-, 10-, and 12-bit, dual-channel, current output digital-to-analog converters (DAC), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suited to battery-powered and other applications.

As a result of being manufactured on a CMOS submicron process, these parts offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of 10 MHz.

The applied external reference input voltage (V the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external current-to-voltage precision amplifier.

These DACs use a double-buffered, 3-wire serial interface that is compatible with SPI, QSPI™, MICROWIRE™, and most DSP interface standards. In addition, a serial data out (SDO) pin allows daisy-chaining when multiple packages are used. Data readback allows the user to read the contents of the DAC register via the SDO pin. On power-up, the internal shift register and latches are filled with 0s, and the DAC outputs are at zero scale.

The AD5429/AD5439/AD5449 DACs are available in 16-lead TSSOP packages. The EVAL-AD5415/AD5449SDZ evaluation board is available for evaluating DAC performance. For more information, see the UG-297 evaluation board user guide.

) determines

REF

FUNCTIONAL BLOCK DIAGRAM

V

SYNC

SCLK

SDIN

SDO

CLR

1

U.S. Patent Number 5,689,257.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5429/AD5439/AD5449

DD

SHIFT

REGISTER

POWER-ON

RESET

INPUT

REGISTER

INPUT

REGISTER

V

A

REF

RFB

R

A

FB

I

1A

DAC

REGISTER

LDAC

DAC

REGISTER

LDAC

8-/10-/12-BIT R-2R DAC A

8-/10-/12-BIT R-2R DAC B

V

B

REF

RFB

OUT

I

2A

OUT

I

1B

OUT

I

2B

OUT

RFBB

R

04464-001

Figure 1.

AD5429/AD5439/AD5449

REVISION HISTORY

6/11—Rev. C to Rev. D

Changes to General Description .................................................... 1

Deleted Evaluation Board for the DAC Section ......................... 24

Changes to Ordering Guide.......................................................... 30

4/10—Rev. B to Rev. C

Added to Figure 4............................................................................. 6

3/08—Rev. A to Rev. B

Added t

Changes to Figure 2.......................................................................... 5

Changes to Figure 3.......................................................................... 6

Changes to Figure 38...................................................................... 16

Changes to Ordering Guide.......................................................... 30

7/05—Rev. 0 to Rev. A

Changes to Features List.................................................................. 1

Changes to Specifications................................................................ 3

Changes to Timing Characteristics................................................ 5

and t14 Parameters to Table 2 ......................................... 5

13

Changes to Absolute Maximum Ratings Section..........................7

Changes to General Description Section .................................... 15

Changes to Table 5.......................................................................... 15

Changes to Table 6.......................................................................... 16

Changes to Single-Supply Applications Section ......................... 17

Changes to Divider or Programmable Gain Element Section.... 18

Changes to Table 7 Through Table 10 ......................................... 20

Added ADSP-BF5xx-to-AD5429/AD5439/AD5449

Interface Section ........................................................................ 23

Change to PCB Layout and

Power Supply Decoupling Section .......................................... 25

Changes to Power Supplies for the Evaluation Board Section.... 25

Changes to Table 13 ....................................................................... 29

Updated Outline Dimensions....................................................... 30

Changes to Ordering Guide.......................................................... 30

7/04—Revision 0: Initial Version

Rev. D | Page 2 of 28

AD5429/AD5439/AD5449

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, V otherwise noted. DC performance is measured with the OP177, and ac performance is measured with the AD8038, unless otherwise noted.

Table 1.

Parameter1 Min Typ Max Unit Conditions

STATIC PERFORMANCE

AD5429

Resolution 8 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic

AD5439

Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic

AD5449

Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Gain Error ±25 mV Gain Error Temperature

Coefficient

Output Leakage Current ±5 nA Data = 0x0000, TA = 25°C, I ±15 nA Data = 0x0000, I REFERENCE INPUT

Reference Input Range ±10 V V

A, V

REF

V

REF

B Input Resistance 9 11 13 kΩ Input resistance temperature coefficient = −50 ppm/°C

REF

A-to-V

B Input Resistance

REF

Mismatch

Input Capacitance

Code 0 3.5 pF

Code 4095 3.5 pF DIGITAL INPUTS/OUTPUT

Input High Voltage, VIH 1.7 V VDD = 3.6 V to 5.5 V

1.7 V VDD = 2.5 V to 3.6 V Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V

0.7 V VDD = 2.5 V to 2.7 V Output High Voltage, VOH V

V

Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5.5 V, I

0.4 V VDD = 2.5 V to 3.6 V, I

Input Leakage Current, IIL 1 μA Input Capacitance 4 10 pF

DYNAMIC PERFORMANCE

Reference-Multiplying Bandwidth 10 MHz V Output Voltage Settling Time

Measured to ±1 mV of FS 80 120 ns Measured to ±4 mV of FS 35 70 ns Measured to ±16 mV of FS 30 60 ns Digital Delay 20 40 ns Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry, V

= 10 V, I

REF

2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T

OUT

±5 ppm FSR/°C

1

OUT

1.6 2.5 % Typical = 25°C, maximum = 125°C

− 1 V VDD = 4.5 V to 5.5 V, I

DD

− 0.5 V VDD = 2.5 V to 3.6 V, I

DD

= ±3.5 V p-p, DAC loaded all 1s

REF

= 100 Ω, C

R

LOAD

SOURCE

SINK

= 15 pF, V

LOAD

= 200 μA = 200 μA

DAC latch alternately loaded with 0s and 1s

MIN

1

OUT

= 200 μA = 200 μA

= 10 V,

REF

to T

REF

MAX

= 0 V

, unless

Rev. D | Page 3 of 28

AD5429/AD5439/AD5449

Parameter1 Min Typ Max Unit Conditions

Multiplying Feedthrough Error DAC latches loaded with all 0s, V 70 dB 1 MHz 48 dB 10 MHz

Output Capacitance 12 17 pF DAC latches loaded with all 0s

25 30 pF DAC latches loaded with all 1s

Digital Feedthrough 3 5 nV-sec

Feedthrough to DAC output with CS

alternate loading of all 0s and all 1s Output Noise Spectral Density 25 nV/√Hz @ 1 kHz Analog THD 81 dB V Digital THD Clock = 10 MHz, V

100 kHz f 50 kHz f

61 dB

OUT

66 dB

OUT

SFDR Performance (Wide Band) AD5449, 65k codes, V

= 3. 5 V p-p, all 1s loaded, f = 1 kHz

REF

= 3.5 V

REF

= 3.5 V

REF

Clock = 10 MHz

500 kHz f 100 kHz f 50 kHz f

55 dB

OUT

63 dB

OUT

65 dB

OUT

Clock = 25 MHz

500 kHz f 100 kHz f 50 kHz f

SFDR Performance (Narrow Band) AD5449, 65k codes, V

50 dB

OUT

60 dB

OUT

62 dB

OUT

= 3.5 V

REF

Clock = 10 MHz

500 kHz f 100 kHz f 50 kHz f

73 dB

OUT

80 dB

OUT

87 dB

OUT

Clock = 25 MHz

500 kHz f 100 kHz f 50 kHz f

Intermodulation Distortion AD5449, 65k codes, V

70 dB

OUT

75 dB

OUT

80 dB

OUT

= 3.5 V

REF

f1 = 40 kHz, f2 = 50 kHz 72 dB Clock = 10 MHz f1 = 40 kHz, f2 = 50 kHz 65 dB Clock = 25 MHz

POWER REQUIREMENTS

Power Supply Range 2.5 5.5 V

IDD 0.7 μA TA = 25°C, logic inputs = 0 V or VDD

0.5 10 μA TA = −40°C to +125°C, logic inputs = 0 V or VDD Power Supply Sensitivity 0.001 %/% ∆VDD = ±5%

1

Guaranteed by design and characterization, not subject to production test.

= ±3.5 V

REF

high and

Rev. D | Page 4 of 28

AD5429/AD5439/AD5449

2

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, V

= 10 V, I

REF

Table 2.

Parameter1 Limit at T

f

50 MHz max Maximum clock frequency

SCLK

t1 20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time t4 13 ns min t5 5 ns min Data setup time t6 4 ns min Data hold time t7 5 ns min

t8 30 ns min t9 0 ns min t10 12 ns min t11 10 ns min

3

t

25 ns min SCLK active edge to SDO valid, strong SDO driver

12

60 ns min SCLK active edge to SDO valid, weak SDO driver t13 12 ns min

t14 4.5 ns min Update Rate 2.47 MSPS

1

Guaranteed by design and characterization, not subject to production test.

2

Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.

3

Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 5.

2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications T

OUT

, T

MIN

Unit Conditions/Comments2

MAX

falling edge to SCLK falling edge setup time

SYNC

rising edge to SCLK falling edge

SYNC Minimum SYNC

high time

SCLK falling edge to LDAC

pulse width

LDAC SCLK falling edge to LDAC

pulse width

CLR

rising edge to LDAC falling edge

SYNC Consists of cycle time, SYNC

falling edge

rising edge

high time, data setup, and output voltage settling time

MIN

to T

, unless otherwise noted.

MAX

TIMING DIAGRAMS

SCLK

SYNC

SDIN

1

LDAC

2

LDAC

1

ASYNCHRONOUS LDAC UPD ATE MODE. SYNCHRONOUS LDAC UPD AT E MODE.

NOTES

1. ALTERNATIVELY, DATA CAN BE CLOCKED I NTO THE I NPUT SHIFT REGIST ER ON THE RIS ING EDGE OF SCLK AS DETERMINED BY T HE CONTROL BITS. T IMING I S AS ABOVE, WITH SCL K INVERTED.

t

1

t

4

t

8

t

6

t

5

DB15

2

t

3

t

7

DB0

t

10

t

9

t

11

04464-002

Figure 2. Standalone Mode Timing Diagram

Rev. D | Page 5 of 28

AD5429/AD5439/AD5449

S

SCLK

t

YNC

SDIN

SDO

NOTES

1. ALTERNATIVELY, DATA CAN BE CLOCKED I NTO THE I NPUT SHIFT REGIST ER ON THE RI SING EDG E OF SCLK AS DETERMINED BY THE CONTROL BITS. I N THIS CASE, DATA WOUL D BE CLOCKED OUT OF SDO O N THE FALL ING EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED.

4

DB15

(N)

t

6

t

5

2

t

1

t

3

DB15

DB0

(N + 1)

(N)

t

12

DB15

(N)

DB0

(N + 1)

DB0

(N)

t

7

t

8

04464-003

Figure 3. Daisy-Chain Timing Diagram

SCLK

SYNC

16 32

SDIN

SDO

DB15 DB0 DB15 DB0

INPUT WORD SPECIFIES

REGISTER TO BE READ

UNDEFINED

DB15

NOP CONDITI ON

SELECTED REG ISTER DATA

CLOCKED OUT

DB0

04464-059

Figure 4. Readback Mode Timing Diagram

200μAI

TO OUTPUT

C

L

50pF

200μAI

Figure 5. Load Circuit for SDO Timing Specifications

OL

VOH (MIN) + VOL (MAX)

OH

2

04464-004

Rev. D | Page 6 of 28

AD5429/AD5439/AD5449

ABSOLUTE MAXIMUM RATINGS

Transient currents of up to 100 mA do not cause SCR latch-up. T

= 25°C, unless otherwise noted.

A

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V V

x, RFBx to GND −12 V to +12 V

REF

I

1, I

OUT

Input Current to Any Pin Except Supplies ±10 mA Logic Inputs and Output1 −0.3 V to VDD + 0.3 V Operating Temperature Range

Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 16-Lead TSSOP, θJA Thermal Impedance 150°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C

1

Overvoltages at SCLK,

2 to GND −0.3 V to +7 V

OUT

Extended (Y Version) −40°C to +125°C

SYNC

, and SDIN are clamped by internal diodes.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.

ESD CAUTION

Rev. D | Page 7 of 28

AD5429/AD5439/AD5449

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

1A

I

OUT

2

I

2A

OUT

3

R

A

FB

V

REF

GND

LDAC

SCLK

SDIN SDO

AD5429/

4

A

AD5439/

AD5449

5

TOP VIEW

6

(Not to Scale)

7

8

NC = NO CONNECT

16

I

1B

OUT

15

I

2B

OUT

14

R

B

FB

13

V

B

REF

12

V

DD

11

CLR

10

SYNC

9

04464-005

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 I 2 I

1A DAC A Current Output.

OUT

2A

DAC A Analog Ground. This pin should typically be tied to the analog ground of the system, but it can be biased to achieve single-supply operation.

3 RFBA

DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external amplifier output.

4 V

A DAC A Reference Voltage Input Pin.

REF

5 GND Ground Pin. 6

Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is

LDAC

asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected, whereby the DAC is updated on the 16th clock falling

when in daisy-chain mode.

7 SCLK

edge when the device is in standalone mode, or on the rising edge of SYNC Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock

input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of SCLK.

8 SDIN

Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, data is clocked at power-on into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to a rising edge.

9 SDO

Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and clocked out via SDO on the rising edge of SCLK. Data is always clocked out on the alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes the DAC register contents available for readback on the SDO pin, and they are clocked out on the next 16 opposite clock edges to the active clock edge.

10

Active Low Control Input. This pin provides the frame synchronization signal for the input data. When SYNC

SYNC

goes low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded into the shift register on the active edge of the subsequent clocks. In standalone mode, the serial interface counts the clocks, and data is latched into the shift register on the 16th active clock edge.

11

Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the

CLR

user to enable the hardware CLR

pin as a clear-to-zero scale or midscale, as required. 12 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. 13 V 14 RFBB

B DAC B Reference Voltage Input Pin.

REF

DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external amplifier output.

15 I

OUT

2B

DAC B Analog Ground. This pin typically should be tied to the analog ground of the system, but it can be biased to achieve single-supply operation.

16 I

1B DAC B Current Output.

OUT

Rev. D | Page 8 of 28

AD5429/AD5439/AD5449

TYPICAL PERFORMANCE CHARACTERISTICS

0.20

0.15

0.10

TA = 25°C V

= 10V

REF

V

= 5V

DD

0.20

0.15

0.10

TA = 25°C V

= 10V

REF

V

= 5V

DD

0.05

0

INL (LSB)

–0.05

–0.10

–0.15

–0.20

0 50 100 150 200 250

CODE

Figure 7. INL vs. Code (8-Bit DAC) Figure 10. DNL vs. Code (8-Bit DAC)

0.5

TA = 25°C

0.4 V

= 10V

REF

V

= 5V

DD

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 200 400 600 800 1000

CODE

Figure 8. INL vs. Code (10-Bit DAC) Figure 11. DNL vs. Code (10-Bit DAC)

04464-017

04464-018

0.05

0

DNL (LSB)

–0.05

–0.10

–0.15

–0.20

0 50 100 150 200 250

CODE

0.5

TA = 25°C

0.4 V

= 10V

REF

V

= 5V

DD

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 200 400 600 800 1000

CODE

04464-020

04464-021

INL (LSB)

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

0

1.0

TA = 25°C V

= 10V

REF

V

= 5V

DD

20001500500 10000 2500 3000 3500 4000

CODE

DNL (LSB)

04464-019

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

TA = 25°C V

= 10V

REF

V

= 5V

DD

0

20001500500 10000 2500 3000 3500 4000

CODE

Figure 9. INL vs. Code (12-Bit DAC) Figure 12. DNL vs. Code (12-Bit DAC)

Rev. D | Page 9 of 28

04464-022

ANALOG DEVICES AD5429 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS