Analog Devices AD5428 40 47 Datasheet

Dual 8-,10-,12-Bit, High Bandwidth

FEATURES

10 MHz multiplying bandwidth
Fast parallel interface (58 MSPS write cycle)
AD7528 upgrade (AD5428)
AD7547 upgrade (AD5447)

2.5 V to 5.5 V supply operation
±10 V reference input
20- and 24-lead TSSOP packages
Dual 8-, 10-, and 12-bit current output DACs
Guaranteed monotonic
4-quadrant multiplication
Power-on reset
Readback function

0.5 µA typical current consumption

APPLICATIONS

Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming

Multiplying DACs with Parallel Interface

AD5428/AD5440/AD5447

FUNCTIONAL BLOCK DIAGRAM

V

A

REF

AD5428/AD5440/AD5447

DATA

INPUTS

V

DB0

DB7
DB9

DB11

DAC A/B

R/W

DGND

DD

INPUT

BUFFER

CS

CONTROL

LOGIC

POWER-ON

RESET

LATCH

LATCH

8-/10-/12-BIT
R-2R DAC A

8-/10-/12-BIT
R-2R DAC B

B

V

REF

R

R

Figure 1. AD5428/AD5440/AD5447

GENERAL DESCRIPTION

The AD5428/AD5440/AD54471 are dual CMOS 8-, 10-, and
12-bit current output digital-to-analog converters (DACs),
respectively.

These devices operate from a 2.5 V to 5.5 V power supply,
making them suited to battery-powered and other applications.

The DACs utilize data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with zeros and the DAC
outputs are at zero scale.

As a result of manufacture on a CMOS submicron process, they
offer excellent 4-quadrant multiplication characteristics, with
large signal multiplying bandwidths of up to 10 MHz.

R

FB

I

OUT

AGND

R

FB

I

OUT

A

A

B

B

04462-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

The applied external reference input voltage (V

REF)

the full-scale output current. An integrated feedback resistor

) provides temperature tracking and full-scale voltage

(R

FB

output when combined with an external I-to-V precision
amplifier.

The AD5428 is available in a small 20-lead TSSOP package,
while the AD5440/AD5447 DACs are available in small 24-lead
TSSOP packages.

1

US Patent Number 5,689,257.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

determines

AD5428/AD5440/AD5447

TABLE OF CONTENTS

Specifications..................................................................................... 3

Used as a Divider or Programmable Gain Element............... 19

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Te r m in o l o g y .................................................................................... 10

Typical Performance Characteristics........................................... 11

General Description................................................................... 16

Circuit Operation ....................................................................... 16

Single-Supply Applications........................................................ 18

Positive Output Voltage ............................................................. 19

Adding Gain................................................................................ 19

REVISION HISTORY

7/04—Revision 0: Initial Version

Reference Selection .................................................................... 20

Amplifier Selection .................................................................... 20

Parallel Interface ......................................................................... 20

Microprocessor Interfacing....................................................... 20

PCB Layout and Power Supply Decoupling ........................... 21

Evaluation Board for the DACs................................................ 21

Power Supplies for the Evaluation board................................ 21

Bill of Materials............................................................................... 25

Overview of AD54xx Devices....................................................... 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD5428/AD5440/AD5447

SPECIFICATIONS

Temperature range for Y version is –40°C to +125°C.

= 2.5 V to 5.5 V, V

V

DD

REF

A = V

B = +10 V, AGND = 0 V. All specifications T

REF

MIN

to T

, unless otherwise noted. DC performance

MAX

measured with OP1177, AC performance with AD8038, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Conditions

STATIC PERFORMANCE
AD5428
Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
AD5440
Resolution 10 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
AD5447
Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity –1/+2 LSB Guaranteed monotonic
Gain Error ±10 m V
Gain Error Temp CoefficientT1 ±5 ppm FSR/°C
Output Leakage Current ±10 nA Data = 0000H, TA = 25°C.
±25 nA Data = 0000H.
REFERENCE INPUT1
Reference Input Range ±10 V
V

A, V

B Input Resistance 8 10 12 k Ω Input resistance TC = –50 ppm/°C

REF

A to V

B Input

REF

1.6 2.5 % Typ = 25°C, max = 125°C

V

REF

REF

Resistance Mismatch
R

A,RFBB Input Resistance 8 10 12 k Ω Input resistance TC = –50 ppm/°C

FB

Input Capacitance
Code 0 3 6 pF

Code 4095 5 8 pF
DIGITAL INPUTS/OUTPUT1
Input High Voltage, VIH 1.7 V VDD = 2.5 V to 5.5 V
Input Low Voltage, V

IL

0.8 V VDD = 2.7 V to 5.5 V

0.7 V VDD = 2.5 V to 2.7 V
Input Leakage Current, IIL 2 µA
Input Capacitance 4 10 pF
V

= 4.5 V to 5.5 V

DD

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH
V

= 2.5 V to 3.6 V

DD

V

−1

DD

V I

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH

V

− 0.5

DD

V I

= 200 µA

SINK

SOURCE

= 200 µA

SINK

SOURCE

= 200 µA

= 200 µA
DYNAMIC PERFORMANCE1
Reference Multiplying BW 10 MHz V
Output Voltage Settling Time V

= ±3.5 V, DAC loaded all 1s

REF

= ±10 V, R

REF

= 100 Ω, C

LOAD

LOAD

= 15 pF
DAC latch alternatively loaded with 0s and 1s
AD5428 30 60 ns Measured to ±16 mV of FS
AD5440 35 70 ns Measured to ±4 mV of FS
AD5447 80 120 ns Measured to ±1 mV of FS

Rev. 0 | Page 3 of 28

AD5428/AD5440/AD5447

Parameter Min Typ Max Unit Conditions

Digital Delay 20 40 ns Interface delay time
10% to 90% Settling Time 15 30 Ns
Digital-to-Analog Glitch Impulse 2

nV-s

Multiplying Feedthrough Error –75 dB DAC latches loaded with all 0s. Reference = 10 kHz
Output Capacitance
I

2 22 25 pF DAC latches loaded with all 0s

OUT

10 12 pF DAC latches loaded with all 1s
I

1 12 17 pF DAC latches loaded with all 0s

OUT

25 30 pF DAC latches loaded with all 1s
Digital Feedthrough 1

Total Harmonic Distortion

−81

Output Noise Spectral Density 25

dB V

nV−s

nV/√Hz @ 1 kHz

SFDR Performance (Wideband) AD5447, 65 k codes, V
Clock = 10 MHz
500 kHz f
100 kHz f
50 kHz f

OUT

OUT

OUT

55 dB
63 dB

65 dB
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f

OUT

OUT

OUT

50 dB

60 dB

62 dB
SFDR Performance (Narrow Band) AD5447, 65 k codes, V
Clock = 10 MHz
500 kHz f
100 kHz f
50k Hz f

OUT

OUT

OUT

73 dB

80 dB

87 dB
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f

OUT

OUT

OUT

70 dB

75 dB

80 dB
Intermodulation Distortion AD5447, 65 k codes, V
Clock = 10 MHz
f1 = 400 kHz, f2 = 500 kHz 65 dB
f1 = 40 kHz, f2 = 50 kHz 72 dB
Clock = 25 MHz
f1 = 400 kHz, f2 = 500 kHz 51 dB
f1 = 40 kHz, f2 = 50 kHz 65 dB
POWER REQUIREMENTS
Power Supply Range 2.5 5.5 V
IDD 0.6 µA TA = 25°C. Logic inputs = 0 V or V

0.5 10 µA Logic inputs = 0 V or V
Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5%

Rise and fall time, V

= 10 V, R

REF

LOAD

= 100 Ω

1 LSB change around major carry, V

Feedthrough to DAC output with

CS high and

alternate loading of all 0s and all 1s

= 3.5 V p-p, all 1s loaded, f = 1 kHz

REF

= 3.5 V

REF

= 3.5 V

REF

= 3.5 V

REF

DD

DD

REF

= 0 V

1

Guaranteed by design, not subject to production test.

Rev. 0 | Page 4 of 28

AD5428/AD5440/AD5447

B

TIMING CHARACTERISTICS

Temperature range for Y version is –40°C to +125°C. Guaranteed by design and characterization, not subject to production test.

All input signals are specified with tr = tf = 1 ns (10% to 90% of V
timing measured with load circuit in Figure 3. V

= 2.5 V to 5.5 V, V

DD

) and timed from a voltage level of (VIL + VIH)/2. Digital output

DD

= 10 V, I

REF

2 = 0 V. All specifications T

OUT

otherwise noted.

Table 2.

Parameter Limit at T

MIN

, T

Unit Conditions/Comments

MAX

Write Mode

R/

t1 0 ns min
t2 0 ns min
t3 10 ns min

W to CS setup time

R/

W to CS hold time

CS low time
t4 10 ns min Address setup time
t

5

0 ns min Address hold time
t6 6 ns min Data setup time
t7 0 ns min Data hold time

R/

t8 5 ns min
t

9

7 ns min

W high to CS low

CS min high time

Data Readback Mode

t10 0 ns typ Address setup time
t11 0 ns typ Address hold time
t12 5 ns typ Data access time
25 ns max
t13 5 ns typ Bus relinquish time

10 ns max

MIN

to T

MAX

, unless

DACA/DAC

DATA

R/W

CS

t

1

t

3

t

t

8

DATA VALID DATA VALID

t

2

t

4

5

t

8

t

9

t

10

t

7

Figure 2. Timing Diagram

TO OUTPUT

PIN

200µAI

C

L

50pF

200µAI

OL

V

OH (MIN)

OH

Figure 3. Load Circuit for Data Output Timing Specifications

t

+ V

2

12

OL (MAX)

t

11

04462-0-003

t

2

t

13

04462-0-002

Rev. 0 | Page 5 of 28

AD5428/AD5440/AD5447

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V
V

A, V

REF

I

OUT

Logic Inputs and Output
Operating Temperature Range

Automotive (Y Version)
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
20-lead TSSOP θJA Thermal Impedance 143°C/W
24-lead TSSOP θJA Thermal Impedance 128°C/W
Lead Temperature, Soldering

(10 seconds)
IR Reflow, Peak Temperature

(< 20 seconds)

1

Overvoltages at DBx, CS, and W/R are clamped by internal diodes. Current

should be limited to the maximum ratings given.

B, RFBA, RFBB to DGND –12 V to +12 V

REF

1, I

2 to DGND –0.3 V to +7 V

OUT

1

–0.3 V to VDD + 0.3 V
–40°C to +125°C

300°C

235°C

Stresses above those listed in Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability. Only one absolute maximum rating may be applied
at any one time.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 28

AD5428/AD5440/AD5447

B

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AGND

I

OUT

R

V

REF

DGND

DAC A/

FB

DB7
DB6
DB5
DB4

A
A
A

10

1

2

3

AD5428

4

TOP VIEW

(Not to Scale)

5

6

7

8

9

20

19

18

17

16

15

14

13

12

11

B

I

OUT

R

B

FB

V

B

REF

V

DD

R/W
CS
DB0 (LSB)
DB1
DB2
DB3

04462-0-004

Figure 4. Pin Configuration 20-Lead TSSOP (RU-20)

Table 4. AD5428 Pin Function Descriptions

Pin No. Mnemonic Function

1 AGND

DAC Ground Pin. Typically, this pin should be tied to the analog ground of the system, but may be biased to
achieve single-supply operation.

2, 20 I

OUT

A, I

B DAC Current Outputs.

OUT

3, 19 RFBA, RFBB DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to external amplifier output.
4, 18 V

REF

A, V

B DAC Reference Voltage Input Terminals.

REF

5 DGND Digital Ground Pin.
6 DAC A/B Selects DAC A or B. Low selects DAC A, or, alternatively, high selects DAC B.
7 to14 DB7 to DB0 Parallel Data Bits 7 through 0.
15

CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read

data from the DAC register.

16

W Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction

R/

CS to read back contents of the DAC register.

with

17 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.

Rev. 0 | Page 7 of 28

AD5428/AD5440/AD5447

AGND

I

OUT

R

FB

V

REF

DGND

DAC A/B

DB9
DB8
DB7
DB6
DB5
DB4

1

2

A

3

A

4

A

AD5440

TOP VIEW

5

(Not to Scale)

6

7

8

9

10

11

12

NC = NO CONNECT

24

23

22

21
20

19

18

17

16

15

14

13

B

I

OUT

B

R

FB

V

B

REF

V

DD

R/W
CS
NC
NC
DB0 (LSB)
DB1
DB2
DB3

04462-0-005

Figure 5. Pin Configuration 24-Lead TSSOP (RU-24)

Table 5. AD5440 Pin Function Descriptions

Pin No. Mnemonic Function

1 AGND

2, 24 I

OUT

A, I

OUT

DAC Ground pin. Typically, this pin should be tied to the analog ground of the system, but may be biased to
achieve single-supply operation.

B DAC Current Outputs.
3, 23 RFBA, RFBB DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to external amplifier output.
4, 22 V

REF

A, V

B DAC Reference Voltage Input Terminals.

REF

5 DGND Digital Ground pPin.
6 DAC A/B Selects DAC A or B. Low selects DAC A, or, alternatively, high selects DAC B.
7 to16 DB9 to DB0 Parallel Data Bits 9 through 0.

19

20

CS

R/

W

Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register.

Read/Write. When low, used in conjunction with

CS to load parallel data. When high, used in conjunction with

CS to read back contents of the DAC register.

21 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.

Rev. 0 | Page 8 of 28

AD5428/AD5440/AD5447

AGND

I

OUT

R

FB

V

REF

DGND

DAC A/B

DB11
DB10

DB9
DB8
DB7
DB6

A
A
A

10

11
12

1

2

3

4

AD5447

5

TOP VIEW

(Not to Scale)

6

7

8

9

24

I

23

22

21
20

19

18

17

16

15

14

13

B

OUT

B

R

FB

B

V

REF

V

DD

R/W
CS
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5

04462-0-006

Figure 6. Pin Configuration 24-Lead TSSOP (RU-24)

Table 6. AD5447 Pin Function Descriptions

Pin No. Mnemonic Function

1 AGND

DAC Ground pin. Typically, this pin should be tied to the analog ground of the system, but may be biased to
achieve single-supply operation.

2, 24 I

OUT

A, I

B DAC Current Outputs.

OUT

3, 23 RFBA, RFBB DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to external amplifier output.
4, 22 V

REF

A, V

B DAC Reference Voltage Input Terminals.

REF

5 DGND Digital Ground Pin.
6 DAC A/B Selects DAC A or B. Low selects DAC A, or, alternatively, high selects DAC B.
7 to 18 DB11 to DB0 Parallel Data Bits 11 through 0.
19

CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read

data from the DAC register. When

CS and R/W are held low, the latches are transparent; any changes on the

data lines will be reflected on the relevant DAC output.

20

W Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with

R/

CS to read back contents of DAC register. When CS and R/W are held low, the latches are transparent; any
changes on the data lines are reflected on the relevant DAC output.

21 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.

Rev. 0 | Page 9 of 28