ANALOG DEVICES AD5428, AD5440, AD5447 Service Manual
Dual 8-/10-/12-Bit, High Bandwidth,
Data Sheet
FEATURES
10 MHz multiplying bandwidth
INL of ±0.25 LSB @ 8 bits
20-lead and 24-lead TSSOP packages
2.5 V to 5.5 V supply operation
±10 V reference input
21.3 MSPS update rate
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset
0.5 μA typical current consumption
Guaranteed monotonic
Readback function
AD7528 upgrade (AD5428)
AD7547 upgrade (AD5447)
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
Multiplying DACs with Parallel Interface
AD5428/AD5440/AD5447
GENERAL DESCRIPTION
The AD5428/AD5440/AD54471 are CMOS, 8-, 10-, and 12-bit,
dual-channel, current output digital-to-analog converters (DACs),
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
As a result of being manufactured on a CMOS submicron process,
they offer excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The DACs use data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with 0s, and the DAC
outputs are at zero scale.
The applied external reference input voltage (V
the full-scale output current. An integrated feedback resistor (R
provides temperature tracking and full-scale voltage output when
combined with an external I-to-V precision amplifier.
The AD5428 is available in a small 20-lead TSSOP package, and
the AD5440/AD5447 DACs are available in small 24-lead TSSOP
packages.
1
U.S. Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
V
A
REF
) determines
REF
)
FB
AD5428/AD5440/AD5447
V
DD
DB0
DATA
INPUTS
DB7
DB9
DB11
DAC A/B
R/W
DGND
CS
INPUT
BUFFER
CONTROL
LOGIC
POWER-ON
RESET
Figure 1. AD5428/AD5440/AD5447
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devi ces for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
R
LATCH
LATCH
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
8-/10-/12-BIT
R-2R DAC A
8-/10-/12-BIT
R-2R DAC B
B
V
REF
R
R
FB
I
OUT
AGND
R
FB
I
OUT
A
A
B
B
04462-001
AD5428/AD5440/AD5447 Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
Divider or Programmable Gain Element................................ 20
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ........................................... 10
Te r mi n ol o g y .................................................................................... 15
General Description....................................................................... 16
DAC Section................................................................................ 16
Circuit Operation ....................................................................... 16
Single-Supply Applications ....................................................... 19
Adding Gain ................................................................................19
REVISION HISTORY
8/11—Rev. B to Rev. C
CS
Changes to
3/11—Rev. A to Rev. B
Changes to Evaluation Board For the AD5447 Section ............ 23
Changes to Figure 47 Caption....................................................... 24
Changes to Figure 49...................................................................... 25
Change to U1 Description in Table 12......................................... 27
Change to Ordering Guide............................................................ 29
7/05—Rev. 0 to Rev. A
Changed Pin DAC A/B to DAC
Changes to Features List.................................................................. 1
Changes to Specifications................................................................ 3
Changes to Timing Characteristics................................................ 5
Change to Figure 2 ........................................................................... 5
Change to Absolute Maximum Ratings Section........................... 6
Change to Figure 13, Figure 14, and Figure 18........................... 11
Change to Figure 32 Through Figure 34 .....................................14
Pin Description, Table 6........................................ 9
/B................................Universal
A
Reference Selection .................................................................... 20
Amplifier Selection .................................................................... 20
Parallel Interface ......................................................................... 22
Microprocessor Interfacing....................................................... 22
PCB Layout and Power Supply Decoupling ........................... 23
Evaluation Board for the AD5447............................................ 23
Power Supplies for the Evaluation Board................................ 23
Bill of Materials ............................................................................... 27
Overview of AD54xx Devices....................................................... 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
Changes to General Description Section .................................... 16
Changes to Figure 37...................................................................... 16
Changes to Single-Supply Applications Section......................... 19
Changes to Figure 40 Through Figure 42.................................... 19
Changes to Divider or Programmable Gain Element Section.... 20
Changes to Figure 43...................................................................... 20
Changes to Table 9 Through Table 11 ......................................... 21
Changes to Microprocessor Interfacing Section ........................ 22
Added Figure 44 Through Figure 46 ........................................... 22
Added 8xC51-to-AD5428/AD5440/AD5447
Interface Section ........................................................................ 22
Added ADSP-BF5xx-to-AD5428/AD5440/AD5447
Interface Section ........................................................................ 22
Changes to Power Supplies for the Evaluation Board Section.... 23
Changes to Table 13 ....................................................................... 28
Updated Outline Dimensions....................................................... 29
Changes to Ordering Guide.......................................................... 29
7/04—Revision 0: Initial Version
Rev. C | Page 2 of 32
Data Sheet AD5428/AD5440/AD5447
SPECIFICATIONS1
VDD = 2.5 V to 5.5 V, V
otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Conditions
STATIC PERFORMANCE
AD5428
Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
AD5440
Resolution 10 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
AD5447
Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity –1/+2 LSB Guaranteed monotonic
Gain Error ±25 mV
Gain Error Temperature Coefficient ±5 ppm FSR/°C
Output Leakage Current ±5 nA Data = 0x0000, TA = 25°C
±15 nA Data = 0x0000
REFERENCE INPUT
Reference Input Range ±10 V
V
A, V
REF
V
REF
B Input Resistance 8 10 13 kΩ Input resistance TC = –50 ppm/°C
REF
A-to-V
B Input
REF
Resistance Mismatch
Input Capacitance
Code 0 3.5 pF
Code 4095 3.5 pF
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH 1.7 V VDD = 3.6 V to 5.5 V
1.7 V VDD = 2.5 V to 3.6 V
Input Low Voltage, V
0.7 V VDD = 2.5 V to 2.7 V
Output High Voltage, VOH V
V
Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5.5 V, I
0.4 V VDD = 2.5 V to 3.6 V, I
Input Leakage Current, IIL 1 µA
Input Capacitance 4 10 pF
DYNAMIC PERFORMANCE
Reference-Multiplying BW 10 MHz V
Output Voltage Settling Time R
Measured to ±1 mV of FS 80 120 ns
Measured to ±4 mV of FS 35 70 ns
Measured to ±16 mV of FS 30 60 ns
Digital Delay 20 40 ns Interface delay time
10% to 90% Settling Time 15 30 ns Rise and fall times, V
Digital-to-Analog Glitch Impulse 3
= 10 V, I
REF
2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T
OUT
1.6 2.5 % Typ = 25°C, max = 125°C
0.8 V VDD = 2.7 V to 5.5 V
IL
− 1 V VDD = 4.5 V to 5.5 V, I
DD
− 0.5 V VDD = 2.5 V to 3.6 V, I
DD
= ±3.5 V p-p, DAC loaded all 1s
REF
= 100 Ω, C
LOAD
DAC latch alternately loaded with 0s and 1s
nV-sec
1 LSB change around major carry, V
SOURCE
SOURCE
SINK
SINK
= 15 pF, V
LOAD
REF
= 200 µA
= 200 µA
= 200 µA
= 200 µA
REF
= 10 V, R
to T
MIN
= 10 V
LOAD
, unless
MAX
= 100 Ω
= 0 V
REF
Rev. C | Page 3 of 32
AD5428/AD5440/AD5447 Data Sheet
Parameter Min Typ Max Unit Conditions
Multiplying Feedthrough Error DAC latches loaded with all 0s, V
70 dB 1 MHz
48 dB 10 MHz
Output Capacitance 12 17 pF DAC latches loaded with all 0s
25 30 pF DAC latches loaded with all 1s
Digital Feedthrough 1 nV-sec
Feedthrough to DAC output with CS
alternate loading of all 0s and all 1s
Output Noise Spectral Density 25
Analog THD 81 dB V
Digital THD Clock = 10 MHz, V
100 kHz f
50 kHz f
61 dB
OUT
66 dB
OUT
SFDR Performance (Wide Band) AD5447, 65k codes, V
nV/√Hz @ 1 kHz
= 3.5 V p-p, all 1s loaded, f = 100 kHz
REF
= 3.5 V
REF
REF
= 3.5 V
Clock = 10 MHz
500 kHz f
100 kHz f
50 kHz f
55 dB
OUT
63 dB
OUT
65 dB
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f
SFDR Performance (Narrow Band) AD5447, 65k codes, V
50 dB
OUT
60 dB
OUT
62 dB
OUT
= 3.5 V
REF
Clock = 10 MHz
500 kHz f
100 kHz f
50k Hz f
73 dB
OUT
80 dB
OUT
87 dB
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f
Intermodulation Distortion AD5447, 65k codes, V
70 dB
OUT
75 dB
OUT
80 dB
OUT
= 3.5 V
REF
f1 = 40 kHz, f2 = 50 kHz 72 dB Clock = 10 MHz
f1 = 40 kHz, f2 = 50 kHz 65 dB Clock = 25 MHz
POWER REQUIREMENTS
Power Supply Range 2.5 5.5 V
IDD 0.7 µA TA = 25°C, logic inputs = 0 V or VDD
0.5 10 µA TA = −40°C to +125°C, logic inputs = 0 V or VDD
Power Supply Sensitivity 0.001 %/% VDD = ±5%
1
Guaranteed by design, not subject to production test.
= ±3.5 V
REF
high and
Rev. C | Page 4 of 32
Data Sheet AD5428/AD5440/AD5447
B
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
V
= 10 V, I
REF
Table 2.
Parameter1 Limit at T
Write Mode
t1 0 ns min
t2 0 ns min
t3 10 ns min
t4 10 ns min Address setup time
t5 0 ns min Address hold time
t6 6 ns min Data setup time
t7 0 ns min Data hold time
t8 5 ns min
t9 7 ns min
Data Readback Mode
t10 0 ns typ Address setup time
t11 0 ns typ Address hold time
t12 5 ns typ Data access time
25 ns max
t13 5 ns typ Bus relinquish time
10 ns max
Update Rate 21.3 MSPS
1
Guaranteed by design and characterization, not subject to production test.
2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications T
OUT
, T
MIN
Unit Conditions/Comments
MAX
R/W
to CS setup time
R/W
to CS hold time
CS
low time
R/W
high to CS low
CS
min high time
Consists of CS
voltage settling time
to T
MIN
, unless otherwise noted.
MAX
min high time, CS low time, and output
DACA/DAC
DATA
R/W
CS
t
1
t
3
t
4
t
8
DATA VALID DATA VALID
t
2
t
5
t
8
t
9
t
10
t
7
Figure 2. Timing Diagram
TO OUTPUT
PIN
200μAI
C
L
50pF
200μAI
OL
V
OH (MIN)
OH
Figure 3. Load Circuit for Data Output Timing Specifications
t
+ V
12
2
OL (MAX)
t
11
04462-003
t
2
t
13
04462-002
Rev. C | Page 5 of 32
AD5428/AD5440/AD5447 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
T
= 25°C, unless otherwise noted.
A
Table 3.
Parameter Rating
VDD to GND –0.3 V to +7 V
V
A, V
REF
I
OUT
Logic Inputs and Output1 –0.3 V to VDD + 0.3 V
Operating Temperature Range
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
20-lead TSSOP θJA Thermal Impedance 143°C/W
24-lead TSSOP θJA Thermal Impedance 128°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 235°C
1
Overvoltages at DBx, CS, and R/
B, RFBA, RFBB to DGND –12 V to +12 V
REF
1, I
2 to DGND –0.3 V to +7 V
OUT
Automotive (Y Version) –40°C to +125°C
W
are clamped by internal diodes.
Stresses above those listed in Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability. Only one absolute maximum rating may be applied
at any one time.
ESD CAUTION
Rev. C | Page 6 of 32
Data Sheet AD5428/AD5440/AD5447
B
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AGND
I
OUT
R
V
REF
DGND
DAC A/
FB
DB7
DB6
DB5
DB4
A
A
A
10
1
2
3
AD5428
4
TOP VIEW
(Not to Scale)
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
I
B
OUT
R
B
FB
B
V
REF
V
DD
R/W
CS
DB0 (LSB)
DB1
DB2
DB3
04462-004
Figure 4. Pin Configuration 20-Lead TSSOP (RU-20)
Table 4. AD5428 Pin Function Descriptions
Pin No. Mnemonic Description
1 AGND
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
2, 20 I
3, 19 RFBA, RFBB
OUT
A, I
B DAC Current Outputs.
OUT
DAC Feedback Resistor Pins. These pins establish voltage output for the DAC by connecting to an external
amplifier output.
4, 18 V
REF
A, V
B DAC Reference Voltage Input Terminals.
REF
5 DGND Digital Ground Pin.
6
DAC A
/B
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
7 to14 DB7 to DB0 Parallel Data Bits 7 Through 0.
15
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
CS
data from the DAC register.
16
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction
R/W
with CS to read back contents of the DAC register.
17 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 7 of 32
AD5428/AD5440/AD5447 Data Sheet
AGND
I
OUT
R
FB
V
REF
DGND
DAC A/B
DB9
DB8
DB7
DB6
DB5
DB4
1
2
A
3
A
4
A
AD5440
5
TOP VIEW
(Not to Scale)
6
7
8
9
10
11
12
NC = NO CONNECT
24
23
22
21
20
19
18
17
16
15
14
13
I
B
OUT
B
R
FB
V
B
REF
V
DD
R/W
CS
NC
NC
DB0 (LSB)
DB1
DB2
DB3
04462-005
Figure 5. Pin Configuration 24-Lead TSSOP (RU-24)
Table 5. AD5440 Pin Function Descriptions
Pin No. Mnemonic Function
1
2, 24 I
AGND
A, I
OUT
OUT
3, 23 RFBA, RFBB
4, 22 V
REF
A, V
REF
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
B DAC Current Outputs.
DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier
output.
B DAC Reference Voltage Input Terminals.
5 DGND Digital Ground Pin.
DAC A
6
/B
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
7 to16 DB9 to DB0 Parallel Data Bits 9 Through 0.
19
20
CS
R/W
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register.
Read/Write. When low, used in conjunction with CS
to load parallel data. When high, used in conjunction with
CS to read back contents of the DAC register.
21 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 8 of 32
Data Sheet AD5428/AD5440/AD5447
AGND
I
OUT
R
FB
V
REF
DGND
DAC A/B
DB11
DB10
DB9
DB8
DB7
DB6
A
A
A
10
11
12
1
2
3
4
AD5447
5
TOP VIEW
(Not to Scale)
6
7
8
9
24
I
23
R
22
V
21
V
20
R/W
19
CS
18
DB0 (LSB)
17
DB1
16
DB2
15
DB3
14
DB4
13
DB5
OUT
FB
REF
DD
B
B
B
04462-006
Figure 6. Pin Configuration 24-Lead TSSOP (RU-24)
Table 6. AD5447 Pin Function Descriptions
Pin No. Mnemonic Description
1 AGND
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
2, 24 I
3, 23 RFBA, RFBB
OUT
A, I
B DAC Current Outputs.
OUT
DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier
output.
4, 22 V
REF
A, V
B DAC Reference Voltage Input Terminals.
REF
5 DGND Digital Ground Pin.
6
DAC A
/B
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
7 to 18 DB11 to DB0 Parallel Data Bits 11 Through 0.
19
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
CS
data from the DAC register.
20
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with
R/W
to read back the contents of the DAC register. When CS and R/W are held low, the latches are transparent.
CS
Any changes on the data lines are reflected in the relevant DAC output.
21 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 9 of 32
AD5428/AD5440/AD5447 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.15
0.10
TA = 25°C
V
= 10V
REF
V
= 5V
DD
0.20
0.15
0.10
TA = 25°C
V
= 10V
REF
V
= 5V
DD
0.05
0
INL (LSB)
–0.05
–0.10
–0.15
–0.20
0 50 100 150 200 250
CODE
Figure 7. INL vs. Code (8-Bit DAC)
0.5
TA = 25°C
0.4
V
= 10V
REF
V
= 5V
DD
0.3
0.2
0.1
0
INL (LSB)
–0.1
–0.2
–0.3
–0.4
–0.5
0 200 400 600 800 1000
CODE
Figure 8. INL vs. Code (10-Bit DAC)
04462-007
04462-008
0.05
0
DNL (LSB)
–0.05
–0.10
–0.15
–0.20
0 50 100 150 200 250
CODE
Figure 10. DNL vs. Code (8-Bit DAC)
0.5
TA = 25°C
0.4
V
= 10V
REF
V
= 5V
DD
0.3
0.2
0.1
0
DNL (LSB)
–0.1
–0.2
–0.3
–0.4
–0.5
0 200 400 600 800 1000
CODE
Figure 11. DNL vs. Code (10-Bit DAC)
04462-010
04462-011
INL (LSB)
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
–1.0
1.0
TA = 25°C
V
= 10V
REF
V
= 5V
DD
0
DNL (LSB)
20001500500 10000 2500 3000 3500 4000
CODE
04462-009
Figure 9. INL vs. Code (12-Bit DAC)
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
–1.0
TA = 25°C
V
= 10V
REF
V
= 5V
DD
0
20001500500 10000 2500 3000 3500 4000
CODE
04462-012
Figure 12. DNL vs. Code (12-Bit DAC)
Rev. C | Page 10 of 32
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