Dual 8-/10-/12-Bit, High Bandwidth,
Data Sheet
FEATURES
10 MHz multiplying bandwidth
INL of ±0.25 LSB @ 8 bits
20-lead and 24-lead TSSOP packages
2.5 V to 5.5 V supply operation
±10 V reference input
21.3 MSPS update rate
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset
0.5 μA typical current consumption
Guaranteed monotonic
Readback function
AD7528 upgrade (AD5428)
AD7547 upgrade (AD5447)
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
Multiplying DACs with Parallel Interface
AD5428/AD5440/AD5447
GENERAL DESCRIPTION
The AD5428/AD5440/AD54471 are CMOS, 8-, 10-, and 12-bit,
dual-channel, current output digital-to-analog converters (DACs),
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
As a result of being manufactured on a CMOS submicron process,
they offer excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The DACs use data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with 0s, and the DAC
outputs are at zero scale.
The applied external reference input voltage (V
the full-scale output current. An integrated feedback resistor (R
provides temperature tracking and full-scale voltage output when
combined with an external I-to-V precision amplifier.
The AD5428 is available in a small 20-lead TSSOP package, and
the AD5440/AD5447 DACs are available in small 24-lead TSSOP
packages.
1
U.S. Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
V
A
REF
) determines
REF
)
FB
AD5428/AD5440/AD5447
V
DD
DB0
DATA
INPUTS
DB7
DB9
DB11
DAC A/B
R/W
DGND
CS
INPUT
BUFFER
CONTROL
LOGIC
POWER-ON
RESET
Figure 1. AD5428/AD5440/AD5447
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devi ces for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
R
LATCH
LATCH
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
8-/10-/12-BIT
R-2R DAC A
8-/10-/12-BIT
R-2R DAC B
B
V
REF
R
R
FB
I
OUT
AGND
R
FB
I
OUT
A
A
B
B
04462-001
AD5428/AD5440/AD5447 Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
Divider or Programmable Gain Element................................ 20
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ........................................... 10
Te r mi n ol o g y .................................................................................... 15
General Description....................................................................... 16
DAC Section................................................................................ 16
Circuit Operation ....................................................................... 16
Single-Supply Applications ....................................................... 19
Adding Gain ................................................................................19
REVISION HISTORY
8/11—Rev. B to Rev. C
CS
Changes to
3/11—Rev. A to Rev. B
Changes to Evaluation Board For the AD5447 Section ............ 23
Changes to Figure 47 Caption....................................................... 24
Changes to Figure 49...................................................................... 25
Change to U1 Description in Table 12......................................... 27
Change to Ordering Guide............................................................ 29
7/05—Rev. 0 to Rev. A
Changed Pin DAC A/B to DAC
Changes to Features List.................................................................. 1
Changes to Specifications................................................................ 3
Changes to Timing Characteristics................................................ 5
Change to Figure 2 ........................................................................... 5
Change to Absolute Maximum Ratings Section........................... 6
Change to Figure 13, Figure 14, and Figure 18........................... 11
Change to Figure 32 Through Figure 34 .....................................14
Pin Description, Table 6........................................ 9
/B................................Universal
A
Reference Selection .................................................................... 20
Amplifier Selection .................................................................... 20
Parallel Interface ......................................................................... 22
Microprocessor Interfacing....................................................... 22
PCB Layout and Power Supply Decoupling ........................... 23
Evaluation Board for the AD5447............................................ 23
Power Supplies for the Evaluation Board................................ 23
Bill of Materials ............................................................................... 27
Overview of AD54xx Devices....................................................... 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
Changes to General Description Section .................................... 16
Changes to Figure 37...................................................................... 16
Changes to Single-Supply Applications Section......................... 19
Changes to Figure 40 Through Figure 42.................................... 19
Changes to Divider or Programmable Gain Element Section.... 20
Changes to Figure 43...................................................................... 20
Changes to Table 9 Through Table 11 ......................................... 21
Changes to Microprocessor Interfacing Section ........................ 22
Added Figure 44 Through Figure 46 ........................................... 22
Added 8xC51-to-AD5428/AD5440/AD5447
Interface Section ........................................................................ 22
Added ADSP-BF5xx-to-AD5428/AD5440/AD5447
Interface Section ........................................................................ 22
Changes to Power Supplies for the Evaluation Board Section.... 23
Changes to Table 13 ....................................................................... 28
Updated Outline Dimensions....................................................... 29
Changes to Ordering Guide.......................................................... 29
7/04—Revision 0: Initial Version
Rev. C | Page 2 of 32
Data Sheet AD5428/AD5440/AD5447
SPECIFICATIONS1
VDD = 2.5 V to 5.5 V, V
otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Conditions
STATIC PERFORMANCE
AD5428
Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
AD5440
Resolution 10 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
AD5447
Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity –1/+2 LSB Guaranteed monotonic
Gain Error ±25 mV
Gain Error Temperature Coefficient ±5 ppm FSR/°C
Output Leakage Current ±5 nA Data = 0x0000, TA = 25°C
±15 nA Data = 0x0000
REFERENCE INPUT
Reference Input Range ±10 V
V
A, V
REF
V
REF
B Input Resistance 8 10 13 kΩ Input resistance TC = –50 ppm/°C
REF
A-to-V
B Input
REF
Resistance Mismatch
Input Capacitance
Code 0 3.5 pF
Code 4095 3.5 pF
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH 1.7 V VDD = 3.6 V to 5.5 V
1.7 V VDD = 2.5 V to 3.6 V
Input Low Voltage, V
0.7 V VDD = 2.5 V to 2.7 V
Output High Voltage, VOH V
V
Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5.5 V, I
0.4 V VDD = 2.5 V to 3.6 V, I
Input Leakage Current, IIL 1 µA
Input Capacitance 4 10 pF
DYNAMIC PERFORMANCE
Reference-Multiplying BW 10 MHz V
Output Voltage Settling Time R
Measured to ±1 mV of FS 80 120 ns
Measured to ±4 mV of FS 35 70 ns
Measured to ±16 mV of FS 30 60 ns
Digital Delay 20 40 ns Interface delay time
10% to 90% Settling Time 15 30 ns Rise and fall times, V
Digital-to-Analog Glitch Impulse 3
= 10 V, I
REF
2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T
OUT
1.6 2.5 % Typ = 25°C, max = 125°C
0.8 V VDD = 2.7 V to 5.5 V
IL
− 1 V VDD = 4.5 V to 5.5 V, I
DD
− 0.5 V VDD = 2.5 V to 3.6 V, I
DD
= ±3.5 V p-p, DAC loaded all 1s
REF
= 100 Ω, C
LOAD
DAC latch alternately loaded with 0s and 1s
nV-sec
1 LSB change around major carry, V
SOURCE
SOURCE
SINK
SINK
= 15 pF, V
LOAD
REF
= 200 µA
= 200 µA
= 200 µA
= 200 µA
REF
= 10 V, R
to T
MIN
= 10 V
LOAD
, unless
MAX
= 100 Ω
= 0 V
REF
Rev. C | Page 3 of 32
AD5428/AD5440/AD5447 Data Sheet
Parameter Min Typ Max Unit Conditions
Multiplying Feedthrough Error DAC latches loaded with all 0s, V
70 dB 1 MHz
48 dB 10 MHz
Output Capacitance 12 17 pF DAC latches loaded with all 0s
25 30 pF DAC latches loaded with all 1s
Digital Feedthrough 1 nV-sec
Feedthrough to DAC output with CS
alternate loading of all 0s and all 1s
Output Noise Spectral Density 25
Analog THD 81 dB V
Digital THD Clock = 10 MHz, V
100 kHz f
50 kHz f
61 dB
OUT
66 dB
OUT
SFDR Performance (Wide Band) AD5447, 65k codes, V
nV/√Hz @ 1 kHz
= 3.5 V p-p, all 1s loaded, f = 100 kHz
REF
= 3.5 V
REF
REF
= 3.5 V
Clock = 10 MHz
500 kHz f
100 kHz f
50 kHz f
55 dB
OUT
63 dB
OUT
65 dB
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f
SFDR Performance (Narrow Band) AD5447, 65k codes, V
50 dB
OUT
60 dB
OUT
62 dB
OUT
= 3.5 V
REF
Clock = 10 MHz
500 kHz f
100 kHz f
50k Hz f
73 dB
OUT
80 dB
OUT
87 dB
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f
Intermodulation Distortion AD5447, 65k codes, V
70 dB
OUT
75 dB
OUT
80 dB
OUT
= 3.5 V
REF
f1 = 40 kHz, f2 = 50 kHz 72 dB Clock = 10 MHz
f1 = 40 kHz, f2 = 50 kHz 65 dB Clock = 25 MHz
POWER REQUIREMENTS
Power Supply Range 2.5 5.5 V
IDD 0.7 µA TA = 25°C, logic inputs = 0 V or VDD
0.5 10 µA TA = −40°C to +125°C, logic inputs = 0 V or VDD
Power Supply Sensitivity 0.001 %/% VDD = ±5%
1
Guaranteed by design, not subject to production test.
= ±3.5 V
REF
high and
Rev. C | Page 4 of 32
Data Sheet AD5428/AD5440/AD5447
B
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
V
= 10 V, I
REF
Table 2.
Parameter1 Limit at T
Write Mode
t1 0 ns min
t2 0 ns min
t3 10 ns min
t4 10 ns min Address setup time
t5 0 ns min Address hold time
t6 6 ns min Data setup time
t7 0 ns min Data hold time
t8 5 ns min
t9 7 ns min
Data Readback Mode
t10 0 ns typ Address setup time
t11 0 ns typ Address hold time
t12 5 ns typ Data access time
25 ns max
t13 5 ns typ Bus relinquish time
10 ns max
Update Rate 21.3 MSPS
1
Guaranteed by design and characterization, not subject to production test.
2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications T
OUT
, T
MIN
Unit Conditions/Comments
MAX
R/W
to CS setup time
R/W
to CS hold time
CS
low time
R/W
high to CS low
CS
min high time
Consists of CS
voltage settling time
to T
MIN
, unless otherwise noted.
MAX
min high time, CS low time, and output
DACA/DAC
DATA
R/W
CS
t
1
t
3
t
4
t
8
DATA VALID DATA VALID
t
2
t
5
t
8
t
9
t
10
t
7
Figure 2. Timing Diagram
TO OUTPUT
PIN
200μAI
C
L
50pF
200μAI
OL
V
OH (MIN)
OH
Figure 3. Load Circuit for Data Output Timing Specifications
t
+ V
12
2
OL (MAX)
t
11
04462-003
t
2
t
13
04462-002
Rev. C | Page 5 of 32
AD5428/AD5440/AD5447 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
T
= 25°C, unless otherwise noted.
A
Table 3.
Parameter Rating
VDD to GND –0.3 V to +7 V
V
A, V
REF
I
OUT
Logic Inputs and Output1 –0.3 V to VDD + 0.3 V
Operating Temperature Range
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
20-lead TSSOP θJA Thermal Impedance 143°C/W
24-lead TSSOP θJA Thermal Impedance 128°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 235°C
1
Overvoltages at DBx, CS, and R/
B, RFBA, RFBB to DGND –12 V to +12 V
REF
1, I
2 to DGND –0.3 V to +7 V
OUT
Automotive (Y Version) –40°C to +125°C
W
are clamped by internal diodes.
Stresses above those listed in Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability. Only one absolute maximum rating may be applied
at any one time.
ESD CAUTION
Rev. C | Page 6 of 32
Data Sheet AD5428/AD5440/AD5447
B
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AGND
I
OUT
R
V
REF
DGND
DAC A/
FB
DB7
DB6
DB5
DB4
A
A
A
10
1
2
3
AD5428
4
TOP VIEW
(Not to Scale)
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
I
B
OUT
R
B
FB
B
V
REF
V
DD
R/W
CS
DB0 (LSB)
DB1
DB2
DB3
04462-004
Figure 4. Pin Configuration 20-Lead TSSOP (RU-20)
Table 4. AD5428 Pin Function Descriptions
Pin No. Mnemonic Description
1 AGND
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
2, 20 I
3, 19 RFBA, RFBB
OUT
A, I
B DAC Current Outputs.
OUT
DAC Feedback Resistor Pins. These pins establish voltage output for the DAC by connecting to an external
amplifier output.
4, 18 V
REF
A, V
B DAC Reference Voltage Input Terminals.
REF
5 DGND Digital Ground Pin.
6
DAC A
/B
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
7 to14 DB7 to DB0 Parallel Data Bits 7 Through 0.
15
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
CS
data from the DAC register.
16
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction
R/W
with CS to read back contents of the DAC register.
17 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 7 of 32
AD5428/AD5440/AD5447 Data Sheet
AGND
I
OUT
R
FB
V
REF
DGND
DAC A/B
DB9
DB8
DB7
DB6
DB5
DB4
1
2
A
3
A
4
A
AD5440
5
TOP VIEW
(Not to Scale)
6
7
8
9
10
11
12
NC = NO CONNECT
24
23
22
21
20
19
18
17
16
15
14
13
I
B
OUT
B
R
FB
V
B
REF
V
DD
R/W
CS
NC
NC
DB0 (LSB)
DB1
DB2
DB3
04462-005
Figure 5. Pin Configuration 24-Lead TSSOP (RU-24)
Table 5. AD5440 Pin Function Descriptions
Pin No. Mnemonic Function
1
2, 24 I
AGND
A, I
OUT
OUT
3, 23 RFBA, RFBB
4, 22 V
REF
A, V
REF
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
B DAC Current Outputs.
DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier
output.
B DAC Reference Voltage Input Terminals.
5 DGND Digital Ground Pin.
DAC A
6
/B
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
7 to16 DB9 to DB0 Parallel Data Bits 9 Through 0.
19
20
CS
R/W
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register.
Read/Write. When low, used in conjunction with CS
to load parallel data. When high, used in conjunction with
CS to read back contents of the DAC register.
21 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 8 of 32
Data Sheet AD5428/AD5440/AD5447
AGND
I
OUT
R
FB
V
REF
DGND
DAC A/B
DB11
DB10
DB9
DB8
DB7
DB6
A
A
A
10
11
12
1
2
3
4
AD5447
5
TOP VIEW
(Not to Scale)
6
7
8
9
24
I
23
R
22
V
21
V
20
R/W
19
CS
18
DB0 (LSB)
17
DB1
16
DB2
15
DB3
14
DB4
13
DB5
OUT
FB
REF
DD
B
B
B
04462-006
Figure 6. Pin Configuration 24-Lead TSSOP (RU-24)
Table 6. AD5447 Pin Function Descriptions
Pin No. Mnemonic Description
1 AGND
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
2, 24 I
3, 23 RFBA, RFBB
OUT
A, I
B DAC Current Outputs.
OUT
DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier
output.
4, 22 V
REF
A, V
B DAC Reference Voltage Input Terminals.
REF
5 DGND Digital Ground Pin.
6
DAC A
/B
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
7 to 18 DB11 to DB0 Parallel Data Bits 11 Through 0.
19
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
CS
data from the DAC register.
20
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with
R/W
to read back the contents of the DAC register. When CS and R/W are held low, the latches are transparent.
CS
Any changes on the data lines are reflected in the relevant DAC output.
21 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 9 of 32
AD5428/AD5440/AD5447 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.15
0.10
TA = 25°C
V
= 10V
REF
V
= 5V
DD
0.20
0.15
0.10
TA = 25°C
V
= 10V
REF
V
= 5V
DD
0.05
0
INL (LSB)
–0.05
–0.10
–0.15
–0.20
0 50 100 150 200 250
CODE
Figure 7. INL vs. Code (8-Bit DAC)
0.5
TA = 25°C
0.4
V
= 10V
REF
V
= 5V
DD
0.3
0.2
0.1
0
INL (LSB)
–0.1
–0.2
–0.3
–0.4
–0.5
0 200 400 600 800 1000
CODE
Figure 8. INL vs. Code (10-Bit DAC)
04462-007
04462-008
0.05
0
DNL (LSB)
–0.05
–0.10
–0.15
–0.20
0 50 100 150 200 250
CODE
Figure 10. DNL vs. Code (8-Bit DAC)
0.5
TA = 25°C
0.4
V
= 10V
REF
V
= 5V
DD
0.3
0.2
0.1
0
DNL (LSB)
–0.1
–0.2
–0.3
–0.4
–0.5
0 200 400 600 800 1000
CODE
Figure 11. DNL vs. Code (10-Bit DAC)
04462-010
04462-011
INL (LSB)
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
–1.0
1.0
TA = 25°C
V
= 10V
REF
V
= 5V
DD
0
DNL (LSB)
20001500500 10000 2500 3000 3500 4000
CODE
04462-009
Figure 9. INL vs. Code (12-Bit DAC)
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
–1.0
TA = 25°C
V
= 10V
REF
V
= 5V
DD
0
20001500500 10000 2500 3000 3500 4000
CODE
04462-012
Figure 12. DNL vs. Code (12-Bit DAC)
Rev. C | Page 10 of 32
Data Sheet AD5428/AD5440/AD5447
INL (LSB)
0.6
0.5
0.4
0.3
0.2
0.1
–0.1
–0.2
–0.3
MAX INL
TA = 25°C
V
= 5V
DD
0
MIN INL
65342 78910
REFERENCE VOLTAGE
04462-013
Figure 13. INL vs. Reference Voltage
8
7
6
5
4
3
CURRENT (mA)
2
1
0
1.00.50
VDD = 5V
VDD = 3V
VDD = 2.5V
INPUT VOLTAGE (V)
Figure 16. Supply Current vs. Logic Input Voltage
TA = 25°C
4.54.03.53.02.52.01.5
5.0
04462-022
–0.40
TA = 25°C
V
= 5V
DD
–0.45
–0.50
–0.55
DNL (LSB)
–0.60
–0.65
–0.70
MIN DNL
65342789
REFERENCE VOLTAGE
Figure 14. DNL vs. Reference Voltage
5
4
3
2
1
0
–1
ERROR (mV)
–2
–3
–4
–5
–60 –40 –20 0 20 40 60 80 100 120 140
VDD = 5V
V
= 2.5V
DD
= 10V
V
REF
TEMPERATURE (°C)
Figure 15. Gain Error vs. Temperature
1.6
1.4
1.2
1.0
0.8
0.6
1 LEAKAGE (nA)
0.4
OUT
I
0.2
0
10
04462-014
0.50
0.45
0.40
0.35
0.30
0.25
0.20
CURRENT (μA)
0.15
0.10
0.05
0
–60 –40 –20 0 20 40 60 80 100 120 140
04462-015
I
1 VDD = 5V
OUT
I
1 VDD = 3V
OUT
4020–20 0–40 60 80 100 120
TEMPERATURE (°C)
Figure 17. I
1 Leakage Current vs. Temperature
OUT
VDD = 5V
ALL 0s
ALL 1s
VDD = 2.5V
ALL 0sALL 1s
TEMPERATURE (°C)
Figure 18. Supply Current vs. Temperature
04462-023
04462-024
Rev. C | Page 11 of 32
AD5428/AD5440/AD5447 Data Sheet
14
TA = 25°C
LOADING ZS TO FS
12
V
= 5V
DD
= 3V
V
DD
= 2.5V
V
DD
(mA)
DD
I
10
8
6
4
2
0
10k1k10 1001 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 19. Supply Current vs. Update Rate
6
TA = 25°C
0
LOADING
–6
ZS TO FS
–12
–18
–24
–30
–36
–42
–48
GAIN (dB)
–54
–60
–66
–72
–78
–84
–90
–96
–102
1 100 1k 10k 100k 1M 10M 100M
ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ALL OFF
10
FREQUENCY (Hz)
TA = 25°C
V
= 5V
DD
= ±3.5V
V
REF
=1.8pF
C
COMP
AMP = AD8038
Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code
04462-025
04462-026
3
TA = 25°C
= 5V
V
DD
0
–3
GAIN (dB)
V
= ±2V, AD8038 CC 1.47pF
REF
–6
–9
10k 100k 1M 10M 100M
= ±2V, AD8038 CC 1pF
V
REF
V
= ±0.15V, AD8038 CC 1pF
REF
= ±0.15V, AD8038 CC 1.47pF
V
REF
= ±3.51V, AD8038 CC 1.8pF
V
REF
FREQUENCY (Hz)
Figure 22. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
0.045
0x7FF TO 0x800
0.040
0.035
0.030
0.025
0.020
0.015
0.010
OUTPUT VOLTAGE (V)
0.005
0
–0.005
–0.010
0 20 40 60 80 100 120 140 160 180 200
VDD = 5V
VDD = 3V
0x800 TO 0x7FF
VDD = 3V
VDD = 5V
TIME (ns)
Figure 23. Midscale Transition, V
TA = 25°C
= 0V
V
REF
AMP = AD8038
C
COMP
= 0 V
REF
04462-028
= 1.8pF
04462-041
0.2
0
–0.2
GAIN (dB)
–0.4
TA = 25°C
–0.6
–0.8
= 5V
V
DD
=±3.5V
V
REF
= 1.8pF
C
COMP
AMP = AD8038
10k1k10 1001 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 21. Reference Multiplying Bandwidth—All 1s Loaded
OUTPUT VOLTAGE (V)
04462-027
Rev. C | Page 12 of 32
–1.68
–1.69
–1.70
–1.71
–1.72
–1.73
–1.74
–1.75
–1.76
–1.77
0x7FF TO 0x800
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
0x800 TO 0x7FF
0 20 40 60 80 100 120 140 160 180 200
TIME (ns)
Figure 24. Midscale Transition, V
TA = 25°C
V
REF
AMP = AD8038
C
COMP
= 3.5 V
REF
= 3.5V
= 1.8pF
04462-042
Data Sheet AD5428/AD5440/AD5447
20
TA = 25°C
= 3V
V
DD
AMP = AD8038
0
–20
–40
–60
PSRR (dB)
–80
–100
–120
1 100 1k 10k 100k 1M 10M
10
FULL SCALE
ZERO SCALE
FREQUENCY (Hz)
Figure 25. Power Supply Rejection Ratio vs. Frequency
04462-043
90
80
70
60
50
40
SFDR (dB)
30
20
10
MCLK = 5MHz
MCLK = 10MHz
MCLK = 25MHz
TA = 25°C
V
0
0 100 200 300 400 500 600 700 800 900 1000
f
(kHz)
OUT
Figure 28. Wideband SFDR vs. f
AMP = AD8038
Frequency
OUT
REF
= 3.5V
04462-046
–60
TA = 25°C
= 3V
V
DD
= 3.5V p-p
V
REF
–65
–70
–75
THD + N (dB)
–80
–85
–90
100 1k1 10 10k 100k 1M
FREQUENCY (Hz)
Figure 26. THD + Noise vs. Frequency
100
MCLK = 1MHz
80
MCLK = 200kHz
60
MCLK = 0.5MHz
SFDR (dB)
40
20
0
0 20 40 60 80 100 120 140 160 180 200
f
(kHz)
OUT
Figure 27. Wideband SFDR vs. f
TA = 25°C
V
AMP = AD8038
Frequency
OUT
REF
= 3.5V
04462-044
04462-045
0
–10
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
0
2 4 6 8 10 12
Figure 29. Wideband SFDR, f
0
–10
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
–100
0.5 1.5 3.0 3.5 4.01.0 2.0 2.5 4.5 5.0
0
Figure 30. Wideband SFDR, f
FREQUENCY (MHz)
= 100 kHz, Clock = 25 MHz
OUT
FREQUENCY (MHz)
= 500 kHz, Clock = 10 MHz
OUT
TA = 25°C
V
= 5V
DD
AMP = AD8038
65k CODES
TA = 25°C
V
= 5V
DD
AMP = AD8038
65k CODES
04462-047
04462048
Rev. C | Page 13 of 32
AD5428/AD5440/AD5447 Data Sheet
0
–10
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
TA = 25°C
V
= 5V
DD
AMP = AD8038
65k CODES
0
0.5 1.5 3.0 3.5 4.01.0 2.0 2.5 4.5 5.0
FREQUENCY (MHz)
04462-049
0
–10
–20
–30
–40
–50
IMD (dB)
–60
–70
–80
–90
–100
70 12075 80 85 115
95
90 100 105 110
FREQUENCY (kHz)
TA = 25°C
= 3V
V
DD
AMP = AD8038
65k CODES
04462-052
Figure 31. Wideband SFDR, f
0
–10
–20
–30
–40
–50
–60
SFDR (dB)
–70
–80
–90
–100
250 750300 350 400 650 700
FREQUENCY (kHz)
Figure 32. Narrow-Band SFDR, f
20
0
–20
–40
–60
SFDR (dB)
–80
–100
= 50 kHz, Clock = 10 MHz Figure 34. Narrow-Band IMD, f
OUT
450 500 550 600
= 500 kHz, Clock = 25 MHz
OUT
TA = 25°C
= 3V
V
DD
AMP = AD8038
65k CODES
TA = 25°C
= 3V
V
DD
AMP = AD8038
65k CODES
04462-050
= 90 kHz, 100 kHz, Clock = 10 MHz
OUT
0
–10
–20
–30
–40
–50
IMD (dB)
–60
–70
–80
–90
–100
0 400
50 300 350100 150 200 250
Figure 35. Wideband IMD, f
300
ZERO SCALE LOADED TO DAC
250
200
150
100
OUTPUT NOISE (nV/ Hz)
50
MIDSCALE LOADED TO DAC
FREQUENCY (kHz)
= 90 kHz, 100 kHz, Clock = 25 MHz
OUT
FULL SCALE LOADED TO DAC
TA = 25°C
V
DD
AMP = AD8038
65k CODES
TA = 25°C
AMP = AD8038
= 5V
04462-53
–120
50 150
60 70 80 130 140
Figure 33. Narrow-Band SFDR, f
90 100 110 120
FREQUENCY (kHz)
= 100 kHz, Clock = 25 MHz
OUT
04462-051
Rev. C | Page 14 of 32
0
100 1k 10k 100k
FREQUENCY (Hz)
Figure 36. Output Noise Spectral Density
04462-054
Data Sheet AD5428/AD5440/AD5447
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is measured after adjusting for zero and full scale and is
typically expressed in LSBs or as a percentage of the full-scale
reading.
Differential Nonlinearity
The difference in the measured change and the ideal 1 LSB
change between two adjacent codes. A specified differential
nonlinearity of −1 LSB maximum over the operating
temperature range ensures monotonicity.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
V
– 1 LSB. The gain error of the DACs is adjustable to zero
REF
with an external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when they
are turned off. For the I
loading all 0s to the DAC and measuring the I
Minimum current flows into the I
1 terminal, it can be measured by
OUT
1 current.
OUT
2 line when the DAC is
OUT
loaded with all 1s.
Output Capacitance
Capacitance from I
OUT
1 or I
2 to AGND.
OUT
Output Current Settling Time
The amount of time for the output to settle to a specified level
for a full-scale input change. For these devices, it is specified
with a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs is capacitively coupled through the
device and produces noise on the I
pins and, subsequently,
OUT
on the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC I
1 terminal when all 0s are
OUT
loaded to the DAC.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as second to fifth harmonics.
2222
VVVV
+++
THD
log20
=
32
V
1
54
Digital Intermodulation Distortion
Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones digitally generated
by the DAC and the second-order products at 2fa − fb and
2fb − fa.
Spurious-Free Dynamic Range (SFDR)
SFDR is the usable dynamic range of a DAC before spurious
noise interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonic or nonharmonic spur from dc to full
Nyquist bandwidth (half the DAC sampling rate, or fs/2).
Narrow-band SFDR is a measure of SFDR over an arbitrary
window size, in this case 50%, of the fundamental. Digital SFDR
is a measure of the usable dynamic range of the DAC when the
signal is a digitally generated sine wave.
Rev. C | Page 15 of 32
AD5428/AD5440/AD5447 Data Sheet
GENERAL DESCRIPTION
DAC SECTION
The AD5428/AD5440/AD5447 are CMOS 8-, 10-, and 12-bit,
dual-channel, current output DACs consisting of a standard
inverting R-2R ladder configuration. Figure 37 shows a simplified
diagram for a single channel of the 8-bit AD5428. The feedback
resistor R
(with a minimum of 8 kΩ and a maximum of 12 kΩ). If I
and AGND are kept at the same potential, a constant current
flows into each ladder leg, regardless of digital input code.
Therefore, the input resistance presented at V
constant and nominally of value R. The DAC output (I
code-dependent, producing various resistances and
capacitances. When choosing an external amplifier, take into
account the variation in impedance generated by the DAC on
the amplifier’s inverting input node.
A has a value of R. The value of R is typically 10 kΩ
FB
A is always
REF
OUT
V
REF
RR R
2R 2R 2R 2R 2R
S1 S2 S3 S8
DAC DATA LATCHES
AND DRIVERS
Figure 37. Simplified Ladder
R
A
R
FB
A
I
OUT
AGND
OUT
) is
04462-029
1
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 38. When an output amplifier
is connected in unipolar mode, the output voltage is given by
n
DVV 2/×−=
OUT
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (8-bit AD5428)
= 0 to 1023 (10-bit AD5440)
= 0 to 4095 (12-bit AD5447)
n is the resolution of the DAC.
Note that the output voltage polarity is opposite to the V
polarity for dc reference voltages. These DACs are designed to
operate with either negative or positive reference voltages. The
power pin is only used by the internal digital logic to drive
V
DD
the on and off states of the DAC switches.
These DACs are also designed to accommodate ac reference
input signals in the range of –10 V to +10 V.
REF
REF
Access is provided to the V
, RFB, and I
REF
terminals of DAC A
OUT
and DAC B, making the devices extremely versatile and
allowing them to be configured in several operating modes,
such as unipolar output mode, 4-quadrant multiplication
bipolar mode, or single-supply mode. Note that a matching
switch is used in series with the internal R
If users attempt to measure R
A, power must be applied to VDD
FB
A feedback resistor.
FB
to achieve continuity.
With a fixed 10 V reference, the circuit in Figure 38 gives a
unipolar 0 V to –10 V output voltage swing. When V
signal, the circuit performs 2-quadrant multiplication.
Tabl e 7 shows the relationship between digital code and the
expected output voltage for unipolar operation using the 8-bit
AD5428.
Table 7. Unipolar Code
Digital Input Analog Output (V)
1111 1111 –V
1000 0000 –V
0000 0001 –V
0000 0000 –V
(255/256)
REF
(128/256) = –V
REF
(1/256)
REF
(0/256) = 0
REF
REF
/2
is an ac
IN
Rev. C | Page 16 of 32
Data Sheet AD5428/AD5440/AD5447
AD5428/AD5440/AD5447
V
DD
DB0
DATA
INPUTS
DB7
DB9
DB11
DAC A/B
CS
R/W
DGND
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2
C1, C2 PHASE COMPENSATION (1pF TO 2pF) IS REQUIRED WHEN USING
HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
INPUT
BUFFER
CONTROL
LOGIC
POWER-ON
RESET
LATCH
LATCH
V
(±10V)
V
A
REF
8-/10-/12-BIT
R-2R DAC A
8-/10-/12-BIT
R-2R DAC B
V
B
REF
VINB
(±10V)
A
IN
1
R1
A
R
FB
R
A
I
OUT
AGND
B
R
FB
R
I
B
OUT
1
R3
1
R2
2
C1
V
A
OUT
AGND
1
R4
2
C2
B
V
OUT
AGND
04462-030
Figure 38. Unipolar Operation
Rev. C | Page 17 of 32
AD5428/AD5440/AD5447 Data Sheet
V
2
3
Bipolar Operation
In some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. This can
easily be accomplished by using another external amplifier and
some external resistors, as shown in Figure 39. In this circuit, the
second amplifier, A2, provides a gain of 2. Biasing the external
amplifier with an offset from the reference voltage results in full
4-quadrant multiplying operation. The transfer function of this
circuit shows that both negative and positive output voltages are
REF
=
OUT
).
created as the input data (D) is incremented from Code 0 (V
) to midscale (V
−V
REF
= 0 V) to full scale (V
OUT
OUT
= +V
When connected in bipolar mode, the output voltage is given by
−1
()
OUT
REF
n
2/
VDVV −×=
REF
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (AD5428)
= 0 to 1023 (AD5440)
= 0 to 4095 (AD5447)
n is the number of bits.
When V
is an ac signal, the circuit performs 4-quadrant
IN
multiplication. Tab l e 8 shows the relationship between digital
code and the expected output voltage for bipolar operation
using the 8-bit AD5428.
V
IN
(±10V)
Table 8. Bipolar Code
Digital Input Analog Output (V)
1111 1111 +V
(127/128)
REF
1000 0000 0
0000 0001 –V
0000 0000 –V
(127/128)
REF
(128/128)
REF
Stability
In the I-to-V configuration, the I
of the DAC and the inverting
OUT
node of the op amp must be connected as close as possible, and
proper PCB layout techniques must be used. Because every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited gain bandwidth product (GBP) and
there is excessive parasitic capacitance at the inverting node.
This parasitic capacitance introduces a pole into the open-loop
response, which can cause ringing or instability in the closedloop applications circuit.
An optional compensation capacitor, C1, can be added in parallel
with R
A for stability, as shown in Figure 38 and Figure 39. Too
FB
small a value of C1 can produce ringing at the output, whereas
too large a value can adversely affect the settling time. C1 should
be found empirically, but 1 pF to 2 pF is generally adequate for
the compensation.
A
1
R1
V
A
AD5428/AD5440/AD5447
V
DD
DATA
DB0
INPUTS
DB7
DB9
DB11
DAC A/B
CS
R/W
DGND
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V
ADJUST R3 FOR
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10.
C1, C2 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER.
INPUT
BUFFER
CONTROL
LOGIC
POWER-ON
RESET
B = 0V WITH CODE 10000000 IN DAC B LATCH.
OUT
LATCH
LATCH
REF
V
REF
(±10V)
8-/10-/12-BIT
R-2R DAC A
8-/10-/12-BIT
R-2R DAC B
B
1
R3
VINB
RR2
R
FB
I
OUT
AGND
R
R
FB
I
OUT
A = 0V WITH CODE 10000000 IN DAC A LATCH.
OUT
Figure 39. Bipolar Operation (4-Quadrant Multiplication)
R5
2
R6
20kΩ
2
R7
10kΩ
1
A
3
A
B
B
C1
A1
AGND
1
R4
3
C2
A3
2
R9
10kΩ
AGND
R10
20kΩ
20kΩ
A2
R11
5kΩ
AGND
R8
20kΩ
AGND
R12
5kΩ
A4
2
V
A
OUT
V
B
OUT
04462-031
Rev. C | Page 18 of 32
Data Sheet AD5428/AD5440/AD5447
.
2
D
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 40 shows the DACs operating in voltage-switching
mode. The reference voltage, V
and the output voltage is available at the V
, is applied to the I
IN
A terminal. In this
REF
configuration, a positive reference voltage results in a positive
output voltage, making single-supply operation possible. The
output from the DAC is voltage at constant impedance (the
DAC ladder resistance). Therefore, an op amp is necessary to
buffer the output voltage. The reference input no longer sees
constant input impedance, but one that varies with code.
Therefore, the voltage input should be driven from a low
impedance source.
Note that V
is limited to low voltages because the switches in
IN
the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and degrades the
integral linearity of the DAC. Also, V
must not go negative by
IN
more than 0.3 V, or an internal diode turns on, causing the
device to exceed the maximum ratings. In this type of
application, the full range of multiplying capability of the DAC
is lost.
V
DD
V
RFBA
V
IN
I
OUT
AGND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
DD
A
GND
V
REF
R1 R2
A
Figure 40. Single-Supply Voltage-Switching Mode
Positive Output Voltage
The output voltage polarity is opposite to the V
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistor’s tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the V
and GND pins of the reference become the virtual
OUT
ground and –2.5 V, respectively, as shown in Figure 41.
A pin,
OUT
V
polarity for
REF
OUT
04462-033
V
= 5V
IN
DD
8-/10-/12-BIT
V
A
REF
V
DD
DAC
GND
R
FB
I
OUT
AGND
A
A
C1
V
=
OUT
0V to 2.5V
ADR03
V
V
OUT
GND
+5V
–2.5V
–5V
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRE
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 41. Positive Voltage Output with Minimum Components
ADDING GAIN
In applications where the output voltage must be greater than
, gain can be added with an additional external amplifier, or
V
IN
it can be achieved in a single stage. Consider the effect of temperature coefficients of the thin film resistors of the DAC. Simply
placing a resistor in series with the R
in the temperature coefficients, resulting in larger gain temperature coefficient errors. Instead, the circuit in Figure 42 shows
the recommended method for increasing the gain of the circuit.
R1, R2, and R3 should have similar temperature coefficients,
but they need not match the temperature coefficients of the
DAC. This approach is recommended in circuits where gains of
greater than 1 are required.
V
DD
A
DD
DAC
R
FB
I
OUT
AGND
V
R1
V
IN
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
8-/10-/12-BIT
V
A
REF
GND
Figure 42. Increasing Gain of Current Output DAC
resistor causes mismatches
FB
C1
A
R3
R2
GAIN =
R1=
V
R2R3
R2
OUT
R2 + R3
R2
R3
+
04462-034
04462-035
Rev. C | Page 19 of 32
AD5428/AD5440/AD5447 Data Sheet
.
(
)
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves to
many applications. If this type of DAC is connected as the
feedback element of an op amp and R
resistor, as shown in Figure 43, the output voltage is inversely
proportional to the digital input fraction, D.
For D = 1 − 2
OUT
−n
, the output voltage is
()
VDVV
−−=−= 21//
ININ
V
V
IN
I
OUT
AGND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
Figure 43. Current-Steering DAC Used as a Divider or
DD
A
R
V
FB
DD
A
GND
Programmable Gain Element
As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and that the required accuracy is
met. For example, an 8-bit DAC driven with the binary code
0x10 (0001 0000)—that is, 16 decimal—in the circuit of
Figure 43 should cause the output voltage to be 16 times V
However, if the DAC has a linearity specification of ±0.5 LSB, D
can have a weight in the range of 15.5/256 to 16.5/256 so that the
possible output voltage is in the range of 15.5 V
an error of 3%, even though the DAC itself has a maximum
error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current into the V
is routed to the I
1 terminal, the output voltage changes as
OUT
follows:
Output Error Voltage Due to DAC Leakage
where R is the DAC resistance at the V
A is used as the input
FB
n
−
V
A
REF
terminal.
REF
V
OUT
04462-040
to 16.5 VIN—
IN
terminal
REF
.
IN
DRLeakage /×=
REFERENCE SELECTION
When selecting a reference for use with the AD54xx series of
current output DACs, pay attention to the reference’s output
voltage temperature coefficient specification. This parameter not
only affects the full-scale error, but can also affect the linearity
(INL and DNL) performance. The reference temperature
coefficient should be consistent with the system accuracy
specifications. For example, an 8-bit system required to hold its
overall specification to within 1 LSB over the temperature range
0° to 50°C dictates that the maximum system drift with temperature should be less than 78 ppm/°C. A 12-bit system with the
same temperature range to overall specification within 2 LSBs
requires a maximum drift of 10 ppm/°C. Choosing a precision
reference with low output temperature coefficient minimizes this
error source. Table 9 lists some references available from Analog
Devices that are suitable for use with these current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. Because of the code-dependent output resistance of the
DAC, the input offset voltage of an op amp is multiplied by the
variable gain of the circuit. A change in the noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic. The input offset voltage should be <1/4 LSB
to ensure monotonic behavior when stepping through codes.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor, R
low enough to prevent significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in voltageswitching circuits, because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolution.
Provided that the DAC switches are driven from true wideband,
low impedance sources (V
Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration,
minimize capacitance at the V
in this application) of the DAC by using low input capacitance
buffer amplifiers and careful board design.
. Most op amps have input bias currents
FB
and AGND), they settle quickly.
IN
node (the voltage output node
REF
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can handle
rail-to-rail signals. Analog Devices offers a wide variety of singlesupply amplifiers (see Tab le 1 0 and Tabl e 11 ).
Rev. C | Page 20 of 32
Data Sheet AD5428/AD5440/AD5447
Table 9. Suitable ADI Precision References
Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) ISS (mA) Output Noise (μV p-p) Package
ADR01 10 0.05 3 1 20 SOIC-8
ADR01 10 0.05 9 1 20 TSOT-23, SC70
ADR02 5 0.06 3 1 10 SOIC-8
ADR02 5 0.06 9 1 10 TSOT-23, SC70
ADR03 2.5 0.10 3 1 6 SOIC-8
ADR03 2.5 0.10 9 1 6 TSOT-23, SC70
ADR06 3 0.10 3 1 10 SOIC-8
ADR06 3 0.10 9 1 10 TSOT-23, SC70
ADR431 2.5 0.04 3 0.8 3.5 SOIC-8
ADR435 5 0.04 3 0.8 8 SOIC-8
ADR391 2.5 0.16 9 0.12 5 TSOT-23
ADR395 5 0.10 9 0.12 8 TSOT-23
Table 10. Suitable ADI Precision Op Amps
0.1 Hz to 10 Hz
Part No. Supply Voltage (V) VOS (Max) (μV) IB (Max) (nA)
OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8
OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8
AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8
AD8603 1.8 to 6 50 0.001 2.3 50 TSOT
AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8
Table 11. Suitable ADI High Speed Op Amps
Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) IB (Max) (nA) Package
AD8065 5 to 24 145 180 1,500 6,000 SOIC-8, SOT-23, MSOP
AD8021 ±2.5 to ±12 490 120 1,000 10,500 SOIC-8, MSOP
AD8038 3 to 12 350 425 3,000 750 SOIC-8, SC70-5
AD9631 ±3 to ±6 320 1,300 10,000 7,000 SOIC-8
Noise (μV p-p)
Supply Current (μA) Package
Rev. C | Page 21 of 32
AD5428/AD5440/AD5447 Data Sheet
PARALLEL INTERFACE
Data is loaded into the AD5428/AD5440/AD5447 in 8-, 10-, or
12-bit parallel word format. Control lines
and R/W allow
CS
data to be written to or read from the DAC register. A write
event takes place when
and R/W are brought low, data
CS
available on the data lines fills the shift register, and the rising
edge of
latches the data and transfers the latched data-word
CS
to the DAC register. The DAC latches are not transparent;
therefore, a write sequence must consist of a falling and rising
edge on
to ensure that data is loaded into the DAC register
CS
and its analog equivalent is reflected on the DAC output.
A read event takes place when R/
is held high and CS is
W
brought low. Data is loaded from the DAC register, goes back
into the input register, and is output onto the data line, where it
can be read back to the controller for verification or diagnostic
purposes. The input and DAC registers of these devices are not
transparent; therefore, a falling and rising edge of
is required
CS
to load each data-word.
MICROPROCESSOR INTERFACING
ADSP-21xx-to-AD5428/AD5440/AD5447 Interface
Figure 44 shows the AD5428/AD5440/AD5447 interfaced to
the ADSP-21xx series of DSPs as a memory-mapped device. A
single wait state may be necessary to interface the AD5428/
AD5440/AD5447 to the ADSP-21xx, depending on the clock
speed of the DSP. The wait state can be programmed via the
data memory wait state control register of the ADSP-21xx (see
the ADSP-21xx family’s user manual for details).
ADDR
ADRR
ADSP-21xx
0
TO
13
1
DMS
ADDRESS
DECODER
ADDRESS BUS
CS
AD5428/
AD5440/
AD5447
1
8xC51-to-AD5428/AD5440/AD5447 Interface
Figure 45 shows the interface between the AD5428/AD5440/
AD5447 and the 8xC51 family of DSPs. To facilitate external
data memory access, the address latch enable (ALE) mode is
enabled. The low byte of the address is latched with this output
pulse during access to the external memory. AD0 to AD7 are
the multiplexed low order addresses and data bus, and they
require strong internal pull-ups when emitting 1s. During
access to external memory, A8 to A15 are the high order
address bytes. Because these ports are open drain, they also
require strong internal pull-ups when emitting 1s.
A8 TO A15
1
8051
ADDRESS
DECODER
WR
ALE
AD0 TO AD7
1
ADDITIONAL PINS OMITTED FOR CLARITY.
8-BIT
LATCH
Figure 45. 8xC51-to-AD5428/AD5440/AD5447 Interface
ADDRESS BUS
DATA BUS
AD5428/
AD5440/
AD5447
CS
R/W
DB0 TO DB11
1
ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface
Figure 46 shows a typical interface between the AD5428/
AD5440/AD5447 and the ADSP-BF5xx family of DSPs. The
asynchronous memory write cycle of the processor drives the
digital inputs of the DAC. The
x line is actually four
AMS
memory select lines. Internal ADDR lines are decoded into
, and then these lines are inserted as chip selects. The
AMS
3–0
rest of the interface is a standard handshaking operation.
04462-057
WR
DATA 0 TO
DATA 23
1
ADDITIONAL PINS OMITTED FOR CLARITY.
DATA BUS
Figure 44. ADSP21xx-to-AD5428/AD5440/AD5447 Interface
R/W
DB0 TO DB11
ADSP-BF5xx
04462-055
1
Rev. C | Page 22 of 32
TO
ADDR
1
ADRR
19
1
AMSx
AWE
DATA 0 TO
DATA 23
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS
DECODER
ADDRESS BUS
CS
R/W
DB0 TO DB11
DATA BUS
Figure 46. ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface
AD5428/
AD5440/
AD5447
1
04462-056
Data Sheet AD5428/AD5440/AD5447
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD5428/AD5440/AD5447 is mounted
should be designed so that the analog and digital sections are
separate and confined to certain areas of the board. If the DAC
is in a system where multiple devices require an AGND-toDGND connection, the connection should be made at one
point only. The star ground point should be established as close
as possible to the device.
These DACs should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close as possible to
the package, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types of capacitors that provide a low impedance path to ground
at high frequencies, to handle transient currents due to internal
logic switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Components, such as clocks, that produce fast-switching signals
should be shielded with digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
microstrip technique is by far the best method, but its use is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to the ground
plane, and signal traces are placed on the soldered side.
It is good practice to use compact, minimum lead length PCB
layout design. Leads to the input should be as short as possible
to minimize IR drops and stray inductance.
The PCB metal traces between V
and RFB should also be
REF
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close as
possible to the device.
EVALUATION BOARD FOR THE AD5447
The evaluation board consists of an AD5447 DAC and a
current-to-voltage amplifier, the AD8065. Included on the
evaluation board is a 10 V reference, the ADR01. An external
reference may also be applied via an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows the
user to write a code to the device.
POWER SUPPLIES FOR THE EVALUATION BOARD
The board requires ±12 V and +5 V supplies. The +12 V VDD
and −12 V V
is used to power the DAC (V
are used to power the output amplifier; the +5 V
SS
) and transceivers (VCC).
DD1
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough on the board. A
Both supplies are decoupled to their respective ground plane
with 10 F tantalum and 0.1 F ceramic capacitors.
Rev. C | Page 23 of 32
AD5428/AD5440/AD5447 Data Sheet
O/P B
J6
TP4
+
C24
C23
10μF
0.1μF
4
SS
2
V
C22
1.8pF
+
C6
C5
10μF
1
DD
V
0.1μF
24
21
AD5447
U1
8
1
0
B
D
23
B
DD
V
0
1
B
B
D
D
7
1
1
B
D
B
FB
OUT
R
I
2
3
4
5
B
D
6
1
2
B
D
6
B
B
B
B
D
D
D
D
2
3
4
5
1
1
1
1
6
5
4
3
B
B
B
B
D
D
D
D
+
C26
C25
10μF
6
7
V–
V+
3
DD
U7
V
TP3 TP2
3
2
A
A
FB
OUT
R
I
/B
A
_
1
0
C
1
7
8
9
1
A
B
B
B
B
B
D
D
D
D
D
D
1
7
0
6
8
9
1
1
1
0
7
8
9
1
1
B
B
B
B
B
D
D
D
D
D
+
C9
10μF
0.1μF
C7
22
4
B
A
REF
REF
V
V
AGND
D
N
S
/W
G
C
R
D
5
0
9
2
1
S
W
C
R
O/P A
J1
TP1
C10
0.1μF
4
SS
2
V
1.8pF
J5J2
EXT
REF B
EXT
REF A
1
D
N
G
D
+
C11
C12
10μF
6
7
V–
V+
3
U3
B
A
LK1
3
J
0.1μF
DD
V
C8
0.1μF
4
1
OUT
V
IN
+V
3
DD
V
2
U2
GND
TRIM
5
C4
0.1μF
+
C3
10μF
1
DD
D
V
N
G
DD
V
4
J
A
C14
10μF
C16
10μF
+
+
CC
V
SS
V
C18
10μF
C20
10μF
+
+
C13
C15
0.1μF
C1
0.1μF
CC
V
5
4
3
6
9
0
1
2
4
1
1
2
2
A
C
B
C
E
V
C
U4
A
A
B
B
E
E
L
O
1
2
1
17
18
7
6
5
4
3
B
B
B
B
B
4
0
1
2
3
A
A
A
A
A
7
3
4
5
6
3
2
2
2
1
1
2
1
0
B
B
B
B
B
A
A
E
E
L
O
B
D
A
N
5
6
7
E
A
A
A
C
G
1
8
9
0
2
1
1
1
74ABT543
CC
V
C2
0.1μF
5
4
3
8
7
6
9
0
1
2
4
1
1
2
2
C
A
C
B
V
E
C
U5
A
A
B
B
E
E
L
O
1
2
1
1
1
7
6
5
4
3
B
B
B
B
B
4
0
1
2
3
A
A
A
A
A
7
3
4
5
6
3
2
2
2
1
1
2
1
0
B
B
B
B
B
A
A
E
E
L
O
B
D
A
74ABT543
N
5
6
7
E
A
A
A
C
8
G
9
0
1
2
1
1
1
3
–
2
P
2
1
0
U6-B
4
1
6
4
7
5
7
–
–
1
1
P
P
–
–
–
–
1
1
1
1
P
P
P
P
CC
V
2
3
4
5
6
0
U6-A
C17
0.1μF
DGND
Y3Y2Y1Y
1
0
A
A
E
1
3
2
8
9
6
–
–
3
1
1
–
P
P
1
P
4
1
1
1
–
3
–
1
–
1
1
P
P
P
0.1μF
4
1
2
–
2
P
0
1
1
9
1
Y3Y2Y1Y
1
0
A
A
E
5
3
1
1
–
–
2
2
P
P
D
N
G
D
P1–19
P1–20
P1–21
C17
P1–22
P1–23
C19
0.1μF
0.1μF
5
6
–
–
2
2
P
P
P1–24
P1–25
P1–26
P1–27
P1–28
P1–29
P1–30
04464-037
Figure 47. Schematic of AD5447 Evaluation Board
Rev. C | Page 24 of 32
Data Sheet AD5428/AD5440/AD5447
04462-036
Figure 48. Component-Side Artwork
04462-038
Figure 49. Silkscreen—Component-Side View ( Top Layer)
Rev. C | Page 25 of 32
AD5428/AD5440/AD5447 Data Sheet
04462-039
Figure 50. Solder-Side Artwork
Rev. C | Page 26 of 32
Data Sheet AD5428/AD5440/AD5447
BILL OF MATERIALS
Table 12.
Name/Position Part Description Value Tolerance (%) Stock Code
C1 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C2 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C3 Tantalum capacitor—Taj series 10 F 20 V 10 FEC 197-427
C4 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C5 Tantalum capacitor—Taj series 10 F 10 V 10 FEC 197-130
C6 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C7 NPO ceramic capacitor 1.8 pF 10 FEC 721-876
C8 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C9 Tantalum capacitor—Taj series 10 F 20 V 10 FEC 197-427
C10 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C11 Tantalum capacitor—Taj series 10 F 20 V 10 FEC 197-427
C12 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C13 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C14 Tantalum capacitor—Taj series 10 F 20 V 10 FEC 197-427
C15 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C16 Tantalum capacitor—Taj series 10 F 20 V 10 FEC 197-427
C17 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C18 Tantalum capacitor—Taj series 10 F 20 V 10 FEC 197-427
C19 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C20 Tantalum capacitor—Taj series 10 F 20 V 10 FEC 197-427
C21 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C22 NPO ceramic capacitor 1.8 pF 10 FEC 721-876
C23 Tantalum capacitor—Taj series 10 F 20 V 10 FEC 197-427
C24 X7R ceramic capacitor 0.1 F 10 FEC 499-675
C25 Tantalum capacitor—Taj series 10 F 20 V 10 FEC 197-427
C26 X7R ceramic capacitor 0.1 F 10 FEC 499-675
CS, DB0 to DB11 Red testpoint FEC 240-345 (Pack)
J1 to J6 SMB socket FEC 310-682
J2 SMB socket FEC 310-682
J3 SMB socket FEC 310-682
J4 SMB socket FEC 310-682
J5 SMB socket FEC 310-682
J6 SMB socket FEC 310-682
LK1 3-pin header (2 × 2) FEC 511-791 and FEC 528-456
P1 36-pin Centronics connector FEC 147-753
P2 6-pin terminal block FEC 151-792
RW Red testpoint FEC 240-345 (Pack)
TP1 to TP4 Red testpoint FEC 240-345 (Pack)
U1 AD5447 AD5447YRU
U2 ADR01 ADR01AR
U3 AD8065 AD8065AR
U4, U5 74ABT543 Fairchild 74ABT543CMTC
U6 74139 CD74HCT139M
U7 AD8065 AD8065AR
Each Corner Rubber stick-on feet FEC 148-922
Rev. C | Page 27 of 32
AD5428/AD5440/AD5447 Data Sheet
OVERVIEW OF AD54xx DEVICES
Table 13.
Part No. Resolution No. DACs INL (LSB) Interface Package1 Features
AD5424 8 1 ±0.25 Parallel RU-16, CP-20
10 MHz BW, 17 ns CS
AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial
AD5428 8 2 ±0.25 Parallel RU-20
10 MHz BW, 17 ns CS
AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial
AD5450 8 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial
AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial
AD5433 10 1 ±0.5 Parallel RU-20, CP-20
10 MHz BW, 17 ns CS
AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial
AD5440 10 2 ±0.5 Parallel RU-24
10 MHz BW, 17 ns CS
AD5451 10 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial
AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial
AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz serial
AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial
AD5405 12 2 ±1 Parallel CP-40
AD5445 12 2 ±1 Parallel RU-20, CP-20
AD5447 12 2 ±1 Parallel RU-24
10 MHz BW, 17 ns CS
10 MHz BW, 17 ns CS
10 MHz BW, 17 ns CS
AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial
AD5452 12 1 ±0.5 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial
AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial
AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial
AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5556 14 1 ±1 Parallel RU-28
4 MHz BW, 20 ns WR
AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5557 14 2 ±1 Parallel RU-38
4 MHz BW, 20 ns WR
AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5546 16 1 ±2 Parallel RU-28
4 MHz BW, 20 ns WR
AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock
AD5547 16 2 ±2 Parallel RU-38
1
RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
4 MHz BW, 20 ns WR
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
Rev. C | Page 28 of 32
Data Sheet AD5428/AD5440/AD5447
Y
OUTLINE DIMENSIONS
7.90
7.80
7.70
13
4.50
4.40
4.30
121
0.65
BSC
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AD
1.20
MAX
SEATING
PLANE
6.40 BSC
0.20
0.09
8°
0°
0.75
0.60
0.45
PIN 1
0.15
0.05
COPLANARIT
0.10
6.60
6.50
6.40
20
1
0.65
BSC
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AC
1.20 MAX
11
10
SEATING
PLANE
4.50
4.40
4.30
6.40 BSC
0.20
0.09
24
PIN 1
0.15
0.05
8°
0°
0.75
0.60
0.45
0.10 COPLANARITY
Figure 51. 20-Lead Thin Shrink Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Figure 52. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Resolution INL (LSB) Temperature Range Package Description Package Option
AD5428YRU 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20
AD5428YRU-REEL 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20
AD5428YRU-REEL7 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20
AD5428YRUZ 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20
AD5428YRUZ-REEL 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20
AD5428YRUZ-REEL7 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20
AD5440YRU 10 ±0.5 –40 °C to +125°C 24-Lead TSSOP RU-24
AD5440YRU-REEL 10 ±0.5 –40 °C to +125°C 24-Lead TSSOP RU-24
AD5440YRU-REEL7 10 ±0.5 –40 °C to +125°C 24-Lead TSSOP RU-24
AD5440YRUZ 10 ±0.5 –40 °C to +125°C 24-Lead TSSOP RU-24
AD5440YRUZ-REEL 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24
AD5440YRUZ-REEL7 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24
AD5447YRU 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24
AD5447YRU-REEL 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24
AD5447YRUZ 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24
AD5447YRUZ-REEL 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24
AD5447YRUZ-REEL7 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24
EVAL-AD5447EBZ Evaluation Kit
1
Z = RoHS Compliant Part.
Rev. C | Page 29 of 32
AD5428/AD5440/AD5447 Data Sheet
NOTES
Rev. C | Page 30 of 32
Data Sheet AD5428/AD5440/AD5447
NOTES
Rev. C | Page 31 of 32
AD5428/AD5440/AD5447 Data Sheet
NOTES
©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04462-0-8/11(C)
Rev. C | Page 32 of 32
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