Analog Devices AD5378 pra Datasheet

32-Channel, 14-Bit, Parallel and

Serial Input, Bipolar Voltage Output DAC

Preliminary Technical Data

FEATURES

32-channel DAC in 13 mm × 13 mm 108-lead CSPBGA Guaranteed monotonic to 14 bits Buffered voltage outputs

Output voltage span of 3.5 V × V Maximum output voltage span of 17.5 V

System calibration function allowing user-programmable

offset and gain Pseudo differential outputs relative to REFGND Clear function to user-defined REFGND (

Simultaneous update of DAC outputs (

DAC increment/decrement mode Channel grouping and addressing features

V

CCVDDVSS

POWER-ON

RESET

REF

(+)

LDAC

pin)

CLR

pin)

FUNCTIONAL BLOCK DIAGRAM

AGND

DGND LDAC V

AD5378

Interface options

Parallel interface DSP/microcontroller-compatible 3-wire serial interface

2.5 V to 5.5 V JEDEC-compliant digital levels SDO daisy-chaining option Power-on reset Digital reset (

APPLICATIONS

Level setting in automatic test equipment (ATE) Variable optical attenuators (VOAs) Optical switches Industrial control systems

BIASVREF

VBIAS

1(+) V

pin and soft reset function)

RESET

1(–) REFGND A1

REF

CLR

DCEN/WR

SYNC/CS

REG0 REG1

DB13

SCLK/DB12

DIN/DB11

DB0

SER/PAR

DIN

SCLK

SDO

FIFOEN

REFGND B1 REFGND B2 REFGND C1 REFGND C2 REFGND D1 REFGND D2

A7

A0

INTERFACE

BUSY

14

STATE MACHINE

INPUT

REG

0–1

14

INPUT

REG

2

14

INPUT

REG

5

14

INPUT

REG

6–7

14

/

14

/

m REG0–1

c REG0–1

14

/

m REG2

c REG2

14

/

m REG7

c REG7

14

/

m REG8–9

c REG8–9

14

/

14

/

14

/

14

/

14

/

14

/

14

/

14

/

Protected by U.S. Patent No. 5,969,657 and 6,823,416; other patents pending.

DAC REG

0–1

DAC REG

2

DAC REG

5

DAC REG

6–7

Figure 1.

14

×4

/

DAC 0–1

DAC 2

DAC 5

DAC 6–7

V

REF

2(+) V

2(–) REFGND A2

REF

VOUT 0 VOUT 1

VOUT 2

VOUT 3

VOUT 4 VOUT 5

VOUT 6 VOUT 7

VOUT 8

VOUT 31

05292-001

Rev. PrA

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AD5378 Preliminary Technical Data

TABLE OF CONTENTS

General Description..........................................................................3

Clear Function ............................................................................ 20

Specifications......................................................................................4

AC Characteristics........................................................................ 5

Timing Characteristics......................................................................6

Serial Interface.............................................................................. 6

Parallel Interface ........................................................................... 9

Absolute Maximum Ratings...........................................................11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions............................12

Typical Performance Characteristics ............................................15

Te r mi n ol o g y .....................................................................................17

Functional Description ...................................................................18

DAC Architecture—General..................................................... 18

Channel Groups.......................................................................... 18

Transfe r Fu nc tion ....................................................................... 18

V

Function ............................................................................. 19

BIAS

BUSY

FIFO vs. Non-FIFO Operation................................................. 21

BUSY

Power-On Reset Function ......................................................... 21

RESET

Increment/Decrement Function .............................................. 21

Interfaces...........................................................................................22

Parallel Interface ......................................................................... 22

Serial Interface............................................................................ 22

Data Decoding.................................................................................24

Address Decoding ...........................................................................25

Power Supply Decoupling ..............................................................26

Power-On .................................................................................... 26

Typical Application Ci r c u it ............................................................27

Outline Dimensions ........................................................................28

LDAC

and

Input Function ................................................................ 21

Input Function .............................................................. 21

Functions...................................................... 20

Reference Selection .................................................................... 19

Calibration................................................................................... 20

REVISION HISTORY

1/05—Revision PrA: Preliminary Version

Ordering Guide .......................................................................... 28

Rev. PrA | Page 2 of 28

Preliminary Technical Data AD5378

GENERAL DESCRIPTION

The AD5378 contains 32 14-bit DACs in one CSPBGA package. The AD5378 provides a bipolar output range determined by the voltages applied to the V

(+) and V

REF

(−) inputs. The maximum

REF

output voltage span is 17.5 V, corresponding to a bipolar output range of −8.75 V to +8.75 V, and is achieved with reference voltages of V

The AD5378 guarantees operation over a wide V

(−) = −3.5 V and V

REF

(+) = +5 V.

REF

SS/VDD

supply range from ±11.4 V to ±16.5 V. The output amplifier headroom requirement is 2.5 V operating with a load current of 1.5 mA, and 2 V operating with a load current of 0.5 mA.

The AD5378 contains a double-buffered parallel interface in which 14 data bits are loaded into one of the input registers under the control of the

WR, CS

, and DAC channel address pins, A0 to A7. It also has a 3-wire serial interface, which is compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.

Table 1. 40-Channel, Bipolar, Voltage Output DAC

Output

Model Resolution Analog Supplies

AD5379ABC 14 Bits ±11.4 V to ±16.5 V 40 ±3 108-Lead CSPBGA BC-108

Channels

Table 2. High Channel Count, Low Voltage, Single-Supply DACs

Output

Model Resolution AVDD Range

AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100 AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100 AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100 AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100 AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100 AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100 AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100 AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100 AD5383BST-5 12 Bits 4.5 V to 5.5 V 32 ±1 100-Lead LQFP ST-100 AD5383BST-3 12 Bits 2.7 V to 3.6 V 32 ±1 100-Lead LQFP ST-100 AD5390BST-5 14 Bits 4.5 V to 5.5 V 16 ±3 52-Lead LQFP ST-52 AD5390BCP-5 14 Bits 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP CP-64 AD5390BST-3 14 Bits 2.7 V to 3.6 V 16 ±4 52-Lead LQFP ST-52 AD5390BCP-3 14 Bits 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP CP-64 AD5391BST-5 12 Bits 4.5 V to 5.5 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-5 12 Bits 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP CP-64 AD5391BST-3 12 Bits 2.7 V to 3.6 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-3 12 Bits 2.7 V to 3.6 V 16 ±1 64-Lead LFCSP CP-64 AD5392BST-5 14 Bits 4.5 V to 5.5 V 8 ±3 52-Lead LQFP ST-52 AD5392BCP-5 14 Bits 4.5 V to 5.5 V 8 ±3 64-Lead LFCSP CP-64 AD5392BST-3 14 Bits 2.7 V to 3.6 V 8 ±4 52-Lead LQFP ST-52 AD5392BCP-3 14 Bits 2.7 V to 3.6 V 8 ±4 64-Lead LFCSP CP-64

Channels

The DAC outputs are updated when the DAC registers receive new data. All the outputs can be updated simultaneously by taking the

LDAC

input low. Each channel has a programmable

gain and an offset adjust register.

Each DAC output is gained and buffered on-chip with respect to an external REFGND input. The DAC outputs can also be

CLR

switched to REFGND via the

pin . Tab l e 1 a n d Ta b le 2 show the product portfolio for high channel count bipolar and unipolar voltage output DACs.

Package

Linearity Error (LSB)

Description

Package Description

Package Option

Rev. PrA | Page 3 of 28

AD5378

SPECIFICATIONS

VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; V 0 V; V

= 5 V; CL = 200 pF to GND; RL = 11 kΩ to 3 V; gain = 1; offset = 0 V; all specifications T

BIAS

Table 3.

Parameter A Version

1

Unit Test Conditions/Comments

ACCURACY

Resolution 14 Bits Relative Accuracy ±3 LSB max −40°C to +85°C ±2.5 LSB max 0°C to 70°C Differential Nonlinearity −1/+1.5 LSB max Guaranteed monotonic by design over temperature Zero-Scale Error ±12 mV max −40°C to +85°C ±5 mV max 0°C to 70°C Full-Scale Error ±12 mV max −40°C to +85°C ±8 mV max 0°C to 70°C Gain Error ±8 mV max −40°C to +85°C ±1/±5 mV typ/max 0°C to 70°C VOUT Temperature Coefficient 5 ppm FSR/°C typ Includes linearity, offset, and gain drift; see Figure 11 DC Crosstalk

2

0.5 mV max Typically 100 µV

REFERENCE INPUTS2

V

(+) DC Input Impedance 1 MΩ min Typically 100 MΩ

REF

V

(−) DC Input Impedance 8 kΩ min Typically 12 kΩ

REF

V

(+) Input Current ±10 µA max Per input; typically ±30 nA

REF

V

(+) Range 1.5/5 V min/max ±2% for specified operation

REF

V

(−) Range −3.5/0 V min/max ±2% for specified operation

REF

REFGND INPUTS2

DC Input Impedance 80 kΩ min Typically 120 kΩ Input Range ±0.5 V min/max

OUTPUT CHARACTERISTICS2

Output Voltage Range VSS + 2/VSS + 2.5 V min I V

− 2/VDD − 2.5 V max I

DD

Short-Circuit Current 15 mA max Load Current ±1.5 mA max Capacitive Load 2200 pF max DC Output Impedance 1 Ω max

DIGITAL INPUTS JEDEC-compliant

Input High Voltage 1.7 V min VCC = 2.7 V to 3.6 V

2.0 V min V Input Low Voltage 0.8 V max VCC = 2.7 V to 5.5 V Input Current (with pull-up/pull-down) ±8 µA max Input Current (no pull-up/pull-down) ±1 µA max All other digital input pins Input Capacitance2 10 pF max

DIGITAL OUTPUTS (BUSY, SDO)

Output Low Voltage 0.5 V max Sinking 200 µA Output High Voltage (SDO) VCC − 0.5 V min Sourcing 200 µA High Impedance Leakage Current −70 µA max SDO only High Impedance Output Capacitance2 10 pF typ

(+) = +5 V; V

REF

(−) = −3.5 V; AGND = DGND = REFGND =

REF

to T

MIN

= ±0.5 mA/±1.5 mA

LOAD

= ±0.5 mA/±1.5 mA

LOAD

= 3.6 V to 5.5 V

CC

PAR, FIFOEN, and RESET pins only

SER/

, unless otherwise noted.

MAX

Rev. PrA | Page 4 of 28

Preliminary Technical Data AD5378

Parameter A Version

1

Unit Test Conditions/Comments

POWER REQUIREMENTS

V

CC

V

DD

V

SS

2.7/5.5 V min/max

8.5/16.5 V min/max

−3/−16.5 V min/max

Power Supply Sensitivity2

∆ Full Scale/∆ V ∆ Full Scale/∆ V ∆ Full Scale/∆ V

I

CC

I

DD

I

SS

DD

SS

CC

−75 dB typ

−90 dB typ 5 mA max VCC = 5.5 V, VIH = VCC, VIL = GND 28 mA max Outputs unloaded; typically 20 mA 23 mA max Outputs unloaded; typically 15 mA

Power Dissipation

Power Dissipation Unloaded (P) 850 mW max VDD = 16.5 V, VSS = −16.5 V Power Dissipation Loaded (P Junction Temperature 130 °C max TJ = TA + P

) 2000 mW max P

TOTAL

= P + Σ(VDD − VO) × I

TOTAL

× θ

TOTAL

+ Σ(VO − VSS) × I

SOURCE

3

J

SINK

1

Temperature range for the A version: −40°C to +85°C. Typical specifications are at 25°C.

2

Guaranteed by design and characterization; not production tested.

3

Where θJ represents the package thermal impedance.

AC CHARACTERISTICS

VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; V AGND = DGND = REFGND = 0 V; V

= 5 V; CL = 220 pF; RL = 11 kΩ to 3 V; gain = 1; offset = 0 V.

BIAS

Table 4.

Parameter A Version

1

Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 20 µs typ Full-scale change to ±1/2 LSB 30 µs max

Slew Rate 1 V/µs typ Digital-to-Analog Glitch Energy 20 nV-s typ Glitch Impulse Peak Amplitude 15 mV max Channel-to-Channel Isolation 100 dB typ V DAC-to-DAC Crosstalk 40 nV-s typ

10 nV-s typ Between DACs from different groups Digital Crosstalk 0.1 nV-s typ Digital Feedthrough 1 nV-s typ Effect of input bus activity on DAC output under test Output Noise Spectral Density @ 1 kHz 350 nV/(Hz)

1

Guaranteed by design and characterization; not production tested.

(+) = +5 V; V

REF

1/2

typ V

(−) = −3.5 V;

REF

DAC latch contents alternately loaded with all 0s and all 1s

(+) = 2 V p-p, (1 V

REF

) 1 kHz, V

BIAS

(−) = −1 V

REF

See the Terminology section; between DACs inside a group

REF

(+) = V

(−) = 0 V

REF

Rev. PrA | Page 5 of 28

AD5378

TIMING CHARACTERISTICS

SERIAL INTERFACE

VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; V AGND = DGND = REFGND = 0 V; V

= 5 V, FIFOEN = 0 V; all specifications T

BIAS

Table 5.

Parameter

t

1

t

2

t

3

t

4

t

5

4

t

6

t

7

t

8

t

9

, 5

4

t

10

t

11

4

t

12

t

13

t

14

t

15

t

16

t

17

t

18

t

19

6, 7

t

20

7

t

21

7

t

22

t

237

5

t

30 ns min

24

t

25

t26

1, , 2 3

Limit at T

MIN

, T

MAX

Unit Description

20 ns min SCLK Cycle Time. 8 ns min SCLK High Time. 8 ns min SCLK Low Time. 10 ns min

15 ns min 25 ns min 10 ns min 5 ns min Data Setup Time.

4.5 ns min Data Hold Time. 30 ns max 330 ns max

20 ns min 20 ns min 150 ns typ 0 ns min 100 ns min 20/30 µs typ/max DAC Output Settling Time. 10 ns min 350 ns max 25 ns max SCLK Rising Edge to SDO Valid. 5 ns min 5 ns min 20 ns min

10 ns min 120 µs max

REF

SYNC Falling Edge to SCLK Falling Edge Setup Time. 24th SCLK Falling Edge to Minimum Minimum

24th SCLK Falling Edge to BUSY Pulse Width Low (Single-Channel Update). See Table 11. 24th SCLK Falling Edge to LDAC Pulse Width Low. BUSY Rising Edge to DAC Output Response Time. BUSY Rising Edge to LDAC Falling Edge. LDAC Falling Edge to DAC Output Response Time.

CLR Pulse Width Low. CLR/RESET Pulse Activation Time.

SCLK Falling Edge to SYNC Rising Edge to SCLK Rising Edge. SYNC Rising Edge to LDAC Falling Edge. SYNC Rising Edge to BUSY Falling Edge. RESET Pulse Width Low. RESET Time Indicated by BUSY Low.

(+) = +5 V; V

to T

MIN

SYNC Low Time. SYNC High Time.

(−) = −3.5 V;

REF

, unless otherwise noted.

MAX

SYNC Falling Edge.

BUSY Falling Edge.

LDAC Falling Edge.

SYNC Rising Edge.

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.

3

See and . Figure 4 Figure 5

4

Standalone mode only.

5

This is measured with the load circuit of . Figure 2

6

This is measured with the load circuit of . Figure 3

7

Daisy-chain mode only.

V

CC

2.2kΩ

R

TO

OUTPUT

CL50pF

Figure 2. Load Circuit for

L

BUSY

Timing Diagram

V

OL

05292-002

OUTPUT

Rev. PrA | Page 6 of 28

I

OL

V

(min) + VOL(max)

OH

2

I

OH

TO

200µA

CL 50pF

200µA

Figure 3. Load Circuit for SDO Timing Diagram

(Serial Interface, Daisy- Chain Mode)

05292-003

Preliminary Technical Data AD5378

t

1

SCLK

SYNC

BUSY

LDAC

VOUT

LDAC

VOUT

DIN

1 2 24 24

t

3

t

4

t

7

DB23 DB0

1

2

t8t

t

6

9

t

18

t

2

t

5

t

10

t

12

t

11

t

13

t

17

t

14

t

15

t

13

t

17

16

CLR

t

19

VOUT

1

LDAC ACTIVE DURING BUSY.

2

LDAC ACTIVE AFTER BUSY.

t

25

RESET

VOUT

BUSY

t

19

t

26

05292-004

Figure 4. Serial Interface Timing Diagram (Standalone Mode)

Rev. PrA | Page 7 of 28

AD5378

t

1

SCLK

SYNC

DIN

SDO

LDAC

BUSY

t

7

t

4

t8t

INPUT WORD FOR DAC N

3

9

24 48

t

2

D0 D0'D23'D23

INPUT WORD FOR DAC N+1

t

20

D23 D0

INPUT WORD FOR DAC NUNDEFINED

t

21

22

t13t

23

t

24

t

11

05292-005

Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)

Rev. PrA | Page 8 of 28

Preliminary Technical Data AD5378

PARALLEL INTERFACE

VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; AGND = DGND = DUTGND = 0 V; V

(−) = −3.5 V, FIFOEN = 0 V; all specifications T

V

REF

MIN

to T

, unless otherwise noted.

MAX

Table 6.

Parameter

t

0

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

4

t

10

4

t

11

t

12

t

13

t

14

4

t

15

t

16

t

17

t

18

t

19

t

20

t

21

t

22

t

23

1, , 2 3

Limit at T

4.5 ns min

4.5 ns min 10 ns min 10 ns min 0 ns min 0 ns min

4.5 ns min

4.5 ns min 20 ns min 240 ns min 0/30 ns min/max 330 ns max 0 ns min 30 ns min 20 ns min 150 ns typ 20 ns min 0 ns min 100 ns typ

MIN

to T

MAX

Unit Description

REG0, REG1, Address to REG0, REG1, Address to CS Pulse Width Low. WR Pulse Width Low. CS to WR Falling Edge Setup Time. WR to CS Rising Edge Hold Time.

WR Rising Edge Setup Time.

Data to

WR Rising Edge Hold Time.

Data to WR Pulse Width High. Minimum

WR Cycle Time (Single-Channel Write). WR Rising Edge to BUSY Falling Edge. BUSY Pulse Width Low (Single-Channel Update). See Table 11. BUSY Rising Edge to WR Rising Edge. WR Rising Edge to LDAC Falling Edge. LDAC Pulse Width Low. BUSY Rising Edge to DAC Output Response Time. LDAC Rising Edge to WR Rising Edge. BUSY Rising Edge to LDAC Falling Edge. LDAC Falling Edge to DAC Output Response Time.

WR Rising Edge Setup Time. WR Rising Edge Hold Time.

20/30 µs typ/ max DAC Output Settling Time. 10 ns min

350 ns max 10 ns min 120 µs max

CLR Pulse Width Low. CLR/RESET Pulse Activation Time. RESET Pulse Width Low. RESET Time Indicated by BUSY Low.

(+) = +5 V;

REF

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.

3

See . Figure 6

4

Measured with load circuit in Figure 2.

Rev. PrA | Page 9 of 28

Analog Devices AD5378 pra Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

SPECIFICATIONS

AC CHARACTERISTICS

TIMING CHARACTERISTICS

SERIAL INTERFACE

PARALLEL INTERFACE