32-channel DAC in a 64-lead LQFP
AD5372/AD5373
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage range of −4 V to +8 V
Multiple, independent output voltage spans available
System calibration function allowing user-programmable
off
set and gain
Channel grouping and addressing features
Thermal shutdown function
DSP/microcontroller-compatible serial interface
SPI serial interface
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
1
guaranteed monotonic to 16/14 bits
V
D
CONTROL
REGISTER
SERIAL
INTERFACE
STATE
MACHINE
V
C
D
C
n
AGND DGND
SS
D
n = 16 FOR AD5372
n = 14 FOR AD5373
8
A/B SELECT
REGISTE R
n
X1 REGISTER
n
M REGISTER
n
C REGISTER
nnnnn
X1 REGISTER
n
M REGISTER
n
C REGISTER
88
A/B SELECT
REGISTE R
n
X1 REGISTER
n
M REGISTER
n
C REGISTER
nnnnn
X1 REGISTER
n
M REGISTER
n
C REGISTER
8
nnn
n
n
n
n
nnn
n
n
n
n
FUNCTIONAL BLOCK DIAGRAM
TO
MUX 2s
A/B
MUX
A/B
MUX
TO
MUX 2s
A/B
MUX
A/B
MUX
X2A REG ISTER
X2B REG ISTER
X2A REG ISTER
X2B REG ISTER
X2A REG ISTER
X2B REG ISTER
X2A REG ISTER
X2B REG ISTER
Serial Input, Voltage Output DAC
AD5372/AD5373
2.5 V to 5.5 V JEDEC-compliant digital levels
Digital reset (
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
LDAC
14
OFS0
REGISTER
DAC 0
2
REGISTER
MUX
DAC 7
2
REGISTER
MUX
14
OFS1
REGISTER
DAC 0
2
REGISTER
MUX
DAC 7
2
REGISTER
MUX
RESET
n
n
n
n
)
OFFSET
DAC 0
DAC 0
DAC 7
OFFSET
DAC 1
DAC 0
DAC 7
BUFFER
BUFFER
BUFFER
BUFFER
GROUP 0
OUTPUT BU FFER
AND POWER-
DOWN CONTROL
OUTPUT B UFFER
AND POWER-
DOWN CONTROL
GROUP 1
OUTPUT BU FFER
AND POWER-
DOWN CONTROL
OUTPUT B UFFER
AND POWER-
DOWN CONTROL
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
SIGG ND0
VREF1
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
AD5372/
AD5373
GROUP 2 TO GROUP 3
ARE ID ENTICA L TO GRO UP 1
VREF1 SUPPLI ES
GROUP 1 TO GROUP 3
SIGGN D2
Figure 1.
1
Protected by U.S. Patent No. 5,969,657; other patents pending.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Changes to Table 3.............................................................................6
Changes to AD5373 Transfer Function Section......................... 16
Changes to Calibration Section.................................................... 17
Changes to Table 8.......................................................................... 18
Changes to Register Update Rates Section.................................. 20
Changes to Ordering Guide.......................................................... 25
8/07—Revision 0: Initial Version
Rev. B | Page 2 of 24
AD5372/AD5373
www.BDTIC.com/ADI
GENERAL DESCRIPTION
The AD5372/AD5373 contain 32 16-/14-bit DACs in a single
64-lead LQFP. The devices provide buffered voltage outputs with
a nominal span of 4× the reference voltage. The gain and offset
of each DAC can be independently trimmed to remove errors. For
even greater flexibility, the device is divided into four groups of
eight DACs. Two offset DACs allow the output range of the groups
to be altered. Group 0 can be adjusted by Offset DAC 0, and
Group 1 to Group 3 can be adjusted by Offset DAC 1.
The AD5372/AD5373 offer guaranteed operation over a wide
pply range: V
su
16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
AD536016 4 × V
AD536114 4 × V
AD536216 4 × V
AD536314 4 × V
AD537016 4 × V
AD537114 4 × V
AD5372 16 4 × V
AD5373 14 4 × V
AD537814 ±8.75 V 32 ±3
AD537914 ±8.75 V 40 ±3
from −16.5 V to −4.5 V and VDD from 9 V to
SS
(20 V) 16 ±4
REF
(20 V) 16 ±1
REF
(20 V) 8 ±4
REF
(20 V) 8 ±1
REF
(12 V) 40 ±4
REF
(12 V) 40 ±1
REF
(12 V) 32 ±4
REF
(12 V) 32 ±1
REF
The AD5372/AD5373 have a high speed serial interface that is
mpatible with SPI, QSPI™, MICROWIRE™, and DSP inter-
co
face standards and can handle clock speeds of up to 50 MHz.
The DAC registers are updated on reception of new data. All
t
he outputs can be updated simultaneously by taking the
input low. Each channel has a programmable gain and an offset
adjust register.
Each DAC output is gained and buffered on chip with respect
an external SIGGNDx input. The DAC outputs can also be
to
switched to SIGGNDx via the
CLR
pin.
LDAC
Rev. B | Page 3 of 24
AD5372/AD5373
www.BDTIC.com/ADI
SPECIFICATIONS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V;
= open circuit; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T
C
L
unless otherwise noted.
MIN
to T
MAX
,
Table 2.
AD5372
Parameter
ACCURACY
Resolution 16 14 Bits
Integral Nonlinearity (INL) ±4 ±1 LSB max
Differential Nonlinearity (DNL) ±1 ±1 LSB max
Zero-Scale Error ±10 ±10 mV max Before calibration
Full-Scale Error ±10 ±10 mV max Before calibration
Gain Error 0.1 0.1 % FSR Before calibration
Zero-Scale Error
Full-Scale Error
Span Error of Offset DAC ±35 ±35 mV max See the Offset DACS section for details
VOUTx Temperature Coefficient 5 5 ppm FSR/°C typ Includes linearity, offset, and gain drift
DC Crosstalk2 100 100 μV max
REFERENCE INPUTS (VREF0, VREF1)
VREFx Input Current ±10 ±10 μA max Per input; typically ±30 nA
VREFx Range 2/5 2/5 V min/V max ±2% for specified operation
SIGGND INPUTS (SIGGND0 TO SIGGND3)2
DC Input Impedance 50 50 kΩ min Typically 55 kΩ
Input Range ±0.5 ±0.5 V min/V max
SIGGNDx Gain 0.995/1.005 0.995/1.005 min/max
OUTPUT CHARACTERISTICS
Output Voltage Range VSS + 1.4 VSS + 1.4 V min I
V
Nominal Output Voltage Range −4 to +8 −4 to +8 V min/V max
Short-Circuit Current 15 15 mA max VOUTx to DVCC, VDD, or VSS
Load Current ±1 ±1 mA max
Capacitive Load 2200 2200 pF max
DC Output Impedance 0.5 0.5 Ω max
DIGITAL INPUTS JEDEC compliant
Input High Voltage 1.7 1.7 V min DVCC = 2.5 V to 3.6 V
2.0 2.0 V min DVCC = 3.6 V to 5.5 V
Input Low Voltage 0.8 0.8 V max DVCC = 2.5 V to 5.5 V
Input Current ±1 ±1 μA max
CLR High Impedance Leakage Current
Input Capacitance
DIGITAL OUTPUTS (SDO, BUSY)
Output Low Voltage 0.5 0.5 V max Sinking 200 μA
Output High Voltage (SDO) DVCC − 0.5 DVCC − 0.5 V min Sourcing 200 μA
SDO High Impedance Leakage Current ±5 ±5 μA max
High Impedance Output Capacitance210 10 pF typ
2
2
2
2
2
B Version
1 1 LSB typ After calibration
1 1 LSB typ After calibration
±20 ±20 μA max
10 10 pF max
1
AD53731
B Version
− 1.4 VDD − 1.4 V max I
DD
Unit Test C
onditions/Comments
Guaranteed monotonic by design over
ature
temper
Typically 20 μV; measured channel at midscale,
le change on any other channel
full-sca
= 1 mA
LOAD
= 1 mA
LOAD
Excluding CLR
pin
2
Rev. B | Page 4 of 24
AD5372/AD5373
www.BDTIC.com/ADI
Parameter
AD5372
B Version
1
AD53731
B Version Unit Test Conditions/Comments
2
POWER REQUIREMENTS
DVCC 2.5/5.5 2.5/5.5 V min/V max
VDD 9/16.5 9/16.5 V min/V max
VSS −16.5/−4.5 −16.5/−4.5 V min/V max
Power Supply Sensitivity
2
∆Full Scale/∆VDD −75 −75 dB typ
∆Full Scale/∆VSS −75 −75 dB typ
∆Full Scale/∆DVCC −90 −90 dB typ
DICC 2 2 mA max DVCC = 5.5 V, VIH = DVCC, VIL = GND
IDD 16 16 mA max Outputs unloaded, DAC outputs = 0 V
18 18 mA max Outputs unloaded, DAC outputs = full scale
ISS −16 −16 mA max Outputs unloaded, DAC outputs = 0 V
−18 −18 mA max Outputs unloaded, DAC outputs = full scale
Power-Down Mode Bit 0 in the control register is 1
DICC 5 5 μA typ
IDD 35 35 μA typ
ISS −35 −35 μA typ
Power Dissipation (Unloaded) 250 250 mW typ VSS = −8 V, VDD = 9.5 V, DVCC = 2.5 V
Junction Temperature
1
Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.
2
Guaranteed by design and characterization; not production tested.
3
θJA represents the package thermal impedance.
3
130 130 °C max TJ = TA + P
TOTAL
× θJA
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M),
offset (C), and DAC offset registers at default values; all specifications T
Table 3.
Parameter B Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
1
Output Voltage Settling Time 20 μs typ Full-scale change
30 μs max DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate 1 V/μs typ
Digital-to-Analog Glitch Energy 5 nV-s typ
Glitch Impulse Peak Amplitude 10 mV max
Channel-to-Channel Isolation 100 dB typ VREF0, VREF1 = 2 V p-p, 1 kHz
DAC-to-DAC Crosstalk 10 nV-s typ
Digital Crosstalk 0.2 nV-s typ
Digital Feedthrough 0.02 nV-s typ Effect of input bus activity on DAC output under test
Output Noise Spectral Density @ 10 kHz 250 nV/√Hz typ VREF0 = VREF1 = 0 V
1
Guaranteed by design and characterization; not production tested.
MIN
to T
, unless otherwise noted.
MAX
Rev. B | Page 5 of 24
AD5372/AD5373
T
www.BDTIC.com/ADI
TIMING CHARACTERISTICS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF to GND;
R
= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T
L
MIN
to T
, unless otherwise noted.
MAX
Table 4. SPI Interface
Parameter
t
1
1 , 2 , 3
Limit at T
MIN
, T
Unit Description
MAX
20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 11 ns min
t
5
20 ns min
t6 10 ns min
t
7
5 ns min Data setup time
falling edge to SCLK falling edge setup time
SYNC
Minimum SYNC
th
SCLK falling edge to SYNC rising edge
24
high time
t8 5 ns min Data hold time
4
t
9
t10 1/1.5 μs typ/μs max
42 ns max
rising edge to BUSY falling edge
SYNC
pulse width low (single-channel update); see Table 9
BUSY
t11 600 ns max Single-channel update cycle time
t12 20 ns min
t13 10 ns min
t14 3 μs max
t15 0 ns min
t16 3 μs max
rising edge to LDAC falling edge
SYNC
pulse width low
LDAC
rising edge to DAC output response time
BUSY
rising edge to LDAC falling edge
BUSY
falling edge to DAC output response time
LDAC
t17 20/30 μs typ/μs max DAC output settling time
t18 140 ns max
t19 30 ns min
t20 400 μs max
t21 270 ns min
5
t
22
25 ns max SCLK rising edge to SDO valid
t23 80 ns max
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
See Figure 4 and Figure 5.
4
t9 is measured with the load circuit shown in Figure 2.
5
t22 is measured with the load circuit shown in Figure 3.
/RESET pulse activation time
CLR
pulse width low
RESET
time indicated by BUSY low
RESET
Minimum SYNC
rising edge to BUSY falling edge
RESET
high time in readback mode
50pF
C
200µAI
L
200µAI
DV
CC
R
L
TO
OUTPUT
PIN
Figure 2. Load Circuit for
2.2kΩ
C
L
50pF
BUSY
Timing Diagram
V
OL
05815-002
Rev. B | Page 6 of 24
O OUTPUT
PIN
Figure 3. Load Circuit for SDO Timing Diagram
OL
OH
VOH (MIN) – VOL (MAX)
2
5815-003
AD5372/AD5373
V
V
www.BDTIC.com/ADI
t
1
SCLK
SYNC
BUSY
LDAC
OUTx
LDAC
OUTx
SDI
1
1
2
2
1
2
t
3
t
4
t
5
t
7
t
8
DB23
24
t
2
t
6
DB0
t
9
t
1
t
11
t
10
12
t
13
24
t
17
t
14
t
15
t
13
t
17
t
16
CLR
t
18
VOUTx
t
19
RESET
VOUTx
BUSY
1
LDAC ACTIVE DURING BUSY.
2
LDAC ACTIVE AFTER BUSY.
t
23
t
18
t
20
05815-004
Figure 4. SPI Write Timing
Rev. B | Page 7 of 24
AD5372/AD5373
C
www.BDTIC.com/ADI
SCLK
SYN
SDI
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
t
22
DB0DB23DB23
LSB FROM PREVIOUS WRITE
t
21
NOP CONDITI ON
DB0
DB23DB15
SELECTED REG ISTER DATA CL OCKED OUT
48
DB0
DB0
05815-005
Figure 5. SPI Read Timing
OUTPUT
VOLTAGE
8V
ACTUAL
TRANSFER
FUNCTION
IDEAL
TRANSFER
FUNCTION
FULL-SCALE
ERROR
+
ZERO-SCALE
ERROR
016383
–4V
DAC CODE
ZERO-SCALE
ERROR
Figure 6. DAC Tran
sfer Function
05815-006
Rev. B | Page 8 of 24
AD5372/AD5373
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
60 mA do not cause SCR latch-up.
Table 5.
Parameter Rating
VDD to AGND −0.3 V to +17 V
VSS to AGND −17 V to +0.3 V
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to DVCC + 0.3 V
Digital Outputs to DGND −0.3 V to DVCC + 0.3 V
VREF0, VREF1 to AGND −0.3 V to +5.5 V
VOUT0 through VOUT31 to AGND VSS − 0.3 V to VDD + 0.3 V
SIGGNDx to AGND −1 V to +1 V
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range (TA)
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 130°C
θJA Thermal Impedance
64-Lead LQFP 45.5°C/W
Reflow Soldering
Peak Temperature 230°C
Time at Peak Temperature 10 sec to 40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 9 of 24
AD5372/AD5373
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VOUT26
VOUT25
VOUT24
AGND
DGND
DVCCSDO
SDI
SCLK
DVCCDGND
VOUT7
CLR
LDAC
64 63 62 61 60 59 58 57
56 55
54 53 52 51 50 49
SYNC
VOUT6
1
RESET
2
BUSY
3
VOUT27
VOUT28
VOUT29
VOUT30
VOUT31
NC
NC
NC
NC
NC
NC
NC
V
4
5
6
7
8
9
10
11
12
13
14
15
16
DD
SIGGND3
NC = NO CONNECT
PIN 1
INDICATOR
AD5372/AD5373
TOP VIEW
(Not to Scale)
17 18 19 202122 23 24
SS
NC
V
NC
VREF1
VOUT8
VOUT9
VOUT10
25 26 27 28 29 30 31 32
VOUT11
VOUT12
VOUT13
VOUT15
VOUT14
SIGGND1
VOUT16
48
VOUT5
47
VOUT4
46
SIGGND0
45
VOUT3
44
VOUT2
43
VOUT1
42
VOUT0
41
VREF0
40
VOUT23
39
VOUT22
38
VOUT21
37
VOUT20
36
V
SS
V
35
DD
34
SIGGND2
33
VOUT19
VOUT17
VOUT18
05815-007
Figure 7. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
42 to 45, 47 to 50, 21
to 24, 26 to 33, 37 to
RESET
BUSY
VOUT0 to
VOUT
31
40, 60 to 62, 3, 5 to 8
4 SIGGND3 Reference Ground for DAC 24 to DAC 31. VOUT24 to VOUT31 are referenced to this voltage.
9 to 15, 19, 20 NC No Connect.
16, 35 VDD Positive Analog Power Supply; 9 V to 16.5 V for specified performance. These pins should be decoupled with
17, 36 VSS Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins should be decoupled
18 VREF1 Reference Input for DAC 8 to DAC 31. This reference voltage is referred to AGND.
25 SIGGND1 Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage.
34 SIGGND2 Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage.
41 VREF0 Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND.
46 SIGGND0 Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage.
51, 58 DGND Ground for All Digital Circuitry. The DGND pins should be connected to the DGND plane.
52, 57 DVCC Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF
53
SYNC
54 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at
55 SDI Serial Data Input. Data must be valid on the falling edge of SCLK.
56 SDO Serial Data Output. CMOS output. SDO can be used for readback. Data is clocked out on SDO on the rising
59 AGND Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane.
63
64
LDAC
CLR
Digital Reset Input.
Digital Input/Open-Drain Output.
BUSY
is open drain when an output. See the
BUSY
and
LDAC
Functions
section for more information.
DAC Outputs. Buffered analog outputs for each of the 32 DAC channels. Each analog output is capable of
driving an output load of 10 kΩ to ground. Typical output impedance of these amplifiers is 0.5 Ω.
0.1 μF ceramic capacitors and 10 μF capacitors.
with 0.1 μF ceramic capacitors and 10 μF capacitors.
capacitors.
Active Low Input. This is the frame synchronization signal for the serial interface.
clock speeds up to 50 MHz.
edge of SCLK and is valid on the falling edge of SCLK.
Load DAC Logic Input (Active Low). See the
BUSY
and
LDAC
Functions section for more information.
Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for more information.
Rev. B | Page 10 of 24
AD5372/AD5373
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
2
1
0
INL (LSB)
–1
–2
065535
163843276849152
DAC CODE
Figure 8. Typical AD5372 INL Plot
1.0
0.5
VDD = +15V
= –15V
V
SS
= +5V
DV
CC
VREFx = +3V
05815-008
0.0050
0.0025
0
AMPLITUDE (V)
–0.0025
–0.0050
05
1234
TIME (µs)
TA = 25°C
V
= –15V
SS
V
= +15V
DD
VREFx = +4.096V
05815-011
Figure 11. Digital Crosstalk
1.0
0.5
0
INL ERROR (LSB)
–0.5
–1.0
08
204060
TEMPERATURE (° C)
05815-009
0
0
DNL (LSB)
–0.5
–1.0
065535
Figure 9. Typical INL Error vs. Temperature
0
TA = 25°C
= –15V
V
SS
= +15V
V
DD
VREFx = +4. 096V
–0.01
AMPLITUDE ( V)
–0.02
024681
Figure 10. Analog Crosstalk Due to
TIME (µs)
LDAC
0
5815-010
600
500
400
300
200
OUTPUT NOISE (nV/√Hz)
100
0
05
163843276849152
DAC CODE
Figure 12. Typical AD5372 DNL Plot
1234
FREQUENCY (Hz)
Figure 13. Output Noise Spectral Density
05815-012
05815-013
Rev. B | Page 11 of 24
AD5372/AD5373
www.BDTIC.com/ADI
0.50
0.45
0.40
(mA)
CC
DI
0.35
0.30
VSS = –12V
V
= +12V
DD
VREFx = +3V
DVCC = +5.5V
DV
= +2.5V
CC
DV
CC
= +3.6V
14
12
10
8
6
NUMBER OF UNITS
4
2
V
SS
V
DD
T
A
= –15V
= +15V
= 25°C
0.25
–4080
–200206040
TEMPERATURE (°C)
Figure 14. DI
13.5
13.0
(mA)
12.5
SS
/I
DD
I
12.0
VSS= –12V
VDD = +12V
VREFx = +3V
11.5
–200206040
–4080
Figure 15. I
vs. Temperature
CC
I
DD
I
SS
TEMPERATURE (°C)
vs. Temperature
DD/ISS
05815-014
05815-015
0
12.612.813.0
Figure 16. Typical I
14
12
10
8
6
NUMBER OF UNITS
4
2
0
0.300.350.40
IDD (mA)
DD
DICC (mA)
13.213.4
Distribution
0.450.50
DV
T
A
CC
= 25°C
Figure 17. Typical DI
Distribution
CC
05815-016
= 5V
05815-017
Rev. B | Page 12 of 24
AD5372/AD5373
www.BDTIC.com/ADI
TERMINOLOGY
Integral Nonlinearity (INL)
Integral nonlinearity, or endpoint linearity, is a measure of
t
he maximum deviation from a straight line passing through
the endpoints of the DAC transfer function. It is measured
after adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
cha
nge and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when
al
l 0s are loaded into the DAC register. Zero-scale error is a
measure of the difference between VOUT (actual) and VOUT
(ideal), expressed in millivolts, when the channel is at its minimum value. Zero-scale error is mainly due to offsets in the
output amplifier.
Full-Scale Error
Full-scale error is the error in the DAC output voltage when
al
l 1s are loaded into the DAC register. Full-scale error is a
measure of the difference between VOUT (actual) and VOUT
(ideal), expressed in millivolts, when the channel is at its maximum value. Full-scale error does not include zero-scale error.
Gain Error
Gain error is the difference between full-scale error and
zer
o-scale error. It is expressed as a percentage of the full-
scale range (FSR).
Gain Error = F
VOUT Temperature Coefficient
The VOUT temperature coefficient includes output error
co
ntributions from linearity, offset, and gain drift.
DC Output Impedance
DC output impedance is the effective output source resistance.
I
t is dominated by package lead resistance.
DC Crosstalk
The DAC outputs are buffered by op amps that share common
V
and VSS power supplies. If the dc load current changes in
DD
one channel (due to an update), this change can result in a
further dc change in one or more channel outputs. This effect is
more significant at high load currents and is reduced as the load
currents are reduced. With high impedance loads, the effect is
virtually immeasurable. Multiple V
provided to minimize dc crosstalk.
ull-Scale Error − Zero-Scale Error
and VSS terminals are
DD
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
t
he output of a DAC to settle to a specified level for a full-scale
input change.
Digital-to-Analog Glitch Energy
Digital-to-analog glitch energy is the amount of energy that is
i
njected into the analog output at the major code transition. It is
specified as the area of the glitch in nV-s. It is measured by
toggling the DAC register data between 0x7FFF and 0x8000
(AD5372) or 0x1FFF and 0x2000 (AD5373).
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
s
ignal from the reference input of one DAC that appears at the
output of another DAC operating from another reference. It is
expressed in decibels and measured at midscale.
DAC-to-DAC C rosst a l k
DAC-to-DAC crosstalk is the glitch impulse that appears at
t
he output of one converter due to both the digital change
and subsequent analog output change at another converter. It
is specified in nV-s.
Digital Crosstalk
Digital crosstalk is defined as the glitch impulse transferred to
t
he output of one converter due to a change in the DAC register
code of another converter. It is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity
o
n the digital inputs of the device can be capacitively coupled
both across and through the device to appear as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.
Output Noise Spectral Density
Output noise spectral density is a measure of internally
gen
erated random noise. Random noise is characterized as a
spectral density (voltage per √Hz). It is measured by loading
all DACs to midscale and measuring noise at the output. It is
measured in nV/√Hz.
Rev. B | Page 13 of 24
AD5372/AD5373
www.BDTIC.com/ADI
THEORY OF OPERATION
DAC ARCHITECTURE
The AD5372/AD5373 contain 32 DAC channels and 32 output
amplifiers in a single package. The architecture of a single DAC
channel consists of a 16-bit (AD5372) or 14-bit (AD5373)
resistor-string DAC followed by an output buffer amplifier.
The resistor-string section is simply a string of resistors (of
equal value) from VREF0 or VREF1 to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit
(AD5372) or 14-bit (AD5373) binary digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off before being fed into the output amplifier.
Table 7. AD5372/AD5373 Registers
Word Length
Register Name
X1A (Group) (Channel) 16 (14) Input Data Register A, one for each DAC channel.
X1B (Group) (Channel) 16 (14) Input Data Register B, one for each DAC channel.
M (Group) (Channel) 16 (14) Gain trim registers, one for each DAC channel.
C (Group) (Channel) 16 (14) Offset trim registers, one for each DAC channel.
X2A (Group) (Channel) 16 (14)
X2B (Group) (Channel) 16 (14)
DAC (Group) (Channel)
OFS0 14 Offset DAC 0 data register: sets offset for Group 0.
OFS1 14 Offset DAC 1 data register: sets offset for Group 1 to Group 3.
Control 3
A/B Select 0 8
A/B Select 1 8
A/B Select 2 8
A/B Select 3 8
in Bits Description
Output Data Register A, one for each DAC channel. These registers store the final, calibrated
AC data after gain and offset trimming. They are not readable or directly writable.
D
Output Data Register B, one for each DAC channel. These registers store the final, calibrated
AC data after gain and offset trimming. They are not readable or directly writable.
D
Data registers from which the DACs take their final input data. The DAC registers are updated
om the X2A or X2B registers. They are not readable or directly writable.
fr
Bit 2 = A
Bit 1 = enable thermal shutdown.
Bit 0 = software power-down.
Each bit in this register determines whether a D
or Register X2B (0 = X2A, 1 = X2B).
Each bit in this register determines whether a D
or Register X2B (0 = X2A, 1 = X2B).
Each bit in this register determines whether a D
or Register X2B (0 = X2A, 1 = X2B).
Each bit in this register determines whether a D
or Register X2B (0 = X2A, 1 = X2B).
/B.
0 = global selection of X1A input data registers.
1 = globa
0 = disable thermal shutdown.
1 = enabl
0 = software power-up.
1 = software power-down.
l selection of X1B input data registers.
e thermal shutdown.
The output amplifier multiplies the DAC output voltage by 4.
The nominal output span is 12 V with a 3 V reference and 20 V
with a 5 V reference.
CHANNEL GROUPS
The 32 DAC channels of the AD5372/AD5373 are arranged into
four groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 to Group 3 derive
their reference voltage from VREF1. Each group has its own
signal ground pin.
Register Name AD5372 Default Value AD5373 Default Value
X1A, X1B 0x5554 0x1555
M 0xFFFF 0x3FFF
C 0x8000 0x2000
OFS0, OFS1 0x1555 0x1555
Control 0x00 0x00
A/B Select 0 to A/B Select 3 0x00 0x00
Rev. B | Page 14 of 24
AD5372/AD5373
www.BDTIC.com/ADI
A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT
Each DAC channel has seven data registers. The actual DAC
data-word can be written to either the X1A or the X1B input
X2A
X2B
A
/B bit in the control
MUX
DAC
REGISTER
DAC
register, depending on the setting of the
register. If the
A
If the
A
/B bit is 0, data is written to the X1A register.
/B bit is 1, data is written to the X1B register. Note that
this single bit is a global control and affects every DAC channel
in the device. It is not possible to set up the device on a perchannel basis so that some writes are to X1A registers and
some writes are to X1B registers.
X1A
REGISTER
X1B
REGISTER
REGISTER
REGISTER
Figure 18. Data Registers Associated with Each DAC Channel
MUX
M
C
REGISTER
REGISTER
Each DAC channel also has a gain (M) register and an offset
(C) register, which allow trimming out of the gain and offset
errors of the entire signal chain. Data from the X1A register is
operated on by a digital multiplier and adder controlled by the
contents of the M and C registers. The calibrated DAC data is
then stored in the X2A register. Similarly, data from the X1B
register is operated on by the multiplier and adder and stored in
the X2B register.
Although a multiplier and adder symbol are shown in Figure 18
fo
r each channel, there is only one multiplier and one adder in the
device, which are shared among all channels. This has implications for the update speed when several channels are updated at
once, as described in the
Register Update Rates section.
Each time data is written to the X1A register, or to the M or
register with the
C
A
/B control bit set to 0, the X2A data is
recalculated and the X2A register is automatically updated.
Similarly, X2B is updated each time data is written to X1B,
or to M or C with
A
/B set to 1. The X2A and X2B registers
are not readable or directly writable by the user.
Data output from the X2A and X2B registers is routed to the
inal DAC register by a multiplexer. Whether each individual
f
DAC takes its data from the X2A or from the X2B register is
controlled by an 8-bit A/B select register associated with each
group of eight DACs. If a bit in this register is 0, the DAC takes
its data from the X2A register; if 1, the DAC takes its data from
the X2B register (Bit 0 through Bit 7 control DAC 0 to DAC 7).
Note that because there are 32 bits in four registers, it is possible to
et up, on a per-channel basis, whether each DAC takes its data
s
from the X2A or X2B register. A global command is also provided
that sets all bits in the A/B select registers to 0 or to 1.
05815-018
LOAD DAC
All DACs in the AD5372/AD5373 can be updated simultane-
LDAC
ously by taking
low when each DAC register is updated
from either its X2A or X2B register, depending on the setting
of the A/B select registers. The DAC register is not readable or
directly writable by the user.
LDAC
can be permanently tied
low, and the DAC output is updated whenever new data appears
in the appropriate DAC register.
OFFSET DACs
In addition to the gain and offset trim for each DAC, there are
two 14-bit offset DACs, one for Group 0 and one for Group 1 to
Group 3. These allow the output range of all DACs connected to
them to be offset within a defined range. Thus, subject to the
limitations of headroom, it is possible to set the output range of
Group 0 or Group 1 to Group 3 to be unipolar positive, unipolar
negative, or bipolar, either symmetrical or asymmetrical about
0 V. The DACs in the AD5372/AD5373 are factory trimmed with
the offset DACs set at their default values. This gives the best offset
and gain performance for the default output range and span.
When the output range is adjusted by changing the value of the
ffset DAC, an extra offset is introduced due to the gain error of
o
the offset DAC. The amount of offset is dependent on the
magnitude of the reference and how much the offset DAC
moves from its default value. See the
his offset. The worst-case offset occurs when the offset DAC is
t
at positive or negative full scale. This value can be added to the
offset present in the main DAC channel to give an indication of
the overall offset for that channel. In most cases, the offset can
be removed by programming the C register of the channel with
an appropriate value. The extra offset caused by the offset DAC
needs to be taken into account only when the offset DAC is
changed from its default value.
de range that can be loaded to the offset DAC, depending on
co
the reference value used. Thus, for a 5 V reference, the offset
DAC should not be programmed with a value greater than 8192
(0x2000).
5
4
3
VREF (V)
2
1
0
0
4096819212288
OFFSET DAC CODE
Figure 19. Offset DAC Code Range
Specifications section for
Figure 19 shows the allowable
RESERVED
16383
05815-019
Rev. B | Page 15 of 24
AD5372/AD5373
T
www.BDTIC.com/ADI
OUTPUT AMPLIFIER
Because the output amplifiers can swing to 1.4 V below the
positive supply and 1.4 V above the negative supply, this limits
how much the output can be offset for a given reference voltage.
For example, it is not possible to have a unipolar output range
of 20 V, because the maximum supply voltage is ±16.5 V.
S1
S2
CLR
SIGGNDx
ier and Offset DAC
R6
10kΩ
S3
OUTPU
CLR
05815-020
SIGGNDx
DAC
CHANNEL
R4
R3
60kΩ
20kΩ
OFFSET
DAC
Figure 20. Output Amplif
R5
60kΩ
R1
20kΩ
R2
20kΩ
CLR
Figure 20 shows details of a DAC output amplifier and its
connections to the offset DAC. On power-up, S1 is open,
disconnecting the amplifier from the output. S3 is closed, so
the output is pulled to SIGGNDx (R1 and R2 are greater than
R6). S2 is also closed to prevent the output amplifier from being
open-loop. If
condition until
CLR
is low at power-up, the output remains in this
CLR
is taken high. The DAC registers can be
programmed, and the outputs assume the programmed values
CLR
when
is taken high. Even if
output remains in the previous condition until V
V
< −4 V and the initialization sequence has finished. The
SS
CLR
is high at power-up, the
DD
> 6 V and
outputs then go to their power-on default value.
TRANSFER FUNCTION
The output voltage of a DAC in the AD5372/AD5373 is dependent on the value in the input register, the value of the M and C
registers, and the value in the offset DAC.
AD5372 Transfer Function
The input code is the value in the X1A or X1B register that is
applied to the DAC (X1A, X1B default code = 21,844).
DAC_CODE = INPUT_CODE × (M + 1)/2
where:
M = code in gain register − default code = 2
C = code in offset register − default code = 2
16
– 1.
15
.
The DAC output voltage is calculated as follows:
VOUT = 4 × VREFx × (DAC_
16
4))/2
+ V
SIGGND
CODE – (OFFSET_CODE ×
16
+ C − 2
15
where:
DAC_CODE should be within the range of 0 to 65,535.
For 12 V span, VREFx = 3.0 V.
For 20 V span, VREFx = 5.0 V.
OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function because this DAC is
a 14-bit device. On power-up, the default code loaded to the
offset DAC is 5461 (0x1555). With a 3 V reference, this gives
a span of −4 V to +8 V.
AD5373 Transfer Function
The input code is the value in the X1A or X1B register that is
applied to the DAC (X1A, X1B default code = 5461).
DAC_CODE = INPUT_CODE ×
(M + 1)/2
14
+ C − 213
where:
M = co
de in gain register − default code = 2
C = code in offset register − default code = 2
14
13
– 1.
.
The DAC output voltage is calculated as follows:
VOUT = 4 × VREFx × (DAC_
OFFSET_CODE)/2
14
+ V
SIGGND
CODE –
where:
AC_CODE should be within the range of 0 to 16,383.
D
For 12 V span, VREFx = 3.0 V.
For 20 V span, VREFx = 5.0 V.
OFFSET_CODE is the code loaded to the offset DAC.
On power-up, the default code loaded to the offset DAC
is 5461 (0x1555). With a 3 V reference, this gives a span
of −4 V to +8 V.
REFERENCE SELECTION
The AD5372/AD5373 have two reference input pins. The
voltage applied to the reference pins determines the output
voltage span on VOUT0 to VOUT31. VREF0 determines the
voltage span for VOUT0 to VOUT7 (Group 0), and VREF1
determines the voltage span for VOUT8 to VOUT31 (Group 1
to Group 3). The reference voltage applied to each VREF pin
can be different, if required, allowing the groups to have
different voltage spans. The output voltage range and span
can be adjusted further by programming the offset and gain
registers for each channel as well as programming the offset
DACs. If the offset and gain features are not used (that is, the
M and C registers are left at their default values), the required
reference levels can be calculated as follows:
VREF = (VOUT
If the offset and gain features of the AD5372/AD5373 are used,
t
he required output range is slightly different. The selected
output range should take into account the system offset and
gain errors that need to be trimmed out. Therefore, the selected
output range should be larger than the actual required range.
– VOUT
MAX
MIN
)/4
Rev. B | Page 16 of 24
AD5372/AD5373
www.BDTIC.com/ADI
The required reference levels can be calculated as follows:
dentify the nominal output range on VOUT.
1. I
2. I
dentify the maximum offset span and the maximum gain
required on the full output signal range.
3. C
alculate the new maximum output range on VOUT,
including the expected maximum offset and gain errors.
4. Ch
oose the new required VOUT
keeping the VOUT limits centered on the nominal values.
Note that V
5. C
alculate the value of VREF as follows:
VREF = (
and VSS must provide sufficient headroom.
DD
VOUT
– VOUT
MAX
MIN
and VOUT
MAX
)/4
MIN
,
Reference Selection Example
If
Nominal output range = 12 V (−4 V to +8 V)
Zero-scale error = ±70 mV
Gain error = ±3%, and
SIGGNDx = AGND = 0 V
Then
Gain error = ±3%
=> Maximum positive gain error = 3%
=
> Output range including gain error = 12 + 0.03(12) = 12.36 V
Zero-scale error = ±70 mV
=> Maximum offset error span = 2(70 mV) = 0.14 V
=> O
utput range including gain error and zero-scale error =
12.36 V + 0.14 V = 12.5 V
VREF calculation
Actual output range = 12.5 V, that is, −4.25 V to +8.25 V;
VREF = (8.25 V + 4.25 V)/4 = 3.125 V
If the solution yields an inconvenient reference level, the user
can a
dopt one of the following approaches:
se a resistor divider to divide down a convenient, higher
•U
reference level to the required level.
elect a convenient reference level above VREF and modify
•S
the gain and offset registers to digitally downsize the reference.
In this way, the user can use almost any convenient reference
level but can reduce the performance by overcompaction of
the transfer function.
•U
se a combination of these two approaches.
CALIBRATION
The user can perform a system calibration on the AD5372/
AD5373 to reduce gain and offset errors to below 1 LSB. This
reduction is achieved by calculating new values for the M and C
registers and reprogramming them.
The M and C registers should not be programmed until both
t
he zero-scale and full-scale errors are calculated.
Reducing Zero-Scale Error
Zero-scale error can be reduced as follows:
et the output to the lowest possible value.
1. S
2. M
easure the actual output voltage and compare it to the
required value. This gives the zero-scale error.
alculate the number of LSBs equivalent to the error and
3. C
add this number to the default value of the C register. Note
that only negative zero-scale error can be reduced.
Reducing Full-Scale Error
Full-scale error can be reduced as follows:
1. M
easure the zero-scale error.
2. S
et the output to the highest possible value.
3. M
easure the actual output voltage and compare it to the
required value. Add this error to the zero-scale error. This
is the span error, which includes the full-scale error.
alculate the number of LSBs equivalent to the span error
4. C
and subtract this number from the default value of the M
register. Note that only positive full-scale error can be
reduced.
AD5372 Calibration Example
This example assumes that a −4 V to +8 V output is required.
The DAC output is set to −4 V but is measured at −4.03 V. This
gives a zero-scale error of −30 mV.
1 LSB = 12 V/65,536 = 183.105 μV
30 mV = 164 LSBs
The full-scale error can now be calculated. The output is set to
8 V a
nd a value of 8.02 V is measured. This gives a full-scale
error of +20 mV and a span error of +20 mV – (–30 mV) =
+50 mV.
50 mV = 273 LSBs
The errors can now be removed as follows:
1. A
dd 164 LSBs to the default C register value:
(32,768 + 164) = 32,932
2. S
ubtract 273 LSBs from the default M register value:
(65,535 − 273) = 65,262
rogram the M register to 65,262; program the C register
3. P
to 32,932.
Rev. B | Page 17 of 24
AD5372/AD5373
www.BDTIC.com/ADI
ADDITIONAL CALIBRATION
The techniques described in the previous section are usually
enough to reduce the zero-scale and full-scale errors in most
applications. However, there are limitations whereby the errors
may not be sufficiently reduced. For example, the offset (C)
register can only be used to reduce the offset caused by the
negative zero-scale error. A positive offset cannot be reduced.
Likewise, if the maximum voltage is below the ideal value, that
is, a negative full-scale error, the gain (M) register cannot be
used to increase the gain to compensate for the error.
These limitations can be overcome by increasing the reference
va
lue. With a 3 V reference, a 12 V span is achieved. The ideal
voltage range, for the AD5372 or the AD5373, is −4 V to +8 V.
Using a +3.1 V reference increases the range to −4.133 V to
+8.2667 V. Clearly, in this case, the offset and gain errors are
insignificant, and the M and C registers can be used to raise
the negative voltage to −4 V and then reduce the maximum
voltage to +8 V to give the most accurate values possible.
RESET FUNCTION
The reset function is initiated by the
RESET
edge of
reset sequence to reset the X, M, and C registers to their default
values. This sequence typically takes 300 μs, and the user should
not write to the part during this time. On power-up, it is recommended that the user bring
properly initialize the registers.
When the reset sequence is complete (and provided that
high), the DAC output is at a potential specified by the default
register settings, which is equivalent to SIGGNDx. The DAC
outputs remain at SIGGNDx until the X, M, or C register is
updated and
returned to the default state by pulsing
30 ns. Note that, because the reset function is triggered by the
rising edge, bringing
of the AD5372/AD5373.
, the AD5372/AD5373 state machine initiates a
RESET
LDAC
is taken low. The AD5372/AD5373 can be
RESET
low has no effect on the operation
RESET
pin. On the rising
high as soon as possible to
CLR
RESET
low for at least
is
CLEAR FUNCTION
CLR
is an active low input that should be high for normal opera-
CLR
tion. The
When
stages (VOUT0 to VOUT31) is switched to the externally set
potential on the relevant SIGGNDx pin. While
LDAC
DAC outputs return to their previous values. The contents of the
input registers and DAC Register 0 to DAC Register 31 are not
affected by taking
on the outputs,
span is adjusted by writing to the offset DAC.
pin has an internal 500 kΩ pull-down resistor.
CLR
is low, the input to each of the DAC output buffer
CLR
pulses are ignored. When
CLR
low. To prevent glitches from appearing
CLR
should be brought low whenever the output
CLR
is taken high again, the
is low, all
BUSY AND LDAC FUNCTIONS
The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
During the calculation of X2, the
BUSY
is low, the user can continue writing new data to the X1,
M, or C register (see the Register Update Rates section for more
det
ails), but no DAC output updates can take place.
BUSY
The
resistor. When multiple AD5372 or AD5373 devices are used in
one system, the
when it is required that no DAC in any device be updated until
all other DACs are ready. When each device has finished updating
the X2 (A or B) registers, it releases the
device has not finished updating its X2 registers, it holds
low, thus delaying the effect of
The DAC outputs are updated by taking the
LDAC
and the DAC outputs are updated immediately after
high. A user can also hold the
this case, the DAC outputs are updated immediately after
goes high. Whenever the A/B select registers are written to,
also goes low, for approximately 500 ns.
The AD5372/AD5373 have flexible addressing that allows
iting of data to a single channel, all channels in a group, the
wr
same channel in Group 0 to Group 3, the same channel in
Group 1 to Group 3, or all channels in the device. This means
that 1, 4, 8, or 32 DAC register values may need to be calculated
and updated. Because there is only one multiplier shared among
32 channels, this task must be done sequentially so that the
length of the
channels being updated.
Table 9.
Action
Loading input, C, or M to 1 channel
Loading input, C, or M to 4 channels 3.3 μs maximum
Loading input, C, or M to 8 channels 5.7 μs maximum
Loading input, C, or M to 32 channels 20.1 μs maximum
1
BUSY
2
A single channel update is typically 1 μs.
The AD5372/AD5373 contain an extra feature whereby a DAC
register is not updated unless its X2A or X2B register has been
written to since the last time
when
contents of the X2A or X2B register, depending on the setting of
the A/B select registers. However, the AD5372/AD5373 update
the DAC register only if the X2A or X2B data has changed,
thereby removing unnecessary digital crosstalk.
pin is bidirectional and has a 50 kΩ internal pull-up
BUSY
pins can be tied together. This is useful
goes low while
BUSY
BUSY
pulse width = ((number of channels + 1) × 600 ns) + 300 ns.
LDAC
is brought low, the DAC registers are filled with the
BUSY
pulse varies according to the number of
Pulse Widths
BUSY
output goes low. While
BUSY
pin. If another
LDAC
going low.
LDAC
is active, the
LDAC
LDAC
LDAC
input permanently low. In
Pulse Width
BUSY
2
1.5 μs maximum
was brought low. Normally,
BUSY
input low. If
event is stored
BUSY
goes
BUSY
BUSY
1
Rev. B | Page 18 of 24
AD5372/AD5373
www.BDTIC.com/ADI
POWER-DOWN MODE
The AD5372/AD5373 can be powered down by setting Bit 0 in
the control register to 1. This turns off the DACs, thus reducing
the current consumption. The DAC outputs are connected to
their respective SIGGNDx potentials. The power-down mode
does not change the contents of the registers, and the DACs
return to their previous voltage when the power-down bit is
cleared to 0.
THERMAL SHUTDOWN FUNCTION
The AD5372/AD5373 can be programmed to shut down the
DACs if the temperature on the die exceeds 130°C. Setting Bit 1
in the control register to 1 enables this function (see Tabl e 16 ).
I
f the die temperature exceeds 130°C, the AD5372/AD5373 enter
a thermal shutdown mode, which is equivalent to setting the
power-down bit in the control register to 1. To indicate that the
AD5372/AD5373 have entered thermal shutdown mode, Bit 4
of the control register is set to 1. The AD5372/AD5373 remain
in thermal shutdown mode, even if the die temperature falls,
until Bit 1 in the control register is cleared to 0.
TOGGLE MODE
The AD5372/AD5373 have two X2 registers per channel, X2A
and X2B, which can be used to switch the DAC output between
two levels with ease. This approach greatly reduces the overhead
required by a microprocessor, which would otherwise need to
write to each channel individually. When the user writes to the
X1A, X1B, M, or C register, the calculation engine takes a certain
amount of time to calculate the appropriate X2A or X2B value.
If an application, such as a data generator, requires that the
DAC output switch between two levels only, any method that
reduces the amount of calculation time necessary is advantageous. For the data generator example, the user needs only to
set the high and low levels for each channel once by writing to
the X1A and X1B registers. The values of X2A and X2B are
calculated and stored in their respective registers. The calculation
delay, therefore, happens only during the setup phase, that is,
when programming the initial values. To toggle a DAC output
between the two levels, it is only required to write to the relevant
A/B select register to set the MUX2 register bit. Furthermore,
because there are eight MUX2 control bits per register, it is
possible to update eight channels with a single write.
s
If the bit is set to 0, Register X2A is selected. If the bit is set to 1, Register X2B is selected.
F7 F6 F5 F4 F3 F2 F1 F0
Bits1
Rev. B | Page 19 of 24
AD5372/AD5373
www.BDTIC.com/ADI
SERIAL INTERFACE
The AD5372/AD5373 contain a high speed SPI operating at
clock frequencies up to 50 MHz (20 MHz for read operations).
To minimize both the power consumption of the device and
on-chip digital noise, the interface powers up fully only when
the device is being written to, that is, on the falling edge of
SYNC
. The serial interface is 2.5 V LVTTL-compatible when
operating from a 2.5 V to 3.6 V DV
four pins:
data input pin), SCLK (clocks data in and out of the device),
and SDO (serial data output pin for data readback).
SYNC
(frame synchronization input), SDI (serial
supply. It is controlled by
CC
SPI WRITE MODE
The AD5372/AD5373 allow writing of data via the serial interface
to every register directly accessible to the serial interface, that is,
all registers except the X2A, X2B, and DAC registers. The X2A
and X2B registers are updated when writing to the X1A, X1B,
M, and C registers, and the DAC data registers are updated by
LDAC
. The serial word (see Tabl e 11 or Tabl e 12 ) is 24 bits long:
16 (AD5372) or 14 (AD5373) of these bits are data bits; six bits
are address bits; and two bits are mode bits that determine what
is done with the data. Two bits are reserved on the AD5373.
The serial interface works with both a continuous and a burst
ted) serial clock. Serial data applied to SDI is clocked into
(ga
the AD5372/AD5373 by clock pulses applied to SCLK. The first
falling edge of
clock edges must be applied to SCLK to clock in 24 bits of data
before
th
the 24
If a continuous clock is used,
th
25
falling clock edge. This inhibits the clock within the AD5372/
AD5373. If more than 24 falling clock edges are applied before
SYNC
is taken high again, the input data becomes corrupted. If
an externally gated clock of exactly 24 pulses is used,
be taken high any time after the 24
The input register addressed is updated on the rising edge of
SYNC
. For another serial transfer to take place,
taken low again.
SYNC
starts the write cycle. At least 24 falling
SYNC
is taken high again. If
falling clock edge, the write operation is aborted.
SYNC
is taken high before
SYNC
must be taken high before the
th
falling clock edge.
SYNC
SYNC
must be
can
SPI READBACK MODE
The AD5372/AD5373 allow data readback via the serial
interface from every register directly accessible to the serial
interface, that is, all registers except the X2A, X2B, and DAC
data registers. To read back a register, it is first necessary to tell
the AD5372/AD5373 which register is to be read. This is achieved
by writing a word whose first two bits are the Special Function
Code 00 to the device. The remaining bits then determine which
register is to be read back.
If a readback command is written to a special function register,
ata from the selected register is clocked out of the SDO pin
d
during the next SPI operation. The SDO pin is normally threestated but becomes driven as soon as a read command is issued.
The pin remains driven until the register data is clocked out.
See
Figure 5 for the read timing diagram. Note that due to the
ming requirements of t
ti
SPI interface during a read operation should not exceed 20 MHz.
(25 ns), the maximum speed of the
22
REGISTER UPDATE RATES
The value of the X2A register or the X2B register is calculated
each time the user writes new data to the corresponding X1, C,
or M register. The calculation is performed by a three-stage
process. The first two stages take approximately 600 ns each, and
the third stage takes approximately 300 ns. When the write to an
X1, C, or M register is complete, the calculation process begins.
If the write operation involves the update of a single DAC
channel, the user is free to write to another register, provided
that the write operation does not finish until the first-stage
calculation is complete (that is, 600 ns after the completion of
the first write operation). If a group of channels is being updated
by a single write operation, the first-stage calculation is repeated
for each channel, taking 600 ns per channel. In this case, the
user should not complete the next write operation until this time
has elapsed.
Bit I1 and Bit I0 are reserved for future use and should be 0 when writing the serial word. These bits read back as 0.
Rev. B | Page 20 of 24
AD5372/AD5373
www.BDTIC.com/ADI
CHANNEL ADDRESSING AND SPECIAL MODES
If the mode bits are not 00, the data-word D15 to D0 (AD5372)
or D13 to D0 (AD5373) is written to the device. Address Bit A5
to Address Bit A0 determine which channels are written to, and
the mode bits determine to which register (X1A, X1B, C, or M)
the data is written, as shown in
e written to the X1A register when the
b
register is 0, or to the X1B register when the
The AD5372/AD5373 have very flexible addressing that allows
he writing of data to a single channel, all channels in a group,
t
the same channel in Group 0 to Group 3, the same channel in
Group 1 to Group 3, or all channels in the device.
hich groups and which channels are addressed for every
w
combination of Address Bit A5 to Address Bit A0.
Table 14. Group and Channel Addressing
Address Bit A2
to Address Bit A0
000 All groups,
001 Group 0, all
010 Group 1, all
011 Group 2, all
100 Group 3, all
101 Reserved Group 0,
110 Reserved Group 0,
111 Reserved Group 0,
000 001 010 011 100 101 110 111
all channels
channels
channels
channels
channels
Ta bl e 13 and Tab le 1 4. Data is to
A
/B bit in the control
A
/B bit is 1.
Table 1 4 shows
Group 0,
Channel 0
Group 0,
Channel 1
Group 0,
Channel 2
Group 0,
Channel 3
Group 0,
Channel 4
Channel 5
Channel 6
Channel 7
Group 1,
Channel 0
Group 1,
Channel 1
Group 1,
Channel 2
Group 1,
Channel 3
Group 1,
Channel 4
Group 1,
Channel 5
Group 1,
Channel 6
Group 1,
Channel 7
Address Bit A5 to Address Bit A3
Group 2,
Channel 0
Group 2,
Channel 1
Group 2,
Channel 2
Group 2,
Channel 3
Group 2,
Channel 4
Group 2,
Channel 5
Group 2,
Channel 6
Group 2,
Channel 7
Table 13. Mode Bits
M1 M0 Action
1 1 Write to DAC data (X) register
1 0 Write to DAC offset (C) register
0 1 Write to DAC gain (M) register
0 0
Special function, used in combination with other
bits of the da
ta-word
Group 3,
Channel 0
Group 3,
Channel 1
Group 3,
Channel 2
Group 3,
Channel 3
Group 3,
Channel 4
Group 3,
Channel 5
Group 3,
Channel 6
Group 3,
Channel 7
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 0
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 1
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 2
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 3
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 4
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 5
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 6
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 7
Group 1,
Group 2,
Group 3;
Channel 0
Group 1,
Group 2,
Group 3;
Channel 1
Group 1,
Group 2,
Group 3;
Channel 2
Group 1,
Group 2,
Group 3;
Channel 3
Group 1,
Group 2,
Group 3;
Channel 4
Group 1,
Group 2,
Group 3;
Channel 5
Group 1,
Group 2,
Group 3;
Channel 6
Group 1,
Group 2,
Group 3;
Channel 7
Rev. B | Page 21 of 24
AD5372/AD5373
www.BDTIC.com/ADI
SPECIAL FUNCTION MODE
If the mode bits are 00, then the special function mode is selected, as shown in Tabl e 15 . Bit I21 to Bit I16 of the serial data-word select the
special function, and the remaining bits are data required for execution of the special function, for example, the channel address for data
readback. The codes for the special functions are shown in Table 16. Tabl e 17 shows the addresses for data readback.
F3 = reserved. This bit should be 0 when writing to the control register.
F2 = 1: Select Register X1B for input.
F2 = 0: Select Register X1A for input.
F1 = 1: Enable thermal shutdown mode.
F1 = 0: Disable thermal shutdown mode.
F0 = 1: Software power-down.
F0 = 0: Software power-up.
0 0 0 0 1 0 XX[F13:F0] Write data in F13 to F0 to OFS0 register.
0 0 0 0 1 1 XX[F13:F0] Write data in F13 to F0 to OFS1 register.
0 0 0 1 0 0 Reserved
0 0 0 1 0 1 See Table 17Select register for readback.
0 0 0 1 1 0 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 0.
0 0 0 1 1 1 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 1.
0 0 1 0 0 0 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 2.
0 0 1 0 0 1 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 3.
0 0 1 0 1 0 Reserved
0 0 1 0 1 1 XXXX XXXX [F7:F0] Block write to A/B select registers.
F7 to F0 = 0: Write all 0s (all channels use the X2A register).
F7 to F0 = 1: Write all 1s (all channels use the X2B register).
Data (F15 to F0) Action
F4 = overtemperature indicator (read-only bit). This bit should be 0 when
Bit F6 to Bit F0 are don’t cares for the data readback function.
Bit F12 to Bit F7 select the channel to be read back,
from Channel 0 = 001000 to Channel 31 = 100111
Rev. B | Page 22 of 24
M register
AD5372/AD5373
www.BDTIC.com/ADI
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit boards on
which the AD5372/AD5373 are mounted should be designed
so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5372/AD5373 are
in a system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device. For supplies with multiple pins (V
, VDD, DVCC),
SS
it is recommended that these pins be tied together and that each
supply be decoupled only once.
The AD5372/AD5373 should have ample supply decoupling of
10 μF in p
arallel with 0.1 μF on each supply located as close to
the package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor
should have low effective series resistance (ESR) and low effective
series inductance (ESI)—typical of the common ceramic types
that provide a low impedance path to ground at high frequencies—
to handle transient currents due to internal logic switching.
Digital lines running under the device should be avoided because
t
hey can couple noise onto the device. The analog ground plane
should be allowed to run under the AD5372/AD5373 to avoid
noise coupling. The power supply lines of the AD5372/AD5373
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
Fast switching digital signals should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
they should never be run near the reference inputs. It is essential
to minimize noise on the VREF0 and VREF1 lines.
Avoid crossover of digital and analog signals. Traces on
o
pposite sides of the board should run at right angles to
each other. This reduces the effects of feedthrough through
the board. A microstrip technique is by far the best approach,
but it is not always possible with a double-sided board. In this
technique, the component side of the board is dedicated to
ground plane, while signal traces are placed on the solder side.
As is the case for all thin packages, care must be taken to avoid
lexing the package and to avoid a point load on the surface of
f
this package during the assembly process.
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5372/AD5373, it is
important that the AGND and DGND pins be connected to the
relevant ground plane before the positive or negative supplies
are applied. In most applications, this is not an issue because the
ground pins for the power supplies are connected to the ground
pins of the AD5372/AD5373 via ground planes. When the
AD5372/AD5373 are to be used in a hot-swap card, care should
be taken to ensure that the ground pins are connected to the
supply grounds before the positive or negative supplies are
connected. This is required to prevent currents from flowing
in directions other than toward an analog or digital ground.
INTERFACING EXAMPLES
The SPI interface of the AD5372/AD5373 is designed to allow
the parts to be easily connected to industry-standard DSPs and
microcontrollers. Figure 21 shows how the AD5372/AD5373
co
nnects to the Analog Devices, Inc., Blackfin® DSP. The Blackfin
has an integrated SPI port that can be connected directly to the
SPI pins of the AD5372/AD5373 and programmable I/O pins
that can be used to set or read the state of the digital input or
output pins associated with the interface.
AD5372/
AD5373
SYNC
SCLK
SDI
SDO
RESET
LDAC
CLR
BUSY
SYNC
SCLK
SDI
SDO
RESET
LDAC
CLR
BUSY
AD5372/
AD5373
05815-022
SPISELx
SCK
MOSI
MISO
PF10
ADSP-BF531
Figure 21. Interfacing to a Blackfin DSP
PF9
PF8
PF7
The Analog Devices ADSP-21065L is a floating-point DSP with
two serial ports (SPORTs). Figure 22 shows how one SPORT can
be us
ed to control the AD5372/AD5373. In this example, the
transmit frame synchronization (TFSx) pin is connected to the
receive frame synchronization (RFSx) pin. Similarly, the transmit
and receive clocks (TCLKx and RCLKx) are also connected. The
user can write to the AD5372/AD5373 by writing to the transmit
register of the ADSP-21065L. A read operation can be accomplished by first writing to the AD5372/AD5373 to tell the part
that a read operation is required. A second write operation with
an NOP instruction causes the data to be read from the
AD5372/AD5373. The DSP receive interrupt can be used to
indicate when the read operation is complete.