ANALOG DEVICES AD5372 Service Manual

32-Channel, 16-/14-Bit,

V

www.BDTIC.com/ADI

FEATURES

32-channel DAC in a 64-lead LQFP
AD5372/AD5373
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage range of −4 V to +8 V
Multiple, independent output voltage spans available
System calibration function allowing user-programmable

off

set and gain
Channel grouping and addressing features
Thermal shutdown function
DSP/microcontroller-compatible serial interface
SPI serial interface

SYNC

SDI

SCLK

SDO

BUSY

RESET

CLR

1

guaranteed monotonic to 16/14 bits

V

D

CONTROL
REGISTER

SERIAL

INTERFACE

STATE

MACHINE

V

C

D

C

n

AGND DGND

SS

D

n = 16 FOR AD5372
n = 14 FOR AD5373

8

A/B SELECT

REGISTE R

n

X1 REGISTER

n

M REGISTER

n

C REGISTER

n n n n n

X1 REGISTER

n

M REGISTER

n

C REGISTER

8 8

A/B SELECT

REGISTE R

n

X1 REGISTER

n

M REGISTER

n

C REGISTER

n n n n n

X1 REGISTER

n

M REGISTER

n

C REGISTER

8

n n n

n

n

n

n

n n n

n

n

n

n

FUNCTIONAL BLOCK DIAGRAM

TO
MUX 2s

A/B

MUX

A/B

MUX

TO
MUX 2s

A/B

MUX

A/B

MUX

X2A REG ISTER

X2B REG ISTER

X2A REG ISTER

X2B REG ISTER

X2A REG ISTER

X2B REG ISTER

X2A REG ISTER

X2B REG ISTER

Serial Input, Voltage Output DAC

AD5372/AD5373

2.5 V to 5.5 V JEDEC-compliant digital levels
Digital reset (
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs

APPLICATIONS

Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation

LDAC

14

OFS0

REGISTER

DAC 0

2

REGISTER

MUX

DAC 7

2

REGISTER

MUX

14

OFS1

REGISTER

DAC 0

2

REGISTER

MUX

DAC 7

2

REGISTER

MUX

RESET

n

n

n

n

)

OFFSET

DAC 0

DAC 0

DAC 7

OFFSET

DAC 1

DAC 0

DAC 7

BUFFER

BUFFER

BUFFER

BUFFER

GROUP 0

OUTPUT BU FFER

AND POWER-

DOWN CONTROL

OUTPUT B UFFER

AND POWER-

DOWN CONTROL

GROUP 1

OUTPUT BU FFER

AND POWER-

DOWN CONTROL

OUTPUT B UFFER

AND POWER-

DOWN CONTROL

VREF0

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

SIGG ND0

VREF1

VOUT8

VOUT9

VOUT10

VOUT11

VOUT12

VOUT13

VOUT14

VOUT15

SIGGND1

AD5372/

AD5373

GROUP 2 TO GROUP 3

ARE ID ENTICA L TO GRO UP 1

VREF1 SUPPLI ES
GROUP 1 TO GROUP 3

SIGGN D2

Figure 1.

1

Protected by U.S. Patent No. 5,969,657; other patents pending.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2008 Analog Devices, Inc. All rights reserved.

SIGGN D3

VOUT16
TO
VOUT31

05815-001

AD5372/AD5373

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

Revision History ...............................................................................2

General Description......................................................................... 3

Specifications..................................................................................... 4

AC Characteristics........................................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics........................................... 11

Terminology.................................................................................... 13

Theory of Operation ......................................................................14

DAC Architecture....................................................................... 14

Channel Groups.......................................................................... 14

A/B Registers and Gain/Offset Adjustment............................ 15

Load DAC.................................................................................... 15

Offset DACs ................................................................................15

Output Amplifier........................................................................ 16

Transfer Function....................................................................... 16

REVISION HISTORY

2/08—Rev. A to Rev. B

Added Table 1.................................................................................... 3

anges to t

Ch
Added t

Changes to Figure 4.......................................................................... 7

Changes to Absolute Maximum Ratings Section......................... 9

Changes to Pin Configuration and Function Descriptions

Section.............................................................................................. 10

Changes to Reset Function Section.............................................. 18

Parameter .................................................................6

10

Parameter......................................................................... 6

23

Reference Selection .................................................................... 16

Calibration................................................................................... 17

Additional Calibration............................................................... 18

Reset Function............................................................................ 18

Clear Function............................................................................ 18

and

LDAC

Functions...................................................... 18

BUSY

Power-Down Mode.................................................................... 19

Thermal Shutdown Function ...................................................19

Toggle Mode................................................................................ 19

Serial Interface ................................................................................ 20

SPI Write Mode .......................................................................... 20

SPI Readback Mode................................................................... 20

Register Update Rates................................................................ 20

Channel Addressing and Special Modes................................. 21

Special Function Mode.............................................................. 22

Applications Information.............................................................. 23

Power Supply Decoupling......................................................... 23

Power Supply Sequencing .........................................................23

Interfacing Examples ................................................................. 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

12/07—Rev. 0 to Rev. A

Changes to Table 3.............................................................................6

Changes to AD5373 Transfer Function Section......................... 16

Changes to Calibration Section.................................................... 17

Changes to Table 8.......................................................................... 18

Changes to Register Update Rates Section.................................. 20

Changes to Ordering Guide.......................................................... 25

8/07—Revision 0: Initial Version

Rev. B | Page 2 of 24

AD5372/AD5373

www.BDTIC.com/ADI

GENERAL DESCRIPTION

The AD5372/AD5373 contain 32 16-/14-bit DACs in a single
64-lead LQFP. The devices provide buffered voltage outputs with
a nominal span of 4× the reference voltage. The gain and offset
of each DAC can be independently trimmed to remove errors. For
even greater flexibility, the device is divided into four groups of
eight DACs. Two offset DACs allow the output range of the groups
to be altered. Group 0 can be adjusted by Offset DAC 0, and
Group 1 to Group 3 can be adjusted by Offset DAC 1.

The AD5372/AD5373 offer guaranteed operation over a wide

pply range: V

su

16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.

Table 1. High Channel Count Bipolar DACs

Model Resolution (Bits) Nominal Output Span Output Channels Linearity Error (LSB)

AD5360 16 4 × V
AD5361 14 4 × V
AD5362 16 4 × V
AD5363 14 4 × V
AD5370 16 4 × V
AD5371 14 4 × V

AD5372 16 4 × V
AD5373 14 4 × V

AD5378 14 ±8.75 V 32 ±3
AD5379 14 ±8.75 V 40 ±3

from −16.5 V to −4.5 V and VDD from 9 V to

SS

(20 V) 16 ±4

REF

(20 V) 16 ±1

REF

(20 V) 8 ±4

REF

(20 V) 8 ±1

REF

(12 V) 40 ±4

REF

(12 V) 40 ±1

REF

(12 V) 32 ±4

REF

(12 V) 32 ±1

REF

The AD5372/AD5373 have a high speed serial interface that is

mpatible with SPI, QSPI™, MICROWIRE™, and DSP inter-

co
face standards and can handle clock speeds of up to 50 MHz.

The DAC registers are updated on reception of new data. All
t

he outputs can be updated simultaneously by taking the
input low. Each channel has a programmable gain and an offset
adjust register.

Each DAC output is gained and buffered on chip with respect

an external SIGGNDx input. The DAC outputs can also be

to
switched to SIGGNDx via the

CLR

pin.

LDAC

Rev. B | Page 3 of 24

AD5372/AD5373

www.BDTIC.com/ADI

SPECIFICATIONS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V;

= open circuit; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T

C

L

unless otherwise noted.

MIN

to T

MAX

,

Table 2.

AD5372

Parameter

ACCURACY

Resolution 16 14 Bits
Integral Nonlinearity (INL) ±4 ±1 LSB max
Differential Nonlinearity (DNL) ±1 ±1 LSB max

Zero-Scale Error ±10 ±10 mV max Before calibration
Full-Scale Error ±10 ±10 mV max Before calibration
Gain Error 0.1 0.1 % FSR Before calibration
Zero-Scale Error
Full-Scale Error
Span Error of Offset DAC ±35 ±35 mV max See the Offset DACS section for details
VOUTx Temperature Coefficient 5 5 ppm FSR/°C typ Includes linearity, offset, and gain drift
DC Crosstalk2 100 100 μV max

REFERENCE INPUTS (VREF0, VREF1)

VREFx Input Current ±10 ±10 μA max Per input; typically ±30 nA
VREFx Range 2/5 2/5 V min/V max ±2% for specified operation

SIGGND INPUTS (SIGGND0 TO SIGGND3)2

DC Input Impedance 50 50 kΩ min Typically 55 kΩ
Input Range ±0.5 ±0.5 V min/V max
SIGGNDx Gain 0.995/1.005 0.995/1.005 min/max

OUTPUT CHARACTERISTICS

Output Voltage Range VSS + 1.4 VSS + 1.4 V min I
V
Nominal Output Voltage Range −4 to +8 −4 to +8 V min/V max
Short-Circuit Current 15 15 mA max VOUTx to DVCC, VDD, or VSS
Load Current ±1 ±1 mA max
Capacitive Load 2200 2200 pF max
DC Output Impedance 0.5 0.5 Ω max

DIGITAL INPUTS JEDEC compliant

Input High Voltage 1.7 1.7 V min DVCC = 2.5 V to 3.6 V

2.0 2.0 V min DVCC = 3.6 V to 5.5 V
Input Low Voltage 0.8 0.8 V max DVCC = 2.5 V to 5.5 V
Input Current ±1 ±1 μA max

CLR High Impedance Leakage Current
Input Capacitance

DIGITAL OUTPUTS (SDO, BUSY)

Output Low Voltage 0.5 0.5 V max Sinking 200 μA
Output High Voltage (SDO) DVCC − 0.5 DVCC − 0.5 V min Sourcing 200 μA
SDO High Impedance Leakage Current ±5 ±5 μA max
High Impedance Output Capacitance210 10 pF typ

2

2

2

2

2

B Version

1 1 LSB typ After calibration
1 1 LSB typ After calibration

±20 ±20 μA max
10 10 pF max

1

AD53731
B Version

− 1.4 VDD − 1.4 V max I

DD

Unit Test C

onditions/Comments

Guaranteed monotonic by design over

ature

temper

Typically 20 μV; measured channel at midscale,

le change on any other channel

full-sca

= 1 mA

LOAD

= 1 mA

LOAD

Excluding CLR

pin

2

Rev. B | Page 4 of 24

AD5372/AD5373

www.BDTIC.com/ADI

Parameter

AD5372
B Version

1

AD53731
B Version Unit Test Conditions/Comments

2

POWER REQUIREMENTS

DVCC 2.5/5.5 2.5/5.5 V min/V max
VDD 9/16.5 9/16.5 V min/V max
VSS −16.5/−4.5 −16.5/−4.5 V min/V max
Power Supply Sensitivity

2

∆Full Scale/∆VDD −75 −75 dB typ
∆Full Scale/∆VSS −75 −75 dB typ

∆Full Scale/∆DVCC −90 −90 dB typ
DICC 2 2 mA max DVCC = 5.5 V, VIH = DVCC, VIL = GND
IDD 16 16 mA max Outputs unloaded, DAC outputs = 0 V
18 18 mA max Outputs unloaded, DAC outputs = full scale
ISS −16 −16 mA max Outputs unloaded, DAC outputs = 0 V

−18 −18 mA max Outputs unloaded, DAC outputs = full scale
Power-Down Mode Bit 0 in the control register is 1

DICC 5 5 μA typ

IDD 35 35 μA typ

ISS −35 −35 μA typ
Power Dissipation (Unloaded) 250 250 mW typ VSS = −8 V, VDD = 9.5 V, DVCC = 2.5 V
Junction Temperature

1

Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.

2

Guaranteed by design and characterization; not production tested.

3

θJA represents the package thermal impedance.

3

130 130 °C max TJ = TA + P

TOTAL

× θJA

AC CHARACTERISTICS

DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M),
offset (C), and DAC offset registers at default values; all specifications T

Table 3.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

1

Output Voltage Settling Time 20 μs typ Full-scale change
30 μs max DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate 1 V/μs typ
Digital-to-Analog Glitch Energy 5 nV-s typ
Glitch Impulse Peak Amplitude 10 mV max
Channel-to-Channel Isolation 100 dB typ VREF0, VREF1 = 2 V p-p, 1 kHz
DAC-to-DAC Crosstalk 10 nV-s typ
Digital Crosstalk 0.2 nV-s typ
Digital Feedthrough 0.02 nV-s typ Effect of input bus activity on DAC output under test
Output Noise Spectral Density @ 10 kHz 250 nV/√Hz typ VREF0 = VREF1 = 0 V

1

Guaranteed by design and characterization; not production tested.

MIN

to T

, unless otherwise noted.

MAX

Rev. B | Page 5 of 24

AD5372/AD5373

T

www.BDTIC.com/ADI

TIMING CHARACTERISTICS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF to GND;
R

= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T

L

MIN

to T

, unless otherwise noted.

MAX

Table 4. SPI Interface

Parameter

t

1

1 , 2 , 3

Limit at T

MIN

, T

Unit Description

MAX

20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 11 ns min
t

5

20 ns min
t6 10 ns min
t

7

5 ns min Data setup time

falling edge to SCLK falling edge setup time

SYNC
Minimum SYNC

th

SCLK falling edge to SYNC rising edge

24

high time

t8 5 ns min Data hold time

4

t

9

t10 1/1.5 μs typ/μs max

42 ns max

rising edge to BUSY falling edge

SYNC

pulse width low (single-channel update); see Table 9

BUSY
t11 600 ns max Single-channel update cycle time
t12 20 ns min
t13 10 ns min
t14 3 μs max
t15 0 ns min
t16 3 μs max

rising edge to LDAC falling edge

SYNC

pulse width low

LDAC

rising edge to DAC output response time

BUSY

rising edge to LDAC falling edge

BUSY

falling edge to DAC output response time

LDAC
t17 20/30 μs typ/μs max DAC output settling time
t18 140 ns max
t19 30 ns min
t20 400 μs max
t21 270 ns min

5

t

22

25 ns max SCLK rising edge to SDO valid

t23 80 ns max

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 4 and Figure 5.

4

t9 is measured with the load circuit shown in Figure 2.

5

t22 is measured with the load circuit shown in Figure 3.

/RESET pulse activation time

CLR

pulse width low

RESET

time indicated by BUSY low

RESET

Minimum SYNC

rising edge to BUSY falling edge

RESET

high time in readback mode

50pF

C

200µA I

L

200µA I

DV

CC

R

L

TO

OUTPUT

PIN

Figure 2. Load Circuit for

2.2kΩ

C

L

50pF

BUSY

Timing Diagram

V

OL

05815-002

Rev. B | Page 6 of 24

O OUTPUT

PIN

Figure 3. Load Circuit for SDO Timing Diagram

OL

OH

VOH (MIN) – VOL (MAX)

2

5815-003

AD5372/AD5373

V

V

www.BDTIC.com/ADI

t

1

SCLK

SYNC

BUSY

LDAC

OUTx

LDAC

OUTx

SDI

1

1

2

2

1

2

t

3

t

4

t

5

t

7

t

8

DB23

24

t

2

t

6

DB0

t

9

t

1

t

11

t

10

12

t

13

24

t

17

t

14

t

15

t

13

t

17

t

16

CLR

t

18

VOUTx

t

19

RESET

VOUTx

BUSY

1

LDAC ACTIVE DURING BUSY.

2

LDAC ACTIVE AFTER BUSY.

t

23

t

18

t

20

05815-004

Figure 4. SPI Write Timing

Rev. B | Page 7 of 24

AD5372/AD5373

C

www.BDTIC.com/ADI

SCLK

SYN

SDI

INPUT WORD SPECIFIES

REGISTER TO BE READ

SDO

t

22

DB0 DB23DB23

LSB FROM PREVIOUS WRITE

t

21

NOP CONDITI ON

DB0

DB23 DB15

SELECTED REG ISTER DATA CL OCKED OUT

48

DB0

DB0

05815-005

Figure 5. SPI Read Timing

OUTPUT

VOLTAGE

8V

ACTUAL
TRANSFER
FUNCTION

IDEAL
TRANSFER
FUNCTION

FULL-SCALE
ERROR
+
ZERO-SCALE
ERROR

0 16383

–4V

DAC CODE

ZERO-SCALE
ERROR

Figure 6. DAC Tran

sfer Function

05815-006

Rev. B | Page 8 of 24