Analog Devices AD5343BRU, AD5343, AD5342BRU, AD5342, AD5333 Datasheet
...
2.5 V to 5.5 V, 230 A, Parallel Interface
a
FEATURES
AD5332: Dual 8-Bit DAC in 20-Lead TSSOP
AD5333: Dual 10-Bit DAC in 24-Lead TSSOP
AD5342: Dual 12-Bit DAC in 28-Lead TSSOP
AD5343: Dual 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 230 A @ 3 V, 300 A @ 5 V
via PD Pin
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–V
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40ⴗC to +105ⴗC
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
or 0–2 V
REF
REF
Dual Voltage-Output 8-/10-/12-Bit DACs
AD5332/AD5333/AD5342/AD5343*
GENERAL DESCRIPTION
The AD5332/AD5333/AD5342/AD5343 are dual 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 230 µA at 3 V, and feature a power-down pin, PD
that further reduces the current to 80 nA. These devices incorporate an on-chip output buffer that can drive the output to
both supply rails, while the AD5333 and AD5342 allow a choice
of buffered or unbuffered reference input.
The AD5332/AD5333/AD5342/AD5343 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin on the AD5333 and AD5342 allows the output
range to be set at 0 V to V
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
The AD5332/AD5333/AD5342/AD5343 are available in Thin
Shrink Small Outline Packages (TSSOP).
or 0 V to 2 × V
REF
REF
.
AD5332 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
POWER-ON
RESET
DAC
REGISTER
DAC
REGISTER
RESET
INPUT
REGISTER
INPUT
REGISTER
DB
7
.
.
.
DB
0
INTER-
FACE
CS
WR
A0
CLR
LDAC
*Protected by U.S. Patent Number 5,969,657; other patents pending.
LOGIC
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
V
A
REF
8-BIT
DAC
8-BIT
DAC
V
B
REF
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
BUFFER
BUFFER
V
DD
AD5332
POWER-DOWN
LOGIC
PD
GND
V
A
OUT
V
B
OUT
AD5332/AD5333/AD5342/AD5343–SPECIFICATIONS
(VDD = 2.5 V to 5.5 V, V
Parameter
DC PERFORMANCE
DAC REFERENCE INPUT
OUTPUT CHARACTERISTICS
LOGIC INPUTS
POWER REQUIREMENTS
NOTES
1
See Terminology section.
2
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
3
Linearity is tested using a reduced code range: AD5332 (Code 8 to 255); AD5333 (Code 28 to 1023); AD5342/AD5343 (Code 115 to 4095).
4
DC specifications tested with outputs unloaded.
5
This corresponds to x codes. x = Deadband voltage/LSB size.
6
Guaranteed by design and characterization, not production tested.
7
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
“Offset plus Gain” Error must be positive.
Specifications subject to change without notice.
1
AD5332
Resolution 8 Bits
Relative Accuracy ± 0.15 ± 1 LSB
Differential Nonlinearity ± 0.02 ± 0.25 LSB Guaranteed Monotonic By Design Over All Codes
AD5333
Resolution 10 Bits
Relative Accuracy ± 0.5 ± 4 LSB
Differential Nonlinearity ± 0.05 ± 0.5 LSB Guaranteed Monotonic By Design Over All Codes
AD5342/AD5343
Resolution 12 Bits
Relative Accuracy ± 2 ± 16 LSB
Differential Nonlinearity ± 0.2 ± 1 LSB Guaranteed Monotonic By Design Over All Codes
Offset Error ± 0.4 ± 3 % of FSR
Gain Error ± 0.15 ± 1 % of FSR
Lower Deadband
Upper Deadband 10 60 mV VDD = 5 V. Upper Deadband Exists Only if V
Offset Error Drift
Gain Error Drift
DC Power Supply Rejection Ratio
DC Crosstalk
V
REF
V
REF
6
Input Range 1 V
Input Impedance >10 MΩ Buffered Reference (AD5333 and AD5342)
Reference Feedthrough –90 dB Frequency = 10 kHz
Channel-to-Channel Isolation –90 dB Frequency = 10 kHz (AD5332, AD5333, and AD5342)
Minimum Output Voltage
Maximum Output Voltage
DC Output Impedance 0.5 Ω
Short Circuit Current 25 mA VDD = 5 V
Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V
6
Input Current ± 1 µA
VIL, Input Low Voltage 0.8 V V
VIH, Input High Voltage 2.4 V VDD = 5 V ± 10%
Pin Capacitance 3.5 pF
V
DD
IDD (Normal Mode) All DACs active and excluding load currents
VDD = 4.5 V to 5.5 V 300 450 µA Unbuffered Reference. VIH = VDD, V
VDD = 2.5 V to 3.6 V 230 350 µA I
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V 0.2 1 µA
VDD = 2.5 V to 3.6 V 0.08 1 µA
= 2 V. RL = 2 k⍀ to GND; CL =200 pF to GND; all specifications T
REF
B Version
2
Min Typ Max Unit Conditions/Comments
3, 4
5
6
6
6
10 60 mV Lower Deadband Exists Only if Offset Error Is Negative
–12 ppm of FSR/°C
–5 ppm of FSR/°C
–60 dB ∆VDD = ±10%
200 µVR
6
0.25 V
DD
DD
180 kΩ Unbuffered Reference. Gain = 1, Input Impedance = R
90 kΩ Unbuffered Reference. Gain = 2, Input Impedance = R
6
4, 7
4, 7
0.001 V min Rail-to-Rail Operation
VDD – 0.001 V max
16 mA VDD = 3 V
5 µs Coming Out of Power-Down Mode. VDD = 3 V
0.6 V VDD = 3 V ± 10%
0.5 V VDD = 2.5 V
2.1 V VDD = 3 V ± 10%
2.0 V VDD = 2.5 V
2.5 5.5 V
to T
MIN
unless otherwise noted.)
MAX
= 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND;
L
Gain = 0
V Buffered Reference (AD5333 and AD5342)
V Unbuffered Reference
= 5 V ± 10%
DD
= GND.
increases by 50 µA at V
DD
In Buffered Mode extra current is (5 +V
IL
> VDD – 100 mV.
REF
REF/RDAC
= VDD and
REF
REF = VDD
) µA.
DAC
DAC
–2–
REV. 0
AD5332/AD5333/AD5342/AD5343
t
4
t
13
t
7
t
14t15
CS
WR
DATA,
GAIN,
BUF,
HBEN
LDAC
1
LDAC
2
CLR
1
SYNCHRONOUS LDAC UPDATE MODE
2
ASYNCHRONOUS LDAC UPDATE MODE
A0
t
1
t
2
t
3
t
5
t
6
t
8
t
9
t
10
t
11
t
12
(VDD = 2.5 V to 5.5 V. RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T
1
AC CHARACTERISTICS
Parameter
2
otherwise noted.)
B Version
3
Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time V
= 2 V. See Figure 20
REF
MIN
to T
MAX
unless
AD5332 6 8 µs 1/4 Scale to 3/4 Scale Change (40 H to C0 H)
AD5333 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H)
AD5342 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H)
AD5343 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H)
Slew Rate 0.7 V/µs
Major Code Transition Glitch Energy 6 nV-s 1 LSB Change Around Major Carry
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 3 nV-s
Analog Crosstalk 0.5 nV-s
DAC-to-DAC Crosstalk 3.5 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology section.
3
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
Specifications subject to change without notice.
MIN
1, 2, 3
, T
MAX
(VDD = 2.5 V to 5.5 V, All specifications T
Unit Condition/Comments
TIMING CHARACTERISTICS
Parameter Limit at T
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and
timed from a voltage level of (VIL + VIH)/2.
3
See Figure 1.
Specifications subject to change without notice.
0 ns min CS to WR Setup Time
0 ns min CS to WR Hold Time
20 ns min WR Pulsewidth
5 ns min Data, GAIN, BUF, HBEN Setup Time
4.5 ns min Data, GAIN, BUF, HBEN Hold Time
5 ns min Synchronous Mode. WR Falling to LDAC Falling
5 ns min Synchronous Mode. LDAC Falling to WR Rising
4.5 ns min Synchronous Mode. WR Rising to LDAC Rising
5 ns min Asynchronous Mode. LDAC Rising to WR Rising
4.5 ns min Asynchronous Mode. WR Rising to LDAC Falling
20 ns min LDAC Pulsewidth
20 ns min CLR Pulsewidth
50 ns min Time Between WR Cycles
20 ns min A0 Setup Time
0 ns min A0 Hold Time
= 2 V ± 0.1 V p-p. Unbuffered Mode
REF
= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
REF
to T
MIN
unless otherwise noted.)
MAX
REV. 0
Figure 1. Parallel Interface Timing Diagram
–3–
AD5332/AD5333/AD5342/AD5343
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to V
Digital Output Voltage to GND . . . . . –0.3 V to V
Reference Input Voltage to GND . . . . –0.3 V to V
V
to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
OUT
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . (T
θ
Thermal Impedance (20-Lead TSSOP) . . . . . 143°C/W
JA
max – TA)/θJA mW
J
θ
Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W
JA
θ
Thermal Impedance (28-Lead TSSOP) . . . . 97.9°C/W
JA
θ
Thermal Impedance (20-Lead TSSOP) . . . . . . 45°C/W
JC
Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W
θ
JC
θ
Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W
JC
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Package
Model Temperature Range Package Description Option
AD5332BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-20
AD5333BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5342BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28
AD5343BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5332/AD5333/AD5342/AD5343 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. 0
AD5332/AD5333/AD5342/AD5343
DB
DB
CS
WR
A0
CLR
LDAC
AD5332 FUNCTIONAL BLOCK DIAGRAM
V
A
REF
POWER-ON
RESET
DAC
REGISTER
DAC
REGISTER
8-BIT
DAC
8-BIT
V
REF
DAC
BUFFER
BUFFER
B
RESET
INPUT
REGISTER
INPUT
REGISTER
7
.
.
.
0
INTER-
FACE
LOGIC
V
DD
AD5332
POWER-DOWN
LOGIC
PD
GND
V
A
OUT
V
B
OUT
AD5332 PIN CONFIGURATION
8-BIT
20
DB
7
19
DB
6
18
DB
5
17
DB
4
DB
16
3
15
DB
2
14
DB
1
DB
13
0
12
V
DD
11
PD
V
REF
V
REF
V
OUT
V
OUT
GND
CLR
LDAC
B
A
A
B
CS
WR
A0
1
2
3
4
5
AD5332
TOP VIEW
6
(Not to Scale)
7
8
9
10
AD5332 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1V
2V
3V
4V
B Unbuffered reference input for DAC B.
REF
A Unbuffered reference input for DAC A.
REF
A Output of DAC A. Buffered output with rail-to-rail operation.
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
OUT
5 GND Ground reference point for all circuitry on the part.
6 CS Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7 WR Active low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8 A0 Address pin for selecting which DAC A and DAC B.
9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zeros.
10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
11 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
12 V
DD
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.
13–20 DB0–DB
7
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
REV. 0
–5–
AD5332/AD5333/AD5342/AD5343
BUF
GAIN
DB
DB
CS
WR
CLR
LDAC
AD5333 FUNCTIONAL BLOCK DIAGRAM
V
A
REF
POWER-ON
RESET
INPUT
RESET
REGISTER
INPUT
REGISTER
9
.
.
.
0
INTER-
FACE
LOGIC
A0
DAC
REGISTER
DAC
REGISTER
10-BIT
DAC
10-BIT
DAC
V
REF
BUFFER
B
V
DD
AD5333
POWER-DOWN
LOGIC
PD
GND
V
A
OUT
V
BBUFFER
OUT
AD5333 PIN CONFIGURATION
GAIN
BUF
V
REF
V
REF
V
OUT
V
OUT
GND
CLR
LDAC
B
A
A
B
CS
WR
A0
1
2
3
4
10-BIT
5
AD5333
6
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
24
DB
9
23
DB
8
22
DB
7
21
DB
6
20
DB
5
19
DB
4
18
DB
3
17
DB
2
16
DB
1
15
DB
0
14
V
DD
13
PD
AD5333 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V
or 0–2 V
REF
REF
.
2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
3V
4V
5V
6V
B Reference input for DAC B.
REF
A Reference input for DAC A.
REF
A Output of DAC A. Buffered output with rail-to-rail operation.
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
OUT
7 GND Ground reference point for all circuitry on the part.
8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 A0 Address pin for selecting between DAC A and DAC B.
11 CLR Asynchronous active-low control input that clears all input registers and DAC registers to zeros.
12 LDAC Active-low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14 V
DD
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.
15–24 DB0–DB
9
10 Parallel Data Inputs. DB9 is the MSB of these 10 bits.
–6–
REV. 0
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