2.5 V to 5.5 V, 250 µA, 2-Wire Interface
FEATURES
AD5337
2 buffered 8-bit DACs in 8-lead MSOP
AD5338, AD5338-1
2 buffered 10-bit DACs in 8-lead MSOP
AD5339
2 buffered 12-bit DACs in 8-lead MSOP
Low power operation: 250 mA @ 3 V, 300 mA @ 5 V
2-wire (I
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
3 power-down modes
Double-buffered input logic
Output range: 0 V to V
Power-on reset to 0 V
Simultaneous update of outputs (
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range −40°C to +105°C
2
C®compatible) serial interface
REF
LDAC
function)
Dual-Voltage Output, 8-/10-/12-Bit DACs
AD5337/AD5338/AD5339
GENERAL DESCRIPTION
AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit buffered
voltage output DACs in an 8-lead MSOP package, which
operate from a single 2.5 V to 5.5 V supply, consuming 250 µA
at 3 V. On-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/µs. A 2-wire serial interface operates at
clock rates up to 400 kHz. This interface is SMBus-compatible
< 3.6 V. Multiple devices can be placed on the same bus.
at V
DD
The references for the two DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software
power-on reset circuit that ensures that the DAC outputs power
up to 0 V and remain there until a valid write to the device
takes place. A software clear function resets all input and DAC
registers to 0 V. A power-down feature reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated
equipment. The power consumption is typically 1.5 mW at 5 V
and 0.75 mW at 3 V, reducing to 1 µW in power-down mode.
function. The parts incorporate a
LDAC
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
FUNCTIONAL BLOCK DIAGRAM
V
DD
LDAC
SCL
SDA
A0
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
INTERFACE
LOGIC
POWER-ON
RESET
INPUT
REGISTER
INPUT
REGISTER
AD5337/AD5338/AD5339
DAC
REGISTER
DAC
REGISTER
GND
Figure 1.
REFIN
STRING
DAC A
STRING
DAC B
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
BUFFER
BUFFER
POWER-DOWN
LOGIC
www.analog.com
V
A
OUT
V
B
OUT
03756-A-001
AD5337/AD5338/AD5339
TABLE OF CONTENTS
Specifications..................................................................................... 3
Serial Interface............................................................................ 15
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Te r mi n ol o g y ...................................................................................... 9
Typical Performance Characteristics ........................................... 11
Functional Description .................................................................. 15
Digital-to-Analog Converter Section ...................................... 15
Resistor String............................................................................. 15
DAC Reference Inputs ............................................................... 15
Output Amplifier........................................................................ 15
Power-on Reset ........................................................................... 15
REVISION HISTORY
Write Operation.......................................................................... 17
Read Operation........................................................................... 18
Double-Buffered Interface ........................................................ 19
Power-Down Modes .................................................................. 19
Applications..................................................................................... 20
Typical Application Ci r c u it ....................................................... 20
Bipolar Operation....................................................................... 20
Multiple Devices on One Bus ................................................... 20
Product as a Digitally Programmable Window Detector..... 21
Coarse and Fine Adjustment Capabilities............................... 21
Power Supply Decoupling ......................................................... 21
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
10/04—Changed Data Sheet from Rev. 0 to Rev. A
Updated Format..................................................................Universal
Added AD5338-1................................................................Universal
Changes to Specifications................................................................ 4
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide.......................................................... 24
11/03—Rev. 0: Initial Version
Rev. A | Page 2 of 24
AD5337/AD5338/AD5339
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; V
Table 1.
Grade A Grade B
Parameter
DC PERFORMANCE
DAC REFERENCE INPUTS5
OUTPUT CHARACTERISTICS5
5 5 µs
1
3, 4
AD5337
Resolution 8 8 Bits
Relative Accuracy ±0.15 ±1 ±0.15 ±0.5 LSB
Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB
AD5338
Resolution 10 10 Bits
Relative Accuracy ±0.5 ±4 ±0.5 ±2 LSB
Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.50 LSB
AD5339
Resolution 12 12 Bits
Relative Accuracy ±2 ±16 ±2 ±8 LSB
Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB
Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR
Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR
Lower Deadband 20 60 20 60 mV
Offset Error Drift
5
Gain Error Drift5
Power Supply Rejection
5
Ratio
DC Crosstalk5
V
Input Range 0.25 V
REF
V
Input Impedance 37 45 37 45 kΩ Normal operation
REF
>10 >10 MΩ Power-down mode
Reference Feedthrough −90 −90 dB Frequency = 10 kHz
Minimum Output Voltage6 0.001 0.001 V
Maximum Output
6
Voltage
DC Output Impedance 0.5 0.5 Ω
Short Circuit Current 25 25 mA VDD = 5 V
16 16 mA VDD = 3 V
Power-Up Time 2.5 2.5 µs
= 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T
REF
MIN
to T
, unless otherwise noted.
MAX
Min Typ Max Min Typ Max Unit B Version2 Conditions/Comments
Guaranteed monotonic by design over
all codes
Guaranteed monotonic by design over
all codes
Guaranteed monotonic by design over
all codes
Lower deadband exists only if offset error
is negative
ppm of
−12 −12
FSR/°C
ppm of
−5 −5
−60 −60 dB ∆V
200 200 µV R
FSR/°C
= ±10%
DD
= 2 kΩ to GND or V
L
DD
0.25 V
DD
V
This is a measure of the minimum and
maximum drive capabilities of the output
amplifier.
−
V
DD
0.001
−
V
DD
0.001
V
Coming out of power-down mode.
= 5 V
V
DD
Coming out of power-down mode.
= 3 V
V
DD
DD
Rev. A | Page 3 of 24
AD5337/AD5338/AD5339
Grade A Grade B
Parameter
LOGIC INPUTS (A0)5
LOGIC INPUTS (SCL, SDA)5
LOGIC OUTPUT (SDA)5
POWER REQUIREMENTS
1
For explanations of the specific parameters, see the Termin section. ology
2
Temperature range: (A and B versions): −40°C to +105°C; typical at 25°C.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5337 (Codes 8 to 248); AD5338, AD5338-1 (Codes 28 to 995); AD5339 (Codes 115 to 3981).
5
Guaranteed by design and characterization; not production tested.
6
For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V
positive.
7
I
DD
1
Min Typ Max Min Typ Max Unit B Version2 Conditions/Comments
Input Current ±1 ±1 µA
VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ±10%
0.6 0.6 V VDD = 3 V ±10%
0.5 0.5 V VDD = 2.5 V
VIH, Input High Voltage 2.4 2.4 V VDD = 5 V ±10%
2.1 2.1 V VDD = 3 V ±10%
2.0 2.0 V VDD = 2.5 V
Pin Capacitance 3 3 pF
VIH, Input High Voltage 0.7
V
VIL, Input Low Voltage −0.3 +0.3
V
DD
0.3
V
+
DD
0.7
V
–0.3 +0.3
DD
V
DD
0.3
V
+
DD
V SMBus-compatible at VDD < 3.6 V
V SMBus-compatible at VDD < 3.6 V
DD
IIN, Input Leakage Current ±1 ±1 µA
V
, Input Hysteresis 0.05
HYST
V
0.05
DD
V
V
DD
CIN, Input Capacitance 8 8 pF
Glitch Rejection 50 50 ns Input filtering suppresses noise spikes of
less than 50 ns
V
Output Low Voltage 0.4 0.4 V I
OL,
0.6 0.6 V I
Three-State Leakage
±1 ±1 µA
= 3 mA
SINK
= 6 mA
SINK
Current
Three-State Output
8 8 pF
Capacitance
V
DD
IDD (Normal Mode)
7
2.5 5.5 2.5 5.5 V
V
= VDD and VIL = GND
IH
VDD = 4.5 V to 5.5 V 300 375 300 375 µA
VDD = 2.5 V to 3.6 V 250 350 250 350 µA
IDD (Power-Down Mode) VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V 0.2 1.0 0.2 1.0 µA IDD = 4 µA (max) during 0 readback
on SDA
VDD = 2.5 V to 3.6 V 0.08 1.00 0.08 1.00 µA IDD = 1.5 µA (max) during 0 readback
on SDA
= V
and offset plus gain error must be
REF
DD
specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Rev. A | Page 4 of 24
AD5337/AD5338/AD5339
AC CHARACTERISTICS
1
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T
MIN
to T
, unless otherwise noted.
MAX
Table 2.
A and B Versions
Parameter
3
Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time V
2
= VDD = 5 V
REF
AD5337 6 8 µs 1/4 scale to 3/4 scale change (0x40 to 0xC0)
AD5338 7 9 µs 1/4 scale to 3/4 scale change (0x100 to 0x300)
AD5339 8 10 µs 1/4 scale to 3/4 scale change (0x400 to 0xC00)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB change around major carry
Digital Feedthrough 1 nV-s
Digital Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion −70 dB V
= 2 V ± 0.1 V p-p
REF
= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
REF
1
Guaranteed by design and characterization; not production tested.
2
Temperature range: A and B versions: −40°C to +105°C; typical at 25°C.
3
For explanations of the specific parameters, see the Termin section. ology
Rev. A | Page 5 of 24
AD5337/AD5338/AD5339
S
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V. All specifications T
Table 3.
MIN
, T
Parameter
f
SCL
t
1
t
2
t
3
t
4
t
5
1
t
6
Limit at T
(A and B Versions)
400 kHz max SCL clock frequency
2.5 µs min SCL cycle time
0.6 µs min t
1.3 µs min t
0.6 µs min t
100 ns min t
0.9 µs max t
0 µs min t
t
7
t
8
t
9
t
10
0.6 µs min t
0.6 µs min t
1.3 µs min t
300 ns max tR, rise time of SCL and SDA when receiving
0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible)
t
11
250 ns max tF, fall time of SDA when transmitting
0 ns min tF, fall time of SDA when receiving (CMOS-compatible)
300 ns max tF, fall time of SCL and SDA when receiving
20 + 0.1 C
C
B
400 pF max Capacitive load for each bus line
2
B
1
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
falling edge.
2
CB is the total capacitance of one bus line in pF; t
MAX
MIN
to T
, unless otherwise noted.
MAX
Unit Conditions/Comments
ns min tF, fall time of SCL and SDA when transmitting
and tF measured between 0.3 V
R
, SCL high time
HIGH
, SCL low time
LOW
, start/repeated start condition hold time
HD, STA
, data setup time
SU, DAT
, data hold time
HD, DAT
, data hold time
HD, DAT
, setup time for repeated start
SU, STA
, stop condition setup time
SU, STO
, bus free time between a stop and a start condition
BUF
min of the SCL signal) in order to bridge the undefined region of SCL’s
IH
and 0.7 VDD.
DD
DA
SCL
t
9
START
CONDITION
t
3
t
4
t
10
t
6
t
t
11
2
t
5
REPEATED
CONDITION
t
START
t
4
t
7
1
t
8
STOP
CONDITION
03756-A-002
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. A | Page 6 of 24
AD5337/AD5338/AD5339
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +7 V
SCL, SDA to GND −0.3 V to VDD + 0.3 V
A0 to GND −0.3 V to VDD + 0.3 V
Reference Input Voltage to GND −0.3 V to VDD + 0.3 V
V
A−V
OUT
Operating Temperature Range
Industrial (B Version) −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
MSOP Package
Power Dissipation (TJ max − TA)θ
θJA Thermal Impedance 206°C/W
θJC Thermal Impedance 44°C/W
Reflow Soldering
Peak Temperature 220 +5/−0°C
Time at Peak Temperature 10 s to 40 s
B to GND −0.3 V to VDD + 0.3 V
OUT
JA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 7 of 24
AD5337/AD5338/AD5339
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
DD
1
AD5337/
AD5338/
2
V
A
OUT
V
OUT
REFIN
B
3
4
AD5339
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Function
1 V
2 V
3 V
DD
A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
OUT
B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
OUT
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.
4 REFIN Reference Input Pin for the Two DACs. It has an input range from 0.25 V to VDD.
5 GND Ground Reference Point for All Circuitry on the Parts.
6 SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift
register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up
resistor.
7 SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift
register. Clock rates of up to 400 kbps can be accommodated in the 2-wire interface.
8 A0 Address Input. Sets the least significant bit of the 7-bit slave address.
8
A0
7
SCL
6
SDA
GND
5
03756-A-003
Rev. A | Page 8 of 24
AD5337/AD5338/AD5339
TERMINOLOGY
Relative Accuracy (Integral Nonlinearity, INL)
For the DAC, relative accuracy, or integral nonlinearity (INL),
is a measure, in LSBs, of the maximum deviation from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL vs. code plots can be seen in Figure 6, Figure 7, and
Figure 8.
Major-Code Transition Glitch Energy
The energy of the impulse injected into the analog output when
the code in the DAC register changes state. Normally specified
as the area of the glitch in nV-s and is measured when the
digital code is changed by 1 LSB at the major carry transition
(011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified differential
nonlinearity of ±1 LSB maximum ensures monotonicity. This
DAC is guaranteed monotonic by design. Typical DNL vs. code
plots can be seen in Figure 9, Figure 10, and Figure 11.
Offset Error
A measure of the offset error of the DAC and the output
amplifier, expressed as a percentage of the full-scale range.
Gain Error
A measure of the span error of the DAC. It is the deviation in
slope of the actual DAC transfer characteristic from the ideal,
expressed as a percentage of the full-scale range.
Offset Error Drift
A measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error Drift
A measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
a change in V
in dB. V
for full-scale output of the DAC. It is measured
DD
is held at 2 V and VDD is varied ±10%.
REF
OUT
to
Digital Feedthrough
A measure of the impulse injected into the analog output of the
DAC from the digital input pins of the device when the DAC
output is not being updated. Specified in nV-s and measured
with a worst-case change on the digital input pins, such as
changing from all 0s to all 1s or vice-versa.
Digital Crosstalk
The glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s, or
vice versa) in the input register of another DAC. It is expressed
in nV-s.
DAC-to-DAC Crosstalk
The glitch impulse transferred to the output of one DAC due to
a digital code change and subsequent output change of another
DAC. This includes both digital and analog crosstalk. It is
measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s, or vice versa) with the
LDAC
bit set low
and monitoring the output of another DAC. The energy of the
glitch is expressed in nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output.
DC Crosstalk
The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in µV.
Reference Feedthrough
The ratio of the amplitude of the signal at the DAC output to
the reference input when the DAC output is not being updated.
It is expressed in dB.
Rev. A | Page 9 of 24
Total Harmonic Distortion (THD)
The difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonic
distortion present in the DAC output. It is measured in dB.
AD5337/AD5338/AD5339
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
ERROR
AMPLIFIER
FOOTROOM
(1mV)
NEGATIV
OFFSET
ERROR
E
IDEAL
DAC CODE
D
A
E
D
B
A
D
N
S
E
C
D
O
ACTUAL
GAIN ERROR
PLUS
OFFSET ERROR
ACTUAL
OUTPUT
VOLTAGE
IDEAL
POSITIVE
OFFSET
DAC CODE
Figure 5. Transfer Function with Positive Offset
GAIN ERROR
PLUS
OFFSET ERROR
03756-A-005
03756-A-004
Figure 4. Transfer Function with Negative Offset
Rev. A | Page 10 of 24
AD5337/AD5338/AD5339
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.5
TA = 25°C
VDD = 5V
0.3
0.2
0.1
TA = 25°C
VDD = 5V
0
INL ERROR (LSB)
–0.5
–1.0
0 50 100 150 200 250
CODE
Figure 6. AD5337 Typical INL Plot
3
TA = 25°C
V
= 5V
DD
2
1
0
INL ERROR (LSB)
–1
–2
–3
0 200 400 600 800 1000
CODE
Figure 7. AD5338 Typical INL Plot
0
–0.1
DNL ERROR (LSB)
–0.2
–0.3
0 50 100 150 200 250
03756-A-006
CODE
03756-A-009
Figure 9. AD5337 Typical DNL Plot
0.6
TA = 25°C
V
= 5V
DD
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
0 200 400 600 800 1000
03756-A-007
Figure 10. AD5338 Typical DNL Plot
CODE
03756-A-010
12
8
4
0
INL ERROR (LSB)
–4
–8
–12
TA = 25°C
= 5V
V
DD
20001500500 10000 2500 3000 3500 4000
CODE
Figure 8. AD5339 Typical INL Plot
03756-A-008
Rev. A | Page 11 of 24
1.0
TA = 25°C
= 5V
V
DD
0.5
0
DNL ERROR (LSB)
–0.5
–1.0
20001500500 10000 2500 3000 3500 4000
CODE
Figure 11. AD5339 Typical DNL Plot
03756-A-011
AD5337/AD5338/AD5339
0.50
TA = 25°C
= 5V
V
DD
0.25
MAX DNL
MAX INL
0
ERROR (LSB)
MIN DNL
0.2
0.1
0
–0.1
–0.2
ERROR (%)
–0.3
TA = 25°C
V
= 2V
REF
GAIN ERROR
–0.25
–0.50
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
MIN INL
(V)
V
REF
Figure 12. AD5337 INL and DNL Error vs. V
0.5
VDD = 5V
0.4
0.3
0.2
0.1
–0.1
ERROR (LSB)
–0.2
–0.3
–0.4
–0.5
= 3V
V
REF
0
MAX DNL
MIN INL
0–40 40 80 120
TEMPERATURE (°C)
Figure 13. AD5337 INL and DNL Error vs. Temperature
MAX INL
MIN DNL
–0.4
–0.5
–0.6
03756-A-012
REF
Figure 15. Offset Error and Gain Error vs. V
OFFSET ERROR
2301 456
(V)
V
DD
DD
03756-A-015
5
5V SOURCE
4
3
(V)
OUT
V
2
1
0
03756-A-013
Figure 16. V
3V SOURCE
5V SINK
3V SINK
2301 456
SINK/SOURCE CURRENT (mA)
Source and Sink Current Capability
OUT
03756-A-016
1.0
VDD = 5V
V
= 2V
REF
0.5
0
ERROR (%)
–0.5
–1.0
GAIN ERROR
0–40 40 80 120
TEMPERATURE (°C)
Figure 14. AD5337 Offset Error and Gain Error vs. Temperature
OFFSET ERROR
03756-A-014
Rev. A | Page 12 of 24
300
250
200
A)
µ
150
(
DD
I
100
50
TA = 25°C
V
= 5V
DD
= 2V
V
REF
0
ZERO SCALE FULL SCALE
CODE
Figure 17. Supply Current vs. Code
03756-A-017
AD5337/AD5338/AD5339
300
–40°C
250
+25°C
200
A)
µ
150
(
DD
I
100
50
+105°C
CH1
CH2
TA = 25°C
= 5V
V
DD
= 5V
V
REF
V
SCL
OUT
A
0
3.5 4.02.5 3.0 4.5 5.0 5.5
(V)
V
DD
03756-A-018
Figure 18. Supply Current vs. Supply Voltage
0.5
0.4
0.3
A)
µ
(
DD
I
0.2
0.1
0
+25°C
3.5 4.02.5 3.0 4.5 5.0 5.5
(V)
V
DD
–40°C
+105°C
03756-A-019
Figure 19. Power-Down Current vs. Supply Voltage
400
TA = 25°C
350
300
DECREASING
250
A)
µ
200
(
DD
I
150
VDD = 3V
VDD = 5V
INCREASING
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
Figure 21. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
TA = 25°C
V
= 5V
DD
= 2V
V
REF
CH1
V
DD
V
A
OUT
CH2
CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV
Figure 22. Power-On Reset to 0 V
TA = 25°C
= 5V
V
DD
V
= 2V
REF
CH1
V
A
OUT
SCL
03756-A-021
03756-A-022
100
50
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
V
LOGIC
Figure 20. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage
Increasing and Decreasing
Rev. A | Page 13 of 24
CH2
03756-A-020
CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV
03756-A-023
Figure 23. Existing Power-Down to Midscale
AD5337/AD5338/AD5339
0.02
TA = 25°C
V
= 5V
DD
VDD = 5VVDD = 3V
FREQUENCY
150 200 250 300
Figure 24. I
IDD (µA)
Histogram with VDD = 3 V and VDD = 5 V
DD
03756-A-024
2.50
2.49
(V)
OUT
V
2.48
0.01
0
FULL-SCALE ERROR (V)
–0.01
–0.02
2301 456
(V)
V
REF
Figure 27. Full-Scale Error vs. V
REF
03756-A-027
1mV/DIV
2.47
1µs/DIV
Figure 25. AD5339 Major-Code Transition Glitch Energy
10
0
–10
–20
dB
–30
–40
–50
–60
Figure 26. Multiplying Bandwidth (Small-Signal Frequency Response)
1k 10k10 100 100k 1M 10M
FREQUENCY (Hz)
03756-A-025
50ns/DIV
03756-A-028
Figure 28. DAC-to-DAC Crosstalk
03756-A-026
Rev. A | Page 14 of 24
AD5337/AD5338/AD5339
FUNCTIONAL DESCRIPTION
The AD5337/AD5338/AD5339 are dual resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and
12 bits, respectively. Each contains two output buffer amplifiers
and is written to via a 2-wire serial interface. The DACs operate
from single supplies of 2.5 V to 5.5 V, and the output buffer
amplifiers provide rail-to-rail output swing with a slew rate of
0.7 V/µs. The two DACs share a single reference input pin.
Each DAC has three programmable power-down modes that
allow the output amplifier to be configured with either a 1 kΩ
load to ground, a 100 kΩ load to ground, or as a high
impedance three-state output.
DIGITAL-TO-ANALOG CONVERTER SECTION
The architecture of one DAC channel consists of a resistorstring DAC followed by an output buffer amplifier. The voltage
at the REFIN pin provides the reference voltage for the DAC.
Figure 29 shows a block diagram of the DAC architecture.
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
DV
×
V
OUT
REF
=
where:
D is the decimal equivalent of the binary code, which is loaded
to the DAC register;
0–255 for AD5337 (8 bits)
0–1023 for AD5338 and AD5338-1 (10 bits)
0–4095 for AD5339 (12 bits)
N is the DAC resolution
N
2
REFIN
DAC REFERENCE INPUTS
There is a single reference input pin for the two DACs. The
reference input is unbuffered. The user can have a reference
voltage as low as 0.25 V and as high as V
restriction due to headroom and foot room of any reference
amplifier.
It is recommended to use a buffered reference in the external
circuit, for example, REF192. The input impedance is typically
45 kΩ.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, which gives an output range of 0 V to
when the reference is VDD. The amplifier is capable of
V
DD
driving a load of 2 kΩ to GND or V
GND or V
amplifier can be seen in the plot in Figure 16.
The slew rate is 0.7 V/µs with a half-scale settling time to
±0.5 LSB (at 8 bits) of 6 µs.
R
R
R
R
R
Figure 30. Resistor String
. The source and sink capabilities of the output
DD
TO OUTPUT
AMPLIFIER
03756-A-030
, since there is no
DD
in parallel with 500 pF to
DD
INPUT
REGISTER
DAC
REGISTER
Figure 29. DAC Channel Architecture
RESISTOR
STRING
OUTPUT BUFFER
AMPLIFIER
V
OUT
RESISTOR STRING
The resistor string portion is shown in Figure 30. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines the node at which the voltage is
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches that connects the
string to the amplifier. Because the DAC comprises a string
of resistors, it is guaranteed to be monotonic.
Rev. A | Page 15 of 24
A
POWER-ON RESET
The AD5337/AD5338/AD5339 power on in a defined state via a
power-on reset function. The power-on state is normal
03756-A-029
operation, with output voltage set to 0 V.
Both input and DAC registers are filled with zeros until a valid
write sequence is made to the device. This is particularly useful
in applications where it is important to know the state of the
DAC outputs while the device is powering on.
SERIAL INTERFACE
The AD5337/AD5338/AD5339 are controlled via an I2Ccompatible serial bus. The DACs are connected to this bus as
slave devices—that is, no clock is generated by the AD5337/
AD5338/AD5339 DACs. This interface is SMBus-compatible at
< 3.6 V.
V
DD
AD5337/AD5338/AD5339
The AD5337/AD5338/AD5339 have a 7-bit slave address. The
six MSBs are 000110, and the LSB is determined by the state of
the A0 pin. The facility of making hardwired changes to A0
allows the use of one or two of these devices on one bus. The
AD5338-1 has a unique 7-bit slave address. The six MSBs are
010001, and the LSB is again determined by the state of the A0
pin. Using a combination of AD5338 and AD5338-1 allows the
user to accommodate four of these dual 10-bit devices (eight
channels) on the same bus.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address, followed by
bit. (This bit determines whether data is read from
an R/
W
or written to the slave device.)
The slave with the address corresponding to the transmitted
address responds by pulling SDA low during the ninth
clock pulse (this is termed the acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its shift register.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits, followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high period
of SCL.
3. When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition. In read mode, the master issues a No
Acknowledge for the ninth clock pulse, that is, the SDA
line remains high. The master then brings the SDA line low
before the 10th clock pulse and high during the 10th clock
pulse to establish a stop condition.
Read/Write Sequence
For the AD5337/AD5338/AD5339, all write access sequences
and most read sequences begin with the device address (with
= 0), followed by the pointer byte. This pointer byte specifies
R/
W
the data format and determines which DAC is being accessed in
the subsequent read/write operation. See Figure 31. In a write
operation, the data follows immediately. In a read operation, the
address is resent with R/
= 1, and then the data is read back.
W
However, it is also possible to perform a read operation by
sending only the address with R/
= 1. The previously loaded
W
pointer settings are then used for the read back operation. See
Figure 32 for a graphical explanation of the interface.
LSBMSB
0
X
X
0
DOUBLE = 0
Figure 31. Pointer Byte
0 DACB DACA
The following table explains the individual bits that make up
the pointer byte.
Table 6. Pointer Byte Bits
Pointer Byte Bits
X Don’t care bits.
0: Bit set to 0.
DOUBLE 0: Data write and readback are done as 2-byte
write/read sequences.
0: Bit set to 0.
0: Bit set to 0.
DACB 1: The following data bytes are for DAC B.
DACA 1: The following data bytes are for DAC A.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as two data bytes on the serial data line, SDA, under the
control of the serial clock input, SCL. The timing diagram for
this operation is shown in Figure 2. The two data bytes consist
of four control bits followed by 8, 10, or 12 bits of DAC data,
depending on the device type. The first two bits loaded are PD1
and PD0 bits that control the mode of operation of the device.
See the Power-Down Modes section for a complete description.
Bit 13 is
CLR
, Bit 12 is
, and the remaining bits are left-
LDAC
justified DAC data bits, starting with the MSB. See Figure 32.
Table 7. Input Shift Register
Register Setting and Result
CLR 0: All DAC registers and input registers are filled with
0s on completion of the write sequence.
1: Normal operation.
LDAC 0: The two DAC registers and therefore all DAC
outputs simultaneously updated on completion of
the write sequence.
1: Addressed input register only is updated. There is
no change in the contents of the DAC registers.
Default Read Back Condition
All pointer byte bits power-up to 0. Therefore, if the user
initiates a readback without writing to the pointer byte first, no
single DAC channel has been specified. In this case, the default
readback bits are all 0, except for the
bit, which is 1.
CLR
Multiple-DAC Write Sequence
Because there are individual bits in the pointer byte for each
DAC, it is possible to write the same data and control bits to two
DACs simultaneously by setting the relevant bits to 1.
03756-A-031
Rev. A | Page 16 of 24
AD5337/AD5338/AD5339
Multiple-DAC Read Back Sequence.
If the user attempts to read back data from more than one DAC
at a time, the part reads back the default, power-on reset
conditions, i.e., all 0s except for
, which is 1.
CLR
WRITE OPERATION
When writing to the AD5337/AD5338/AD5339 DACs, the user
must begin with an address byte (R/
DAC acknowledges that it is prepared to receive data by pulling
SDA low. This address byte is followed by the pointer byte,
which is also acknowledged by the DAC. Two bytes of data are
then written to the DAC, as shown in Figure 33. A stop
condition follows.
MSB
MSB
MSB
PD1
MOST SIGNIFICANT DATA BYTE
PD0
CLR LDAC
PD0
CLR
CLR
PD0 D11 D10 D9
SCL
= 0), after which the
W
8-BIT AD5337
D7 D6 D5 D4PD1
10-BIT AD5338
D9 D8 D7 D6PD1
LDAC
12-BIT AD5339
LDAC
LSB
LSB
LSB
D8
Figure 32. Data Formats for Write and Read Back
MSB
D3 D2 D1
MSB
D5
MSB
D7 D6
LEAST SIGNIFICANT DATA BYTE
D4
8-BIT AD5337
D0 X
10-BIT AD5338
D2 D1 D0 X X
D3
12-BIT AD5339
D4 D3 D2 D1 D0
D5
LSB
XXX
LSB
LSB
03756-A-032
SDA
START
CONDITION
BY
MASTER
SCL
SDA
00011 A0
ADDRESS BYTE
MSB LSB MSB LSB
MOST SIGNIFICANT DATA BYTE
0
R/W
ACK
BY
AD533x
ACK
BY
AD533x
XX LSB
MSB
POINTER BYTE
LEAST SIGNIFICANT DATA BYTE
Figure 33. Write Sequence
ACK
BY
AD533x
ACK
BY
AD533x
STOP
CONDITION
BY
MASTER
03756-A-033
Rev. A | Page 17 of 24
AD5337/AD5338/AD5339
READ OPERATION
When reading data back from the AD5337/AD5338/AD5339
DACs, the user begins with an address byte (R/
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. This address byte is usually followed by the
pointer byte, which is also acknowledged by the DAC. Then the
master initiates another start condition (repeated start) and the
address is resent with R/
= 1. This is acknowledged by the
W
DAC indicating that it is prepared to transmit data. Two bytes
of data are then read from the DAC as shown in Figure 34. A
stop condition follows. Note that in a read sequence, data bytes
are the same as those in the write sequence except that don’t
SCL
= 0), after
W
cares are read back as 0. However, if the master sends an ACK
and continues clocking SCL (no stop is sent), the DAC
retransmits the same two bytes of data on SDA. This allows
continuous read back of data from the selected DAC register.
Alternatively, the user may send a start followed by the address
with R/
= 1. In this case, the previously loaded pointer
W
settings are used and read back of data can begin immediately.
SDA
CONDITION
MASTER
SCL
SDA
SCL
SDA
START
BY
00 0 11 A0 R/W X X
00 0 11
REPEATED
START
CONDITION
BY
MASTER
MSB LSB
ADDRESS BYTE
LEAST SIGNIFICANT DATA BYTE
0
MSB
ACK
BY
AD533x
0
R/W MSB
A0
NO
ACK
BY
MASTER
ACK
BY
AD533x
Figure 34. Read Sequence
STOP
CONDITION
BY
MASTER
LSB
ACK
POINTER BYTEADDRESS BYTE
DATABYTE
BY
AD533x
LSB
ACK
BY
MASTER
03756-A-034
Rev. A | Page 18 of 24
AD5337/AD5338/AD5339
DOUBLE-BUFFERED INTERFACE
The AD5337/AD5338/AD5339 DACs all have a double-buffered
interface consisting of two banks of registers—an input register
and a DAC register per channel. The input register is directly
connected to the input shift register, and the digital code is
transferred to the relevant input register upon completion of a
valid write sequence. The DAC register contains the digital code
used by the resistor string.
Access to the DAC register is controlled by the
the
bit is set high, the DAC register is latched and therefore
LDAC
the input register may change state without affecting the DAC
register. This is useful if the user requires simultaneous updating
of all DAC outputs. The user may write to three of the input
registers individually; by setting the
bit low when writing
LDAC
to the remaining DAC input register, all outputs will update
simultaneously.
LDAC
bit. When
When both bits are 0, the DAC works with its normal power
consumption of 300 µA at 5 V. However, for the three powerdown modes, the supply current falls to 200 nA at 5 V (80 nA at
3 V). Not only does the supply current drop, but the output
stage is also internally switched from the output of the amplifier
to a resistor network of known values. This is advantageous in
that the output impedance of the part is known while the part is
in power-down mode, which provides a defined input condition
for whatever is connected to the output of the DAC amplifier.
There are three options. The output may be connected internally
to GND through a 1 kΩ resistor, a 100 kΩ resistor, or may be
left open-circuited (3-state). Resistor tolerance = ±20%. The
output stage is illustrated in Figure 35.
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
These parts contain an extra feature whereby the DAC register
is only updated if its input register has been updated since the
last time that
was brought low, thereby removing
LDAC
unnecessary digital crosstalk.
POWER-DOWN MODES
The AD5337/AD5338/AD5339 have very low power
consumption, typically dissipating 0.75 mW with a 3 V supply
and 1.5 mW with a 5 V supply. Power consumption can be
further reduced when the DACs are not in use by putting them
into one of three power-down modes, which are selected by
Bits 15 and 14 (PD1 and PD0) of the data byte. Table 8 shows
how the state of the bits corresponds to the mode of operation
of the DAC.
Table 8. PD1/PD0 Operating Modes
PD1 PD0 Operating Mode
0 0 Normal Operation
0 1 Power-Down (1 kΩ Load to GND)
1 0 Power-Down (100 kΩ Load to GND)
1 1 Power-Down (3-State Output)
POWER-DOWN
CIRCUITRY
Figure 35. Output Stage during Power-Down
RESISTOR
NETWORK
03756-A-035
The bias generator, the output amplifiers, the resistor string, and
all other associated linear circuitry are shut down when powerdown mode is activated. However, the contents of the DAC
registers remain unchanged when power-down mode is activated.
The time to exit power-down is typically 2.5 µs for V
and 5 µs when V
= 3 V. This is the time from the rising edge
DD
= 5 V
DD
of the eighth SCL pulse to the time when the output voltage
deviates from its power-down voltage. See Figure 23 for a plot.
Rev. A | Page 19 of 24
AD5337/AD5338/AD5339
A
(
(
(
(
[
APPLICATIONS
TYPICAL APPLICATION CIRCUIT
The AD5337/AD5338/AD5339 can be used with a wide range of
reference voltages for full, one-quadrant multiplying capability
over a reference range of 0 V to V
devices are used with a fixed precision reference voltage.
Suitable references for 5 V operation are the AD780, the REF192,
and the ADR391 (2.5 V references). For 2.5 V operation, a
suitable external reference would be the AD589 or AD1580, a
1.23 V band gap reference. Figure 36 shows a typical setup for
the AD5337/AD5338/AD5339 when using an external reference.
Note that A0 can be high or low.
OUT
10µF
1µF
SERIAL
INTERFACE
0.1µF
V
IN
V
EXT
REF
D780/REF192/ADR391
WITH V
= 5V OR
DD
AD589/AD1580 WITH
VDD = 2.5V
Figure 36. AD5337/AD5338/AD5339 Using External Reference
If an output range of 0 V to VDD is required, the simplest
solution is to connect the reference input to V
supply may be inaccurate and noisy, the AD5337/AD5338/
AD5339 may be powered from a reference voltage, for example,
using a 5 V reference such as the REF195 which provides a
steady output supply voltage. With no load on the DACs, the
REF195 is required to supply 600 µA supply current to the DAC
and 112 µA to the reference input. When the DAC outputs are
loaded, the REF195 also needs to supply the current to the
loads; therefore, the total current required with a 10 kΩ load on
each output is
712 µA + 2(5 V/10 kΩ) = 1.7 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 3.4 ppm (17 µV) for the 1.7 mA
current drawn from it. This corresponds to a 0.0009 LSB error
at 8 bits and a 0.014 LSB error at 12 bits.
. More typically, these
DD
VDD = 2.5V TO 5.5V
AD5337/
AD5338/
AD5339
REFIN
SCL
SDA
A0
GND
DD
V
A
OUT
B
V
OUT
. Because this
03756-A-036
BIPOLAR OPERATION
The AD5337/AD5338/AD5339 are designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 37. This circuit gives an output voltage range of
±5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
R2 = 10kΩ
6V TO 12V
10µF
AD1585
V
IN
GND
R1 = 10kΩ
0.1µF
+5V
V
DD
V
OUT
AD5339
V
OUT
REFIN
1
µ
F
A0
GND
V
OUT
SC
L
SD
2-WIRE
SERIAL
INTERFACE
A
+5V
AD820/
OP295
A
–5V
B
±5V
03756-A-037
Figure 37. Bipolar Operation with the AD5339
The output voltage for any input code can be calculated as
follows:
OUT
)
)
)
121212 RRREFINRRRDREFINV
×−+×
N
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
REFIN is the reference voltage input.
With REFIN = 5 V, R1 = R2 = 10 kΩ:
V
= (10 × D/2N) − 5
OUT
MULTIPLE DEVICES ON ONE BUS
Figure 38 shows two AD5339 devices on the same serial bus.
Each has a different slave address because the state of the A0 pin
is different. This allows each of four DACs to be written to or
read from independently.
V
DD
PULL-UP
RESISTORS
A0
SDA
AD5339
SCL
)
]
MICROCONTROLLER
SCL
SDA
A0
AD5339
03756-A-038
Figure 38. Multiple AD5339 Devices on One Bus
Rev. A | Page 20 of 24
AD5337/AD5338/AD5339
PRODUCT AS A DIGITALLY PROGRAMMABLE WINDOW DETECTOR
Figure 39 shows a digitally programmable upper/lower limit
detector using the two DACs in the AD5337/AD5338/AD5339.
The upper and lower limits for the test are loaded into DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the V
input is not within the programmed window,
IN
an LED indicates the fail condition.
5V
0.1µF
V
REF
REFIN
10µF
V
DD
V
OUT
AD5337/
AD5338/
DIN
SCL
*ADDITIONAL PINS OMITTED FOR CLARITY
SDA
SCL
AD5339*
GND
V
OUT
Figure 39. Window Detection
V
IN
A
1/2
CMP04
B
1k
Ω
FAIL
PASS/FAIL
1/6 74HC05
1k
Ω
PASS
COARSE AND FINE ADJUSTMENT CAPABILITIES
The two DACs in the AD5337/AD5338/AD5339 can be paired
together to form a coarse and fine adjustment function, as
shown in Figure 40. DAC A is used to provide the coarse
adjustment while DAC B provides the fine adjustment. Varying
the ratio of R1 and R2 changes the relative effect of the coarse
and fine adjustments. With the resistor values and external
reference shown, the output amplifier has unity gain for the
DAC A output, thus the output range is 0 V to 2.5 V − 1 LSB.
For DAC B the amplifier has a gain of 7.6 × 10
a range equal to 19 mV.
The circuit is shown with a 2.5 V reference, but reference
voltages up to V
may be used. The op amps indicated will
DD
allow a rail-to-rail output swing.
0.1µF
VDD = 5V
10µF
R3
51.2kΩ
–3
, giving DAC B
R4
390Ω
5V
03756-A-039
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5337/AD5338/AD5339 is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5337/AD5338/AD5339
is in a system where multiple devices require an AGND-toDGND connection, the connection should be made at one
point only. The star ground point should be established as close
as possible to the device. The AD5337/AD5338/AD5339 should
have ample supply bypassing of 10 µF in parallel with 0.1 µF on
the supply located as close to the package as possible, ideally
right up against the device. The 10 µF capacitors are the tantalum
bead type. The 0.1 µF capacitor should have low effective series
resistance (ESR) and low effective series inductance (ESI) to
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching. The
power supply lines of the AD5337/AD5338/ AD5339 should use
as large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
they should never be run near the reference inputs. A ground
line routed between the SDA and SCL lines helps to reduce
crosstalk between them. This is not required on a multilayer
board because there is a separate ground plane, but separating
the lines does help.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. Using a
microstrip technique is the best solution, but its use is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground plane,
while signal traces are placed on the solder side.
V
IN
EXT
REF
VOUT
GND
1µF
REFIN
AD5337/
AD5338/
AD780/REF192/ADR391
= 5V
WITH V
DD
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5339*
Figure 40. Coarse/Fine Adjustment
V
DD
GND
V
A
V
OUT
R1
390Ω
V
B
OUT
R2
51.2kΩ
AD820/
OP295
OUT
03756-A-039
Rev. A | Page 21 of 24
AD5337/AD5338/AD5339
Table 9. Overview of All AD53xx Serial Devices
Part No. Resolution No. of DACs DNL Interface Settling Time Package Pins
Singles
AD5300 8 1 ±0.25 SPI 4 µs SOT-23, MSOP 6, 8
AD5310 10 1 ±0.50 SPI 6 µs SOT-23, MSOP 6, 8
AD5320 12 1 ±1.00 SPI 8 µs SOT-23, MSOP 6, 8
AD5301 8 1 ±0.25 2-Wire 6 µs SOT-23, MSOP 6, 8
AD5311 10 1 ±0.50 2-Wire 7 µs SOT-23, MSOP 6, 8
AD5321 12 1 ±1.00 2-Wire 8 µs SOT-23, MSOP 6, 8
Duals
AD5302 8 2 ±0.25 SPI 6 µs MSOP 8
AD5312 10 2 ±0.50 SPI 7 µs MSOP 8
AD5322 12 2 ±1.00 SPI 8 µs MSOP 8
AD5303 8 2 ±0.25 SPI 6 µs TSSOP 16
AD5313 10 2 ±0.50 SPI 7 µs TSSOP 16
AD5323 12 2 ±1.00 SPI 8 µs TSSOP 16
AD5337 8 2 ±0.25 2-Wire 6 µs MSOP 8
AD5338 10 2 ±0.50 2-Wire 7 µs MSOP 8
AD5338-1 10 2 ±0.50 2-Wire 7 µs MSOP 8
AD5339 12 2 ±1.00 2-Wire 8 µs MSOP 8
Quads
AD5304 8 4 ±0.25 SPI 6 µs MSOP 10
AD5314 10 4 ±0.50 SPI 7 µs MSOP 10
AD5324 12 4 ±1.00 SPI 8 µs MSOP 10
AD5305 8 4 ±0.25 2-Wire 6 µs MSOP 10
AD5315 10 4 ±0.50 2-Wire 7 µs MSOP 10
AD5325 12 4 ±1.00 2-Wire 8 µs MSOP 10
AD5306 8 4 ±0.25 2-Wire 6 µs TSSOP 16
AD5316 10 4 ±0.50 2-Wire 7 µs TSSOP 16
AD5326 12 4 ±1.00 2-Wire 8 µs TSSOP 16
AD5307 8 4 ±0.25 SPI 6 µs TSSOP 16
AD5317 10 4 ±0.50 SPI 7 µs TSSOP 16
AD5327 12 4 ±1.00 SPI 8 µs TSSOP 16
Octals
AD5308 8 8 ±0.25 SPI 6 µs TSSOP 16
AD5318 10 8 ±0.50 SPI 7 µs TSSOP 16
AD5328 12 8 ±1.00 SPI 8 µs TSSOP 16
Visit our website at www.analog.com/support/standard_linear/selection_guides/AD53xx.htm
Rev. A | Page 22 of 24
AD5337/AD5338/AD5339
Table 10. Overview of AD53xx Parallel Devices
Part No. Resolution DNL V
Singles BUF GAIN HBEN
AD5330 8 ±0.25 1 6 µs √ √ √ TSSOP 20
AD5331 10 ±0.50 1 7 µs √ √ TSSOP 20
AD5340 12 ±1.00 1 8 µs √ √ √ TSSOP 24
AD5341 12 ±1.00 1 8 µs √ √ √ √ TSSOP 20
Duals
AD5332 8 ±0.25 2 6 µs √ TSSOP 20
AD5333 10 ±0.50 2 7 µs √ √ √ TSSOP 24
AD5342 12 ±1.00 2 8 µs √ √ √ TSSOP 28
AD5343 12 ±1.00 1 8 µs √ √ TSSOP 20
Quads
AD5334 8 ±0.25 2 6 µs √ √ TSSOP 24
AD5335 10 ±0.50 2 7 µs √ √ TSSOP 24
AD5336 10 ±0.50 4 7 µs √ √ TSSOP 28
AD5344 12 ±1.00 4 8 µs TSSOP 28
Octals
AD5346 8 ±0.25 4 6 µs √ √ √ TSSOP LFCSP 38, 40
AD5347 10 ±0.50 4 7 µs √ √ √ TSSOP 38, 40
AD5348 12 ±1.00 4 8 µs √ √ √ TSSOP 38, 40
Pins Settling Time Additional Pin Functions Package Pins
REF
CLR
Rev. A | Page 23 of 24
AD5337/AD5338/AD5339
OUTLINE DIMENSIONS
3.00
BSC
85
3.00
BSC
PIN 1
0.65 BSC
0.15
0.00
0.38
0.22
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
4
SEATING
PLANE
4.90
BSC
1.10 MAX
0.23
0.08
8°
0°
0.80
0.60
0.40
Figure 41. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD5337ARM −40°C to +105°C 8-Lead MSOP RM-8 D23
AD5337ARM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D23
AD5337BRM −40°C to +105°C 8-Lead MSOP RM-8 D20
AD5337BRM-REEL −40°C to +105°C 8-Lead MSOP RM-8 D20
AD5337BRM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D20
AD5338ARM −40°C to +105°C 8-Lead MSOP RM-8 D24
AD5338ARM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D24
AD5338BRM −40°C to +105°C 8-Lead MSOP RM-8 D21
AD5338BRM-REEL −40°C to +105°C 8-Lead MSOP RM-8 D21
AD5338BRM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D21
AD5338ARMZ-1 −40°C to +105°C 8-Lead MSOP RM-8 D5G
AD5338ARMZ-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D5G
AD5338BRMZ-1 −40°C to +105°C 8-Lead MSOP RM-8 D5J
AD5338BRMZ-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D5J
AD5339ARM −40°C to +105°C 8-Lead MSOP RM-8 D25
AD5339ARM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D25
AD5339BRM −40°C to +105°C 8-Lead MSOP RM-8 D22
AD5339BRM-REEL −40°C to +105°C 8-Lead MSOP RM-8 D22
AD5339BRM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D22
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Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03756-0-10/04(A)
Rev. A | Page 24 of 24
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