ANALOG DEVICES AD5337, AD5338, AD5339 Service Manual
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2.5 V to 5.5 V, 250 µA, 2-Wire Interface
FEATURES
AD5337
2 buffered 8-bit DACs in 8-lead MSOP
AD5338, AD5338-1
2 buffered 10-bit DACs in 8-lead MSOP
AD5339
2 buffered 12-bit DACs in 8-lead MSOP
Low power operation: 250 mA @ 3 V, 300 mA @ 5 V
2-wire (I
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
3 power-down modes
Double-buffered input logic
Output range: 0 V to V
Power-on reset to 0 V
Simultaneous update of outputs (
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range −40°C to +105°C
2
C®compatible) serial interface
REF
LDAC
function)
Dual-Voltage Output, 8-/10-/12-Bit DACs
AD5337/AD5338/AD5339
GENERAL DESCRIPTION
AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit buffered
voltage output DACs in an 8-lead MSOP package, which
operate from a single 2.5 V to 5.5 V supply, consuming 250 µA
at 3 V. On-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/µs. A 2-wire serial interface operates at
clock rates up to 400 kHz. This interface is SMBus-compatible
< 3.6 V. Multiple devices can be placed on the same bus.
at V
DD
The references for the two DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software
power-on reset circuit that ensures that the DAC outputs power
up to 0 V and remain there until a valid write to the device
takes place. A software clear function resets all input and DAC
registers to 0 V. A power-down feature reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated
equipment. The power consumption is typically 1.5 mW at 5 V
and 0.75 mW at 3 V, reducing to 1 µW in power-down mode.
function. The parts incorporate a
LDAC
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
FUNCTIONAL BLOCK DIAGRAM
V
DD
LDAC
SCL
SDA
A0
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
INTERFACE
LOGIC
POWER-ON
RESET
INPUT
REGISTER
INPUT
REGISTER
AD5337/AD5338/AD5339
DAC
REGISTER
DAC
REGISTER
GND
Figure 1.
REFIN
STRING
DAC A
STRING
DAC B
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
BUFFER
BUFFER
POWER-DOWN
LOGIC
www.analog.com
V
A
OUT
V
B
OUT
03756-A-001
AD5337/AD5338/AD5339
TABLE OF CONTENTS
Specifications..................................................................................... 3
Serial Interface............................................................................ 15
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Te r mi n ol o g y ...................................................................................... 9
Typical Performance Characteristics ........................................... 11
Functional Description .................................................................. 15
Digital-to-Analog Converter Section ...................................... 15
Resistor String............................................................................. 15
DAC Reference Inputs ............................................................... 15
Output Amplifier........................................................................ 15
Power-on Reset ........................................................................... 15
REVISION HISTORY
Write Operation.......................................................................... 17
Read Operation........................................................................... 18
Double-Buffered Interface ........................................................ 19
Power-Down Modes .................................................................. 19
Applications..................................................................................... 20
Typical Application Ci r c u it ....................................................... 20
Bipolar Operation....................................................................... 20
Multiple Devices on One Bus ................................................... 20
Product as a Digitally Programmable Window Detector..... 21
Coarse and Fine Adjustment Capabilities............................... 21
Power Supply Decoupling ......................................................... 21
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
10/04—Changed Data Sheet from Rev. 0 to Rev. A
Updated Format..................................................................Universal
Added AD5338-1................................................................Universal
Changes to Specifications................................................................ 4
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide.......................................................... 24
11/03—Rev. 0: Initial Version
Rev. A | Page 2 of 24
AD5337/AD5338/AD5339
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; V
Table 1.
Grade A Grade B
Parameter
DC PERFORMANCE
DAC REFERENCE INPUTS5
OUTPUT CHARACTERISTICS5
5 5 µs
1
3, 4
AD5337
Resolution 8 8 Bits
Relative Accuracy ±0.15 ±1 ±0.15 ±0.5 LSB
Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB
AD5338
Resolution 10 10 Bits
Relative Accuracy ±0.5 ±4 ±0.5 ±2 LSB
Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.50 LSB
AD5339
Resolution 12 12 Bits
Relative Accuracy ±2 ±16 ±2 ±8 LSB
Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB
Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR
Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR
Lower Deadband 20 60 20 60 mV
Offset Error Drift
5
Gain Error Drift5
Power Supply Rejection
5
Ratio
DC Crosstalk5
V
Input Range 0.25 V
REF
V
Input Impedance 37 45 37 45 kΩ Normal operation
REF
>10 >10 MΩ Power-down mode
Reference Feedthrough −90 −90 dB Frequency = 10 kHz
Minimum Output Voltage6 0.001 0.001 V
Maximum Output
6
Voltage
DC Output Impedance 0.5 0.5 Ω
Short Circuit Current 25 25 mA VDD = 5 V
16 16 mA VDD = 3 V
Power-Up Time 2.5 2.5 µs
= 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T
REF
MIN
to T
, unless otherwise noted.
MAX
Min Typ Max Min Typ Max Unit B Version2 Conditions/Comments
Guaranteed monotonic by design over
all codes
Guaranteed monotonic by design over
all codes
Guaranteed monotonic by design over
all codes
Lower deadband exists only if offset error
is negative
ppm of
−12 −12
FSR/°C
ppm of
−5 −5
−60 −60 dB ∆V
200 200 µV R
FSR/°C
= ±10%
DD
= 2 kΩ to GND or V
L
DD
0.25 V
DD
V
This is a measure of the minimum and
maximum drive capabilities of the output
amplifier.
−
V
DD
0.001
−
V
DD
0.001
V
Coming out of power-down mode.
= 5 V
V
DD
Coming out of power-down mode.
= 3 V
V
DD
DD
Rev. A | Page 3 of 24
AD5337/AD5338/AD5339
Grade A Grade B
Parameter
LOGIC INPUTS (A0)5
LOGIC INPUTS (SCL, SDA)5
LOGIC OUTPUT (SDA)5
POWER REQUIREMENTS
1
For explanations of the specific parameters, see the Termin section. ology
2
Temperature range: (A and B versions): −40°C to +105°C; typical at 25°C.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5337 (Codes 8 to 248); AD5338, AD5338-1 (Codes 28 to 995); AD5339 (Codes 115 to 3981).
5
Guaranteed by design and characterization; not production tested.
6
For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V
positive.
7
I
DD
1
Min Typ Max Min Typ Max Unit B Version2 Conditions/Comments
Input Current ±1 ±1 µA
VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ±10%
0.6 0.6 V VDD = 3 V ±10%
0.5 0.5 V VDD = 2.5 V
VIH, Input High Voltage 2.4 2.4 V VDD = 5 V ±10%
2.1 2.1 V VDD = 3 V ±10%
2.0 2.0 V VDD = 2.5 V
Pin Capacitance 3 3 pF
VIH, Input High Voltage 0.7
V
VIL, Input Low Voltage −0.3 +0.3
V
DD
0.3
V
+
DD
0.7
V
–0.3 +0.3
DD
V
DD
0.3
V
+
DD
V SMBus-compatible at VDD < 3.6 V
V SMBus-compatible at VDD < 3.6 V
DD
IIN, Input Leakage Current ±1 ±1 µA
V
, Input Hysteresis 0.05
HYST
V
0.05
DD
V
V
DD
CIN, Input Capacitance 8 8 pF
Glitch Rejection 50 50 ns Input filtering suppresses noise spikes of
less than 50 ns
V
Output Low Voltage 0.4 0.4 V I
OL,
0.6 0.6 V I
Three-State Leakage
±1 ±1 µA
= 3 mA
SINK
= 6 mA
SINK
Current
Three-State Output
8 8 pF
Capacitance
V
DD
IDD (Normal Mode)
7
2.5 5.5 2.5 5.5 V
V
= VDD and VIL = GND
IH
VDD = 4.5 V to 5.5 V 300 375 300 375 µA
VDD = 2.5 V to 3.6 V 250 350 250 350 µA
IDD (Power-Down Mode) VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V 0.2 1.0 0.2 1.0 µA IDD = 4 µA (max) during 0 readback
on SDA
VDD = 2.5 V to 3.6 V 0.08 1.00 0.08 1.00 µA IDD = 1.5 µA (max) during 0 readback
on SDA
= V
and offset plus gain error must be
REF
DD
specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Rev. A | Page 4 of 24
AD5337/AD5338/AD5339
AC CHARACTERISTICS
1
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T
MIN
to T
, unless otherwise noted.
MAX
Table 2.
A and B Versions
Parameter
3
Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time V
2
= VDD = 5 V
REF
AD5337 6 8 µs 1/4 scale to 3/4 scale change (0x40 to 0xC0)
AD5338 7 9 µs 1/4 scale to 3/4 scale change (0x100 to 0x300)
AD5339 8 10 µs 1/4 scale to 3/4 scale change (0x400 to 0xC00)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB change around major carry
Digital Feedthrough 1 nV-s
Digital Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion −70 dB V
= 2 V ± 0.1 V p-p
REF
= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
REF
1
Guaranteed by design and characterization; not production tested.
2
Temperature range: A and B versions: −40°C to +105°C; typical at 25°C.
3
For explanations of the specific parameters, see the Termin section. ology
Rev. A | Page 5 of 24
AD5337/AD5338/AD5339
S
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V. All specifications T
Table 3.
MIN
, T
Parameter
f
SCL
t
1
t
2
t
3
t
4
t
5
1
t
6
Limit at T
(A and B Versions)
400 kHz max SCL clock frequency
2.5 µs min SCL cycle time
0.6 µs min t
1.3 µs min t
0.6 µs min t
100 ns min t
0.9 µs max t
0 µs min t
t
7
t
8
t
9
t
10
0.6 µs min t
0.6 µs min t
1.3 µs min t
300 ns max tR, rise time of SCL and SDA when receiving
0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible)
t
11
250 ns max tF, fall time of SDA when transmitting
0 ns min tF, fall time of SDA when receiving (CMOS-compatible)
300 ns max tF, fall time of SCL and SDA when receiving
20 + 0.1 C
C
B
400 pF max Capacitive load for each bus line
2
B
1
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
falling edge.
2
CB is the total capacitance of one bus line in pF; t
MAX
MIN
to T
, unless otherwise noted.
MAX
Unit Conditions/Comments
ns min tF, fall time of SCL and SDA when transmitting
and tF measured between 0.3 V
R
, SCL high time
HIGH
, SCL low time
LOW
, start/repeated start condition hold time
HD, STA
, data setup time
SU, DAT
, data hold time
HD, DAT
, data hold time
HD, DAT
, setup time for repeated start
SU, STA
, stop condition setup time
SU, STO
, bus free time between a stop and a start condition
BUF
min of the SCL signal) in order to bridge the undefined region of SCL’s
IH
and 0.7 VDD.
DD
DA
SCL
t
9
START
CONDITION
t
3
t
4
t
10
t
6
t
t
11
2
t
5
REPEATED
CONDITION
t
START
t
4
t
7
1
t
8
STOP
CONDITION
03756-A-002
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. A | Page 6 of 24
AD5337/AD5338/AD5339
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +7 V
SCL, SDA to GND −0.3 V to VDD + 0.3 V
A0 to GND −0.3 V to VDD + 0.3 V
Reference Input Voltage to GND −0.3 V to VDD + 0.3 V
V
A−V
OUT
Operating Temperature Range
Industrial (B Version) −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
MSOP Package
Power Dissipation (TJ max − TA)θ
θJA Thermal Impedance 206°C/W
θJC Thermal Impedance 44°C/W
Reflow Soldering
Peak Temperature 220 +5/−0°C
Time at Peak Temperature 10 s to 40 s
B to GND −0.3 V to VDD + 0.3 V
OUT
JA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 7 of 24
AD5337/AD5338/AD5339
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
DD
1
AD5337/
AD5338/
2
V
A
OUT
V
OUT
REFIN
B
3
4
AD5339
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Function
1 V
2 V
3 V
DD
A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
OUT
B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
OUT
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.
4 REFIN Reference Input Pin for the Two DACs. It has an input range from 0.25 V to VDD.
5 GND Ground Reference Point for All Circuitry on the Parts.
6 SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift
register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up
resistor.
7 SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift
register. Clock rates of up to 400 kbps can be accommodated in the 2-wire interface.
8 A0 Address Input. Sets the least significant bit of the 7-bit slave address.
8
A0
7
SCL
6
SDA
GND
5
03756-A-003
Rev. A | Page 8 of 24
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