Analog Devices AD5231 b Datasheet

Nonvolatile Memory,

FEATURES

1024-position resolution Nonvolatile memory maintains wiper setting Power-on refresh with EEMEM setting EEMEM restore time: 140 µs typ Full monotonic operation 10 kΩ, 50 kΩ, and 100 kΩ terminal resistance Permanent memory write protection Wiper setting readback Predefined linear increment/decrement instructions Predefined ±6 dB/step log taper increment/decrement

instructions SPI®-compatible serial interface 3 V to 5 V single-supply or ±2.5 V dual-supply operation 28 bytes extra nonvolatile memory for user-defined data 100-year typical data retention, T

APPLICATIONS

Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Programmable voltage to current conversion Programmable filters, delays, time constants Programmable power supply Low resolution DAC replacement Sensor calibration

GENERAL DESCRIPTION

The AD5231 is a nonvolatile memory,1 digitally controlled potentiometer the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and remote controllability. The AD5231 has versatile programming that uses a standard 3-wire serial interface for 16 modes of operation and adjustment, including scratchpad programming, memory storing and restoring, increment/decrement, ±6 dB/step log taper adjustment, wiper setting readback, and extra EEMEM for user-defined information, such as memory data for other components, look-up table, or system identification information.

In scratchpad programming mode, a specific setting can be programmed directly to the RDAC2 register that sets the resistance between Terminals W–A and W–B. This setting can be stored into the EEMEM and is transferred automatically to the RDAC register during system power-on.

2

with 1024-step resolution. The device performs

= 55°C

A

1024-Position Digital Potentiometer

AD5231

FUNCTIONAL BLOCK DIAGRAM

AD5231

RDAC

2

DIGITAL OUTPUT BUFFER

R

WB

CS

CLK

SDI

GND

SDO

WP

RDY

PR

SDI

SERIAL

INTERFACE

SDO

EEMEM

CONTROL

ADDR

DECODE

28 BYTES

USER EEMEM

RDAC

REGISTER

EEMEM(0)

DIGITAL

REGISTER

EEMEM(1)

Figure 1.

100

) R

(D) – Percent of Nominal (%

(D), R R

AB

WB

WA

75

50

25

0

R

WA

0 1023256

Figure 2. R

512 768

CODE (Decimal)

(D) and RWB (D) vs. Decimal Code

WA

The EEMEM content can be restored dynamically or through

PR

external

strobing, and a WP function protects EEMEM contents. To simplify the programming, the linear-step increment or decrement commands can be used to move the RDAC wiper up or down, one step at a time. The ±6 dB step commands can be used to double or half the RDAC wiper setting.

The AD5231 is available in a 16-lead TSSOP. The part is guaranteed to operate over the extended industrial temperature range of −40°C to +85°C.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

V

A W B

O1 O2

V

DD

SS

02739-0-001

03684-0-002

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD5231

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS RHEOSTAT MODE

Resistor Differential Nonlinearity2 R-DNL RWB, VA = NC, Monotonic −1 ±1/2 +1.8 LSB Resistor Integral Nonlinearity2 R-INL RWB,VA = NC −0.2 +0.2 LSB Nominal Resistor Tolerance ∆RAB/RAB D = 0x3FF −40 +20 % Resistance Temperature Coefficient (∆RWB/RWB)/∆T × 106 600 ppm/°C Wiper Resistance RW

= 100 µA, VDD = 5.5 V,

I

W

Code = half scale

= 100 µA, VDD = 3 V,

I

W

Code = half scale DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE

Resolution N 10 Bits Differential Nonlinearity3 DNL Monotonic, TA = 25°C −1 ±1/2 +1 LSB Monotonic, TA = −40°C or +85°C −1 +1.25 LSB Integral Nonlinearity3 INL −0.4 +0.4 LSB Voltage Divider Temperature

(∆V

)/∆T × 106 Code = half scale 15 ppm/°C

W/VW

Coefficient Full-Scale Error V Zero-Scale Error V

Code = full scale −3 0 % FS

WFSE

Code = zero scale 0 1.5 % FS

WZSE

RESISTOR TERMINALS

Terminal Voltage Range4 V Capacitance A, B5 C

V

A, B, W

f = 1 MHz, measured to GND,

A, B

code = half-scale

Capacitance W5 C

f = 1 MHz, measured to GND,

W

Code = half-scale

Common-Mode Leakage Current

5, 6

ICM V

= VDD/2 0.01 1 µA

W

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V Input Logic High VIH With respect to GND, VDD = 3 V 2.1 V Input Logic Low VIL With respect to GND, VDD = 3 V 0.6 V Input Logic High VIH

Input Logic Low VIL

Output Logic High (SDO, RDY) VOH

With respect to GND, V V

= −2.5 V

SS

With respect to GND, V

= −2.5 V

V

SS

= 2.2 kΩ to 5 V

R

PULL-UP

= +2.5 V,

DD

= +2.5 V,

DD

(see Figure 26)

Output Logic Low VOL

= 1.6 mA, V

I

OL

LOGIC

= 5 V

(see Figure 26) Input Current IIL V Input Capacitance5 C Output Current5 I

4 pF

IL

, IO2 V

O1

V

= 0 V or VDD ±2.5 µA

IN

= 5 V, VSS = 0 V, TA = 25°C 50 mA

DD

= 2.5 V, VSS = 0 V, TA = 25°C 7 mA

DD

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 2.7 5.5 V

SS

Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V Positive Supply Current IDD V

= VDD or VIL = GND 2.7 10 µA

IH

15 100 Ω

50 Ω

VDD V

SS

50 pF

2.0 V

0.5 V

4.9 V

0.4 V

Rev. B | Page 3 of 28

AD5231

Parameter Symbol Conditions Min Typ1 Max Unit

Negative Supply Current ISS

EEMEM Store Mode Current IDD (store)

I EEMEM Restore Mode Current7 I

I Power Dissipation8 P Power Supply Sensitivity5 P

DYNAMIC CHARACTERISTICS

5, 9

(store) VDD = +2.5 V, VSS = −2.5 V −40 mA

SS

(restore)

DD

(restore) VDD = +2.5 V, VSS = −2.5 V −0.3 −3 −9 mA

SS

V

DISS

∆VDD = 5 V ± 10% 0.002 0.01 %/%

SS

Bandwidth BW

= VDD or VIL = GND,

V

IH

= +2.5 V, VSS = −2.5 V

V

DD

= VDD or VIL = GND,

V

IH

V

= GND, ISS ≈ 0

SS

= VDD or VIL = GND,

V

IH

= GND, ISS ≈ 0

V

SS

= VDD or VIL = GND 0.018 0.05 mW

IH

−3 dB, R

= 10 kΩ/50 kΩ/

AB

100 kΩ

Total Harmonic Distortion THDW

VW Settling Time tS

= 1 V rms, VB = 0 V, f = 1 kHz,

V

A

= 10 kΩ

R

AB

= 1 V rms, VB = 0 V, f = 1 kHz,

V

A

R

= 50 kΩ, 100 kΩ

AB

= VDD, VB = 0 V,

V

A

= 0.50% error band,

V

W

Code 0x000 to 0x200 for R

= 10 kΩ/50 kΩ/100 kΩ

AB

Resistor Noise Voltage e

R

N_WB

= 5 kΩ, f = 1 kHz 9

WB

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-

tions. R-DNL measures the relative step change from ideal between successive tap positions. I version, I

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of

−1 LSB minimum are guaranteed monotonic operating condition (see Figure 27).

4

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from any Terminal B–W to a common-mode bias level of VDD/2.

7

EEMEM restore mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 23). To minimize

power dissipation, a NOP Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1).

8

P

9

All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.

~ 50 µA for the RAB = 50 kΩ and IW ~ 25 µA for the RAB = 100 kΩ version (see Figure 26).

W

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

~ 50 µA @ VDD = 2.7 V and IW ~ 400 µA @ VDD = 5 V for the RAB = 10 kΩ

W

0.5 10 µA

40 mA

0.3 3 9 mA

370/85/44 kHz

0.022 %

0.045 %

1.2/3.7/7 µs

Hz

nV/√

Rev. B | Page 4 of 28

AD5231

TIMING CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

INTERFACE TIMING CHARACTERISTICS

Clock Cycle Time (t

) t1 20 ns

CYC

CS Setup Time CLK Shutdown Time to CS Rise Input Clock Pulse Width t4, t5 Clock level high or low 10 ns Data Setup Time t6 From positive CLK transition 5 ns Data Hold Time t7 From positive CLK transition 5 ns CS to SDO-SPI Line Acquire CS to SDO-SPI Line Release CLK to SDO Propagation Delay4 t CLK to SDO Data Hold Time t11 R CS High Pulse Width5 CS High to CS High5 RDY Rise to CS Fall CS Rise to RDY Fall Time Store/Read EEMEM Time6 t Power-On EEMEM Restore Time t Dynamic EEMEM Restore Time t CS Rise to Clock Rise/Fall Setup Preset Pulse Width (Asynchronous) t

Preset Response Time to Wiper Setting t

FLASH/EE MEMORY RELIABILITY

Endurance7 100 kCycles Data Retention8 100 Years

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Guaranteed by design and not subject to production test.

3

See timing diagrams (Figure 3 and Figure 4) for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed

from a voltage level of 1.5 V. Switching characteristics are measured using both V

4

Propagation delay depends on the value of VDD, R

5

Valid for commands that do not activate the RDY pin.

6

RDY pin low only for Instructions 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_2, 3 ~ 20 µs; CMD_8 ~ 1 µs; CMD_9, 10 ~ 0.12 µs. Device operation at TA = −40°C and

V

< 3 V extends the EEMEM store time to 35 ms.

DD

7

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

8

Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.

2, 3

t

10 ns

2

t

1 t

3

t

40 ns

8

t

50 ns

9

R

10

t

10 ns

12

t

4 t

13

t

0 ns

14

t

0.1 0.15 ms

15

Applies to instructions 0x2, 0x3, and 0x9 25 ms

16

RAB = 10 kΩ 140 µs

EEMEM1

RAB = 10 kΩ 140 µs

EEMEM2

t

10 ns

17

Not shown in timing diagram 50 ns

PRW

PRESP

, and CL.

PULL-UP

= 2.2 kΩ, CL < 20 pF 50 ns

P

= 2.2 kΩ, CL < 20 pF 0 ns

P

PR pulsed low to refresh wiper positions

= 3 V and VDD = 35 V.

DD

70 µs

CYC

Rev. B | Page 5 of 28

AD5231

CPHA = 1

CS

CLK

CPOL = 1

SDI

SDO

RDY

t

2

HIGH OR LOW

t

8

B24* B23–MSB B0–LSB

t

14

*NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.

THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

1

t

B23 B0

5

t

4

t

7

t

6

B23–MSB

t

10

t

B0–LSB

11

3

t

12

t

13

t

17

HIGH OR LOW

t

9

t

15

t

16

02739-0-003

Figure 3. CPHA = 1 Timing Diagram

CPHA = 0

CLK

CPOL = 0

CS

t

1

t

2

t

B23 B0

5

t

4

t

3

t

12

t

13

t

17

t

6

B0–LSB

t

10

t

11

t

9

HIGH OR LOW

*

t

7

t

15

t

16

02739-0-004

SDI

SDO

RDY

HIGH OR LOW

t

14

*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER PREVIOUSLY RECEIVED.

THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

B23–MSB IN

t

8

B23–MSB OUT B0–LSB

Figure 4. CPHA = 0 Timing Diagram

Rev. B | Page 6 of 28

AD5231

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameters Ratings

VDD to GND –0.3 V, +7 V VSS to GND +0.3 V, −7 V VDD to VSS 7 V VA, VB, VW to GND VSS − 0.3 V, VDD + 0.3 V A–B, A–W, B–W

Intermittent1 ±20 mA Continuous ±2 mA

Digital Input and Output Voltage to GND −0.3 V, VDD + 0.3 V Operating Temperature Range2 −40°C to +85°C Maximum Junction Temperature (TJ max) 150°C Storage Temperature −65°C to +150°C Lead Temperature, Soldering

Vapor Phase (60 s) 215°C Infrared (15 s) 220°C

Thermal Resistance Junction-to-Ambient

θ

,TSSOP-16

JA

Thermal Resistance Junction-to-Case θJC,

TSSOP-16

Package Power Dissipation (TJ max − TA)/θJA

150°C/W

28°C/W

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance.

2

Includes programming of nonvolatile memory.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. B | Page 7 of 28

AD5231

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

16

O2

15

RDY

14

CS

13

PR

12

WP

11

V

DD

10

A

9

W

02739-0-005

CLK

SDI SDO GND

V

O1

SS

T

B

1

2

3

AD5231

4

TOP VIEW

5

(Not to Scale)

6

7

8

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 O1

Nonvolatile Digital Output 1. ADDR = 0x1, data bit position D0. For example, to store O1 high, the data bit

format is 0x310001. 2 CLK Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. 3 SDI Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. 4 SDO Serial Data Output Pin. Serves readback and daisy-chain functions.

Commands 9 and 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses,

depending on the clock polarity before and after the data-word (see Figure 3, Figure 4, and Table 7).

In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses

depending on the clock polarity (see Figure 3 and Figure 4). This previously shifted-out SDI can be used for

daisy-chaining multiple devices.

Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed. 5 GND Ground Pin, Logic Ground Reference. 6 VSS

Negative Supply. Connect to 0 V for single-supply applications. If V

is used in dual-supply applications, it

SS

must be able to sink 40 mA for 25 ms when storing data to EEMEM. 7 T Reserved for factory testing. Connect to VDD or VSS. 8 B Terminal B of RDAC. 9 W Wiper Terminal of RDAC. ADDR (RDAC) = 0x0. 10 A Terminal A of RDAC. 11 VDD Positive Power Supply Pin. 12

WP Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR and

Instructions 1 and 8 and refreshes the RDAC register from EEMEM. Execute a NOP instruction before returning

WP high. Tie WP to VDD, if not used.

to 13

14 15 RDY 16 O2

PR Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM

register. Factory default loads midscale 512

at the logic high transition. Tie

PR to VDD, if not used.

until EEMEM is loaded with a new value by the user. PR is activated

10

CS Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.

Ready. Active-high open-drain output. Identifies completion of Instructions 2, 3, 8, 9, 10, and

Nonvolatile Digital Output 2. ADDR = 0x1, data bit position D1. For example, to store O2 high, the data bit

format is 0x310002.

PR.

Rev. B | Page 8 of 28

AD5231

TYPICAL PERFORMANCE CHARACTERISTICS

1.5

TA = +85°C

1.0

2.0 VDD = 5V, VSS = 0V

1.5

1.0

TA = –40°C

0.5

0

INL ERROR (LSB)

–0.5

–1.0

128 384 640 896

0

Figure 6. INL vs. Code, T

2.0 VDD = 5V, VSS = 0V

1.5

1.0

0.5

0

–0.5

DNL ERROR (LSB)

–1.0

–1.5

–2.0

0 256 512 768 1024128 384 640 896

Figure 7. DNL vs. Code, T

1.0 VDD = 5V, VSS = 0V

0.5

0

R-INL (LSB)

–0.5

–1.0

0 256 512 768 1024128 384 640 896

Figure 8. R-INL vs. Code, T

TA =–

40°C

256 512 768

CODE (Decimal)

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

TA = –40°C

TA = +85°C

TA = +25°C

CODE (Decimal)

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

TA = +85°C

TA = +25°C

TA = –40°C

CODE (Decimal)

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

TA = +25°C

1024

02739-0-006

02739-0-007

02739-0-008

0.5

0

R-DNL (LSB)

–0.5

–1.0

–1.5

–2.0

0 128 256 384 512 640 768 896 1024

Figure 9. R-DNL vs. Code, T

3000

2500

2000

1500

1000

500

RHEOSTAT MODE TEMPCO (ppm/°C)

0

0 256 512 768 1024128 384 640 896

100

C)

°

80

60

40

20

0

POTENTIOMETER MODE TEMPCO (ppm/

–20

0 256 512 768 1024128 384 640 896

TA = +85°C

VDD = 5.5V, VSS = 0V T

=–40°CTO+85°C

A

Figure 10. (∆R

Figure 11. (∆V

TA = +25°C

CODE (Decimal)

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

CODE (Decimal)

)/∆T × 106

WB/RWB

VDD = 5.5V, VSS = 0V T

= –40°CTO+85°C

A

V

= 0V

B

V

= 2.00V

A

CODE (Decimal)

)/∆T × 106

W/VW

02739-0-009

02739-0-010

02739-0-011

Rev. B | Page 9 of 28

Analog Devices AD5231 b Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

TIMING CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS