ANALOG DEVICES AD5231, AD5232, AD5233 Service Manual

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PRELIMINARY TECHNICAL DATA

a

FEATURES

Nonvolatile Memory Preset Maintains Wiper Settings
AD5231 Single, 1024 Position Resolution
AD5232 Dual, 256 Position Resolution
AD5233 Quad, 64 Position Resolution
10K, 50K, 100K Ohm Terminal Resistance
Linear or Log taper Settings
Increment/Decrement Commands, Push Button Command
SPI Compatible Serial Data Input with Readback Function
+3 to +5V Single Supply or ±2.5V Dual Supply Operation
User EEMEM nonvolatile memory for constant storage

APPLICATIONS

Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
DIP Switch Setting

GENERAL DESCRIPTION

The AD5231/AD5232/AD5233 family provides a single­/dual-/quad-channel, digitally controlled variable resistor (VR)
with resolutions of 1024/256/64 positions respectively. These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. The AD523X’s versatile
programming via a Micro Controller allows multiple modes of
operation and adjustment.

In the direct program mode a predetermined setting of the
RDAC register can be loaded directly from the micro controller.
Another key mode of operation allows the RDAC register to be
refreshed with the setting previously stored in the EEMEM
register. When changes are made to the RDAC register to
establish a new wiper position, the value of the setting can be
saved into the EEMEM by executing an EEMEM save
operation. Once the settings are saved in the EEMEM register
these values will be transferred automatically to the RDAC
register to set the wiper position at system power ON. Such
operation is enabled by the internal preset strobe and the preset
can also be accessed externally.

The basic mode of adjustment is the increment and decrement
command controlling the present setting of the Wiper position
setting (RDAC) register. An internal scratch pad RDAC register
can be moved UP or DOWN, one step of the nominal terminal
resistance between terminals A-and-B. This linearly changes the
wiper to B terminal resistance (R
the device's end-to-end resistance (RAB). For
exponential/logarithmic changes in wiper setting, a left/right
shift command adjusts levels in +/-6dB steps, which can be
useful for sound and light alarm applications.

The AD523X are available in the thin TSSOP package. All
parts are guaranteed to operate over the extended industrial
temperature range of -40°C to +85°C.

REV PrF, 22 MAR '01

Information fur nished by Analog Devices is believed to be acc urate and reliable. However, no
responsibility is assumed by Analog Devices for its use; nor for any infringements of patents
or other rights of third parties, which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices.

) by one position segment of

WB

Nonvolatile Memory

Digital Potentiometers

AD5231/AD5232/AD5233

FUNCTIONAL BLOCK DIAGRAMS

CS

CLK

SDI

GND

SDO

WP

RDY

PR

CS

CLK

SDI

GND

SDO

WP

RDY

PR

CS

CLK

SDI

SDO

WP

RDY

GND

O

1

O

2

PR

One Technology Way, P.O. Box 9106,
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax:[phone] © Analog Devices, Inc., 1999

ADDR

DECODE

SDI

SERIAL

INT E RF A CE

SDO

EEMEM

CONTROL

28 BYTE S

USER EEMEM

ADDR

DECODE

SDI

SERIAL

INT E RF A CE

SDO

EEMEM

CONTROL

14 BYTES

USER EEMEM

ADDR

DECODE

SDI

SERIAL

INT E RF A CE

SDO

EEMEM

CONTROL

11 BYT ES

USER EEMEM

DIGITAL
OUTPUT
BUFFER

2

DIGITAL 5
REGISTER

EEMEM5

RDAC1

REGISTER

EEMEM1

DIGITAL 2

REGISTER

EEMEM2

RDAC1

REGISTER

EEMEM1

RDAC2

REGISTER

EEMEM2

RDAC1

REGISTER

EEMEM1

RDAC2

REGISTER

EEMEM2

RDAC3

REGISTER

EEMEM3

RDAC4

REGISTER

EEMEM4

Norwood, MA 02062-9106 U.S.A.

AD5231

RDAC1

DIGITAL

2

OUTPUT
BUFFER

AD5232

RDAC1

RDAC2

AD5233

RDAC1

RDAC2

RDAC3

RDAC4

V

DD

A

1

W

1

B

1

O

1

O

2

V

SS

V

DD

A

1

W

1

B

1

A

2

W

2

B

2

V

SS

V

DD

A

1

W

1

B

1

A

2

W

2

B

2

A

3

W

3

B

3

A

4

W

4

B

4

V

SS

PRELIMINARY TECHNICAL DATA

AD5231/AD5232/AD5233 -

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS

= +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)

V

A

(VDD = +3V±10% or +5V±10% and VSS=0V,

Parameter Symbol Conditions Min Typ1 Max Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs

Resistor Differential Nonlinearity2 R-DNL RWB, VA=NC -1 ±1/4 +1 LSB

Resistor Nonlinearity2 R-INL RWB, VA=NC -1 ±1/2 +1 %FS
Nominal resistor tolerance ∆R TA = 25°C, VAB = VDD,Wiper (VW) = No connect -30 30 %

Resistance Temperature Coefficent RAB/∆T V

Wiper Resistance RW I
Wiper Resistance RW I

= VDD, Wiper (VW) = No Connect 500 ppm/°C

AB

= 1 V/R, VDD = +5V 50 100 Ω

W

= 1 V/R, VDD = +3V 200 Ω

W

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs

Resolution N AD5231/AD5232/AD5233 10 / 8 / 6 Bits
Integral Nonlinearity3 INL –1 ±1/2 +1 %FS
Differential Nonlinearity3 DNL –1 ±1/4 +1 LSB

Voltage Divider Temperature Coefficent ∆VW/∆T Code = Half-scale 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = Full-scale –3 +0 %FS

WFSE

Code = Zero-scale 0 +3 %FS

WZSE

RESISTOR TERMINALS

Voltage Range4 V
Capacitance5 Ax, Bx C

VSS V

A,B,W

f = 1 MHz, measured to GND, Code = Half-scale 45 pF

A,B

V

DD

Capacitance5 Wx CW f = 1 MHz, measured to GND, Code = Half-scale 60 pF

Common-mode Leakage Current6 I

V

CM

= VB = VDD/2 0.01 1 µA

A

DIGITAL INPUTS & OUTPUTS

Input Logic High VIH with respect to GND, VDD = 5V 2.4 V
Input Logic Low VIL with respect to GND, VDD = 5V 0.8 V
Input Logic High VIH with respect to GND, VDD = 3V 2.1 V
Input Logic Low VIL with respect to GND, VDD = 3V 0.6 V
Output Logic High VOH R
Output Logic High VOH IOH = 40µA, V
Output Logic Low VOL I
Input Current IIL V

Input Capacitance5 C

5 pF

IL

= 2.2KΩ to +5V 4.9 V

PULL-UP

= +5V 4 V

= 1.6mA, V

OL

= 0V or VDD ±1 µA

IN

LOGIC

= +5V 0.4 V

LOGIC

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0V 2.7 5.5 V

SS

Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD V

Programming Mode Current I
Read Mode Current13 I

VIH = VDD or VIL = GND 35 mA

DD(PG)

DD(READ)

Negative Supply Current ISS V

Power Dissipation7 P

V

DISS

= VDD or VIL = GND 2 20 µA

IH

VIH = VDD or VIL = GND 0.9 9 mA

= VDD or VIL = GND, V

IH

= VDD or VIL = GND 0.1 mW

IH

= 2.5V, V

DD

= -2.5V 10 µA

SS

Power Supply Sensitivity PSS ∆VDD = +5V ±10% 0.002 0.01 %/%

DYNAMIC CHARACTERISTICS

5, 8

Bandwidth –3dB BW_10K R = 10KΩ 600 KHz
Total Harmonic Distortion THDW V

VW Settling Time tS V

=1Vrms, VB = 0V, f=1KHz 0.003 %

A

= VDD, VB=0V, 50% of final value

A

For RAB = 10K/50K/100K 1 / 3 / 6 µs
Resistor Noise Voltage e

Crosstalk (CW1/CW2) CT V

RWB = 5KΩ, f = 1KHz 9 nV√Hz

N_WB

= VDD, VB = 0V, Measure VW with adjacent

A

VR making full scale change -65 dB

NOTES: See bottom of table next page.

REV PrF 2 22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL[phone]; FAX [phone]; [e-mail]

PRELIMINARY TECHNICAL DATA

AD5231/AD5232/AD5233 -

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS

V

= +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)

A

Parameter Symbol Conditions Min Typ1 Max Units

(VDD = +3V±10% to +5V±10% and VSS=0V,

INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 9)

Clock Cycle Time t 1 20 ns
Input Clock Pulse Width t 2 , t 3 Clock level high or low 10 ns
CS Setup Time t

10 ns

4

Data Setup Time t 5 From Positive CLK transition 5 ns
Data Hold Time t 6 From Positive CLK transition 5 ns
CLK Shutdown Time t 7 0 ns

CS Rise to Clock Rise Setup t
CS High Pulse Width t

CLK to SDO Propagation Delay10 t

10 ns

8

10 ns

9

RP = 1KΩ, CL < 20pF 1 25 ns

10

Store to Nonvolatile EEMEM Save Time11 t 12 Applies to Command 2H, 3H, 9H 25 ms

CS to SDO - SPI line acquire t
CS to SDO - SPI line release t

ns

13

ns

14

RDY Rise to CS Fall t15 ns
Startup Time t16 ms
CLK Setup Time t17 For 1 CLK period (t4 - t3 = 1 CLK period) ns
Preset Pulse Width (Asynchronous) tPR 50 ns
Preset Response Time t

PR pulsed low then high 70 us

PRESP

NOTES:

1. Typicals represent average readings at +25°C and VDD = +5V.

2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step c hange from ideal between successive tap positions. Parts are guaranteed monotonic. I

3. INL and DNL are measured at V

DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.

4. Resistor terminals A, B, W have no limitations on polarity with respect to each other.

5. Guaranteed by design and not subject to production test.

6. Common mode leakage current is a measure of the DC leakage from any terminal A, B, W to a common mode bias level of V

7. P

8. All dynamic char acteristics use V

9. See timing diagram for location of measured values. All input control voltages are specified with t

10. Propagation delay depends on value of V

11. Low only for instruction commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.12ms; CMD_2,3 ~20ms

12. Dual Supply Operation primarily affects the POT terminals.

13. Read Mode current is not continuous.

is calculated from (IDD x VDD) + (ISS X VSS).

DISS

characteristics are measur ed using both V

with the RDA C configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = VSS.

W

= +5V.

DD

= +3V or +5V.

DD

, R

DD

PULL_UP

, and CL see applications text.

= VDD/R for both VDD=+3V or VDD=+5V.

W

/ 2.

DD

=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching

R=tF

Timing Diagram

CLK

t

17

t

4

t

1

CS

t

5

SDI

SDO

SDO

t

13

1

2

t

MSB LSB

t

10

MSB LSB

MSB LSB

15

RDY

SDO1 CLK IDLES LOW SDO2 CLK IDLES HIGH

Figure 1. Timing Diagram

REV PrF 3 22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL[phone]; FAX [phone]; [e-mail]

t

t

2

3

t

7

t

6

t

8

t

9

t

14

t

16

t

12

PRELIMINARY TECHNICAL DATA

Nonvolatile Memory Digital Potentiometers

Absolute Maximum Rating (

TA = +25°C, unless

otherwise noted)
V

to GND..............................................................-0.3, +7V

DD

to GND .................................................................0V, -7V

V

SS

to VSS.........................................................................+7V

V

DD

, VB, VW to GND..................................................VSS, VDD

V

A

A

– BX, AX – WX, BX – W

X

X

Intermittent ...................................................±20mA

Continuous................................................... ±1.3mA

Digital Inputs & Output Voltage to GND .................. 0V, +7V

Operating Temperature Range ........................ -40°C to +85°C

Maximum Junction Temperature (T

Storage Temperature..................................... -65°C to +150°C

Lead Temperature (Soldering, 10 sec) .........................+300°C

Package Power Dissipation........................ (T

Thermal Resistance θ

TSSOP-16 ..................................................... 150°C/W

TSSOP-24 ..................................................... 128°C/W

AD5231/AD5232/AD5233

) ..................+150°C

MAX

J

- TA) /

θ

JA

JA,

MAX

J

Ox to GND .................................................................. 0V, VDD

Ordering Guide

Number of End to End Temp Package Package #Devices Top Mark
Model Channels R (k Ohm) Range Description Option per Container

AD5231BRU10 X1 10 -40/+85°C TSSOP-16 RU-16
AD5231BRU10-REEL7 X1 10 -40/+85°C TSSOP-16 RU-16 1,000
AD5231BRU50 X1 50 -40/+85°C TSSOP-16 RU-16
AD5231BRU50-REEL7 X1 50 -40/+85°C TSSOP-16 RU-16 1,000
AD5231BRU100 X1 100 -40/+85°C TSSOP-16 RU-16
AD5231BRU100-REEL7 X1 100 -40/+85°C TSSOP-16 RU-16 1,000

AD5232BRU10 X2 10 -40/+85°C TSSOP-16 RU-16
AD5232BRU10-REEL7 X2 10 -40/+85°C TSSOP-16 RU-16 1,000
AD5232BRU50 X2 50 -40/+85°C TSSOP-16 RU-16
AD5232BRU50-REEL7 X2 50 -40/+85°C TSSOP-16 RU-16 1,000
AD5232BRU100 X2 100 -40/+85°C TSSOP-16 RU-16

AD5232BRU100-REEL7 X2 100 -40/+85°C TSSOP-16 RU-16 1,000

AD5233BRU10 X4 10 -40/+85°C TSSOP-24 RU-24
AD5233BRU10-REEL7 X4 10 -40/+85°C TSSOP-24 RU-24
AD5233BRU50 X4 50 -40/+85°C TSSOP-24 RU-24
AD5233BRU50-REEL7 X4 50 -40/+85°C TSSOP-24 RU-24
AD5233BRU100 X4 100 -40/+85°C TSSOP-24 RU-24
AD5233BRU100-REEL7 X4 100 -40/+85°C TSSOP-24 RU-24

The AD5231/AD5232/AD5233 contains 9,646 transistors.
Die size: 69 mil x 115 mil, 7,993 sq. mil

REV PrF 4 22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL[phone]; FAX [phone]; [e-mail]

PRELIMINARY TECHNICAL DATA

Nonvolatile Memory Digital Potentiometers

AD5231

PIN CONFIGURATION

O1

CLK

SDI

SDO

GND

V

B1

1

2

3

4

5

6

SS

7

T1

8

O2

16

15

RDY

14

CS

CS

CSCS

13

PR

PR

PRPR

12

WP

WP

WPWP

11

V

DD

10

A1

9

W1

AD5231 PIN FUNCTION DESCRIPTION

# Name Description

1 O1 Non-Volatile Digital Output #1, ADDR(O1) =

1H, data bit position D0

2 CLK Serial Input Register clock pin. Shifts in one

bit at a time on positive clock CLK edges.

3 SDI Serial Data Input Pin.

4 SDO Serial Data Output Pin. Open Drain Output

requires external pull-up resistor. Commands 9
& 10 activate the SDO output. See Instruction
operation Truth Table. Other commands shift
out the previously loaded bit pattern delayed
by 24 clock pulses. This allows daisy-chain
operation of multiple packages.

5 GND Ground pin, logic ground reference.

6 V

7 T1 Used as digital input during factory test mode.

8 B1 B terminal of RDAC1.

9 W1 Wiper terminal of RDAC1,

10 A1 A terminal of RDAC1.

11 VDD Positive Power Supply Pin. Should be ≥ the

12 WP Write Protect Pin. When active low WP

13 PR Hardware over ride preset pin. Refreshes the

14 CS Serial Register chip select active low. Serial

15 RDY Ready. Active-high open drain output.

16 O2 Non-Volatile Digital Output #2, ADDR(O2) =

Negative Supply. Connect to zero volts for

SS

single supply applications.

Leave pin floating or connect to V

ADDR(RDAC1) = 0

H

or VSS.

DD

input-logic HIGH voltage.

prevents any changes to the present contents
except retrieving EEMEM contents and
RESET.

scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 200

until EEMEM loaded with a

H

new value by the user (PR is activated at the
rising logic high transition)

register operation takes place when CS returns
to logic high.

Identifies completion of commands 2, 3, 8, 9,

10.

1H, data bit position D1.

AD5232 PIN FUNCTION DESCRIPTION

# Name Description

1 CLK Serial Input Register clock pin. Shifts in one

2 SDI Serial Data Input Pin. Shifts in one bit at a

3 SDO Serial Data Output Pin. Open Drain Output

4 GND Ground pin, logic ground reference

5 V

6 A1 A terminal of RDAC1.

7 W1 Wiper terminal of RDAC1,

8 B1 B terminal of RDAC1.

9 B2 B terminal of RDAC2.

10 W2 Wiper terminal of RDAC2,

11 A2 A terminal of RDAC2.

12 V

13 WP Write Protect Pin. When active low, WP

14 PR Hardware over ride preset pin. Refreshes the

15 CS Serial Register chip select active low. Serial

16 RDY Ready. Active-high open drain output.

AD5231/AD5232/AD5233

AD5232

Negative Supply. Connect to zero volts for

SS

Positive Power Supply Pin. Should be ≥ the

DD

PIN CONFIGURATION

CLK

1

2

SDI

3

SDO

4

GND

5

V

SS

6

A1

7

W1

8

B1

bit at a time on positive clock edges.

time on positive clock CLK edges.

requires external pull-up resistor. Commands 9
& 10 activate the SDO output. See Instruction
operation Truth Table. Other commands shift
out the previously loaded bit pattern delayed
by 16 clock pulses. This allows daisy-chain
operation of multiple packages.

single supply applications.

ADDR(RDAC1) = 0

ADDR(RDAC2) = 1H.

input-logic HIGH voltage.

prevents any changes to the present contents,
except retrieving EEMEM content and
RESET.

scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 80

until EEMEM loaded with a new

H

value by the user (PR is activated at the logic
high transition).

register operation takes place when CS returns
to logic high.

Identifies completion of commands 2, 3, 8, 9,

10.

RDY

16

15

CS

CS

CSCS

14

PR

PR

PRPR

13

WP

WP

WPWP

12

V

DD

11

A2

10

W2

9

B2

.

H

REV PrF 5 22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL[phone]; FAX [phone]; [e-mail]