..
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,. ANALOG
W DEVICES
[
FEATURES
Programmable Gainsfrom 0.1 to 1000
Differential Inputs
HighCMRR: 11OdBmin
Low Drift: 2p.Vfc max (L)
Complete Input Protection, Power ON and Power OFF
Functionally Complete with the Addition of Two Resistors
Internally Compensated
Gain Bandwidth Product: 4OMHz
Output Current Limited: 25mA
Very LowNoise: 05p.V p-p, 0.1Hzto 10Hz, RTI (I G -1000
Chips are Available
Not Recommended for new Designs
PRODUCTDESCRIPTION
The AD521 is a second generation, low cost, monolithic IC
instrUmentation amplifier developed by Analog Devices.Asa
trUeinstrUmentation amplifier, the AD521 is a gain block with
differential inputs and an accurately programmable input/
output gain relationship.
The AD521 ICinstrUmentation amplifier should not be con-
fused with an operational amplifier, although severalmanu-
factUrers(including AnalogDevices)offer op amps which can
be used as building blocks in variablegain instrumentation
amplifier circuits. Op amps are general-purpose components
which, when used with precision-matched external resistors,
can perform the instrUmentation amplifier function.
An instrumentation amplifier is a precision differential volt-
agegain device optimized for operation in a real world envi-
ronment, and is intended to be used wherever acquisition of a
useful signal isdifficult. It is characterized by high input im-
pedance, balanced differential inputs, low bias currents and
high CMR.
Asa complete instrUmentation amplifier, the AD521 requires
only two resistors to set its gain to any value between 0.1 and
1000. The ratio matching of these resistors does not affect the
high CMRR(up to 120dB) or the high input impedance (3 X
109il) of the AD521. Furthermore, unlike most operational
amplifier-basedinstrUmentation amplifiers, the inputs are
protected against overvoltagesup to :1:15volts beyond the
supplies.
The AD521 IC instrumentation amplifier is availablein four
different versions of accuracy and operating temperatUrerange.
The economical "J" grade, the low drift "K" grade, and the
lower drift, higher linearity "L" grade are specified from 0 to
PrecisionInstrumentationAmplifier
PIN CONFIGURATION
+ INPUT I 1
GAI~ 12
OFFSET
TRIM 4
OFFSET
TRIM 8
OUTPUT I 7
+70°C.The "S" grade guarantees performance to specification
over the eXtended temperatUre range: -SSoCto +125°C.
PRODUCTHIGHLIGHTS
1. The ADS21 is a trUeinstrumentation amplifier in integrated
circuit form, offering the user performance comparable to
many modular instrumentation amplifiers at a fraction of
the cost.
2. The AD521 has low guaranteed input offset voltage drift
(21lVf Cfor L grade) and low noise for precision, high gain
applications.
3. The AD521 is functionally complete with the addition of
two resistors. Gain can be preset from 0.1 to more than
1000.
4. The AD521 is fully protected for input levelsup to 15V
beyond the supply voltagesand JOV differential at the
inputs.
5. Internally compensated for allgains, the AD521 also offers
the user the provision for limiting bandwidth.
6. Offset nulling can be achieved with an optional trim pot.
7. The AD521 offers superior dynamic performance with a
gain-bandwidth product of 40MHz, full peak response of
100kHz (independent of gain) and a settling time of 5p.s
to 0.1%of a 10V step.
IntegratedCircuit
AD521 I
141 ~AIN
131 ~ALE
I
I
9 ICOMPo
81 v+
a
01::\/ 1\
-~ ~-- ~_. ~
AD521-SPECIFICATIONS(typical@ Vs =:t15V, RL=2kO and TA= +25°Cunlessotherwisespecified)
www.BDTIC.com/ADI
~
GAIN
Ra..e (For Spocified Operation, Note I)
Equation
Error from Equation
Nonlin..rity (NatO 2)
I..G<IOOO
Gain Temporaturo C""fficient
OUTPUT CHARACTERISTICS
RatOd Output
Output at Maximum Oporati.. Temporaturo
Impodance
DYNAMIC RESPONSE
Small Signal Bandwidth (13dB)
G=I
G= 10
G= 100
G = 1000
Small Signal, t1.0% Flatn..s
G=I
G= 10
G= 100
G = 1000
Full Peak Response (NatO 3)
Skw RatO, I..G ..1000
Settling Time (any 10V stOp to within 10mV of Final Value)
G-I
G= 10
G. 100
Not Recommended for new Designs
G.lOOO
DifforcntiaJ Overload Recovery (130V Input to within
10mV of Final Value) (NatO 4)
G - 1000
Common Mode StOp Recovery (30V Input to within
10mV of Final Value) (NatO 5)
G =1000
VOLTAGE OFFSET (may be nulled)
Input Offset Voltage (Vas,)
vs. Temporature
vs. Supply
Output Offset Voltage (Vaso)
vs. Temporature
vs. Supply (Narc 6)
INPUT CURRENTS
Input Bias Current (either input)
vs. Temporature
vs. Supply
Input Offser Current
vs. Temporature
INPUT
Differential Input Impodance (NatO 7)
Common Mode Input Impedance (NatO 8)
Input Voltage Range for Specified Poriorrnance
(with rospect to ground)
Maximum Voltage without Damage to Unit, Power ON
or OFF Differential Mode (Note 9)
Voltage at either input (Narc 9)
Common Mode Rejection Ratio, DC to 60Hz with IH1
source unbalance
Gol
GolO
GolOO
G . 1000
NOISE
Voltage RTO (p-p)@O.IHz to 10Hz (Narc 10)
RMS RTO, 10Hz to 10kHz
Input Current, rms, 10Hz to 10kHz
REFERENCE TERMINAL
Bias Current
Input Resistance
Voltage Range
Gain to Output
POWER SUPPLY
Oporati!ll Voltage Ra..e
Quincent Supply Current
TEMPERATURE RANGE
Spooned Performance
Oporating
Storage
°Specificatiom AD521JD.
ooSpec:if'ocatioaa AD5Z1KD.
Specificatioaaoubjoct10<!wit<without DOO«.
AD521JD
I to 1000
G. Rs/RC V/V
(to.25~.004G)%
0.2% max
t(3 to.05G)f£mtC
UOV, tlOmA min
tlOV @ SmA min
0.10
>2MHz
300kHz
200kHz
40kHz
75kHz
26kHz
24kHz
6kHz
100kHz
10V/lis
711'
511S
lOlls
35l1s
SOliS
lOllS
3mV max (2mV typ)
1511VtC max (7I1VtC typ)
311V/%
4OOmV max (200mV typ)
4OOIIVtCmax (l50IlV!':C typ)
0.005VOSO/%
80nA max
InAtC max
2%IV
20nA max
250pAtC max
3 x 1O911111.8pF
6 x lO'O11113.0pF
tlOV
30V
Vs tl5V
70dB min (74dB typ)
90dB min (94dB typ)
lOOdB min (l04dB typ)
lOOdB min (lIOdB typ)
311A
IOM11
tlOV
I
t5V to U8V
SmA max
0 to +70.C
-25.C to +85.C
-65.C to +150.C
AD521KD
l.5mV max (0.5mV ryp)
511VtC max (l.5I1Vfc typ)
200mV max (30mV typ)
150llVfc max (50IlV!':C typ)
.
4OnA max
500pAfC max
.
10nA max
125pAtC max
74dB min (80dB typ)
94dB min (lOOdB typ)
1O4dB min (l14dB typ)
llOdB min (l20dB trP,)
AD5HW
0.1% max
.
l.Omv max (0.5mV typ)
2IIV/.C max
.
lOOmV max
7511VtCmax
.
AD521SD
(AD5HSDI883B)
t(l5 to.4G)f£mtc
-
-
-
-55.Cto+125.C
-55.C to +125.C
--
-
---
-- -
--------
REV.A
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[
www.BDTIC.com/ADI
NOTES:
1. Gains below 1 and above 1000 are obtained by simply ad-
justing the gain setting resistors. (Input voltage should be re-
stricted to :t10V for gains equal to or less than 1.)
2. Nonlinearity is defined as the ratio of the deviation from
the "best straight line" through a full scale output range of
1:9volts. With a combination of high gain and :tlO volt output
swing, distortion may increase to as much as 0.3%.
3. Full Peak Response is the frequency below which a typical
amplifier will produce full output swing.
4. Differential Overload Recovery is the time it takes the ampli-
fier to recover from a pulsed 30V differential input with 15V
of common mode voltage, to within 10mV of final value. The
test input is a 30V, 10,us pulse at a 1kHz rate. (When a differ-
ential signal of greater than 11V is applied between the inputs,
transistor clamps are activated which drop the exces!' input
voltage across internal input resistors. If a continuous overload
is maintained, power dissipated in these resistors causes temper-
Not Recommended for new Designs
atUre gradients and a corresponding change in offset voltage,
as well as added thermal time constant, but will not damage
the device.)
5. Common Mode Step Recovery is the time it takes the amp-
lifier to recover from a 30V common mode input with zero
volts of differential signal to within 10mV of final value. The
test input is 30V, 10,us pulse at a 1kHz rate. (When a com-
mon mode signal greater than Vs -o.5V is applied to the
inputs, transistor clamps are activated which drop the excessive
input voltage across internal input resistors. Power dissipated
in these resistors causes temperatUre gradients and a correspon-
ding change in offset voltage, as well as an added thermal time
constant, but will not damage the device.)
6. Output Offset Voltage versus Power Supply includes a
constant 0.005 times the unnulled output offset per percent
change in either power supply. If the output offset is nulled,
the output offset change versus supply change is substantially
reduced.
7. Differential Input Impedance is the impedance between the
two inputs.
8. Common Mode Input Impedance is the impedance from
either input to the power supplies.
9. Maximum Input Voltage (differential or at either input) is
30V when using :t15V supplies. A more general specification is
that neither input may exceed either supply (even when
=0) by more than 15V and that the difference between the
Vs
two inputs must not exceed 30V. (See also Notes 4 and 5.)
10. O.lHz to 10Hz Peak-to-Peak Voltage Noise is defined as
the maximum peak-to-peak voltage noise ovserved during 2
of 3 separate 10 second periods with the test circuit of Fig-
ure 8.
ApplyingtheAD521
a
ORDERING GUIDE
Model
AD52lJD
AD52IKD
AD521LD
AD521SD - 55°C to + 125°C
AD521SD/883B2 - 55°Cto + 125°C
AD52lJ Chips
AD521K Chips
AD521S Chips
NOTES
IFor outline information see Package Information section.
2Standard military drawing available.
Temperature
Range Description Option!
DoC to + 7DoC
DoC to + 7DoC 14-Pin Ceramic DIP
DoC to + 7DoC 14-Pin Ceramic DIP
DoC to + 7DoC Die
DoC to + 7DoC
- 55°C to + 125°C
14-Pin Ceramic DIP
14-Pin Ceramic DIP
14-Pin Ceramic DIP
Die
Die
Package
D-14
D-14
D-14
D-14
D-14
RGAIN
+INPUT
14
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
1
2 3 4 5 6
R GAIN -INPUT OFFSET -Vs OFFSET
~
0.110 {2.8001
TRIM TRIM
8BLA
fN~TRf !MFNTA TfnN AMP! !FfFR.C; 4-,ffl;
AD521
www.BDTIC.com/ADI
DESIGNPRINCIPLE
Figure 1 is a simplifiedschematic of the AD521. A differential
input voltage,VIN,appears across RG causing an imbalance in
the currents through Ql and <l2,~I=VIN/RG' That imbalance
is forced to flow in Rs because the collector currents of Q3
and <4 are constrained to be equal by their biasing (current
mirror). These conditions can only be satisfiedif the differen-
tial voltage across Rs (and hence the output voltage of the
AD521) is equal to ~I X Rs. The feedback amplifier, ApB
4. Do not exceed the allowable input signalrange. The line-
arity of the ADS21 decreases if the inputs are drivenwithin
5 volts of the supply rails, particularly when the deviceis
used at a gain less than 1.Toavoidthispossibility,atten-
uate the input signalthrough a resistivedivider networkand
use the ADS21 as a buffer, as shown in Figure 4. The resis-
tor R/2 matches the impedance seen by both AD521 in-
puts so that the voltage offset caused by bias currents will
be minimized.
performs that function. Therefore, VOUT= V~ X Rs or
VOUT - Rs
VIN - ~
+V
5. Use the compensation pin (pin 9) and the applicable com-
pensation circuit when the amplifier is required to drive a
capacitive load. It is worth mentioning that coaxial cables
can '~invisibly" provide such capacitance since many popu-
lar coaxial cables display capacitance in the vicinity of 3OpF
I-IrQ
VON
per foot.
This compensation (bandwidth control) feature permits the
VOUT V,N
"'RI. 1IQ
OR-VOUT.,,"
v-. Ira
Not Recommended for new Designs
SENSE
user to fit the response of the AD521 to the particular appli-
cation as illustrated by Figure S. In cases of extremely high
load capacitance the compensation circuit may be changed
as follows:
1. Reduce 680n to 24n
2. Reduce BOn to 7.5n
3. Increase 1000pF to O.IJ,LF
4. Set Cx to 1000pF if no compensation was originally
used. Otherwise, do not alter the original value.
'i
t'x
CURRENT MIRROR
IX t
V-
~~,
.'
Figure 7.Simplified AD527 Schematic
APPLICATION NOTES FOR THE AD521
These notes ensure the AD521 will achieve the high level of
performance necessary for many diversified IA applications.
This allows stable operation for load capacitances up to
3000pF, but limits the slew rate to approximately 0.16VIJ,Ls;
6. Signals having frequency components above the Instrumen-
tation Amplifier's output amplifier closed-loop bandwidth
will be transmitted from V- to the output with little or no
attenuation. Therefore, it is advisable to decouple the V-
supply line to the output common or to pin 11.1
V+
1. Gains below 1 are realized by adjusting the gain setting
resistors as shown in Figure 2 (the resistor, as betWeen
pins 10 and 13 should remain 100kn :1:15%,see application
note 3). For best results, the input voltage should be re-
stricted to :tl0V even though the gain may be less than 1.
See Figure 6 for gains above 1000.
2. Provide a return path to ground for input bias currents. The
AD521 is an instrumentation amplifier, not an isolation
amplifier. When using a thermocouple or other "floating"
source, this return path may be provided directly to ground
or indirectly through a resistor to ground from pins 1 and/
+IN
-IN
OUTPUT
OUTPUT
SIGNAL
COMMON
GAIN VALUE OF RO
0.1 1I0Il1
1 1(JOkS1
10 101<!J
100 1k!1
1000 100!J
or 3, as shown in Figure 3. If the return path is not pro-
vided, bias currents will cause the output to saturate. The
Figure 2. Operating Connections for AD527
value of the resistor may be determined by dividing the
maximum allowable common mode voltage for the appli-
cation by the bias current of the instrumentation amplifier.
3. The resistors betWeen pins 10 and 13, (RSCALE) must equal
l00kn :t15% (Figure 2). If RSCALE is too low (below 85kn)
the output swing of the AD521 is reduced. At values below
80kU and above 120kU the stability of the AD521 may be
impaired.
--
- - -
. - - ---
--
I For further details, refer to "An I.C. User's Guide to Decoupling,
Grounding, and Making Things Go Right for a Change," by A. 'ceS
Paul Brokaw. This application note is available from Analog Devi
without charge upon request.
REV. A
- -- - -- - -
j
~
www.BDTIC.com/ADI
[
AD521
R.
~
":'
a). Transformer Coupled, Direct Return
R.
~
b). Thermocouple, Direct Return
Not Recommended for new Designs
c). AC Coupled, Indirect Return
R.
INPUT OFFSET AND OUTPUT OFFSET
When specifying offsets and other errors in an operational
amplifier, it is often convenient to refer these errors to the
inputs. This enables the user to calculate the maximum error
he would see at the output with any gain or circuit configura-
tion. An op amp with 1mV of input offset voltage, for
example, would produce 1V of offset at the output in a gain
of 1000 configuration.
In the case of an instrumcntation amplifier, where the gain is
controlled in the amplifier, it is more convenient to separate
errors into two categories. Those errors which simply add to
the output signal and are unaffected by the gain can be classi-
fied as output errors. Those which act as if they are associated
with the input signal, such that their effect at the output is
proportional to the gain, can be classified as input errors.
As an illustration, a typical ADS21 might have a +30mV output
offset and a -o.7mV input offset. In a unity gain configuration,
the total output offset would be +29.3mV or the sum of the ~
tWo. At a gain of 100, the output offset would be -40mV or:
30mV + 100(-o.7mV) =-40mV.
By separating these errors, one can evaluate the total error
independent of the gain settings used, similar to the situation
with the input offset specifications on an op amp. In a given
gain configuration, both errors can be combined to give a total
error referred to the input (R.T.I.) or output (R.T.O.) by the
following formula:
Total Error R.T.I. =input error + (output error/gain)
Total Error R.T.O. =(Gain x input error) + output error
a
Figure3. Ground Rerums for "Floating" Transducers
7
VOUT
1. ~~~~~:~~:~CK UPGAINLOSTBYR
2. INPUT SIGNAL MUST BE REDUCED IN
PROPORTION TO POWER SUPPLY VOLTAGE LEVEL
Figure 4. Operating Conditions for V/~VS= 10V
V+
+
Villi
Cx = 10fJ1rftwhen ft is the desired bandwidth.
Figure5. Optional Compensation Circuit
RO
V-
1
(ft in kHz, Cx in J.l.F)
GAIN.~
The offset trim adjustment (pins 4 and 6, Figure 2) is associ-
ated primarily with the output offset. At any gain it can be
used to introduce an output offset equal and opposite to the
input offset voltage multiplied by the gain. As a result, the
total output offset can be reduced to zero.
As shown in Figure 6, the gain range on the ADS 21 can be
extended considerably by adding an attenuator in the sense
terminal feedback path (as well as adjusting the ratio, Rs/~).
Since the sense terminal is the inverting input to the output
amplifier, the additional gain to the output is controlled by
Rl and Rz. This gain factor is 1 + Rz/Rl'
RI
V,
VOUT
V2
VOUT .[VREF +(~)(VI -V2)][R' ;,R2]
Figure6. Circuitfor utilizing some of the unique features of the
AD521. Note that gain changesintroduced by changingR1 and
R2 willhave a minimum effect on output offsst if the offsst is
carefully nulled at the highest gainsetting.
R2
R,
OUTPUT COMMON
R~lL--l1
INSTRUMENTA nON AMPLIFIERS 4-21
AD521
www.BDTIC.com/ADI
Where offset errors are critical, a resistor equal to the parallel
combination of Rl and Rz should be placed between pin 11
and VREF. This minimizes the offset errors resulting from the
input current flowing in Rl and Rz at the sense tenninal. Note
that gain changes introduced by changing the Rl/Rz attenua-
tor will have a minimum effect on output offset if the offset
is carefully nulled at the highest gain setting.
When a predetennined output offset is desired, VREF can be
placed in series with pin 11. This offset is then multiplied by
the gain factor 1 + R2/Rl as shown in the equation of
Figure 6.
+15V
Not Recommended for new Designs
I
1
O.,&,.FT
I
lOOk
3Oon
1
14
HF
lOOk
Figure 7. Ground loop elimination. The reference input, Pin 11,
allows remote referencing of ground potential. Differences in
ground potentials are attenuated by the high CMRR of the
AD521.
VIN
I
I VCM
L - -.4'}---------
'-
RG
lOOk
RS
VOUT=VIN
IOk
8
CHART
RECORDER
~
RG
---tt-
2.5j.F
F
10Mn
I
COMMON
-15V
O.I&,.F I I
3Oon
-
=1
Figure 8. Test circuit for measuring peak to peak noise in the
bandwidth 0.1Hz to 10Hz. Typical measurements are found by
reading the maximum peak to peak voltage noise of the device
under test fD.U. T.) for 3 observation periods of 10 seconds each.
- - ---
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REV.A
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