ANALOG DEVICES AD5206 Service Manual

4-/6-Channel

www.BDTIC.com/ADI

FEATURES

256 positions Multiple independently programmable channels

AD5204—4-channel

AD5206—6-channel Potentiometer replacement Terminal resistance of 10 kΩ, 50 kΩ, 100 kΩ 3-wire SPI-compatible serial data input +2.7 V to +5.5 V single-supply operation; ±2.7 V dual-supply

oper

ation

Power-on midscale preset

APPLICATIONS

Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, time constants Line impedance matching

GENERAL DESCRIPTION

The AD5204/AD5206 provides 4-/6-channel, 256-position digitally controlled variable resistor (VR) devices. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the AD5204/AD5206 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 10 k, 50 k, or 100 k has a nominal temperature coefficient of 700 ppm/°C.

Each VR has its own VR latch that holds its programmed re

sistance value. These VR latches are updated from an internal serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eleven data bits make up the data-word clocked into the serial input register. The first three bits are decoded to determine which VR latch will be loaded with the last eight bits of the data-word when the strobe is returned to logic high. A serial data output pin at the opposite end of the serial register (AD5204 only) allows simple daisy chaining in multiple VR applications without requiring additional external decoding logic.

CS

Digital Potentiometers

AD5204/AD5206

FUNCTIONAL BLOCK DIAGRAMS

D7

D0

D7

D0

AD5204

RDAC

LATCH

#1

R

RDAC

LATCH

#4

R

CS

CLK

SDO

SDI

GND

A2 A1 A0

DO

D7

SER REG

DI

D0

POWER-ON

PRESET

EN

ADDR

DEC

8

Figure 1.

D7

D0

D7

D0

AD5206

RDAC

LATCH

#1

R

RDAC

LATCH

#6

R

CS

CLK

SDI

GND

A2 A1 A0

D7

SER REG

DI

D0

POWER-ON

PRESET

EN

ADDR

DEC

8

Figure 2.

An optional reset (PR) pin forces all the AD5204 wipers to the midscale position by loading 0x80 into the VR latch.

The AD5204/AD5206 is available in the 24-lead surface-mount

IC, TSSOP, and PDIP packages. The AD5204 is also available in

SO a 32-lead, 5 mm × 5 mm LFCSP package. All parts are guaranteed to operate over the extended industrial temperature range of

−40°C to +85°C. For additional single-, dual-, and quad-channel devices, see the

AD8400/AD8402/AD8403 data sheets.

V

DD

A1

W1

B1

A4

W4

B4

SHDN

V

SS

PR

V

DD

A1

W1

B1

A6

W6

B6

V

SS

6884-001

06884-002

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5204/AD5206

www.BDTIC.com/ADI

REVISION HISTORY

11/07—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Added 32-Lead LFCSP Package........................................Universal

Changed R

Changes to Absolute Maximum Ratings....................................... 6

Changes to Operation Section ...................................................... 12

Updated Outline Dimensions....................................................... 17

Changes to Ordering Guide.......................................................... 18

9/99—Revision 0: Initial Version

to RAB.............................................................Universal

BA

Pin Configurations and Function Descriptions............................7

Typical Performance Characteristics........................................... 10

Operation......................................................................................... 12

Programming the Variable Resistor............................................. 13

Rheostat Operation.................................................................... 13

Programming the Potentiometer Divider................................... 14

Voltage Output Operation......................................................... 14

Digital Interfacing .......................................................................... 15

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 18

Rev. A | Page 2 of 20

AD5204/AD5206

www.BDTIC.com/ADI

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = 5 V ± 10% or 3 V ± 10%, VSS = 0 V, VA = +VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS RHEOSTAT MODE

Resistor Differential NL Resistor Nonlinearity Error Nominal Resistor Tolerance

3

4

2

R-DNL RWB, VA = no connect −1 ±1/4 +1 LSB R-INL RWB, VA = no connect −2 ±1/2 +2 LSB ΔRAB TA = 25°C −30 +30 %

1

Max Unit

Resistance Temperature Coefficient ΔRAB/ΔT VAB = VDD, wiper = no connect 700 ppm/°C Nominal Resistance Match ΔR/RAB

Channel 1 to Channel 2, Channel 3, and Channel V

4, or to Channel 5 and Channel 6;

= VDD

AB

0.25 1.5 %

Wiper Resistance RW IW = 1 V/R, VDD = 5 V 50 100 Ω

DC CHARACTERISTICS POTENTIOMETER

DIVIDER MODE

2

Resolution N 8 Bits Differential Nonlinearity Integral Nonlinearity Voltage Divider Temperature

5

DNL −1 ±1/4 +1 LSB INL −2 ±1/2 +2 LSB ΔV

/ΔT Code = 0x40 15 ppm/°C

W

Coefficient Full-Scale Error V Zero-Scale Error V

Code = 0x7F −2 −1 0 LSB

WFSE

Code = 0x00 0 +1 +2 LSB

WZSE

RESISTOR TERMINALS

Voltage Range Capacitance7 Ax, Bx CA, CB

Capacitance7 Wx CW

Shutdown Current

6

8

VA, VB, VW VSS VDD V

f = 1 MHz, measured to GND,

ode = 0x40

c f = 1 MHz, measured to GND,

ode = 0x40

c

I

0.01 5 μA

A_SD

45 pF

60 pF

Common-Mode Leakage ICM VA = VB = VW = 0, VDD = +2.7 V, VSS = −2.5 V 1 nA

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH VDD = 5 V/3 V 2.4/2.1 V Input Logic Low VIL VDD = 5 V/3 V 0.8/0.6 V Output Logic High VOH R Output Logic Low VOL IOL = 1.6 mA, V

= 1 kΩ to 5 V 4.9 V

PULL–UP

= 5 V 0.4 V

LOGI C

Input Current IIL VIN = 0 V or 5 V ±1 μA Input Capacitance

7

CIL 5 pF

POWER SUPPLIES

Power Single-Supply Range VDD range VSS = 0 V 2.7 5.5 V Power Dual-Supply Range

V

DD/VSS

±2.3 ±2.7 V

range Positive Supply Current IDD VIH = 5 V or VIL = 0 V 12 60 μA Negative Supply Current ISS VSS = –2.5 V, VDD = +2.7 V 12 60 μA Power Dissipation

9

P

VIH = 5 V or VIL = 0 V 0.3 mW

DISS

Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% 0.0002 0.005 %/%

DYNAMIC CHARACTERISTICS

7, 10

Bandwidth –3 dB BW_10K RAB = 10 kΩ 721 kHz BW_50K RAB = 50 kΩ 137 kHz BW_100K RAB = 100 kΩ 69 kHz

Rev. A | Page 3 of 20

AD5204/AD5206

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ

1

Max Unit

Total Harmonic Distortion THDW VA = 1.414 V rms, VB = 0 V dc, f = 1 kHz 0.004 %

t

VW Settling Time

VA = 5 V, VB = 0 V, ±1 LSB error band 2/9/18 μs

S

(10 kΩ/50 kΩ/100 kΩ)

Resistor Noise Voltage e

INTERFACE TIMING CHARACTERISTICS

7, 11 , 12

N_WB

= 5 kΩ , f = 1 kHz, PR = 0

R

WB

9 nV/√Hz

Input Clock Pulse Width tCH, tCL Clock level high or low 20 ns Data Setup Time tDS 5 ns Data Hold Time tDH 5 ns CLK-to-SDO Propagation Delay CS Setup Time CS High Pulse Width

13

tPD RL = 2 kΩ , CL < 20 pF 1 150 ns t

15 ns

CSS

t

40 ns

CSW

Reset Pulse Width tRS 90 ns

t

CLK Fall to CS Fall Setup CLK Fall to CS Rise Hold Time CS Rise to Clock Rise Setup

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Applies to all VRs.

3

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from the ideal position between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 28. IW = VDD/R for both VDD = 3 V and VDD = 5 V.

4

VAB = VDD, wiper (VW) = no connect.

5

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 27.

6

Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other.

7

Guaranteed by design and not subject to production test.

8

Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.

9

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

10

All dynamic characteristics use VDD = 5 V.

11

Applies to all parts.

12

See the timing diagrams (Figure 3 to Figure 5) for the location of the measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V)

and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V.

13

The propagation delay depends on the values of VDD, RL, and CL (see the Operation section).

0 ns

CSH0

t

0 ns

CSH1

t

10 ns

CS1

Rev. A | Page 4 of 20

AD5204/AD5206

www.BDTIC.com/ADI

TIMING DIAGRAMS

1

SDI

CLK

CS

V

OUT

(DATA IN)

(DATA OUT)

V

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

V

DD

0V

RDAC LATCH LOAD

Figure 3. Timing Diagram

1

SDI

SDO

CLK

CS

OUT

Ax OR Dx Ax OR Dx

0

1

Ax OR Dx Ax OR Dx

0

1

0

t

CSH0

1

0

V

DD

0V

t

DS

t

CH

t

CSS

Figure 4. Detailed Timing Diagram

1

PR

0

V

DD

V

OUT

0V

±1 LSB ERROR BAND

Figure 5. AD5204 Preset Timing Diagram

t

DH

CL

±1 LSB ER ROR BAND

t

RS

t

S

t

PD_MAX

t

CS1

t

±1LSB

CSH1

t

06884-003

t

CSW

S

±1 LSB

06884-004

6884-005

Rev. A | Page 5 of 20

AD5204/AD5206

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

VDD to GND −0.3 V to +7 V VSS to GND 0 V to −7 V VDD to VSS 7 V VA, VB, VW to GND VSS, VDD Ax – Bx, Ax – Wx, Bx – Wx ±20 mA Digital Input and Output Voltage to GND 0 V to +7 V Operating Temperature Range −40°C to +85°C Maximum Junction Temperature (TJ max) 150°C Storage Temperature –65°C to +150°C Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 20 sec to 40 sec Package Power Dissipation (TJ max – TA)/θJA Thermal Resistance, θ

PDIP (N-24-1) 63°C/W

SOIC (RW-24) 52°C/W

TSSOP (RU-24) 50°C/W

LFCSP (CP-32-3) 32.5°C/W

1

Thermal resistance (JEDEC 4-layer (2S2P) board). Paddle soldered to board.

1

JA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 6 of 20

ANALOG DEVICES AD5206 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION