Analog Devices AD5204 6 Datasheet

4-/6-Channel

D7

D0

A1
W1
B1

V

DD

AD5204

CS

CLK

8

EN

ADDR

DEC

A2
A1
A0

SDI

DI

SER
REG

D0

D7

A4
W4
B4

GND

RDAC

LATCH

#1

R

D7

D0

RDAC

LATCH

#4

R

POWER-

ON

PRESET

V

SS

SDO

DO

PR

SHDN

D7

D0

A1
W1
B1

V

DD

AD5206

CS

CLK

8

EN

ADDR

DEC

A2
A1
A0

SDI

DI

SER

REG

D0

D7

A6
W6
B6

GND

RDAC

LATCH

#1

R

D7

D0

RDAC

LATCH

#6

R

POWER-

ON

PRESET

V

SS

a

FEATURES
256 Position
Multiple Independently Programmable Channels

AD5204—4-Channel

AD5206—6-Channel
Potentiometer Replacement
10 k⍀, 50 k⍀, 100 k⍀
3-Wire SPI-Compatible Serial Data Input
+2.7 V to +5.5 V Single Supply; ⴞ2.7 V Dual Supply

Operation

Power ON Midscale Preset

APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching

GENERAL DESCRIPTION

The AD5204/AD5206 provides four-/six-channel, 256 position
digitally-controlled Variable Resistor (VR) devices. These de­vices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the AD5204/
AD5206 contains a fixed resistor with a wiper contact that taps
the fixed resistor value at a point determined by a digital code
loaded into the SPI-compatible serial-input register. The resis­tance between the wiper and either endpoint of the fixed resistor
varies linearly with respect to the digital code transferred into
the VR latch. The variable resistor offers a completely program­mable value of resistance between the A terminal and the wiper
or the B Terminal and the wiper. The fixed A-to-B terminal

resistance of 10 kΩ, 50 kΩ, or 100 kΩ has a nominal tempera­ture coefficient of 700 ppm/°C.

Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eleven data bits make up
the data word clocked into the serial input register. The first
three bits are decoded to determine which VR latch will be
loaded with the last eight bits of the data word when the CS
strobe is returned to logic high. A serial data output pin at
the opposite end of the serial register (AD5204 only) allows
simple daisy-chaining in multiple VR applications without
additional external decoding logic.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Digital Potentiometers

AD5204/AD5206

FUNCTIONAL BLOCK DIAGRAMS

An optional reset (PR) pin forces all the AD5204 wipers to the
midscale position by loading 80

The AD5204/AD5206 is available in both surface mount
(SOL-24), TSSOP-24 and the 24-lead plastic DIP package. All
parts are guaranteed to operate over the extended industrial

temperature range of –40°C to +85°C. For additional single,

dual, and quad channel devices, see the AD8400/AD8402/
AD8403 products.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

into the VR latch.

H

AD5204/AD5206–SPECIFICATIONS

(VDD = +5 V ⴞ 10% or +3 V ⴞ 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40ⴗC < TA < +85ⴗC

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ1Max Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs

Resistor Differential NL
Resistor Nonlinearity Error
Nominal Resistor Tolerance

Resistance Temperature Coefficient ∆R
Nominal Resistance Match ∆R/R

Wiper Resistance R

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs

Resolution N 8 Bits
Differential Nonlinearity
Integral Nonlinearity

Voltage Divider Temperature Coefficient ∆V

Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

5

6

Ax, Bx C

6

Wx C
Shutdown Current
Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance

POWER SUPPLIES

Power Single Supply Range V
Power Dual Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation

Power Supply Sensitivity PSS ∆VDD = +5 V ± 10% 0.0002 0.005 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10K R

Total Harmonic Distortion THD

Settling Time (10K/50K/100K) t

V

W

Resistor Noise Voltage e

INTERFACE TIMING CHARACTERISTICS Applies to All Parts

Input Clock Pulsewidth tCH, t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay

CS Setup Time t
CS High Pulsewidth t

Reset Pulsewidth t
CLK Fall to CS Fall Setup t
CLK Fall to CS Rise Hold Time t
CS Rise to Clock Rise Setup t

NOTES

1

Typicals represent average readings at +25°C and V

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-

tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. IW = VDD/R
for both V

3

VAB = VDD, Wiper (VW) = No connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 22 test circuit.

= +3 V or VDD = +5 V.

DD

2

2

3

4

4

R-DNL RWB, V
R-INL RWB, V

∆R

DNL –1 ±1/4 +1 LSB
INL –2 ±1/2 +2 LSB

VA, VB, V

7

6

8

6, 9

I

C

P

BW_50K R
BW_100K R

11

t

unless otherwise noted.)

= No Connect –1 ±1/4 +1 LSB

A

= No Connect –2 ±1/2 +2 LSB

A

T

AB

/∆TV

AB

AB

W

/∆T Code = 40

W

WFSE

WZSE

W

A, CB

W

A_SD

CM

IH

IL

OH

OL

IL

IL

Range VSS = 0 V 2.7 5.5 V

DD

Range ±2.3 ±2.7 V

DD/SS

DD

SS

DISS

W

S

N_WB

CL

DS

DH

PD

CSS

CSW

RS

CSH0

CSH1

CS1

= +5 V.

DD

= +25°C –30 +30 %

A

= V

AB

CH1 to 2, 3, 4, or 5, 6; V
IW = 1 V/R, V

Code = 7F
Code = 00

f = 1 MHz, Measured to GND, Code = 40
f = 1 MHz, Measured to GND, Code = 40

, Wiper = No Connect 700 ppm/°C

DD

= +5 V 50 100 Ω

DD

H

H

H

AB

= V

DD

0.25 1.5 %

15 ppm/°C

–2 –1 0 LSB
0+1+2LSB

V

SS

H

H

45 pF
60 pF

V

DD

0.01 5 µA

VA = VB = VW = 0, VDD = +2.7 V, VSS = –2.5 V 1 nA

VDD = +5 V/+3 V 2.4/2.1 V
VDD = +5 V/+3 V 0.8/0.6 V
R
IOL = 1.6 mA, V
V

= 1 kΩ to +5 V 4.9 V

PULL–UP

= 0 V or +5 V ±1 µA

IN

= +5 V 0.4 V

LOGIC

5pF

VIH = +5 V or V
VSS = –2.5 V, V

= 0 V 12 60 µA

IL

= +2.7 V 12 60 µA

DD

VIH = +5 V or VIL = 0 V 0.3 mW

= 10 kΩ 721 kHz

AB

= 50 kΩ 137 kHz

AB

= 100 kΩ 69 kHz

AB

VA = 1.414 V rms, VB = 0 V dc, f = 1 kHz 0.004 %
VA = 5 V, V
R

= 5 kΩ, f = 1 kHz, PR = 0 9 nV/√Hz

WB

= 0 V, ±1 LSB Error Band 2/9/18 µs

B

6, 10

Clock Level High or Low 20 ns

5ns
5ns

R

= 2 kΩ, C

L

< 20 pF 1 150 ns

L

15 ns
40 ns
90 ns
0ns
0ns
10 ns

V

–2–

REV. 0

AD5204/AD5206

WARNING!

ESD SENSITIVE DEVICE

5

Resistor Terminals A, B, W, have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.

8

P

is calculated from (I

DISS

9

All dynamic characteristics use VDD = +5 V.

10

See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V. Switching characteristics are measured using both VDD = +3 V or +5 V.

11

Propagation delay depends on value of VDD, RL and CL. See Operation section.

Specifications subject to change without notice.

× V

). CMOS logic level inputs result in minimum power dissipation.

DD

DD

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C, unless otherwise noted)

A

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V

V

SS

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V

V

DD

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

V

A

Ax–Bx, Ax–Wx, Bx–Wx . . . . . . . . . . . . . . . . . . . . . . ±20 mA

Digital Input and Output Voltage to GND . . . . . . . 0 V, +7 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

MAX) . . . . . . . .+150°C

J

Package Power Dissipation . . . . . . . . . . . . . . (TJ max–T

Thermal Resistance θ

JA

P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W

SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W

TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

DD

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5204/AD5206 features proprietary ESD protection circuitry, permanent dam­age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

)/θ

A

JA

REV. 0

–3–

AD5204/AD5206

PR

V

OUT

V

DD

1

0

0V

61 LSB

t

S

61 LSB ERROR BAND

t

RS

1

SDI

CLK

CS

V

OUT

(DATA IN)

(DATA OUT)

V

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0
1
0
1
0

V

DD

0V

Figure 1. Timing Diagram

1

SDI

SDO

CLK

CS

OUT

Ax OR Dx Ax OR Dx

0

1

Ax OR Dx Ax OR Dx

0

1

0

t

CSH0

1
0

V

DD

0V

t

t

DS

CH

t

CSS

RDAC LATCH LOAD

t

DH

t

CL

61 LSB ERROR BAND

t

PD_MAX

t

CS1

t

CSH1

Figure 3. AD5204 Preset Timing Diagram

t

CSW

t

S

61 LSB

Figure 2. Detail Timing Diagram

ORDERING GUIDE

Model k⍀ Temperature Range Package Descriptions Package Options

AD5204BN10 10 –40°C to +85°C 24-Lead Narrow Body (PDIP) N-24
AD5204BR10 10 –40°C to +85°C 24-Lead Wide Body (SOIC) R-24/SOL-24
AD5204BRU10 10 –40°C to +85°C 24-Lead Thin Shrink SO Package (TSSOP) RU-24

AD5204BN50 50 –40°C to +85°C 24-Lead Narrow Body (PDIP) N-24
AD5204BR50 50 –40°C to +85°C 24-Lead Wide Body (SOIC) R-24/SOL-24
AD5204BRU50 50 –40°C to +85°C 24-Lead Thin Shrink SO Package (TSSOP) RU-24

AD5204BN100 100 –40°C to +85°C 24-Lead Narrow Body (PDIP) N-24
AD5204BR100 100 –40°C to +85°C 24-Lead Wide Body (SOIC) R-24/SOL-24
AD5204BRU100 100 –40°C to +85°C 24-Lead Thin Shrink SO Package (TSSOP) RU-24

AD5206BN10 10 –40°C to +85°C 24-Lead Narrow Body (PDIP) N-24
AD5206BR10 10 –40°C to +85°C 24-Lead Wide Body (SOIC) R-24/SOL-24
AD5206BRU10 10 –40°C to +85°C 24-Lead Thin Shrink SO Package (TSSOP) RU-24
AD5206BN50 50 –40°C to +85°C 24-Lead Narrow Body (PDIP) N-24
AD5206BR50 50 –40°C to +85°C 24-Lead Wide Body (SOIC) R-24/SOL-24
AD5206BRU50 50 –40°C to +85°C 24-Lead Thin Shrink SO Package (TSSOP) RU-24
AD5206BN100 100 –40°C to +85°C 24-Lead Narrow Body (PDIP) N-24
AD5206BR100 100 –40°C to +85°C 24-Lead Wide Body (SOIC) R-24/SOL-24
AD5206BRU100 100 –40°C to +85°C 24-Lead Thin Shrink SO Package (TSSOP) RU

The AD5204/AD5206 contains 5,925 transistors. Die size; 92 mil × 114 mil, 10,488 sq. mil.

-24

–4– REV. 0