Analog Devices AD5203 Datasheet

4-Channel, 64-Position

SHDN

DAC 1

A1
W1
B1
AGND1

6

V

DD

DGND

SDI

CLK

CS

AD5203

SDO

SHDN

A2
W2
B2
AGND2

A3
W3

B3
AGND3

A4
W4
B4
AGND4

6

2

RS

6-BIT

LATCH

CK

RS

6

6-BIT

LATCH

CK

RS

SHDN

DAC 2

SHDN

DAC 3

6

6

SHDN

DAC 4

6-BIT

LATCH

CK

RS

6-BIT

LATCH

CK

RS

DAC

SELECT

A1, A0

1
2
3
4

8-BIT

SERIAL

LATCH

D

CK

Q

RS

a

Digital Potentiometer

AD5203

FEATURES
64 Position
Replaces Four Potentiometers
10 k⍀, 100 k⍀
Power Shutdown—Less than 5 ␮A
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single Supply Operation
Midscale Preset

APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment

GENERAL DESCRIPTION

The AD5203 provides a quad channel, 64-position digitally­controlled variable resistor (VR) device. These parts perform the
same electronic adjustment function as a potentiometer or vari­able resistor. The AD5203 contains four independent variable
resistors in a 24-lead SOIC and the compact TSSOP-24 pack­ages. Each part contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a digi­tal code loaded into the controlling serial input register. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code transferred
into the VR latch. Each variable resistor offers a completely
programmable value of resistance, between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B

terminal resistance of 10 kΩ, or 100 kΩ has a ±1% channel-to-

channel matching tolerance with a nominal temperature coeffi-

cient of 700 ppm/°C.

Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eight data bits make up the
data word clocked into the serial input register. The data word is
decoded where the first two bits determine the address of the VR
latch to be loaded, the last 6-bits are data. A serial data output
pin at the opposite end of the serial register allows simple daisy­chaining in multiple VR applications without additional external
decoding logic.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

The reset RS pin forces the wiper to the midscale position by
loading 20
tor to an end-to-end open circuit condition on terminal A and
shorts the wiper to terminal B, achieving a microwatt power
shutdown state. When shutdown is returned to logic-high the
previous latch settings put the wiper in the same resistance set­ting prior to shutdown.

The AD5203 is available in a narrow body P-DIP-24, the
24-lead surface mount package, and the compact 1.1 mm thin
TSSOP-24 package. All parts are guaranteed to operate over the

extended industrial temperature range of –40°C to +85°C.

For pin compatible higher resolution applications, see the 256­position AD8403 product.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

FUNCTIONAL BLOCK DIAGRAM

into the VR latch. The SHDN pin forces the resis-

H

AD5203–SPECIFICATIONS

(VDD = +3 V ⴞ 10% or +5 V ⴞ 10%, VA = +VDD, VB = 0 V, –40ⴗC < TA < +85ⴗC unless

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ1Max Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs

Resistor Differential NL
Resistor Nonlinearity Error
Nominal Resistor Tolerance

Resistance Temperature Coefficient ∆R

Wiper Resistance R

Nominal Resistance Match ∆R/R

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs

Resolution N 6 Bits
Differential Nonlinearity Error
Integral Nonlinearity Error

Voltage Divider Temperature Coefficient ∆V

Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

5

6

Ax, Bx C

6

Wx C
Shutdown Supply Current
Shutdown Wiper Resistance R

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance

POWER SUPPLIES

Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)

Power Supply Sensitivity PSS ∆V

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10K R

Total Harmonic Distortion THD

Settling Time tS_10K VA = VDD, V

V

W

Resistor Noise Voltage e

Crosstalk

11

INTERFACE TIMING CHARACTERISTICS Applies to All Parts

Input Clock Pulsewidth tCH, t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay

CS Setup Time t
CS High Pulsewidth t

Reset Pulsewidth t
CLK Fall to CS Rise Hold Time t

CS Rise to Clock Rise Setup t

2

2

3

4

4

R-DNL RWB, V
R-INL RWB, V

∆R

DNL –0.25 ±0.1 +0.25 LSB
INL –0.75 ±0.1 +0.75 LSB

VA, VB, V

7

6

8

9

I

C

I
P

PSS ∆VDD = +3 V ± 10% 0.006 0.03 %/%

6, 10

BW_100K R

t

C

13

t

otherwise noted)

= No Connect –0.25 ±0.1 +0.25 LSB

A

= No Connect –0.5 ±0.1 +0.5 LSB

A

AB

/∆TV

AB

W

O

/∆T Code = 20

W

WFSE

WZSE

A, CB

W

A_SD

W_SD

IH

IL

IH

IL

OH

OL

IL

IL

Range 2.7 5.5 V

DD

DD

DD

DISS

W

_100K VA = VDD, V

S

NWB

T

CL

DS

DH

PD

CSS

CSW

RS

CSH

CS1

= V

AB

IW = 1 V/R
CH 1 to CH 2, VAB = VDD , T

Code = 3F
Code = 00

W

, Wiper = No Connect 700 ppm/°C

DD

AB

H

H

H

= +25°C 0.2 1 %

A

f = 1 MHz, Measured to GND, Code = 20
f = 1 MHz, Measured to GND, Code = 20
VA = VDD, V
VA = VDD, VB = 0 V, SHDN = 0, V

= 0 V, SHDN = 0 0.01 5 µA

B

= +5 V 45 100 Ω

DD

VDD = +5 V 2.4 V
VDD = +5 V 0.8 V
VDD = +3 V 2.1 V
VDD = +3 V 0.6 V
R

= 2.2 kΩ to V

L

DD

IOL = 1.6 mA, VDD = +5 V 0.4 V
VIN = 0 V or +5 V, V

VIH = VDD or V

= +5 V ±1 µA

DD

= 0 V 0.01 5 µA

IL

VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, V

= +5 V ± 10% 0.0002 0.001 %/%

DD

= 10 kΩ 600 kHz

AB

= 100 kΩ 71 kHz

AB

= +5.5 V 27.5 µW

DD

VA =1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %

= 0 V, ±1 LSB Error Band 2 µs

B

= 0 V, ±1 LSB Error Band 18 µs

R

WB

R

WB

B

= 5 kΩ, f = 1 kHz, RS = 0 9 nV/√Hz
= 50 kΩ, f = 1 kHz, RS = 0 29 nV/√Hz

VA = VDD, VB = 0 V –65 dB

6, 12

Clock Level High or Low 10 ns

R

= 2.2 kΩ, C

L

< 20 pF 1 25 ns

L

–30 +30 %

45 100 Ω

20 ppm/°C

–0.75 –0.2 0 LSB
0 +0.1 +0.75 LSB

0V

H

H

75 pF
120 pF

DD

VDD–0.1 V

5pF

5ns
5ns

10 ns
10 ns
50 ns

0ns

10 ns

V

–2– REV. 0

AD5203

WARNING!

ESD SENSITIVE DEVICE

SDI

CLK

CS

V

OUT

1

0

1

0

1

0

V

DD

0V

D0D1D2D3D4D5A0A1

DAC REGISTER LOAD

CLK

V

OUT

1
0

1
0

1
0

V

DD

0V

SDI

(DATA IN)

SDO

(DATA OUT)

CS

1
0

Ax OR Dx Ax OR Dx

A'x OR D'x

t

DStDH

t

PD MAX

t

PD MIN

t

CH

t

CS1

t

CL

t

CSS

t

CSH

61 LSB

6 1 LSB ERROR BAND

t

CSW

t

S

A'x OR D'x

V

OUT

V

DD

0V

RS

1
0

61 LSB

61 LSB ERROR BAND

t

S

t

RS

NOTES

1

Typicals represent average readings at +25°C and V

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-

tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. IW = VDD/R
for both V

3

VAB = VDD, Wiper (VW) = No connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode.

8

Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of IDD vs. logic voltage

inputs result in minimum power dissipation.

9

P

DISS

10

All dynamic characteristics use VDD = +5 V.

11

Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

12

See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V

13

Propagation delay depends on value of VDD, RL and CL. See Operation section.

= +3 V or VDD = +5 V.

DD

is calculated from (I

× V

). CMOS logic level inputs result in minimum power dissipation.

DD

DD

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C, unless otherwise noted)

A

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

V

A

IAB, IAW, I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

BW

Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

J

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C

Package Power Dissipation . . . . . . . . . . . . . . (T

Thermal Resistance θ

JA

P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W

SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W

TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

= +5 V.

DD

= +3 V or +5 V. Input logic should have a 1 V/ µs minimum slew rate.

DD

DD

MAX) . . . . . . . .+150°C

max–T

J

)/θ

A

Figure 1a. Timing Diagram

JA

Table I. Serial-Data Word Format

ADDR DATA
B7 B6 B5 B4 B3 B2 B1 B0

A1 A0 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB

7

2

6

2

5

2

0

2

Figure 1b. Detail Timing Diagram

Figure 1c. Reset Timing Diagram

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–3–REV. 0

AD5203

PIN CONFIGURATION

AGND2

B2
A2
W2

AGND4

B4
A4
W4

DGND

SHDN

CS

SDI

1
2
3
4
5

AD5203

6

(Not to Scale)

7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

B1
A1
W1
AGND1
B3
A3
W3
AGND3
V

DD

RS

CLK
SDO

PIN FUNCTION DESCRIPTIONS

Pin
No. Name Description

1 AGND2 Analog Ground #2*
2 B2 B Terminal RDAC #2
3 A2 A Terminal RDAC #2
4 W2 Wiper RDAC #2, addr = 01

2

5 AGND4 Analog Ground #4*
6 B4 B Terminal RDAC #4
7 A4 A Terminal RDAC #4
8 W4 Wiper RDAC #4, addr = 11

2

9 DGND Digital Ground*
10 SHDN Active Low Input. Terminal A open circuit.

Shutdown controls Variable Resistors #1
through #4.

11 CS Chip Select Input, Active Low. When CS

returns high data in the serial input register
is decoded based on the address bits and

loaded into the target DAC register.
12 SDI Serial Data Input
13 SDO Serial Data Output. Open drain transistor

requires pull-up resistor.
14 CLK Serial Clock Input, positive edge triggered.
15 RS Active low reset to midscale; sets RDAC

16 V

DD

registers to 20

Positive power supply, specified for opera-

.

H

tion at both +3 V and +5 V.
17 AGND3 Analog Ground #3*
18 W3 Wiper RDAC #3, addr =10

2

19 A3 A Terminal RDAC #3
20 B3 B Terminal RDAC #3
21 AGND1 Analog Ground #1*
22 W1 Wiper RDAC #1, addr = 00

2

23 A1 A Terminal RDAC #1
24 B1 B Terminal RDAC #1

*All AGNDs must be connected to DGND voltage potential.

ORDERING GUIDE

Model k⍀ Temperature Range Package Descriptions Package Options

AD5203AN10 10 –40°C to +85°C 24-Lead Narrow Body Plastic DIP N-24
AD5203AR10 10 –40°C to +85°C 24-Lead Wide Body (SOIC) SOL-24
AD5203ARU10 10 –40°C to +85°C 24-Lead Thin Surface Mount Package (TSSOP) RU-24
AD5203AN100 100 –40°C to +85°C 24-Lead Narrow Body Plastic DIP N-24
AD5203AR100 100 –40°C to +85°C 24-Lead Wide Body (SOIC) SOL-24
AD5203ARU100 100 –40°C to +85°C 24-Lead Thin Surface Mount Package (TSSOP) RU-24

–4– REV. 0