Analog Devices AD5201BRM50-REEL7, AD5201BRM10-REEL7, AD5200BRM50-REEL7, AD5200BRM10-REEL7 Datasheet

256-Position and 33-Position

a

FEATURES
AD5200—256-Position
AD5201—33-Position
10 k, 50 k
3-Wire SPI-Compatible Serial Data Input
Single Supply 2.7 V to 5.5 V or
Dual Supply 2.7 V for AC or Bipolar Operations
Internal Power-On Midscale Preset

APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching

GENERAL DESCRIPTION

The AD5200 and AD5201 are programmable resistor devices,
with 256 positions and 33 positions respectively, that can be digi­tally controlled through a 3-wire SPI serial interface. The terms
programmable resistor, variable resistor (VR), and RDAC are
commonly used interchangeably to refer to digital potentiometers.
These devices perform the same electronic adjustment function
as a potentiometer or variable resistor. Both AD5200/AD5201
contain a single variable resistor in the compact µSOIC-10
package. Each device contains a fixed wiper resistance at the
wiper contact that taps the programmable resistance at a point
determined by a digital code. The code is loaded in the serial
input register. The resistance between the wiper and either end
point of the programmable resistor varies linearly with respect to
the digital code transferred into the VR latch. Each variable
resistor offers a completely programmable value of resistance,
between the A terminal and the wiper, or the B terminal and the
wiper. The fixed A-to-B terminal resistance of 10 kΩ or 50 kΩ

Digital Potentiometers

AD5200/AD5201

FUNCTIONAL BLOCK DIAGRAM

V

CS

CLK

SDI

GND

DD

AD5200/AD5201

SER
REG

8/6

Dx

PWR-ON
PRESET

RDAC

REG

has a nominal temperature coefficient of 500 ppm/°C. The VR
has a VR latch that holds its programmed resistance value. The
VR latch is updated from an SPI-compatible serial-to-parallel
shift register that is loaded from a standard 3-wire serial-input
digital interface. Eight data bits for the AD5200 and six data
bits for the AD5201 make up the data word that is clocked into
the serial input register. The internal preset forces the wiper to
the midscale position by loading 80

and 10H into AD5200 and

H

AD5201 VR latches respectively. The SHDN pin forces the
resistor to an end-to-end open-circuit condition on the A terminal
and shorts the wiper to the B terminal, achieving a microwatt
power shutdown state. When SHDN is returned to logic high,
the previous latch setting puts the wiper in the same resistance
setting prior to shutdown. The digital interface is still active dur­ing shutdown so that code changes can be made that will produce
a new wiper position when the device is returned from shutdown.

All parts are guaranteed to operate over the extended industrial
temperature range of –40°C to +85°C.

V

SS

A

W

B

SHDN

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD5200/AD5201–SPECIFICATIONS

(VDD = 5 V  10%, or 3 V  10%, VSS = 0 V, VA = +VDD, VB = 0 V,

AD5200 ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient R
Wiper Resistance R

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)

Resolution N 8 Bits
Differential Nonlinearity
Integral Nonlinearity

4

4

Voltage Divider Temperature Coefficient ∆V
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

5

6

A, B CA,

6

WC
Shutdown Supply Current
Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

6

POWER SUPPLIES

Logic Supply V
Power Single-Supply Range V
Power Dual-Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation

8

Power Supply Sensitivity PSS ∆VDD = +5 V ± 10%, Code = Midscale –0.01 0.001 +0.01 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10 kΩ RAB = 10 kΩ, Code = 80

Total Harmonic Distortion THD

Settling Time (10 kΩ/50 kΩ)tSVA = 5 V, VB = 0 V, ± 1 LSB Error Band 2/9 µs

V

W

Resistor Noise Voltage Density e

NOTES

1

Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi­tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
VSS = –2.7 V.

3

VAB = VDD, Wiper (VW) = No connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.

5

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. A terminal is open-circuited in shutdown mode.

8

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

9

All dynamic characteristics use VDD = 5 V, VSS = 0 V.

Specifications subject to change without notice.

2

2

3

R-DNL RWB, VA = No Connect –1 ± 0.25 +1 LSB
R-INL RWB, VA = No Connect –2 ± 0.5 +2 LSB
∆R

AB

/∆TV

AB

W

DNL –1 ± 1/4 +1 LSB
INL –2 ±1/2 +2 LSB

/∆T Code = 80

W

WFSE

WZSE

VA, B,

W

B

7

6, 9

W

I

DD_SD

CM

IH

IL

IH

IL

IL

C

IL

LOGIC

DD RANGE

DD/SS RANGE

DD

SS

P

DISS

BW_50 kΩ R

W

N_WB

–40C < TA < +85C unless otherwise noted.)

TA = 25°C –30 +30 %

= VDD, Wiper = No Connect 500 ppm/ °C

AB

VDD = 5 V 50 100 Ω

Code = FF
Code = 00

f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80

H

H

H

H

H

VDD = 5.5 V 0.01 5 µA
VA = VB = VDD/2 1 nA

VDD = 3 V, VSS = 0 V 2.1 V
VDD = 3 V, VSS = 0 V 0.6 V
VIN = 0 V or 5 V ±1 µA

VSS = 0 V –0.3 5.5 V

VIH = +5 V or VIL = 0 V 15 40 µA
VSS = –5 V 15 40 µA
VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = 0 V 0.2 mW

= 50 kΩ, Code = 80

AB

H

H

VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ 0.003 %

RWB = 5 kΩ, RS = 0 9 nV√Hz

5 ppm/ °C

–1.5 –0.5 0 LSB
0 +0.5 +1.5 LSB

V

SS

V

V

DD

45 pF
60 pF

2.4 V

0.8 V

5pF

2.7 5.5 V

± 2.3 ±2.7 V

600 kHz
100 kHz

= VDD/R for both VDD = +2.7 V,

W

= VDD and VB = 0 V. DNL

A

–2–

REV. B

AD5200/AD5201

(VDD = 5 V  10%, or 3 V  10%, VSS = 0 V, VA = +VDD, VB = 0 V,

AD5201 ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient R
Wiper Resistance R

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)

Resolution
Differential Nonlinearity
Integral Nonlinearity

4

5

5

Voltage Divider Temperature Coefficient ∆V
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

6

7

A, B CA,

7

WC
Shutdown Supply Current
Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

7

POWER SUPPLIES

Logic Supply V
Power Single-Supply Range V
Power Dual-Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation

9

Power Supply Sensitivity PSS ∆VDD = +5 V ± 10% –0.01 0.001 +0.01 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10 kΩ RAB = 10 kΩ, Code = 10

Total Harmonic Distortion THD

Settling Time (10 kΩ/50 kΩ)tSVA = 5 V, VB = 0 V, ± 1 LSB Error Band 2/9 µs

V

W

Resistor Noise Voltage Density e

NOTES

1

Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi­tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
VSS = –2.7 V.

3

VAB = VDD, Wiper (VW) = No connect.

4

Six bits are needed for 33 positions even though it is not a 64-position device.

5

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.

6

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

7

Guaranteed by design and not subject to production test.

8

Measured at the A terminal. A terminal is open-circuited in shutdown mode.

9

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

10

All dynamic characteristics use VDD = 5 V, VSS = 0 V.

Specifications subject to change without notice.

2

2

3

R-DNL RWB, VA = No Connect –0.5 ± 0.05 +0.5 LSB
R-INL RWB, VA = No Connect –1 ± 0.1 +1 LSB
∆R

AB

/∆TV

AB

W

N 6 Bits
DNL –0.5 ±0.01 +0.5 LSB
INL –1 ±0.02 +1 LSB

/∆T Code = 10

W

WFSE

WZSE

VA, B,

W

B

8

7, 10

W

I

DD_SD

CM

IH

IL

IH

IL

IL

C

IL

LOGIC

DD RANGEVSS

DD/SS RANGE

DD

SS

P

DISS

BW_50 kΩ R

W

N_WB

–40C < TA < +85C unless otherwise noted.)

TA = 25°C –30 +30 %

= VDD, Wiper = No Connect 500 ppm/ °C

AB

VDD = 5 V 50 100 Ω

Code = 20
Code = 00

f = 1 MHz, Measured to GND, Code = 10
f = 1 MHz, Measured to GND, Code = 10

H

H

H

H

H

VDD = 5.5 V 0.01 5 µA
VA = VB = VDD/2 1 nA

VDD = 3 V, VSS = 0 V 2.1 V
VDD = 3 V, VSS = 0 V 0.6 V
VIN = 0 V or 5 V ±1 µA

= 0 V –0.3 5.5 V

VIH = +5 V or VIL = 0 V 15 40 µA
VSS = –5 V 15 40 µA
VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = –5 V 0.2 mW

= 50 kΩ, Code = 10

AB

H

H

VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ 0.003 %

RWB = 5 kΩ, RS = 0 9 nV√Hz

W

5 ppm/ °C

–1/2 –1/4 0 LSB
0 +1/4 +1/2 LSB

V

SS

V

V

DD

45 pF
60 pF

2.4 V

0.8 V

5pF

2.7 5.5 V

± 2.3 ±2.7 V

600 kHz
100 kHz

= VDD/R for both VDD = +2.7 V,

= VDD and VB = 0 V. DNL

A

REV. B

–3–

AD5200/AD5201–SPECIFICATIONS

(VDD = 5 V  10%, or 3 V  10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40C < TA < +85C

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ

INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 2, 3])

Input Clock Pulsewidth t
Data Setup Time t
Data Hold Time t

CS Setup Time t
CS High Pulsewidth t

CLK Fall to CS Fall Hold Time t
CLK Fall to CS Rise Hold Time t
CS Rise to Clock Rise Setup t

NOTES

1

Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.

2

Guaranteed by design and not subject to production test.

3

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of

1.5 V. Switching characteristics are measured using V

Specifications subject to change without notice.

SDI

CLK

CS

VOUT

unless otherwise noted.)

, t

CH

CL

DS

DH

CSS

CSW

CSH0

CSH1

CS1

= 5 V.

LOGIC

1

0

1

0
1

0
1

0

Figure 1a. AD5200 Timing Diagram

Clock Level High or Low 20 ns

D7 D6 D5 D4 D3 D2 D1 D0

DAC REGISTER LOAD

1

Max Unit

5ns
5ns
15 ns
40 ns
0ns
0ns
10 ns

1

SDI D5D4D3D2D1D0

0
1

CLK

0

CS

VOUT

1

0
1

0

DAC REGISTER LOAD

Figure 1b. AD5201 Timing Diagram

1

SDI

(DATA IN)

CLK

CS

VOUT

0

1

0

1

0

V

DD

0

Dx Dx

t

CSH0

t

CSS

t

DS

t

CH

t

CL

t

DH

Figure 1c. Detail Timing Diagram

t

CSH1

t

CS1

t

CSW

t

S

1LSB

–4–

REV. B

AD5200/AD5201

TOP VIEW

(Not to Scale)

10

9

8

7

6

1

2

3

4

5

AD5200/

AD5201

B

V

SS

GND

CS

SDI

A

W

V

DD

SHDN

CLK

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted)

1

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +7 V

V

DD

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V

SS

V

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

A

I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA

MAX

DD

2

Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

Max) . . . . . . . . . 150°C

J

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300° C

Thermal Resistance θ
Package Power Dissipation = (T

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

2

Max current is bounded by the maximum current handling of the switches,

maximum power dissipation of the package, and maximum applied voltage across
any two of the A, B, and W terminals at a given resistance. Please refer to TPC 31
and TPC 32 for detail.

µSOIC-10 . . . . . . . . . . . . . 200°C/W

JA,

Max – TA)/θ

J

JA

PIN FUNCTION DESCRIPTIONS

Pin Name Description

1 B B Terminal.
2V

SS

Negative Power Supply, specified for opera­tion from 0 V to –2.7 V.

3 GND Ground.
4 CS Chip Select Input, Active Low. When CS

returns high, data will be loaded into the

DAC register.
5 SDI Serial Data Input.
6 CLK Serial Clock Input, positive edge triggered.
7 SHDN Active Low Input. Terminal A open circuit.

Shutdown controls Variable Resistors of

RDAC to temporary infinite.
8V

DD

Positive Power Supply (Sum of VDD + V

SS

≤ 5.5 V).
9 W Wiper Terminal.
10 A A Terminal.

PIN CONFIGURATION

ORDERING GUIDE

Temperature Package Package Full Branding

Model RES k Range Description Option Reel Qty. Information

AD5200BRM10-REEL7 256 10 –40°C/+85°C µSOIC-10 RM-10 5000 DLA
AD5200BRM50-REEL7 256 50 –40°C/+85°C µSOIC-10 RM-10 5000 DLB
AD5201BRM10-REEL7 33 10 –40°C/+85°C µSOIC-10 RM-10 5000 DMA
AD5201BRM50-REEL7 33 50 –40°C/+85°C µSOIC-10 RM-10 5000 DMB

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although

WARNING!

the AD5200/AD5201 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. B

–5–

ESD SENSITIVE DEVICE