ANALOG DEVICES AD5040 Service Manual

Fully Accurate 14-/16-Bit V

nanoDAC

OUT

™

SPI Interface 2.7 V to 5.5 V, in an SOT-23

FEATURES

Single 14-/16-bit DAC, 1 LSB INL
Power-on reset to midscale or zero scale
Guaranteed monotonic by design
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
Small 8-lead SOT-23 package, low power
Fast settling time of 4 μs typically

2.7 V to 5.5 V power supply
Low glitch on power-up

interrupt facility

SYNC

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

GENERAL DESCRIPTION

The AD5040 and the AD5060, members of the ADI nanoDAC
family, are low power, single 14-/16-bit buffered voltage-out
DACs that operate from a single 2.7 V to 5.5 V supply. The
AD5040/AD5060 parts offer a relative accuracy specification
of ±1 LSB and operation are guaranteed monotonic with a
±1 LSB DNL specification. The parts use a versatile 3-wire serial
interface that operates at clock rates up to 30 MHz and is
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards. The reference for both the AD5040
and AD5060 is supplied from an external V
buffer is also provided on-chip. The AD5060 incorporates a
power-on reset circuit that ensures the DAC output powers up
to midscale or zero scale and remains there until a valid write
takes place to the device. The AD5040 and the AD5060 both
contain a power-down feature that reduces the current con­sumption of the device to typically 330 nA at 5 V and provides
software-selectable output loads while in power-down mode.
The parts are put into power-down mode over the serial
interface. Total unadjusted error for the parts is <2 mV.
Both parts exhibit very low glitch on power-up.

pin. A reference

REF

AD5040/AD5060

FUNCTIONAL BLOCK DIAGRAM

V

REF

POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

SCLK DIN

SYNC DACGND

BUF

REF(+)

DAC

POWER-DOWN

CONTROL LOGIC

Figure 1.

PRODUCT HIGHLIGHTS

1. Available in a small, 8-lead SOT-23 package.

2. 14-/16-bit accurate, 1 LSB INL.

3. Low glitch on power-up.

4. High speed serial interface with clock speeds up to 30 MHz.

5. Three power-down modes available to the user.

6. Reset to known output voltage (midscale, zero scale).

Table 1. Related Devices

Part No. Description

AD5061 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 4 LSB INL, SOT-23
AD5062 2.7 V to 5.5 V, 16-bit nanoDAC D/A,1 LSB INL, SOT-23
AD5063 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 1 LSB INL, MSOP

V

DD

AD5040/

OUTPUT
BUFFER

AD5060

RESISTOR
NETWORK

V

OUT

AGND

04767-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005-2010 Analog Devices, Inc. All rights reserved.

AD5040/AD5060

TABLE OF CONTENTS

Features .............................................................................................. 1

Reference Buffer ......................................................................... 15

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ..................................................................... 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

DAC Architecture ....................................................................... 15

REVISION HISTORY

Serial Interface ............................................................................ 15

Power-On reset ........................................................................... 16

Software Reset ............................................................................. 16

Power-Down Modes .................................................................. 17

Microprocessor Interfacing ....................................................... 17

Applications ..................................................................................... 19

Choosing a Reference for the AD5040/ AD5060 ................... 19

Bipolar Operation Using the AD5040/ AD5060 .................... 19

Using the AD5040/AD5060 with a Galvanically Isolated

Interface Chip ............................................................................. 20

Power Supply Bypassing and Grounding ................................ 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21



1/10—Rev. 0 to Rev. A

Changes to Table 2, Relative Accuracy (INL) and Endnote 1 .... 3

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 21

10/05—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD5040/AD5060

SPECIFICATIONS

VDD = 5.5 V, V

Table 2.

A, B, and Y Grades1
Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

Resolution 16 Bits AD5060
14 Bits AD5040
Relative Accuracy (INL)2 ±0.5 ±2 LSB −40°C to +85°C, AD5040/AD5060 A grade
±0.5 ±1 LSB −40°C to +85°C, AD5040/AD5060 B grade
±0.5 ±1.5 −40°C to +125°C, AD5060 Y grade
Total Unadjusted Error (TUE)2 ±0.1 ±2.0 mV −40°C to +85°C, AD5040/AD5060
±0.1 ±2.0 −40°C to +125°C, AD5060 Y grade
Differential Nonlinearity (DNL)2 ±0.5 ±1 LSB

±0.5 ±1

Gain Error ±0.01 ±0.02 % of FSR TA = −40°C to +85°C, AD5040/AD5060
±0.01 ±0.03 TA = −40°C to +125°C AD5060 Y grade
Gain Error Temperature Coefficient 1 ppm of FSR/°C
Offset Error ±0.02 ±1.5 mV TA = −40°C to + 85°C, AD5040/AD5060
±0.02 ±2.0 TA = −40°C to + 125°C, AD5060 Y grade
Offset Error Temperature Coefficient 0.5 μV/°C
Full-Scale Error ±0.05 ±2.0 mV

±0.05 ±2.0

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 V
Output Voltage Settling Time 4 μs

Output Noise Spectral Density 64

Output Voltage Noise 6 μV p-p

Digital-to-Analog Glitch Impulse 2 nV-s

Digital Feedthrough 0. 003 nV-s DAC code = full scale
DC Output Impedance (Normal) 0. 015 Ω Output impedance tolerance ±10%
DC Output Impedance (Power-Down)

(Output Connected to 1 kΩ Network)4 1 kΩ Output impedance tolerance ±400 Ω
(Output Connected to 100 kΩ

Network)

Capacitive Load Stability 1 nF Loads used RL = 5 kΩ, RL = 100 kΩ, RL = ∞
Slew Rate 1. 2 V/μs

Short-Circuit Current 60 ma

45

DAC Power-Up Time 4.5 μs

DC Power Supply Rejection Ratio −92.11 db VDD ± 10%, DAC code = full scale

= 4.096 V @ RL = unloaded, CL = unloaded; T

REF

100 kΩ Output impedance tolerance ±20 kΩ

to T

MIN

, unless otherwise noted.

MAX

V

REF

nV/√Hz

Guaranteed monotonic,

−40°C to +85°C, AD5040/AD5060

Guaranteed monotonic,

−40°C to +125°C, Y grade

All 1s loaded to DAC register,

AD5040 AD5060; T

= −40°C to +85°C

A

All 1s loaded to DAC register,

= −40°C to +125°C, AD5060 Y grade

T

A

¼ scale to ¾ scale code transition to

±1 LSB, R

= 5 kΩ

L

DAC code = midscale, 1 kHz

DAC code = midscale , 0.1 Hz to 10 Hz

bandwidth

1 LSB change around code 57386,

= 5 kΩ, CL = 200 pF

R

L

¼ scale to ¾ scale code transition to

±1 LSB, R

= 5 kΩ, CL = 200 pF

L

DAC code = full scale, output shorted to

GND, TA = 25°C

DAC code = zero scale, output shorted to

, TA = 25°C

V

DD

Time to exit power-down mode to normal

mode of AD5060, 24

th

clock edge to 90%

of DAC final value, output unloaded

Rev. A | Page 3 of 24

AD5040/AD5060

A, B, and Y Grades1
Parameter Min Typ Max Unit Test Conditions/Comments

Wideband Spurious-Free Dynamic

Range (SFDR)

REFERENCE INPUT/OUTPUT

V

Input Range5 2 V

REF

Input Current (Power-Down) ±0.1 μA Zero scale loaded
Input Current (Normal) ±0.5 μA
DC Input Impedance 1 MΩ

LOGIC INPUTS

Input Current6 ±1 ±2 μA
VIL, Input Low Voltage 0.8 V VDD = 4.5 V to 5.5 V

0.8 VDD = 2.7 V to 3.6 V
VIH, Input High Voltage 2.0 V VDD = 2.7 V to 5.5 V

1.8 VDD = 2.7 V to 3.6 V
Pin Capacitance 4 pF

POWER REQUIREMENTS

VDD 2.7 5.5 V All digital inputs at 0 V or VDD
IDD (Normal Mode) DAC active and excluding load current
VDD = 2.7 V to 5.5 V

IDD (All Power-Down Modes)

VDD = 2.5 V to 5.5 V 0.33

0.065

1

Temperature range for the A and B grades is −40°C to + 85° C, typical at 25°C; temperature range for the Y grade is −40°C to +125°C.

2

Linearity calculated using a reduced code range (160 to code 65535 for AD5060 ) and (40 to code 16383 for AD5040).

3

Guaranteed by design and characterization, not production tested.

4

1 kΩ power-down network not available with the AD5040.

5

The typical output supply headroom performance for various reference voltages at −40°C can be seen in Figure 26.

6

Total current flowing into all pins.

−67 db Output frequency = 10 kHz

− 50 mV

DD

1.0

0. 82

1.2

1. 0

1

mA

μA

= VDD and VIL = GND, VDD = 5.0 V,

V

IN

= 4.096 V, code = midscale

V

REF

V

= VDD and VIL = GND, VDD = 3.0 V,

IN

V

= 2.7 V, code = midscale

REF

= VDD and VIL = GND, VDD = 5.5 V,

V

IH

= 4.096 V, code = midscale

V

REF

= VDD and VIL = GND, VDD = 3.0 V,

V

IH

= 4.096 V, code = midscale

V

REF

Rev. A | Page 4 of 24

AD5040/AD5060

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications T

Table 3.

Parameter Limit

2

t

1

t2
t3
t4
t5
t6
t7
t8
t9

1

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 30 MHz.

1

33 ns min SCLK cycle time
5 ns min SCLK high time
3 ns min SCLK low time
10 ns min
3 ns min Data setup time
2 ns min Data hold time
0 ns min

12 ns min
9 ns min

MIN

to T

unless otherwise noted.

MAX

,

Unit Test Conditions/Comments

SYNC to SCLK falling edge setup time

SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore

SCLK

SYNC

DIN

t

4

t

8

t

t

2

1

t

3

t

6

t

5

Figure 2. AD5060 Timing Diagram

t

9

t

7

D0D1D2D22D23

D23 D22

04767-002

Rev. A | Page 5 of 24

AD5040/AD5060

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7.0 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

V

to GND −0.3 V to VDD + 0.3 V

REF

Operating Temperature Range

Industrial (A, B Grade) −40°C to +85°C
Extended Automotive Temperature

Range (Y Grade)
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
SOT-23 Package

Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance 206°C/W
θJc Thermal Impedance 91°C/W

Reflow Soldering (Pb-free)

Peak Temperature 260°C
Time-at-Peak Temperature 10 sec to 40 sec

ESD (AD5040/AD5060) 1. 5 kV

−40°C to +125°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance integrated circuit with an
ESD rating of <2 kV. It is ESD sensitive. Proper precautions
should be taken for handling and assembly.

Rev. A | Page 6 of 24

AD5040/AD5060

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

18

DIN

AD5040/

V

27

DD

AD5060

TOP VIEW

36

V

(Not to Scale)

REF

45

OUT

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 DIN

Serial Data Input. These parts have a 16-/24-bit shift register. Data is clocked into the register on the falling edge of

the serial clock input.
2
3 V
4 V

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and VDD should be decoupled to GND.

V

DD

Reference Voltage Input.

REF

Analog Output Voltage from DAC.

OUT

5 AGND Ground Reference Point for Analog Circuitry.
6 DACGND Ground Input to the DAC Core.
7

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

SYNC

goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.

The DAC is updated following the 16th/24th clock cycle unless SYNC

the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
8 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 30 MHz.

SCLK

SYNC
DACGND

AGND

04767-003

is taken high before this edge, in which case

Rev. A | Page 7 of 24

AD5040/AD5060

TYPICAL PERFORMANCE CHARACTERISTICS

1.6
VDD = 5.5V

1.4
V

= 4.096V

REF

1.2

T

= 25°C

A

1.0

0.8

0.6

0.4

0.2

0
–0.2
–0.4

INL ERROR (LSB)

–0.6
–0.8
–1.0
–1.2
–1.4
–1.6

160 10160 30160 50160 6016020160 40160

Figure 4. Typical AD5060 INL Plot Figure 7. Typical AD5040 INL Plot

1.6
VDD = 5.5V

1.4

= 4.096V

V

REF

1.2

T

= 25°C

A

1.0

0.8

0.6

0.4

0.2

0
–0.2
–0.4

DNL ERROR (LSB)

–0.6
–0.8
–1.0
–1.2
–1.4
–1.6

160 10160 30160 50160 6016020160 40160

Figure 5. Typical AD5060 DNL Plot

0.10
VDD = 5.5V

= 4.096V

V

REF

0.08

= 25°C

T

A

0.06

0.04

0.02

0

–0.02

TUE ERROR (mV)

–0.04

–0.06

–0.08

–0.10

160 10160 30160 50160 6016020160 40160

Figure 6. Typical AD5060 TUE Plot

DAC CODE

DAC CODE

DAC CODE

04767-040

04767-039

04767-041

0.6
VDD = 5.5V

0.5

V

= 4.096V

REF

T

= 25°C

A

0.4

0.3

0.2

0.1

0

–0.1

INL ERROR (LSB)

–0.2
–0.3
–0.4
–0.5
–0.6

160 2260 8560 12760 148604360 6460 10660

0.40
VDD = 5.5V

DNL ERROR (LSB)

0.35

0.30

0.25

0.20

0.15

0.10

0.05

–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40

= 4.096V

V

REF

= 25°C

T

A

0

160 2260 6460 10660 12760 148604360 8560

Figure 8. Typical AD5040 DNL Plot

0.020
VDD = 5.5V

= 4.096V

V

REF

0.015

= 25°C

T

A

0.010

0.005

0

–0.005

TUE ERROR (mV)

–0.010

–0.015

–0.020

160 2260 8560 12760 14860 169604360 6460 10660

DAC CODE

Figure 9. Typical AD5040 TUE Plot

DAC CODE

DAC CODE

04767-061

04767-060

04767-062

Rev. A | Page 8 of 24

AD5040/AD5060

1.6
TA = 25°C

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0
–0.2
–0.4

INL ERROR (LSB)

–0.6
–0.8
–1.0
–1.2
–1.4
–1.6

2.0

Figure 10. INL vs. Reference Input Voltage

1.6
TA = 25°C

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0
–0.2
–0.4

DNL ERROR (LSB)

–0.6
–0.8
–1.0
–1.2
–1.4
–1.6

2.0

Figure 11. DNL vs. Reference Input Voltage

1.2
TA = 25°C

1.0

0.8

0.6

0.4

0.2

0

–0.2

TUE ERROR (mV)

–0.4
–0.6
–0.8
–1.0
–1.2

2.0

Figure 12. TUE vs. Reference Input Voltage

MAX INL ERROR @ VDD = 5.5V

MIN INL ERROR @ VDD = 5.5V

REFERENCE VOLTAGE (V)

MAX DNL ERROR @ VDD = 5.5V

MIN DNL ERROR @ VDD = 5.5V

REFERENCE VOLTAGE (V)

MAX TUE ERROR @ VDD = 5.5V

MIN TUE ERROR @ VDD = 5.5V

REFERENCE VOLTAGE (V)

04767-009

5.55.04.54.03.53.02.5

1

04767-010

5.55.04.54.03.53.02.5

1

04767-011

5.55.04.54.03.53.02.5

1

1

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

OFFSET ERROR (mV)

–0.8
–1.0
–1.2
–1.4
–1.6
–1.8

–40 140120100806040200–20

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

GAIN ERROR (% FSR)

–0.3

–0.4

–0.5

–40 140120100806040200–20

1.4

1.2

1.0

0.8

0.6

0.4

0.2
0

INL ERROR (LSB)

–0.2
–0.4
–0.6
–0.8
–1.0

–40 140120100806040200–20

AD5060 only.

VDD = 5.5V, V
V

= 2.7V, V

DD

MAX OFFSET ERROR @

= 4.096V

REF

= 2.0V

REF

MAX OFFSET ERROR @
V

= 2.7V

V

= 5.5V

DD

MIN OFFSET ERROR @

DD

V

= 2.7V

DD

TEMPERATURE (°C)

MIN OFFSET ERROR @
V

= 5.5V

DD

Figure 13. Typical Offset Error vs. Temperature

VDD = 5.5V, V
V

= 2.7V, V

DD

= 4.096V

REF

= 2.0V

REF

MAX GAIN ERROR @

MIN GAIN ERROR @

TEMPERATURE (°C)

MAX GAIN ERROR @

V

= 5.5V

DD

V

= 5.5V

DD

MIN GAIN ERROR @

Figure 14. Typical Gain Error vs. Temperature

VDD = 5.5V, V
V

= 2.7V, V

DD

MAX INL ERROR @

MIN INL ERROR @

= 4.096V

REF

= 2.0V

REF

V

= 2.7V

DD

V

= 5.5V

DD

MIN INL ERROR @
V

= 2.7V

DD

MAX INL ERROR @
V

DD

TEMPERATURE (°C)

= 5.5V

Figure 15. Typical INL Error vs. Temperature

04767-067

1

V

= 2.7V

DD

V

= 2.7V

DD

04767-066

1

04767-069

1

Rev. A | Page 9 of 24

AD5040/AD5060

1.0
VDD = 5.5V, V
V

= 2.7V, V

0.8

DD

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

–40 140120100806040200–20

Figure 16. Typical DNL Error vs. Temperature

1.0
VDD = 5.5V, V
V

= 2.7V, V

0.8

DD

0.6

0.4

0.2

0

–0.2

TUE ERROR (mV)

–0.4

–0.6

–0.8

–1.0

–40 140120100806040200–20

Figure 17. Typical TUE Error vs. Temperature

1.4
VDD = 5.5V, V
V

= 2.7V, V

DD

1.2

1.0

0.8

(mA)

DD

I

0.6

0.4

0.2

0

–40 140120100806040200–20

Figure 18. Typical Supply Current vs. Temperature

= 4.096V

REF

= 2.0V

REF

MAX DNL ERROR @

V

MAX DNL ERROR @

V

= 4.096V

REF

= 2.0V

REF

MAX TUE ERROR @
V

= 5.5V

DD

MIN TUE ERROR @
V

= 2.7V

DD

= 4.096V

REF

= 2.0V

REF

= 2.7V

DD

= 5.5V

DD

TEMPERATURE (°C)

TEMPERATURE (°C)

TEMPERATURE (°C)

MIN DNL ERROR @

MIN DNL ERROR @

MAX TUE ERROR @
V

= 5.5V

V

DD

= 2.7V

V

DD

1

= 2.7V

DD

MIN TUE ERROR @

= 5.5V

V

DD

1

MAX IDD @
V

= 5.5V

DD

@

MAX I

DD

V

= 2.7V

DD

1

04767-071

04767-068

04767-072

1.8
VDD = 5.5V
V

= 4.096V

REF

1.6
T

= 25°C

A

1.4

1.2

1.0

(mA)

0.8

DD

I

0.6

0.4

0.2

0

0 5M 10M 15M 20M 25M 30M 35M 40M 45M

THREE QUARTER SCALE

MID-SCALE

QUARTER-SCALE

FREQUENCY (Hz)

FULL-SCALE

Figure 19. Typical Supply Current vs. Frequency @ 5.5 V1

1.6
VDD = 3V
V

= 2.5V

REF

1.4

T

= 25°C

A

1.2

1.0

0.8

(mA)

DD

I

0.6

0.4

0.2

0

0 5M 10M 15M 20M 25M 30M 35M 40M 45M

FULL-SCALE

THREE QUARTER SCALE

MID-SCALE

FREQUENCY (Hz)

QUARTER-SCALE

ZERO-SCALE

Figure 20. Typical Supply Current vs. Frequency @ 3 V1

2.0
V

= 2.5V

REF

1.8

T

= 25°C

A

CODE = MIDSCALE

1.6

1.4

1.2

A)

μ

1.0

(

DD

I

0.8

0.6

0.4

0.2

0

2.5
SUPPLY VOLTAGE (V)

Figure 21. Typical Supply Current vs. Supply Voltage

ZERO-SCALE

1

04767-044

04767-045

04767-015

6.05.55.04.54.03.53.0

1

AD5060 only.

Rev. A | Page 10 of 24

AD5040/AD5060

3.00
TA = 25°C

2.75

2.50

2.25

2.00

1.75

1.50

(mA)

DD

I

1.25

1.00

0.75

0.50

0.25

0

0

VDD = 5.5V, V

VDD = 3.0V, V

DAC CODE

REF

Figure 22. Typical Supply Current vs. Digital Input Code

REF

= 2.5V

= 4.096V

04767-014

70000600005000040000300002000010000

1

VDD = 3V
DAC = FULL SCALE
V

= 2.7V

REF

T

= 25°C

A

Y AXIS = 2μV/DIV
X AXIS = 4s/DIV

Figure 25. 0.1 Hz to 10 Hz Noise Plot

04767-020

24TH CLOCK FALLING

CH1 = SCLK

CH2 = V

OUT

CH2 50mV/DIV CH1 2V/DIV TIME BASE 400ns/DIV

Figure 23. AD5060 Digital-to-Analog Glitch Impulse

(See Figure 24)

0.117

0.116

0.115

0.114

0.113

0.112

0.111

0.110

0.109

0.108

AMPLITUDE

0.107

0.106

0.105

0.104

0.103

0.102

0.101

0

255075

100

125

150

175

200

225

250

275

300

SAMPLES

325

Figure 24. AD5060 Digital-to-Analog Glitch Energy

VDD = 5V
V

REF

R = 5kΩ
C = 220pF
CODE = 57386

350

375

400

= 4.096V

425

450

475

04767-017

500

04767-043

525

0.50

0.45

0.40

0.35

0.30

0.25

0.20

HEADROOM (V)

0.15

0.10

0.05

0

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1
REFERENCE VOLTAGE (V)

Figure 26. VDD Headroom vs. Reference Voltage

5.05
VDD = 5.0V

T

= 25°C

A

5.00
DAC = FULL-SCALE

4.95

4.90

4.85

4.80

4.75

4.70

DAC OUTPUT VOLTAGE (V)

4.65

4.60

4.55

4.70 4.72 4.74 4.76 4.78 4.80 4.82 4.84 4.86 4.88 4.90 4.92 4.94 4.96 4.98 5.00

V

(V)

REF

Figure 27. Output Voltage vs. Reference Voltage

04767-091

5.55.3

04767-042

1

AD5060 only.

Rev. A | Page 11 of 24

AD5040/AD5060

5.005
V

= 5V

REF

T

= 25°C

A

5.000

4.995

4.990

DAC OUTPUT (V)

4.985

4.980

C4 = 143mV p-p

1kΩ TO GNDZERO-SCALE

4.975

5.50 5.005.055.105.155.205.255.305.355.405.45
VDD (V)

Figure 28. Typical Output vs. Supply Voltage

CH3 = SCLK

CH2 = V

OUT

CH1 = TRIGGER

CH2 2V/DIVCH1 2V/DIV TIME BASE = 5.00μsCH3 2V

Figure 29. Time to Exit Power-Down to Midscale

400

350

FULL-SCALE

300

250

200

150

100

50

NOISE SPECTRAL DENSITY (nV/ Hz)

0

–50

100 1k 10k 100k 1M

MID-SCALE

QUARTER-SCALE

ZERO-SCALE

FREQUENCY (Hz)

Figure 30. Noise Spectral Density

VDD = 5V
V

= 4.096V

REF

T

= 25°C

A

04767-019

04767-065

04767-046

CH4 50.0mV M4.00μs CH1 1.64V

04767-047

Figure 31. Glitch upon Entering Software Power-Down to Zero Scale

1kΩ TO GND ZERO-SCALE

CH4 20.0mV M1.00μs CH1 1.64V

C4 = 50mV p-p

04767-048

Figure 32. Glitch upon Exiting Software Power-Down to Zero Scale

C2
25mV p-p

2

3

CH3 2.00V CH2 50mV M1.00ms CH3 1.36V

T

T

C3

4.96V p-p

C3 FALL

935.0μs

C3 RISE
∞s
NO VALID
EDGE

04767-049

Figure 33. Glitch upon Entering Hardware Power-Down to Three-State

Rev. A | Page 12 of 24

AD5040/AD5060

2.1

VDD = 5.5V
V

= 4.096V

2.0

REF

C2
30mV p-p

2

3

CH3 2.00V CH2 50mV M1.00ms CH3 1.36V

T

T

C3

4.96V p-p

C3 FALL
∞s
NO VALID
EDGE

C3 RISE

946.2μs

04767-050

Figure 34. Glitch upon Exiting Hardware Power-Down to Zero Scale

0.0010
CODE = MID-SCALE

= 5V, V

V

0.0008

DD

= 3V, V

V

DD

0.0006

0.0004

0.0002

0

VOLTAGE (V)

Δ

–0.0002

VDD = 5.5V

–0.0004

–0.0006

–0.0008

–25 –20 –15 –10 –5 0 5 10 15 20 25 30

REF
REF

VDD = 3V

= 4.096V
= 2.5V

CURRENT (mA)

Figure 35. Typical Output Load Regulation

0.10
CODE = MIDSCALE
V

= 5V, V

DD

V

= 3V, V

DD

0

–25 –20 –15 –10 –5 0 5 10 15 20 25 30

(V)

OUT

V

Δ

0.08

0.06

0.04

0.02

–0.02

–0.04

–0.06

–0.08

–0.10

= 4.096V

REF

= 2.5V

REF

VDD = 5V, V

REF

= 4.096V

I

OUT

VDD = 3V, V

(mA)

REF

= 2.5V

Figure 36. Typical Current Limiting Plot

FREQUENCY

04767-051

FREQUENCY

04767-063

10% TO 90% RISE TIME = 0.688
SLEW RATE = 1.16V/

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0
–10

μ

s 9.96μs8μs6μs4μs2μs0–2μs–4μs–6μs–8μs

1.04V

μ

s

DAC

OUTPUT

μ

s

2.04V

Figure 37. Typical Output Slew Rate

16

14

12

10

8

6

4

2

0

0.83 MORE0.910.900.890.880.870.860.850.84
BIN

Figure 38. IDD Histogram VDD = 3.0 V

14

12

10

8

6

4

2

0

1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11MORE

Figure 39. I

BIN

Histogram VDD = 5.0 V

DD

04767-052

04767-076

04767-075

Rev. A | Page 13 of 24

AD5040/AD5060

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical AD5060 INL vs. code plot is shown in
Figure 4.

Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical AD5060 DNL vs. code plot is shown in Figure 5.

Offset Error
Offset error is a measure of the output error when zero code
(0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5040/AD5060 because the output of the DAC cannot go
below 0 V. This is due to a combination of the offset errors in
the DAC and output amplifier. Zero-code error is expressed
in mV.

Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF AD5060, 0x3FFF AD5040) is loaded to the DAC
register. Ideally, the output should be V
error is expressed in percent of full-scale range.

Gain Error

This is a measure of the span error of the DAC. It is the devia­tion in slope of the DAC transfer characteristic from ideal,
expressed as a percent of the full-scale range.

− 1 LSB. Full-scale

DD

Tot a l U n ad ju s te d E rr o r ( TU E )
Total unadjusted error is a measure of the output error taking
all the various errors into account. A typical AD5060 TUE vs.
code plot is shown in Figure 6.

Offset Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the worst case code 53786; see Figure 23 and Figure 24.
The expanded view in Figure 23 shows the glitch generated
following completion of the calibration routine; Figure 24
zooms in on this glitch.

Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus—that is, from all 0s to all 1s, and vice versa.

Rev. A | Page 14 of 24

AD5040/AD5060

THEORY OF OPERATION

The AD5040/AD5060 are single 14-/16-bit, serial input, voltage
output DACs. The parts operate from supply voltages of 2.7 V
to 5.5 V. Data is written to the AD5060 in a 24-bit word format,
and to the AD5040 in a 16-bit word format, via a 3-wire serial
interface.

Both the AD5040 and AD5060 incorporate a power-on reset
circuit that ensures the DAC output powers up to a known out­put state (midscale or zero-scale, see the Ordering Guide). The
devices also have a software power-down mode that reduces the
typical current consumption to less than 1 µa.

DAC ARCHITECTURE

The DAC architecture of the AD5060 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 40. The 4 MSBs of the 16-bit data-word are decoded to
drive 15 switches, E1 to E15. Each of these switches connects
1 of 15 matched resistors to either DACGND or the V

output.

The remaining 12 bits of the data-word drive switches

buffer

REF

S0 to S11 of a 12-bit voltage mode R-2R ladder network.

V

OUT

2R

2R

2R

2R

S1

S0

V

REF

12-BIT R-2R LADDER FOUR MSBs DECODED INTO

Figure 40. AD5060 DAC Ladder Structure

2R

2R

E1

S11

15 EQUAL SEGMENTS

E2

2R
E15

REFERENCE BUFFER

The AD5040 andAD5060 operate with an external reference.
The reference input (V
V

− 50 mV. This input voltage is then used to provide a

DD

buffered reference for the DAC core.

) has an input range of 2 V to

REF

DB15 (MSB) DB0 (LSB)

04767-027

SERIAL INTERFACE

The AD5060/AD5040 have a 3-wire serial interface (
SCLK, and DIN), which is compatible with SPI, QSPI, and

MICROWIRE interface standards, as well as most DSPs.
Figure 2

shows a timing diagram of a typical AD5060 write

sequence.

The write sequence begins by bringing the

SYNC

line low. For

the AD5060, data from the DIN line is clocked into the 24-bit
shift register on the falling edge of SCLK. The serial clock
frequency can be as high as 30 MHz, making these parts
compatible with high speed DSPs. On the 24th falling clock
edge, the last data bit is clocked in and the programmed
function is executed (that is, a change in the DAC output or a
change in the mode of operation).

At this stage, the

line can be kept low or be brought

SYNC

high. In either case, it must be brought high for a minimum of
12 ns before the next write sequence so that a falling edge of

can initiate the next write sequence. Because the

SYNC
buffer draws more current when V

V

= 0.8 V,

IH

should be idled low between write sequences

SYNC

= 1.8 V than it does when

IH

for an even lower power operation of the part. As previously
indicated, however, it must be brought high again just before
the next write sequence. The AD5040 requires 16 clock periods
to update the input shift register. On the 16th falling clock edge,
the last data bit is clocked in and the programmed function is
executed (that is, a change in the DAC output or a change in the
mode of operation).

Input Shift Register

The AD5060 input shift register is 24 bits wide; see Figure 41.
PD1 and PD0 are control bits that control the operating mode
of the part—normal mode or any one of three power-down
modes (see the Power-Down Modes section for more detail).
The next 16 bits are the data bits. These are transferred to the
DAC register on the 24th falling edge of SCLK.

SYNC

SYNC

,

0 0 0 0 0 0 PD1 PD0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

0
0
1
1

NORMAL OPERATION

0

3-STATE

1

100kΩ TO GND

0

1kΩ TO GND

1

Figure 41. AD5060 Input Register Content

Rev. A | Page 15 of 24

POWER-DOWN MODES

04767-028

AD5040/AD5060

The AD5040 input shift register is 16 bits wide; see Figure 42.
PD1 and PD0 are control bits that control the operating mode
of the part—normal mode or any one of two power-down
modes (see Power-Down Modes section for more detail). The
next 14 bits are the data bits. These are transferred to the DAC
register on the 16th falling edge of SCLK.

Interrupt

SYNC

In a normal write sequence for the AD5060, the
kept low for at least 24 falling edges of SCLK, and the DAC is

updated on the 24th falling edge. However, if

SYNC

high before the 24th falling edge, the write sequence is
interrupted. The shift register is reset and the write sequence is
considered invalid. Neither an update of the DAC register
contents nor a change in the operating mode occurs; see

. In a normal write sequence for the AD5040, the

43
is kept low for at least 16 falling edges of SCLK, and the DAC is

updated on the 16th falling edge. However, if

SYNC
high before the 16th falling edge, the write sequence is
interrupted. The shift register is reset and the write sequence is
considered invalid. Neither an update of the DAC register

contents nor a change in the operating mode occurs.

SYNC

is brought

SYNC

is brought

line is

Figure

line

POWER-ON RESET

The AD5040 and AD5060 both contain a power-on reset
circuit that controls the output voltage during power-up. The
DAC register is filled with the zero-scale code or midscale code
and the output voltage is set to zero scale or midscale (see the
Ordering Guide for more details on the reset model). It remains
there until a valid write sequence is made to the DAC. This is
useful in applications where it is important to know the output
state of the DAC while it is in the process of powering up.

SOFTWARE RESET

The AD5060 device can be put into software reset by setting all
bits in the DAC register to 1; this includes writing 1s to Bit D23
and Bit D16, which is not the normal mode of operation. For
the AD5040 this includes writing 1s to Bit D15 and Bit D14,
which is also not the normal mode of operation. Note that the

interrupt command cannot be performed if a software

SYNC
reset command is started in the AD5040 or AD5060.

DB13 (MSB) DB0 (LSB)

D13PD0PD1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

NORMAL OPERATION

0

0

3-STATE

0
1

1

100kΩ TO GND

0

Figure 42. AD5040 Input Register Content

POWER-DOWN MODES

04767-074

SCLK

SYNC

DIN

DB23 DB23 DB0DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24

TH

FALLING EDGE

Figure 43. AD5060

SYNC

Interrupt Facility

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 24TH FALLING EDGE

04767-031

Rev. A | Page 16 of 24

AD5040/AD5060

POWER-DOWN MODES

The AD5060 features four operating modes, and the AD5040
features three operating modes. These modes are software pro­grammable by setting two bits in the control register (Bit DB17
and Bit DB16 in the AD5060 and Bit DB15 and Bit DB14 in the
AD5040). Table 6 and Tab le 7 show how the state of the bits
corresponds to the operating mode of the two devices.

Table 6. Operating Modes for the AD5060

DB17 DB16 Operating Mode

0 0 Normal operation
Power-down modes:
0 1 3-state
1 0 100 kΩ to GND
1 1 1 kΩ to GND

Table 7. Operating Modes for the AD5040

DB15 DB14 Operating Mode

0 0 Normal operation
Power-down modes:
0 1 3-state
1 0 100 kΩ to GND
1 1 See Software Reset section

In both the AD5060 and the AD5040, when the two most
significant bits are set to 0, the part has normal power
consumption. However, for the three power-down modes of the
AD5060 and the two power down modes of the AD5040, the
supply current falls to less than 1A at 5 V (65 nA at 3 V). Not
only does the supply current fall, but the output stage is also
internally switched from the output of the amplifier to a resistor
network of known values. This is advantageous because the
output impedance of the part is known while the part is in
power-down mode. The output is connected internally to GND
through a 1 kΩ resistor (AD5060 only) or a 100 kΩ resistor, or
it is left open-circuited (three-stated). The output stage is
illustrated in Figure 44.

OUTPUT

AD5040/

AD5060

DAC

Figure 44. Output Stage During Power-Down

The bias generator, the DAC core, and other associated linear
circuitry are all shut down when power-down mode is
activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 2.5 µs for V
see Figure 29.

BUFFER

POWER-DOWN

CIRCUITRY

= 5 V, and 5 µs for VDD = 3 V;

DD

RESISTOR
NETWORK

V

OUT

04767-029

MICROPROCESSOR INTERFACING

AD5040/AD5060 to ADSP-2101/ADSP-2103 Interface

Figure 45 shows a serial interface between the AD5040/AD5060
and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
should be set up to operate in the SPORT transmit alternate
framing mode. The ADSP-2101/ADSP-2103 sport is pro­grammed through the SPORT control register and should be
configured for internal clock operation, active low framing, and
16-bit word length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled.

ADSP-2101/

ADSP-2103

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 45. AD5040/AD5060 to ADSP-2101/ADSP-2103 Interface

1

TFS

DT

SCLK

AD5040/AD5060 to 68HC11/68L11 Interface

Figure 46 shows a serial interface between the AD5040/
AD5060 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK pin of the AD5040/AD5060,
while the MOSI output drives the serial data line of the DAC.
The

signal is derived from a port line (PC7). The setup

SYNC

conditions for correct operation of this interface require that the
68HC11/68L11 be configured so that its CPOL bit is 0 and its
CPHA bit is 1. When data is being transmitted to the DAC, the

line is taken low (PC7). When the 68HC11/68L11 is

SYNC
configured where its CPOL bit is 0 and its CPHA bit is 1, data

appearing on the MOSI output is valid on the falling edge of
SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit
bytes with only 8 falling clock edges occurring in the transmit
cycle. Data is transmitted MSB first. In order to load data to the
AD5040/AD5060, PC7 is left low after the first eight bits are
transferred, and a second serial write operation is performed to
the DAC. PC7 is taken high at the end of this procedure.

68HC11/

1

68L11

PC7

SCK

MOSI

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 46. AD5040/AD5060 to 68HC11/68L11 Interface

SYNC
DIN
SCLK

SYNC
SCLK
DIN

AD5040/
AD5060

AD5040/
AD5060

1

1

04767-030

04767-032

Rev. A | Page 17 of 24

AD5040/AD5060

AD5040/AD5060 to Blackfin® ADSP-BF53x Interface

Figure 47 shows a serial interface between the AD5040/
AD5060 and the Blackfin ADSP-53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5040/AD5060, the setup for the interface is: DT0PRI
drives the SDIN pin of the AD5040/AD5060, while TSCLK0
drives the SCLK of the part; the

ADSP-BF53x

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 47. AD5040/AD5060 to Blackfin® ADSP-BF53x Interface

1

DT0PRI

TSCLK0

TFS0

AD5040/AD5060 to 80C51/80L51 Interface

Figure 48 shows a serial interface between the AD5060/
AD5040 and the 80C51/80L51 microcontroller. The setup
for the interface is: TxD of the 80C51/80L51 drives SCLK of
the AD5040/AD5060 while RxD drives the serial data line
of the part. The

signal is again derived from a bit-

SYNC

programmable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5040, P3.3 is
taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
thus only 8 falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the

is driven from TFS0.

SYNC

DIN
SCLK
SYNC

AD5040/
AD5060

1

04767-033

AD5040/AD5060 to MICROWIRE Interface

Figure 49 shows an interface between the AD5040/AD5060 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and is clocked into the
AD5040/AD5060 on the rising edge of the SK.

MICROWIRE

1

ADDITIONAL PINS OMITTED FOR CLARITY

1

CS
SK
SO

SYNC
SCLK
DIN

AD5040/
AD5060

Figure 49. AD5040/AD5060 to MICROWIRE Interface

1

04767-035

second byte of data. P3.3 is taken high following the completion
of this cycle. The 80C51/80L51 outputs the serial data in a
format which has the LSB first. The AD5040/AD5060 require
data to be received with the MSB as the first bit. The
80C51/80L51 transmit routine should take this into account.

80C51/80L51

1

ADDITIONAL PINS OMITTED FOR CLARITY

1

AD5040/
AD5060

P3.3

TxD

RxD

SYNC
SCLK
DIN

Figure 48. AD5040/AD5060 to 80C51/80L51 Interface

1

Rev. A | Page 18 of 24

04767-034

AD5040/AD5060

Ω

APPLICATIONS

CHOOSING A REFERENCE FOR THE AD5040/ AD5060

To achieve the optimum performance from the AD5040/
AD5060, carefully choose a precision voltage reference. The
AD5040/AD5060 have just one reference input, V
voltage on the reference input is used to supply the positive
input to the DAC. Therefore, any error in the reference is
reflected in the DAC.

There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, ppm drift, long-term drift, and output voltage
noise. Initial accuracy on the output voltage of the DAC leads
to a full-scale error in the DAC. To minimize these errors, a
reference with high initial accuracy is preferred. Also, choosing
a reference with an output trim adjustment, such as an ADR43x
device, allows a system designer to trim out system errors by
setting a reference voltage to a voltage other than the nominal.
The trim adjustment can also be used at temperature to trim
out any errors.

Because the supply current required by the AD5040/AD5060 is
extremely low, the parts are ideal for low supply applications.
The ADR395 voltage reference is recommended. This requires
less than 100 µA of quiescent current and can, therefore, drive
multiple DACs in one system, if required. It also provides very
good noise performance at 8 µV p-p in the 0.1 Hz to 10 Hz range.

7V

ADR395

5V

REF

. The

output noise in the 0.1 Hz to 10 Hz region. Tab le 8 shows
examples of recommended precision references for use as a
supply to the AD5040/AD5060.

Table 8. Precision References for the AD5040/AD5060

Part No.

Initial
Accuracy
(mV max)

Temp. Drift
(ppm/°C max)

0.1 Hz to 10 Hz
Noise (μV p-p typ)

ADR435 ±2 3 (SO-8) 8
ADR425 ±2 3 (SO-8) 3.4
ADR02 ±3 3 (SO-8) 10
ADR02 ±3 3 (SC70) 10
ADR395 ±5 9 (TSOT-23) 8

BIPOLAR OPERATION USING THE AD5040/ AD5060

The AD5040/AD5060 have been designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 51. The circuit shown yields an output voltage
range of ±5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD8675/AD820/AD8032 or an OP196/
OP295.

The output voltage for any input code can be calculated as

+

⎡

×=

VV

O

⎢
⎣

⎛
⎜

65536

⎝

⎞

×

⎟
⎠

2R1RD

⎛
⎜
⎝

⎞

V

⎟

1R

⎠

where D represents the input code in decimal (0 to 65536,
AD5060).

With V

= 5 V, R1 = R2 = 10 kΩ:

REF

2R

⎤

⎞

⎛

×−

DDDD

⎟

⎜

⎥

1R

⎠

⎝

⎦

3-WIRE

SERIAL

INTERFACE

SYNC
SCLK

DIN

Figure 50. ADR395 as Reference to AD5060/AD5040

AD5040/

AD5060

V

OUT

= 0V TO 5V

04767-036

Long-term drift is a measure of how much the reference drifts
over time. A reference with a tight long-term drift specification
ensures that the overall solution remains relatively stable during
its entire lifetime. The temperature coefficient of a reference
output voltage affects INL, DNL, and TUE. A reference with a
tight temperature coefficient specification should be chosen to
reduce the temperature dependence of the DAC output voltage
on ambient conditions.

In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered. It
is important to choose a reference with as low an output noise
voltage as practical for the system noise resolution required.
Precision voltage references, such as the ADR435, produce low

Rev. A | Page 19 of 24

10

×=D

65536

⎞

V5

−

⎟
⎠

⎛

V

⎜

O

⎝

Using the AD5060, this is an output voltage range of ±5 V
with 0x0000 corresponding to a −5 V output and 0xFFFF
corresponding to a +5 V output .

R2 = 10k

+5V

0.1μF

10μF

Figure 51. Bipolar Operation with the AD5040/AD5060

R1 = 10kΩ

AD5040/
AD5060

V

REF

3-WIRE

SERIAL

INTERFACE

V

OUT

+5V

–
AD820/
OP295

+

–5V

±5V

04767-037

AD5040/AD5060

USING THE AD5040/AD5060 WITH A GALVANICALLY ISOLATED INTERFACE CHIP

In process control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where the
DAC is functioning. iCoupler® provides isolation in excess of

2.5 kV. Because the AD5040/AD5060 use a 3-wire serial logic
interface, the ADuM130x family provides an ideal digital
solution for the DAC interface.

The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates.
They operate across the full range from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier.

Figure 52 shows a typical galvanically isolated configuration
using the AD5040/AD5060. The power supply to the part
also needs to be isolated; this is accomplished by using a
transformer. On the DAC side of the transformer, a 5 V
regulator provides the 5 V supply required for the
AD5040/AD5060.

5V

POWER

ADuM1300

REGULATOR

SCLKV0AV1ASCLK

SYNCV0BV1BSDI

V

DD

AD5040/

AD5060

V

OUT

0.1μF10μF

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5040/
AD5060 should have separate analog and digital sections, each
having its own area of the board. If the AD5040/AD5060 are in
a system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the
AD5040/AD5060.

The power supply to the AD5040/AD5060 should be bypassed
with 10 µF and 0.1 µF capacitors. The capacitors should be
physically as close as possible to the device with the 0.1 µF
capacitor ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. It is important that the

0.1 µF capacitor has low effective series resistance (ESR) and
effective series inductance (ESI), as do common ceramic types
of capacitors. This 0.1 µF capacitor provides a low impedance
path to ground for high frequencies caused by transient
currents due to internal logic switching.

The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by a digital ground. Avoid crossover of digital and analog
signals, if possible. When traces cross on opposite sides of the
board, ensure that they run at right angles to each other to
reduce feedthrough effects on the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only, and the
signal traces are placed on the solder side. However, this is not
always possible with a two-layer board.

DINV0CV1CDATA

GND

Figure 52. AD5040/AD5060 with a Galvanically Isolated Interface

04767-038

Rev. A | Page 20 of 24

AD5040/AD5060

0

0

V

V

V

V

V

V

V

V

OUTLINE DIMENSIONS

3.00

2.90

2.80

76

1.70

1.60

1.50

PIN 1

INDICATOR

1.30

1.15

0.90

.15 MAX
.05 MIN

8

1234

1.95
BSC

5

0.38 MAX

0.22 MIN

0.65 BSC

1.45 MAX

0.95 MIN

3.00

2.80

2.60

SEATING
PLANE

0.22 MAX

0.08 MIN

8°

0.60

4°

BSC

0°

0.60

0.45

0.30

COMPLIANT TO JEDEC STANDARDS MO-178-BA

Figure 53. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

ORDERING GUIDE

1

Model

AD5040BRJZ-500RL7
AD5040BRJZ-REEL7
AD5060ARJZ-1500RL7 −40°C to +85°C 2 LSB 2.7 V to 5.5 V, reset to 0
AD5060ARJZ-1REEL7
AD5060ARJZ-2REEL7

Temperature
Range

−40°C to +85°C 1 LSB 2.7 V to 5.5 V, reset to 0

−40°C to +85°C 1 LSB 2.7 V to 5.5 V, reset to 0

−40°C to +85°C 2 LSB 2.7 V to 5.5 V, reset to 0

−40°C to +85°C 2 LSB 2.7 V to 5.5 V, reset to mid-

AD5060ARJZ-2500RL7 −40°C to +85°C 2 LSB 2.7 V to 5.5 V, reset to mid-

AD5060BRJZ-1500RL7 −40°C to +85°C 1 LSB 2.7 V to 5.5 V, reset to 0
AD5060BRJZ-1REEL7
AD5060BRJZ-2REEL7

−40°C to +85°C 1 LSB 2.7 V to 5.5 V, reset to 0

−40°C to +85°C 1 LSB 2.7 V to 5.5 V, reset to mid-

AD5060BRJZ-2500RL7 −40°C to +85°C 1 LSB 2.7 V to 5.5 V, reset to mid-

AD5060YRJZ-1500RL7 −40°C to +125°C ±1.5 LSB 2.7 V to 5.5 V, reset to 0
AD5060YRJZ-1REEL7 −40°C to +125°C ±1.5 LSB 2.7 V to 5.5 V, reset to 0
EVAL-AD5060EBZ

1

Z = RoHS Compliant Part.

Evaluation Board

Maximum
INL Description Package Description

scale

scale

scale

scale

121608-A

Package
Option Branding

8 Lead SOT-23 RJ-8 D4C
8 Lead SOT-23 RJ-8 D4C
8 Lead SOT-23 RJ-8 D3Z
8 Lead SOT-23 RJ-8 D3Z
8 Lead SOT-23 RJ-8 D41

8 Lead SOT-23 RJ-8 D41

8 Lead SOT-23 RJ-8 D3W
8 Lead SOT-23 RJ-8 D3W
8 Lead SOT-23 RJ-8 D3X

8 Lead SOT-23 RJ-8 D3X

8 Lead SOT-23 RJ-8 D6F
8 Lead SOT-23 RJ-8 D6F

Rev. A | Page 21 of 24

AD5040/AD5060

NOTES

Rev. A | Page 22 of 24

AD5040/AD5060

NOTES

Rev. A | Page 23 of 24

AD5040/AD5060

NOTES

© 2005-2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04767-0-1/10(A)

Rev. A | Page 24 of 24