Analog Devices AD2S80A b Datasheet

Variable Resolution, Monolithic

a

FEATURES
Monolithic (BiMOS ll) Tracking R/D Converter
40-Lead DIP Package
44-Terminal LCC Package
10-,12-,14-, and 16-Bit Resolution Set by User
Ratiometric Conversion
Low Power Consumption: 300 mW Typ
Dynamic Performance Set by User
High Max Tracking Rate 1040 RPS (10 Bits)
Velocity Output
Industrial Temperature Range Versions
Military Temperature Range Versions
ESD Class 2 Protection (2,000 V Min)
/883 B Parts Available

APPLICATIONS
DC Brushless and AC Motor Control
Process Control
Numerical Control of Machine Tools
Robotics
Axis Control
Military Servo Control

GENERAL DESCRIPTION

The AD2S80A is a monolithic 10-, 12-, 14-, or 16-bit tracking
resolver-to-digital converter contained in a 40-lead DIP or 44­terminal LCC ceramic package. It is manufactured on a BiMOS
II process that combines the advantages of CMOS logic and
bipolar high accuracy linear circuits on the same chip.

The converter allows users to select their own resolution and dynamic
performance with external components. This allows the users great
flexibility in defining the converter that best suits their system
requirements. The converter allows users to select the resolution
to be 10, 12, 14, or 16 bits and to track resolver signals rotating
at up to 1040 revs per second (62,400 rpm) when set to 10-bit
resolution.

The AD2S80A converts resolver format input signals into a
parallel natural binary digital word using a ratiometric tracking
conversion method. This ensures high-noise immunity and toler­ance of lead length when the converter is remote from the resolver.

The 10-, 12-, 14- or 16-bit output word is in a three-state digital
logic available in 2 bytes on the 16 output data lines. BYTE
SELECT, ENABLE and INHIBIT pins ensure easy data trans­fer to 8- and 16-bit data buses, and outputs are provided to
allow for cycle or pitch counting in external counters.

An analog signal proportional to velocity is also available and
can be used to replace a tachogenerator.

The AD2S80A operates over 50 Hz to 20,000 Hz reference
frequency.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Resolver-to-Digital Converter

AD2S80A

FUNCTIONAL BLOCK DIAGRAM

DEMOD I/P

REF I/P

AC ERROR

O/P

DEMOD O/P

INTEGRATOR

I/P

SIN I/P

SIG GND

COS I/P

ANALOG

GND

RIPPLE

CLK

DATA
LOAD

+12V

–12V

A1

SEGMENT

SWITCHING

A2

16-BIT UP/DOWN COUNTER

SC1

SC2

ENABLE

AD2S80A

R-2R
DAC

OUTPUT DATA LATCH

16 DATA BITS

PRODUCT HIGHLIGHTS

Monolithic. A one chip solution reduces the package size

required and increases the reliability.

Resolution Set by User. Two control pins are used to select
the resolution of the AD2S80A to be 10, 12, 14, or 16 bits allowing
the user to use the AD2S80A with the optimum resolution for
each application.

Ratiometric Tracking Conversion. Conversion technique
provides continuous output position data without conversion
delay and is insensitive to absolute signal levels. It also provides
good noise immunity and tolerance to harmonic distortion on
the reference and input signals.

Dynamic Performance Set by the User. By selecting exter­nal resistor and capacitor values the user can determine bandwidth,
maximum tracking rate and velocity scaling of the converter to
match the system requirements. The external components
required are all low cost preferred value resistors and capacitors,
and the component values are easy to select using the simple
instructions given.

Velocity Output. An analog signal proportional to velocity is
available and is linear to typically one percent. This can be used
in place of a velocity transducer in many applications to provide
loop stabilization in servo controls and velocity feedback data.

Low Power Consumption. Typically only 300 mW.

Military Product. The AD2S80A is available processed in

accordance with MIL-STD-883B, Class B.

MODELS AVAILABLE

Information on the models available is given in the section
“Ordering Information.”

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

A3

PHASE

SENSITIVE

DETECTOR

VCO DATA

TRANSFER

BYTE

SELECT

LOGIC

5V

DIG GND

DIR

BUSY

INTEGRATOR
O/P

VCO I/P

INHIBIT

AD2S80A–SPECIFICATIONS

Parameter Conditions Min Typ Max Unit

SIGNAL INPUTS

Frequency 50 20,000 Hz
Voltage Level 1.8 2.0 2.2 V rms
Input Bias Current 60 150 nA
Input Impedance 1.0 MΩ
Maximum Voltage 8V pk

REFERENCE INPUT

Frequency 50 20,000 Hz
Voltage Level 1.0 8.0 V pk
Input Bias Current 60 150 nA
Input Impedance 1.0 MΩ

CONTROL DYNAMICS

Repeatability 1 LSB
Allowable Phase Shift (Signals to Reference) –10 +10 Degrees
Tracking Rate 10 Bits 1040 rps

Bandwidth

ACCURACY

Angular Accuracy A, J, S ⴞ8 +1 LSB arc min

Monotonicity Guaranteed Monotonic
Missing Codes (16-Bit Resolution) A, B, J, K, S, T 4 Codes

VELOCITY SIGNAL

Linearity Over Full Range ±1 ⴞ3 % FSD
Reversion Error ±1 ±2 % FSD
DC Zero Offset
DC Zero Offset Tempco –22 µV/°C
Gain Scaling Accuracy ±10 % FSD
Output Voltage 1 mA Load ±8 ±9 ±10.5 V
Dynamic Ripple Mean Value 1.5 % rms O/P
Output Load 1.0 kΩ

INPUT/OUTPUT PROTECTION

Analog Inputs Overvoltage Protection ± 8V
Analog Outputs Short Circuit O/P Protection ± 5.6 ±8 ±10.4 mA

DIGITAL POSITION

Resolution 10, 12, 14, and 16
Output Format Bidirectional Natural Binary
Load 3 LSTTL

INHIBIT

Sense Logic LO to Inhibit
Time to Stable Data 600 ns

ENABLE

ENABLE Time High Impedance State 35 110 ns

BYTE SELECT

Sense MS Byte DB1–DB8,

LOGIC LO LS Byte DB1–DB8,

Time to Data Available 60 140 ns

SHORT CYCLE INPUTS Internally Pulled High

SC1 SC2

0 0 10 Bit
0 1 12 Bit
1 0 14 Bit
1 1 16 Bit

1

2

3

3

3

12 Bits 260 rps
14 Bits 65 rps
16 Bits 16.25 rps
User Selectable

B, K, T ⴞ4 +1 LSB arc min
L, U ⴞ2 +1 LSB arc min

L, U 1 Code

Logic LO Enables Position
Output. Logic HI Outputs in

LS Byte DB9–DB16

LS Byte DB9–DB16

(100 kΩ) to +V

(typical at 25ⴗC unless otherwise noted)

6 mV

S

–2–

REV. B

AD2S80A

Parameter Conditions Min Typ Max Unit

DATA LOAD

Sense Internally Pulled High (100 kΩ) 150 300 ns

3

BUSY

Sense Logic HI When Position O/P

Width 200 600 ns
Load Use Additional Pull-Up 1 LSTTL

DIRECTION

3

Sense Logic HI Counting Up

Max Load 3 LSTTL

RIPPLE CLOCK

3

Sense Logic HI

Width Dependent on Input Velocity 300
Reset Before Next Busy
Load 3 LSTTL

DIGITAL INPUTS

High Voltage, V

Low Voltage, V

IH

IL

DIGITAL INPUTS

High Current, I

Low Current, I

IH

IL

DIGITAL INPUTS

Low Voltage, V

Low Current, I

IL

IL

DIGITAL OUTPUTS

High Voltage, V

Low Voltage, V

OH

OL

THREE-STATE LEAKAGE DB1–DB16 Only

Current I

NOTES

1

Refer to small signal bandwidth.

2

Output offset dependent on value for R6.

3

Refer to timing diagram.
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.

L

. Logic LO Allows

to V

S

Data to be Loaded into the
Counters from the Data Lines

Changing

Logic LO Counting Down

All 1s to All 0s
All 0s to All 1s

INHIBIT, ENABLE 2.0 V
DB1–DB16, Byte Select
±V

= ±10.8 V, VL = 5.0 V

S

INHIBIT, ENABLE 0.8 V
DB1–DB16, Byte Select
±VS = ±13.2 V, VL = 5.0 V

INHIBIT, ENABLE ⴞ100 µA
DB1–DB16
±V

= ±13.2 V , VL = 5.5 V

S

INHIBIT, ENABLE ⴞ100 µA
DB1–DB16, Byte Select
±VS = ±13.2 V, VL = 5.5 V

ENABLE = HI 1.0 V
SC1, SC2, Data Load

= ±12.0 V, VL = 5.0 V

±V

S

ENABLE = HI –400 µA
SC1, SC2, Data Load
±VS = ±12.0 V, VL = 5.0 V

DB1–DB16 2.4 V
RIPPLE CLK, DIR

= ±12.0 V, VL = 4.5 V

±V

S

= 100 µA

I

OH

DB1–DB16 0.4 V
RIPPLE CLK, DIR

= ±12.0 V, VL = 5.5 V

±V

S

IOL = 1.2 mA

±VS = ±12.0 V, VL = 5.5 V ±100 µA

= 0 V

V

OL

= ±12.0 V, VL = 5.5 V ±100 µA

±V

S

VOH = 5.0 V

REV. B

–3–

AD2S80A–SPECIFICATIONS

WARNING!

ESD SENSITIVE DEVICE

(typical at 25ⴗC unless otherwise noted)

Parameter Conditions Min Typ Max Unit

RATIO MULTIPLIER

AC Error Output Scaling 10 Bit 177.6 mV/Bit

12 Bit 44.4 mV/Bit
14 Bit 11.1 mV/Bit
16 Bit 2.775 mV/Bit

PHASE SENSITIVE DETECTOR

Output Offset Voltage 12 mV
Gain

In Phase w.r.t. REF –0.882 –0.9 –0.918 V rms/V dc
In Quadrature w.r.t. REF ±0.02 V rms/V dc

Input Bias Current 60 150 nA
Input Impedance 1 MΩ
Input Voltage ±8V

INTEGRATOR

Open-Loop Gain At 10 kHz 57 63 dB
Dead Zone Current (Hysteresis) 100 nA/LSB
Input Offset Voltage 15 mV
Input Bias Current 60 150 nA
Output Voltage Range ±VS = ±10.8 V dc ±7V

VCO

Maximum Rate ± V

= ±12 V dc 1.1 MHz

S

VCO Rate Positive Direction 7.1 7.9 8.7 kHz/µA

Negative Direction 7.1 7.9 8.7 kHz/µA

VCO Power Supply Sensitivity

Increase +V

–V

Decrease +V

–V

S

S

S

S

+0.5 %/V
–8.0 %/V
–8.0 %/V

+2.0 %/V
Input Offset Voltage 15 mV
Input Bias Current 70 380 nA
Input Bias Current Tempco –1.22 nA/°C
Input Voltage Range ±8V
Linearity of Absolute Rate

Full Range <2 % FSD
Over 0% to 50% of Full Range <1 % FSD

Reversion Error 1.5 % FSD
Sensitivity of Reversion Error ±8 %/V of

to Symmetry of Power Supplies Asymmetry

POWER SUPPLIES

Voltage Levels

+V
–V
+V

S

S

L

+10.8 +13.2 V
–10.8 –13.2 V
+5 +13.2 V

Current

±I

S

±I

S

±I

L

Specification subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.

±VS @ ±12 V ⴞ12 ⴞ23 mA
±VS @ 13.2 V ⴞ19 ⴞ30 mA

+VL @ ±5.0 V ⴞ0.5 ⴞ1.5 mA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD2S80A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

AD2S80A

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage (+VS, –VS) . . . . . . . . . ±12 V dc ± 10%

Power Supply Voltage V

. . . . . . . . . . . . . . . . . . . 5 V dc ± 10%

L

Analog Input Voltage (SIN and COS) . . . . . . . .2 V rms ± 10%

Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak

Signal and Reference Harmonic Distortion . . . . . . . 10% (max)

Phase Shift Between Signal and Reference . . . ±10 Degrees (max)
Ambient Operating Temperature Range

Commercial (JD, KD, LD) . . . . . . . . . . . . . . . . 0°C to 70°C

Industrial (AD, BD) . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (SD, SE, TD, TE, UD, UE) . . . –55°C to +125°C

ABSOLUTE MAXIMUM RATINGSl

2

+V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc

S

–V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –14 V dc

S

+V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

L

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V

SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V

COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V

(

with respect to GND

)

S

S

S

S

Any Logical Input . . . . . . . . . . . . . . . . . . . –0.4 V dc to +VL dc

Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V

Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V

VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V

S

S

S

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 mW

Operating Temperature

Commercial (JD, KD, LD) . . . . . . . . . . . . . . . . 0°C to 70°C

Industrial (AD, BD) . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (SD, SE, TD, TE, UD, UE) . . . –55°C to +125°C

3

(40-Lead DIP 883 Parts Only) . . . . . . . . . . . . . . . 11°C/W

θ

JC

3

θ

(44-Terminal LCC 883 Parts Only) . . . . . . . . . . . 10°C/W

JC

Storage Temperature (All Grades) . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

CAUTION NOTES:

1

Absolute Maximum Ratings are those values beyond which damage to the device
may occur.

2

Correct polarity voltages must be maintained on the +VS and –VS pins.

3

With reference to Appendix C of MIL-M-38510.

Bit Weight Table

DIP (D) Package

COS

SIGNAL GND

ANALOG GND

SIN

7

+V

8

S

NC

9

MSB DB1

10

DB2

11

DB3

12

DB4

13

DB5

14

DB6

15

DB7

16

DB8

17

18 19 242320 2221 28272625

DB9

DB10

NC = NO CONNECT

PIN CONFIGURATIONS

1

2

3

4

COS

5

6

7

SIN

+V

833

S

MSB DB1

932

AD2S80A

10 31

DB2

TOP VIEW

(Not to Scale)

DB3

11

12 29

DB4

DB5

13

14

DB6

15

DB7

DB8

16

17

DB9

18 23

DB10

19

DB11

20

DB12

NC

VCO I/P

INTEGRATOR I/P

–V

39

RIPPLE CLOCK

38

DIRECTION

37

BUSY

36

DATA LOAD

35

NC

34

33

SC2

SC1

32

DIGITAL GND

31

30

INHIBIT

NC

29

L

V

ENABLE

BYTE SELECT

DEMOD I/P

AC ERROR O/P

3124444342414056

AD2S80A

TOP VIEW

(Not to Scale)

DB11

DB13

DB12

REFERENCE I/P

DEMOD I/P

AC ERROR O/P

ANALOG GND

SIGNAL GND

DEMOD O/P

REFERENCE I/P

INTEGRATOR O/P

DB14

DB15

LSB DB16

DEMOD O/P

40

INTEGRATOR O/P

39

INTEGRATOR I/P

38

37

VCO I/P

–V

36

S

35

RIPPLE CLK

34

DIRECTION

BUSY

DATA LOAD

SC2

SC1

30

DIGITAL GND

28

INHIBIT

27

BYTE SELECT

26

ENABLE

25

V

L

DB16 LSB

24

DB15

22

DB14

21

DB13

LCC (E) Package

S

Binary Resolution Degrees Minutes Seconds
Bits (N) (2N) /Bit /Bit /Bit

0 1 360.0 21600.0 1296000.0
1 2 180.0 10800.0 648000.0
2 4 90.0 5400.0 324000.0
3 8 45.0 2700.0 162000.0
4 1 6 22.5 1350.0 81000.0

5 3 2 11.25 675.0 40500.0
6 6 4 5.625 337.5 20250.0
7 128 2.8125 168.75 10125.0
8 256 1.40625 84.375 5062.5
9 512 0.703125 42.1875 2531.25

10 1024 0.3515625 21.09375 1265.625
11 2048 0.1757813 10.546875 632.8125
12 4096 0.0878906 5.273438 316.40625
13 8192 0.0439453 2.636719 158.20313
14 116384 0.0219727 1.318359 79.10156

15 32768 0.0109836 0.659180 39.55078
16 65536 0.0054932 0.329590 19.77539
17 131072 0.0027466 0.164795 9.88770
18 262144 0.0013733 0.082397 4.94385

REV. B

–5–

PIN DESIGNATIONS

MNEMONIC DESCRIPTION

REFERENCE I/P REFERENCE SIGNAL INPUT
DEMOD I/P DEMODULATOR INPUT
AC ERROR O/P RATIO MULTIPLIER OUTPUT
COS COSINE INPUT
ANALOG GROUND POWER GROUND
SIGNAL GROUND RESOLVER SIGNAL GROUND
SIN SINE INPUT
+V

S

DB1–DB16 PARALLEL OUTPUT DATA
V

L

ENABLE LOGIC Hl-OUTPUT DATA IN HIGH IMPEDANCE

BYTE SELECT LOGIC Hl-MOST SIGNIFICANT BYTE TO DB1–DB8

INHIBIT LOGIC LO INHIBITS DATA TRANSFER TO

DIGITAL GROUND DlGITAL GROUND
SC1–SC2 SELECT CONVERTER RESOLUTION
DATA LOAD LOGIC LO DB1–DB16 INPUTS LOGIC Hl DB1–D16

BUSY CONVERTER BUSY, DATA NOT VALID WHILE

DIRECTION LOGIC STATE DEFINES DIRECTION

RIPPLE CLOCK POSITIVE PULSE WHEN CONVERTER OUTPUT

–V

S

VCO I/P VCO INPUT
INTEGRATOR I/P INTEGRATOR INPUT
INTEGRATOR O/P INTEGRATOR OUTPUT
DEMOD O/P DEMODULATOR OUTPUT

POSITIVE POWER SUPPLY

LOGIC POWER SUPPLY

STATE, LOGIC LO PRESENTS DATA TO THE
OUTPUT LATCHES

LOGIC LO-LEAST SlGNlFlCANT BYTE TO DB1–DB8

OUTPUT LATCHES

OUTPUTS

BUSY Hl

OF INPUT SIGNAL ROTATION

CHANGES FROM 1S TO ALL 0S OR VICE VERSA
NEGATIVE POWER SUPPLY