ANALOG DEVICES AD2S1210 Service Manual
Variable Resolution, 10-Bit to 16-Bit R/D
www.BDTIC.com/ADI
FEATURES
Complete monolithic resolver-to-digital converter
3125 rps maximum tracking rate (10-bit resolution)
±2.5 arc minutes of accuracy
10-/12-/14-/16-bit resolution, set by user
Parallel and serial 10-bit to 16-bit data ports
Absolute position and velocity outputs
System fault detection
Programmable fault detection thresholds
Differential inputs
Incremental encoder emulation
Programmable sinusoidal oscillator on-board
Compatible with DSP and SPI interface standards
5 V supply with 2.3 V to 5 V logic interface
−40°C to +125°C temperature rating
APPLICATIONS
DC and ac servo motor control
Encoder emulation
Electric power steering
Electric vehicles
Integrated starter generators/alternators
Automotive motion sensing and control
Converter with Reference Oscillator
AD2S1210
FUNCTIONAL BLOCK DIAGRAM
EXCITATION
OUTPUTS
INPUTS
FROM
RESOLVER
ENCODER
EMULATION
OUTPUTS
REFERENCE
OSCILLATOR
SYNTHETIC
REFERENCE
ADC
ADC
ENCODER
EMULATION
RESET
(DAC)
TYPE II
TRACKING LO OP
POSITION
REGISTER
MULTIPLEXER
DATA BUS OUTPUT
DATA I/O
REFERENCE
PINS
VOLTAGE
REFERENCE
VELOCITY
REGISTER
Figure 1.
CRYSTAL
INTERNAL
GENERATOR
AD2S1210
FAULT
DETECT ION
CONFIGURATION
REGISTER
CLOCK
FAULT
DETECTION
OUTPUTS
DATA I/O
07467-001
GENERAL DESCRIPTION
The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
resolver-to-digital converter, integrating an on-board programmable sinusoidal oscillator that provides sine wave excitation
for resolvers.
The converter accepts 3.15 V p-p ± 27% input signals, in the range
of 2 kHz to 20 kHz on the sine and cosine inputs. A Type II
servo loop is employed to track the inputs and convert the input
sine and cosine information into a digital representation of the
input angle and velocity. The maximum tracking rate is 3125 rps.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1. Ratiometric tracking conversion. The Type II tracking loop
provides continuous output position data without
conversion delay. It also provides noise immunity and
tolerance of harmonic distortion on the reference and
input signals.
2. System fault detection. A fault detection circuit can sense
loss of resolver signals, out-of-range input signals, input
signal mismatch, or loss of position tracking. The fault
detection threshold levels can be individually programmed
by the user for optimization within a particular application.
3. Input signal range. The sine and cosine inputs can accept
differential input voltages of 3.15 V p-p ± 27%.
4. Programmable excitation frequency. Excitation frequency
is easily programmable to a number of standard frequencies
between 2 kHz and 20 kHz.
5. Triple format position data. Absolute 10-bit to 16-bit angular
position data is accessed via either a 16-bit parallel port or a
4-wire serial interface. Incremental encoder emulation is in
standard A-quad-B format with direction output available.
6. Digital velocity output. 10-bit to 16-bit signed digital velocity
accessed via either a 16-bit parallel port or a 4-wire serial
interface.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
AD2S1210
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 6
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 11
Resolver Format Signals ................................................................. 15
Theory of Operation ...................................................................... 16
Resolver to Digital Conversion ................................................. 16
Fault Detection Circuit .............................................................. 16
On-Board Programmable Sinusoidal Oscillator .................... 18
Synthetic Reference Generation ............................................... 18
Configuration of AD2S1210 ......................................................... 20
Modes of Operation ................................................................... 20
Register Map .................................................................................... 21
Position Register ......................................................................... 21
Velocity Register ......................................................................... 21
REVISION HISTORY
8/08—Revision 0: Initial Version
LOS Threshold Register ............................................................ 21
DOS Overrange Threshold Register ........................................ 21
DOS Mismatch Threshold Register ......................................... 21
DOS Reset Maximum and Minimum Threshold Registers . 22
LOT High Threshold Register .................................................. 22
LOT Low Threshold Register ................................................... 22
Excitation Frequency Register .................................................. 22
Control Register ......................................................................... 22
Software Reset Register ............................................................. 23
Fault Register .............................................................................. 23
Digital interface .............................................................................. 24
SOE
Input .................................................................................... 24
SAMPLE
Data Format ................................................................................ 24
Parallel Interface ......................................................................... 24
Serial Interface ............................................................................ 28
Incremental Encoder Outputs .................................................. 31
Supply Sequencing and Reset ................................................... 31
Circuit Dynamics ........................................................................... 32
Loop Response Model ............................................................... 32
Sources of Error .......................................................................... 33
Outline Dimensions ....................................................................... 34
Ordering Guide .......................................................................... 34
Input............................................................................ 24
Rev. 0 | Page 2 of 36
AD2S1210
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SPECIFICATIONS
MIN
EXC
frequency = 10 kHz to 20 kHz (10-bit); 6 kHz to 20 kHz (12-bit);
to T
; unless otherwise noted.1
MAX
COS to COSLO
AVDD = DVDD = 5.0 V ± 5%, CLKIN = 8.192 MHz ± 25%, EXC,
3 kHz to 12 kHz (14-bit); 2 kHz to 10 kHz (16-bit); T
= T
A
Table 1.
Parameter Min Typ Max Unit Conditions/Comments
SINE, COSINE INPUTS2
Voltage Amplitude 2.3 3.15 4.0 V p-p Sinusoidal waveforms, differential SIN to SINLO,
Input Bias Current 8.25 μA VIN = 4.0 V p-p, CLKIN = 8.192 MHz
Input Impedance 485 kΩ VIN = 4.0 V p-p, CLKIN = 8.192 MHz
Phase Lock Range −44 +44 Degrees Sine/cosine vs. EXC output, Control Register D3 = 0
Common-Mode Rejection ±20 arc sec/V 10 Hz to 1 MHz, Control Register D4 = 0
ANGULAR ACCURACY3
Angular Accuracy ±2.5 + 1 LSB ±5 + 1 LSB arc min B, D grades
±5 + 1 LSB ±10 + 1 LSB arc min A, C grades
Resolution 10, 12, 14, 16 Bits No missing codes
Linearity INL
10-bit ±1 LSB B, D grades
±2 LSB A, C grades
12-bit ±2 LSB B, D grades
±4 LSB A, C grades
14-bit ±4 LSB B, D grades
±8 LSB A, C grades
16-bit ±16 LSB B, D grades
±32 LSB A, C grades
Linearity DNL ±0.9 LSB
Repeatability ±1 LSB
VELOCITY OUTPUT
Velocity Accuracy4
10-bit ±2 LSB B, D grades, zero acceleration
±4 LSB A, C grades, zero acceleration
12-bit ±2 LSB B, D grades, zero acceleration
±4 LSB A, C grades, zero acceleration
14-bit ±4 LSB B, D grades, zero acceleration
±8 LSB A, C grades, zero acceleration
16-bit ±16 LSB B, D grades, zero acceleration
±32 LSB A, C grades, zero acceleration
Resolution5 9, 11, 13, 15 Bits
DYNAMNIC PERFORMANCE
Bandwidth
10-bit 2000 6500 Hz
2900 5300 Hz CLKIN = 8.192 MHz
12-bit 900 2800 Hz
1200 2200 Hz CLKIN = 8.192 MHz
14-bit 400 1500 Hz
600 1200 Hz CLKIN = 8.192 MHz
16-bit 100 350 Hz
125 275 Hz CLKIN = 8.192 MHz
Rev. 0 | Page 3 of 36
AD2S1210
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Parameter Min Typ Max Unit Conditions/Comments
Tracking Rate
10-bit 3125 rps CLKIN = 10.24 MHz
2500 CLKIN = 8.192 MHz
12-bit 1250 rps CLKIN = 10.24 MHz
1000 CLKIN = 8.192 MHz
14-bit 625 rps CLKIN = 10.24 MHz
500 CLKIN = 8.192 MHz
16-bit 156.25 rps CLKIN = 10.24 MHz
125 CLKIN = 8.192 MHz
Acceleration Error
10-bit 30 arc min At 50,000 rps2, CLKIN = 8.192 MHz
12-bit 30 arc min At 10,000 rps2, CLKIN = 8.192 MHz
14-bit 30 arc min At 2500 rps2, CLKIN = 8.192 MHz
16-bit 30 arc min At 125 rps2, CLKIN = 8.192 MHz
Settling Time 10° Step Input
10-bit 0.6 0.9 ms To settle to within ±2 LSB , CLKIN = 8.192 MHz
12-bit 2.2 3.1 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
14-bit 6.5 9.0 ms To settle to within ±2 LSB , CLKIN = 8.192 MHz
16-bit 27.5 40 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
Settling Time 179° Step Input
10-bit 1.5 2.2 ms To settle to within ±2 LSB , CLKIN = 8.192 MHz
12-bit 4.75 6.0 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
14-bit 10.5 14.7 ms To settle to within ±2 LSB , CLKIN = 8.192 MHz
16-bit 45 66 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
EXC
EXC,
VOLTAGE REFERENCE
CLKIN, XTALOUT6
LOGIC INPUTS
LOGIC OUTPUTS
OUTPUTS
Voltage 3.2 3.6 4.0 V p-p Load ±100 μA, typical differential output
Center Voltage 2.40 2.47 2.53 V
Frequency 2 20 kHz
EXC
EXC/
EXC/
THD −58 dB First five harmonics
REFOUT 2.40 2.47 2.53 V ±I
Drift 100 ppm/°C
PSRR −60 dB
VIL Voltage Input Low 0.8 V
VIH Voltage Input High 2.0 V
VIL Voltage Input Low 0.8 V V
0.7 V V
VIH Voltage Input High 2.0 V V
1.7 V V
IIL Low Level Input Current (Non
IIL Low Level Input Current (Pull-Up) 80 μA
IIH High Level Input Current −10 μA
VOL Voltage Output Low 0.4 V V
VOH Voltage Output High 2.4 V V
2.0 V V
I
I
DC Mismatch
EXC
AC Mismatch
Pull-Up)
High Level Three-State Leakage −10 μA
OZH
Low Level Three-State Leakage 10 μA
OZL
EXC
(EXC to
30 mV
100 mV
= 100 μA
OUT
= 2.7 V to 5.25 V
DRIVE
= 2.3 V to 2.7 V
DRIVE
= 2.7 V to 5.25 V
DRIVE
= 2.3 V to 2.7 V
DRIVE
10 μA
RES0, RES1,
= 2.3 V to 5.25 V
DRIVE
= 2.7 V to 5.25 V
DRIVE
= 2.3 V to 2.7 V
DRIVE
) = 7.2 V p-p
RD
, WR/FSYNC, A0, A1, and RESET pins
Rev. 0 | Page 4 of 36
AD2S1210
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Parameter Min Typ Max Unit Conditions/Comments
POWER REQUIREMENTS
AVDD 4.75 5.25 V
DVDD 4.75 5.25 V
V
2.3 5.25 V
DRIVE
POWER SUPPLY
I
12 mA
AVDD
I
35 mA
DVDD
I
2 mA
OVDD
1
Temperature ranges are as follows: A, B grades: –40°C to +85°C; C, D grades: –40°C to +125°C.
2
The voltages, SIN, SINLO, COS, and COSLO, relative to AGND, must always be between 0.15 V and AVDD − 0.2 V.
3
All specifications within the angular accuracy parameter are tested at constant velocity, that is, zero acceleration.
4
The velocity accuracy specification includes velocity offset and dynamic ripple.
5
For example when RES0 = 0 and RES1 = 1, the position output has a resolution of 12 bits. The velocity output has a resolution of 11 bits with the MSB indicating the
direction of rotation. In this example, with a CLKIN frequency of 8.192 MHz the velocity LSB is 0.488 rps, that is, 1000 rps/(211).
6
The clock frequency of the AD2S1210 can be supplied with a crystal, an oscillator, or directly from a DSP/microprocessor digital output. When using a single-ended
clock signal directly from the DSP/microprocessor, the XTALOUT pin should remain open circuit and the logic levels outlined under the logic inputs parameter in Table 1 apply.
Rev. 0 | Page 5 of 36
AD2S1210
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TIMING SPECIFICATIONS
AVDD = DVDD = 5.0 V ± 5%, TA = T
Table 2.
Parameter Description Limit at T
f
Frequency of clock input 6.144 MHz min
CLKIN
10.24 MHz max
tCK Clock period ( = 1/f
163 ns max
t1
t2
A0 and A1 setup time before RD
Delay CS
t3 Address/data setup time during a write cycle 3 ns min
t4 Address/data hold time during a write cycle 2 ns min
t5
t6
Delay WR
Delay CS
t7 Delay between writing address and writing data 2 × tCK + 20 ns min
t8
A0 and A1 hold time after WR
t9 Delay between successive write cycles 6 × tCK + 20 ns min
t10
t11
t12
V
V
V
t13
t
14A
t
14B
t15
t16
t17
t18
t19
V
V
V
t20
t21
V
V
V
t22
t23
V
V
V
Delay between rising edge of WR
Delay CS
Enable delay RD
DRIVE
DRIVE
DRIVE
rising edge to CS rising edge
RD
Disable delay RD
Disable delay CS
Delay between rising edge of RD
SAMPLE
Delay from SAMPLE
Hold time RD
Enable delay RD
DRIVE
DRIVE
DRIVE
pulse width
RD
A0 and A1 set time to data valid when RD
DRIVE
DRIVE
DRIVE
Delay WR
Delay WR
DRIVE
DRIVE
DRIVE
t24 Delay SCLK rising edge to DBx valid
V
V
V
DRIVE
DRIVE
DRIVE
t25 SCLK high time 0.4 × tCK ns min
t26 SCLK low time 0.4 × tCK ns min
t27 SDI setup time prior to SCLK falling edge 3 ns min
t28 SDI hold time after SCLK falling edge 2 ns min
to T
MIN
falling edge to WR/FSYNC rising edge
/FSYNC rising edge to CS rising edge
rising edge to CS falling edge
falling edge to RD falling edge
unless otherwise noted.1
MAX,
, T
MIN
) 98 ns min
CLKIN
/CS low
2 ns min
Unit
MAX
22 ns min
2 ns min
10 ns min
/FSYNC rising edge
/FSYNC and falling edge of RD
2 ns min
2 ns min
2 ns min
low to data valid in configuration mode
= 4.5 V to 5.25 V 37 ns min
= 2.7 V to 3.6 V 25 ns min
= 2.3 V to 2.7 V 30 ns min
2 ns min
high to data high-Z
high to data high-Z
and falling edge of WR/FSYNC
pulse width
before RD/CS low
before RD low
/CS low to data valid
16 ns min
16 ns min
2 ns min
2 × t
+ 20 ns min
CK
6 × t
+ 20 ns min
CK
2 ns min
= 4.5 V to 5.25 V 17 ns min
= 2.7 V to 3.6 V 21 ns min
= 2.3 V to 2.7 V 33 ns min
6 ns min
/CS low
= 4.5 V to 5.25 V 36 ns min
= 2.7 V to 3.6 V 37 ns min
= 2.3 V to 2.7 V 29 ns min
/FSYNC falling edge to SCLK rising edge
/FSYNC falling edge to SDO release from high-Z
3 ns min
= 4.5 V to 5.25 V 16 ns min
= 2.7 V to 3.6 V 26 ns min
= 2.3 V to 2.7 V 29 ns min
= 4.5 V to 5.25 V 24 ns min
= 2.7 V to 3.6 V 18 ns min
= 2.3 V to 2.7 V 32 ns min
Rev. 0 | Page 6 of 36
AD2S1210
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Parameter Description Limit at T
t29
t30
t31
t32
t33
In normal mode, A0 = 0, A1 = 0/1 24 × tCK + 5 ns ns min
In configuration mode, A0 = 1, A1 = 1 8 × tCK + 5 ns ns min
t34
f
Frequency of SCLK input
SCLK
V
V
V
1
Temperature ranges are as follows: A, B grades: –40°C to +85°C; C, D grades: –40°C to +125°C.
2
A0 and A1 should remain constant for the duration of the serial readback. This may require 24 clock periods to read back the 8-bit fault information in addition to the
16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released following 16 clock cycles.
Delay WR
Delay from SAMPLE
Delay CS
A0 and A1 setup time before WR
A0 and A1 hold time after WR
Delay WR
/FSYNC rising edge to SDO high-Z
before WR/FSYNC falling edge
falling edge to WR/FSYNC falling edge in normal mode
/FSYNC falling edge
/FSYNC falling edge2
/FSYNC rising edge to WR/FSYNC falling edge
= 4.5 V to 5.25 V 20 MHz
DRIVE
= 2.7 V to 3.6 V 25 MHz
DRIVE
= 2.3 V to 2.7 V 15 MHz
DRIVE
15 ns min
6 × t
2 ns min
2 ns min
10 ns min
, T
MIN
+ 20 ns ns min
CK
Unit
MAX
Rev. 0 | Page 7 of 36
AD2S1210
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ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
AVDD to AGND, DGND −0.3 V to +7.0 V
DVDD to AGND, DGND −0.3 V to +7.0 V
V
to AGND, DGND −0.3 V to AVDD
DRIVE
AVDD to DVDD −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to V
Digital Output Voltage to DGND −0.3 V to V
Analog Output Voltage Swing −0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range (Ambient)
A, B Grades −40°C to +85°C
C, D Grades −40°C to +125°C
Storage Temperature Range −65°C to +150°C
θJA Thermal Impedance2 54°C/W
θJA Thermal Impedance2 15°C/W
RoHS-Compliant Temperature, Soldering
Reflow
ESD 2 kV HBM
1
Transient currents of up to 100 mA do not cause latch-up.
2
JEDEC 2S2P standard board.
260(−5/+0)oC
DRIVE
DRIVE
+ 0.3 V
+ 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 8 of 36
AD2S1210
T
W
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin
No. Mnemonic Description
1 RES1
Resolution Select 1. Logic input. RES1 in conjunction with RES0 allows the resolution of the AD2S1210 to be
programmed. Refer to the Configuration of AD2S1210 section.
2
3
Chip Select. Active low logic input. The device is enabled when CS is held low.
CS
Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and output
RD
enable for the parallel data outputs, DB15 to DB0. The output buffer is enabled when CS
the SOE pin is low, the RD pin should be held high.
4
/FSYNC Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and input
WR
enable for the parallel data inputs, DB7 to DB0. The input buffer is enabled when CS
When the SOE
5, 19 DGND
Digital Ground. These pins are ground reference points for digital circuitry on the AD2S1210. Refer all digital input
signals to this DGND voltage. Both of these pins can be connected to the AGND plane of a system. The DGND and
AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
6 DVDD
Digital Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD2S1210. The AV
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
7 CLKIN
Clock Input. A crystal or oscillator can be used at the CLKIN and XTALOUT pins to supply the required clock frequency of
the AD2S1210. Alternatively, a single-ended clock can be applied to the CLKIN pin. The input frequency of the AD2S1210 is
specified from 6.144 MHz to 10.24 MHz.
8 XTALOUT
Crystal Output. When using a crystal or oscillator to supply the clock frequency to the AD2S1210, apply the crystal
across the CLKIN and XTALOUT pins. When using a single-ended clock source, the XTALOUT pin should be
considered a no connect pin.
9
Serial Output Enable. Logic input. This pin enables either the parallel or serial interface. The serial interface is selected
SOE
by holding the SOE
10
SAMPLE
Sample Result. Logic input. Data is transferred from the position and velocity integrators to the position and velocity
registers, after a high-to-low transition on the SAMPLE
transition on the SAMPLE
11 DB15/SDO
Data Bit 15/Serial Data Output Bus. When the SOE
controlled by CS
WR/FSYNC. The bits are clocked out on the rising edge of SCLK.
12 DB14/SDI
Data Bit 14/Serial Data Input Bus. When the SOE
and RD. When the SOE pin is low, this pin acts as SDI, the serial data input bus controlled by CS and WR/FSYNC. The
by CS
bits are clocked in on the falling edge of SCLK.
AD2S1210
TOP VIEW
(Not to Scale)
16
18
17
DB9
DB10
DD
SINLO41SIN40AGND39EXC38EXC37A0
42
20
19
DB821DB722DB623DB524DB4
DRIVE
DGND
V
36
35
34
33
32
31
30
29
28
27
26
25
A1
DOS
LOT
RESET
DIR
NM
B
A
DB0
DB1
DB2
DB3
07467-002
RES1
CS
RD
R/FSYNC
DGND
DV
CLKIN
XTALOUT
SOE
SAMPLE
DB15/SDO
DB14/SDI
RES047REFOU
REFBYP45COS44COSLO43AV
48
46
1
PIN 1
2
3
4
5
6
DD
7
8
9
10
11
12
13
14
15
DB11
DB12
DB13/SCLK
Figure 2. Pin Configuration
and RD are held low. When
and WR/FSYNC are held low.
pin is low, the WR/FSYNC pin acts as a frame synchronization signal and enable for the serial data bus.
and DVDD
DD
pin low, and the parallel interface is selected by holding the SOE pin high.
signal. The fault register is also updated after a high-to-low
signal.
pin is high, this pin acts as DB15, a three-state data output pin
and RD. When the SOE pin is low, this pin acts as SDO, the serial data output bus controlled by CS and
pin is high, this pin acts as DB14, a three-state data output pin controlled
Rev. 0 | Page 9 of 36
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Pin
No. Mnemonic Description
13 DB13/SCLK
14 to
17
18 V
20 DB8
21 to
28
29 A
30 B
31 NM
32 DIR
33
34 LOT
35 DOS
36 A1
37 A0
38 EXC
39
40 AGND
41 SIN Positive Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
42 SINLO Negative Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
43 AVDD
44 COSLO Negative Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
45 COS Positive Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
46 REFBYP Reference Bypass. Connect reference decoupling capacitors at this pin. Typical recommended values are 10 μF and 0.01 μF.
47 REFOUT Voltage Reference Output.
48 RES0
DB12 to
DB9
DRIVE
DB7 to DB0
Reset. Logic input. The AD2S1210 requires an external reset signal to hold the RESET input low until VDD is within the
RESET
Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal
EXC
Data Bit 13/Serial Clock. In parallel mode, this pin acts as DB13, a three-state data output pin controlled by CS
serial mode, this pin acts as the serial clock input.
Data Bit 12 to Data Bit 9. Three-state data output pins controlled by CS and RD.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
Decouple this pin to DGND. The voltage range on this pin is 2.3 V to 5.25 V and may be different to the voltage range
and DVDD but should never exceed either by more than 0.3 V.
at AV
DD
Data Bit 8. Three-state data output pin controlled by CS
Data Bit 7 to Data Bit 0. Three-state data input/output pins controlled by CS
Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format
input signals applied to the converter are valid.
Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format
input signals applied to the converter are valid.
North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the
resolver format input signals applied to the converter are valid.
Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The DIR
output indicates the direction of the input rotation and is high for increasing angular rotation.
specified operating range of 4.75 V to 5.25 V.
Loss of Tracking. Logic output. LOT is indicated by a logic low on the LOT pin and is not latched. Refer to the Loss of
Position Tracking Detection section.
Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (sine or cosine)
exceeds the specified DOS sine/cosine threshold or when an amplitude mismatch occurs between the sine and
cosine input voltages. DOS is indicated by a logic low on the DOS pin. Refer to the Signal Degradation Detection
section.
Mode Select 1. Logic input. A1 in conjunction with A0 allows the mode of the AD2S1210 to be selected. Refer to the
Configuration of AD2S1210 section.
Mode Select 0. Logic input. A0 in conjunction with A1 allows the mode of the AD2S1210 to be selected. Refer to the
Configuration of AD2S1210 section.
Excitation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its
complement signal (EXC
frequency register.
(EXC) and its complement signal (EXC
excitation frequency register.
Analog Ground. This pin is the ground reference points for analog circuitry on the AD2S1210. Refer all analog input
signals and any external reference signal to this AGND voltage. Connect the AGND pin to the AGND plane of a
system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V
apart, even on a transient basis.
Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1210. The
and DVDD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
AV
DD
transient basis.
Resolution Select 0. Logic input. RES0 in conjunction with RES1 allows the resolution of the AD2S1210 to be
programmed. Refer to the Configuration of AD2S1210 section.
) to the resolver. The frequency of this reference signal is programmable via the excitation
) to the resolver. The frequency of this reference signal is programmable via the
and RD.
, RD, and WR/FSYNC.
and RD. In
Rev. 0 | Page 10 of 36
AD2S1210
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, AVDD = DVDD = V
400
350
300
250
200
150
HITS P ER CODE
100
50
0
8178
8179
8180
8181
8182
8183
8184
8185
8186
Figure 3. Typical 16-Bit Angular Accuracy Histogram Of Codes, 512 Samples
500
450
400
350
300
250
200
HITS PER CODE
150
100
50
0
8178
8179
8180
8181
8182
8183
8184
8185
8186
Figure 4. Typical 14-Bit Angular Accuracy Histogram of Codes, 512 Samples,
600
500
400
300
HITS PER CODE
200
100
0
2045 2046 2047 2048 2049
Figure 5. Typical 14-Bit Angular Accuracy Histogram of Codes, 512 Samples,
= 5 V, SIN/SINLO = 3.15 V p-p, COS/COSLO = 3.15 V p-p, CLKIN = 8.192 MHz , unless otherwise noted.
DRIVE
200
180
160
140
120
100
80
HITS PER CODE
60
40
20
0
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201
8202
8203
8204
8205
8187
CODE
8206
07467-003
8178
8179
8180
8181
8182
8183
8184
8185
8186
8188
8189
8190
8191
8192
8193
8194
8195
8187
CODE
8196
Figure 6. Typical 12-Bit Angular Accuracy Histogram of Codes, 512 Samples,
Hysteresis Disabled
600
500
400
300
HITS PER CODE
200
100
0
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201
8202
8203
8204
8205
8206
CODE
07467-004
Figure 7. Typical 12-Bit Angular Accuracy Histogram of Codes, 512 Samples,
510 511 512 513 514
CODES
Hysteresis Enabled
Hysteresis Disabled
CODES
07467-005
HITS PER CODE
60
50
40
30
20
10
0
8178
8179
8180
8181
8182
8183
8184
8185
8186
8188
8189
8190
8191
8192
8193
8194
8195
8196
8187
CODE
8197
Figure 8. Typical 10-Bit Angular Accuracy Histogram of Codes, 512 Samples,
Hysteresis Enabled
Hysteresis Disabled
8197
8198
8199
8200
8201
8202
8203
8204
8205
8206
07467-006
07467-017
8198
8199
8200
8201
8202
8203
8204
8205
8206
07467-018
Rev. 0 | Page 11 of 36
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