ANALOG DEVICES AD2S1205 Service Manual

12-Bit R/D Converter

YSTA

FEATURES

Complete monolithic resolver-to-digital converter (RDC)
Parallel and serial 12-bit data ports
System fault detection
±11 arc minutes of accuracy
Input signal range: 3.15 V p-p ± 27%
Absolute position and velocity outputs
1250 rps maximum tracking rate, 12-bit resolution
Incremental encoder emulation (1024 pulses/rev)
Programmable sinusoidal oscillator on board
Single-supply operation (5.00 V ± 5%)

−40°C to +125°C temperature rating
44-lead LQFP
4 kV ESD protection

APPLICATIONS

Automotive motion sensing and control
Hybrid-electric vehicles
Electric power steering
Integrated starter generator/alternator
Industrial motor control
Process control

EXCITATION

OUTPUTS

INPUTS

FROM

RESOLVER

ENCODER

EMULATION

OUTPUTS

with Reference Oscillator

AD2S1205

FUNCTIONAL BLOCK DIAGRAM

CR

AD2S1205

ADC

ADC

ENCODER

EMULATION

RESET

REFERENCE

REFERENCE
OSCILLATOR

(DAC)

SYNTHETIC

REFERENCE

TYPE II TRACKING LOOP

POSITION REGISTER

Figure 1.

PINS

VOLTAGE

REFERENCE

VELOCITY REGISTER

MULTIPLEXER

DATA BUS OUTPUT

DATA I/O

INTERNAL

CLOCK

GENERATOR

FAULT

DETECTION

L

FAULT
DETECTION
OUTPUTS

06339-001

GENERAL DESCRIPTION

The AD2S1205 is a complete 12-bit resolution tracking
resolver-to-digital converter that contains an on-board
programmable sinusoidal oscillator providing sine wave
excitation for resolvers.

The converter accepts 3.15 V p-p ± 27% input signals on the Sin
and Cos inputs. A Type II tracking loop is employed to track the
inputs and convert the input Sin and Cos information into a digital
representation of the input angle and velocity. The maximum
tracking rate is a function of the external clock frequency. The
performance of the AD2S105 is specified across a frequency
range of 8.192 MHz ± 25%, allowing a maximum tracking rate
of 1250 rps.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

PRODUCT HIGHLIGHTS

1. Ratiometric Tracking Conversion. The Type II tracking

loop provides continuous output position data without
conversion delay. It also provides noise immunity and
tolerance of harmonic distortion on the reference and
input signals.

2. System Fault Detection. A fault detection circuit can sense

loss of resolver signals, out-of-range input signals, input
signal mismatch, or loss of position tracking.

3. Input Signal Range. The Sin and Cos inputs can accept

differential input voltages of 3.15 V p-p ± 27%.

4. Programmable Excitation Frequency. Excitation frequency

is easily programmable to 10 kHz, 12 kHz, 15 kHz, or 20 kHz
by using the frequency select pins (the FS1 and FS2 pins).

5. Triple Format Position Data. Absolute 12-bit angular position

data is accessed via either a 12-bit parallel port or a 3-wire
serial interface. Incremental encoder emulation is in standard
A-quad-B format with direction output available.

6. Digital Velocity Output. 12-bit signed digital velocity accessed

via either a 12-bit parallel port or a 3-wire serial interface.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD2S1205

TABLE OF CONTENTS

Features.............................................................................................. 1

False Null Condition.................................................................. 10

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Resolver Format Signals................................................................... 8

Theory of Operation ........................................................................ 9

Fault Detection Circuit................................................................ 9

Monitor Signal .............................................................................. 9

Loss of Signal Detection .............................................................. 9

Signal Degradation Detection .................................................... 9

On-Board Programmable Sinusoidal Oscillator.................... 10

Synthetic Reference Generation............................................... 11

Charge-Pump Output ................................................................ 11

Connecting the Converter ........................................................ 11

Clock Requirements................................................................... 12

Absolute Position and Velocity Output ................................... 12

Parallel Interface......................................................................... 12

Serial Interface............................................................................ 14

Incremental Encoder Outputs.................................................. 16

Supply Sequencing and Reset ................................................... 16

Circuit Dynamics ........................................................................... 17

Loop Response Model ............................................................... 17

Sources of Error.......................................................................... 18

Connecting to the DSP.............................................................. 19

Outline Dimensions....................................................................... 20

Loss of Position Tracking Detection ........................................ 10

Responding to a Fault Condition............................................. 10

REVISION HISTORY

1/07—Revision 0: Initial Version

Ordering Guide .......................................................................... 20

Rev. 0 | Page 2 of 20

AD2S1205

SPECIFICATIONS

AVDD = DVDD = 5.0 V ± 5% at −40°C to +125°C, CLKIN = 8.192 MHz ± 25%, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Conditions/Comments

Sin, Cos INPUTS

Voltage 2.3 3.15 4.0 V p-p

Input Bias Current 12 μA VIN = 3.25 VDC, CLKIN = 10.24 MHz
Input Impedance 0.35 MΩ VIN = 3.25 VDC
Common-Mode Voltage 100 mV peak CMV with respect to REFOUT/2 at 10 kHz
Phase-Lock Range −44 +44 Degrees Sin/Cos vs. EXC output

ANGULAR ACCURACY

Angular Accuracy ±11 Arc minutes Zero acceleration, Y grade
±22 Arc minutes Zero acceleration, W grade
Resolution 12 Bits Guaranteed no missing codes
Linearity INL 2 LSB Zero acceleration, 0 rps to 1250 rps, CLKIN = 10.24 MHz
Linearity DNL 0.3 LSB Guaranteed monotonic
Repeatability 1 LSB
Hysteresis 1 LSB

VELOCITY OUTPUT

Velocity Accuracy 2 LSB Zero acceleration
Resolution 11 Bits
Linearity 1 LSB Guaranteed by design, 2 LSB maximum
Offset 0 1 LSB Zero acceleration
Dynamic Ripple 1 LSB Zero acceleration

DYNAMIC PERFORMANCE

Bandwidth 1000 2400 Hz
Tracking Rate 750 rps CLKIN = 6.144 MHz , guaranteed by design
1000 rps CLKIN = 8.192 MHz , guaranteed by design
1250 rps CLKIN = 10.24 MHz , guaranteed by design
Acceleration Error 30 Arc minutes At 10,000 rps, CLKIN = 8.192 MHz
Settling Time 179° Step Input 5.2 ms To within ±11 arc minutes, Y grade, CLKIN = 10.24 MHz

4.0 ms To within 1 degree, Y grade, CLKIN = 10.24 MHz

EXC, EXC OUTPUTS

Voltage 3.34 3.6 3.83 V p-p Load ±100 μA
Center Voltage 2.39 2.47 2.52 V
Frequency 10 kHz FS1 = high, FS2 = high, CLKIN = 8.192 MHz
12 kHz FS1 = high, FS2 = low, CLKIN = 8.192 MHz
15 kHz FS1 = low, FS2 = high, CLKIN = 8.192 MHz
20 kHz FS1 = low, FS2 = low, CLKIN = 8.192 MHz
EXC/EXC DC Mismatch
THD −58 dB First five harmonics

FAULT DETECTION BLOCK

Loss of Signal (LOS)

Sin/Cos Threshold 2.18 2.24 2.3 V p-p DOS and LOT go low when Sin or Cos fall below threshold
Angular Accuracy (Worst Case) 57 Degrees

Angular Latency (Worst Case) 114 Degrees

Time Latency 125 μs

1

Sinusoidal waveforms, Sin − SinLO and Cos − CosLO,
differential inputs

35 mV

LOS indicated before angular output error exceeds limit
(4.0 V p-p input signal and 2.18 V LOS threshold)

Maximum electrical rotation before LOS is indicated
(4.0 V p-p input signal and 2.18 V LOS threshold)

Rev. 0 | Page 3 of 20

AD2S1205

Parameter Min Typ Max Unit Conditions/Comments

Degradation of Signal (DOS)

Sin/Cos Threshold 4.0 4.09 4.2 V p-p DOS goes low when Sin or Cos exceeds threshold
Angular Accuracy (Worst Case) 33 Degrees DOS indicated before angular output error exceeds limit
Angular Latency (Worst Case) 66 Degrees Maximum electrical rotation before DOS is indicated
Time Latency 125 μs
Sin/Cos Mismatch 385 420 mV

Loss of Tracking (LOT)

Tracking Threshold 5 Degrees

Time Latency 1.1 ms
Hysteresis 4 Degrees Guaranteed by design

VOLTAGE REFERENCE

REFOUT 2.39 2.47 2.52 V ±I
Drift 70 ppm/°C
PSRR −60 dB

CHARGE-PUMP OUTPUT (CPO)

Frequency 204.8 kHz Square wave output, CLKIN = 8.192 MHz
Duty Cycle 50 %

POWER SUPPLY

IDD Dynamic 20 mA

ELECTRICAL CHARACTERISTICS

VIL, Voltage Input Low 0.8 V
VIH, Voltage Input High 2.0 V
VOL, Voltage Output Low 0.4 V +1 mA load
VOH, Voltage Output High 4.0 V −1 mA load
IIL, Low Level Input Current

−10 +10 μA

(Non-Pull-Up)
IIL, Low Level Input Current (Pull-Up) −80 +80 μA
IIH, High Level Input Current −10 +10 μA
I

, High Level Three-State Leakage −10 +10 μA

OZH

I

, Low Level Three-State Leakage −10 +10 μA

OZL

1

The voltages for Sin, SinLO, Cos, and CosLO relative to AGND must be between 0.2 V and AVDD.

DOS latched low when Sin/Cos amplitude mismatch
exceeds threshold

LOT goes low when internal error signal exceeds
threshold; guaranteed by design

= 100 μA

OUT

SAMPLE, CS, RDVEL, CLKIN, SOE

Pins

RD, FS1, FS2, RESET

Pins

Rev. 0 | Page 4 of 20

AD2S1205

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage (VDD) −0.3 V to +7.0 V
Supply Voltage (AVDD) −0.3 V to +7.0 V
Input Voltage −0.3 V to VDD + 0.3 V
Output Voltage Swing −0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) −40°C to +125°C
Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 20

AD2S1205

K

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DD

39

AD2S1205

TOP VIEW

(Not to Scale)

16

17

DD

DV

DGND

SinLO38Sin37AGND36EXC35EXC

DB218DB119DB0

34

20

21

22

CLKIN

TAL OU T

33

32

31

30

29

28

27

26

25

24

23

RESET

FS2

FS1

LOT

DOS

DIR

NM

B

A

CPO

DGND

06339-002

DV

SAMPLE

RDVEL

DB11/SO

DB10/SCL

RD

CS

SOE

DB9

DB8

DB7

REFOUT44REFBYP43AGND42Cos41CosLO40AV

1

DD

2

3

4

5

6

7

8

9

10

11

15

DB612DB513DB414DB3

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin
No.

Mnemonic Description

1, 17 DVDD

Digital Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD2S1205. The AV
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

2

RD Edge-Triggered Logic Input. This pin acts as a frame synchronization signal and output enable. The output buffer is

enabled when

3

CS Chip Select. Active low logic input. The device is enabled when CS is held low.

4

SAMPLE Sample Result. Logic input. Data is transferred from the position and velocity integrators to the position and velocity

registers, respectively, after a high-to-low transition on the

5

RDVEL Read Velocity. Logic input. RDVEL input is used to select between the angular position register and the angular velocity

CS and RD are held low.

SAMPLE signal.

register. RDVEL is held high to select the angular position register and low to select the angular velocity register.

6

SOE Serial Output Enable. Logic input. This pin enables either the parallel or serial interface. The serial interface is selected by

SOE pin low, and the parallel interface is selected by holding the SOE pin high.

SOE pin is high, this pin acts as DB11, a three-state data output pin controlled

7 DB11/SO

holding the
Data Bit 11/Serial Data Output Bus. When the

CS and RD. When the SOE pin is low, this pin acts as SO, the serial data output bus controlled by CS and RD. The bits are

by
clocked out on the rising edge of SCLK.

8 DB10/SCLK

Data Bit 10/Serial Clock. In parallel mode this pin acts as DB10, a three-state data output pin controlled by
serial mode this pin acts as the serial clock input.

9 to
15

16,
23

DB9 to
DB3

DGND

Data Bits 9 to 3. Three-state data output pins controlled by CS and RD.

Digital Ground. These pins are ground reference points for digital circuitry on the AD2S1205. All digital input signals
should be referred to this DGND voltage. Both of these pins can be connected to the AGND plane of a system. The
DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.

18
to

DB2 to
DB0

Data Bits 2 to 0. Three-state data output pins controlled by CS and RD.

20
21 XTALOUT

Crystal Output. To achieve the specified dynamic performance, an external crystal is recommended at the CLKIN and
XTALOUT pins. The position and velocity accuracy are guaranteed for a frequency range of 8.192 MHz ± 25%.

22 CLKIN

Clock Input. To achieve the specified dynamic performance, an external crystal is recommended at the CLKIN and XTALOUT
pins. The position and velocity accuracy are guaranteed for a frequency range of 8.192 MHz ± 25%.

24 CPO

Charge-Pump Output. Analog output. A 204.8 kHz square wave output with a 50% duty cycle is available at the CPO
output pin. This square wave output can be used for negative rail voltage generation or to create a VCC rail.

and DVDD

DD

CS and RD. In

Rev. 0 | Page 6 of 20