Analog Devices AD1893 a Datasheet

Low Cost SamplePort

®

16-Bit Stereo Asynchronous

a

FEATURES
Low Cost
LQFP and PDIP Packages
3 V Supply Performance Specified—Very Low Power
Automatically Senses Sample Frequencies—No

Programming Required
Rejects Sample Clock Jitter
Accommodates Dynamically Changing Asynchronous

Sample Clocks
8 kHz to 56 kHz Sample Clock Frequency Range
Approximately 1:2 to 2:1 Ratio Between Sample

Clocks
–96 dB THD+N at 1 kHz
96 dB Dynamic Range
Optimal Clock Tracking Control—Slow/Fast Settling

Modes
Linear Phase in All Modes
Automatic Output Mute
Flexible Four-Wire Serial Interfaces with Right-Justified

Mode
Power-Down Mode
On-Chip Oscillator

APPLICATIONS
Consumer CD-R, DAT, DCC, MD and 8 mm Video Tape

Recorders Including Portables
Digital Audio Communication/Network Systems
Computer Multimedia Systems

PRODUCT OVERVIEW

The AD1893 SamplePort is a fully digital, stereo Asynchronous
Sample Rate Converter (ASRC) that solves sample rate interfacing
and compatibility problems in digital audio equipment. Concep­tually, this converter interpolates the input data up to a very high
internal sample rate with a time resolution of 300 ps, then deci­mates down to the desired output sample rate. The AD1893 is
intended for 16-bit low cost, non-varispeed applications where low
voltage, low power (i.e., battery-powered) operation is required.
Refer to the AD1890/AD1891 data sheet for other products in the
SamplePort family. This device is asynchronous because the fre­quency and phase relationships between the input and output
sample clocks (both are inputs to the AD1893 ASRC) are arbitrary
and need not be related by a simple integer ratio. There is no need
to explicitly select or program the input and output sample clock
frequencies, as the AD1893 automatically senses the relationship
between the two clocks. The input and output sample clock fre­quencies can nominally range from 8 kHz to 56 kHz, and the ratio
between them can vary from approximately 1:2 to 2:1.

SamplePort is a registered trademark of Analog Devices, Inc.

Sample Rate Converter

AD1893

SYSTEM DIAGRAM

EXAMPLE

FREQUENCIES:

DAT 48kHz OR

CD 44.1kHz OR

BROADCAST 32kHz

INPUT SAMPLE CLOCK

INPUT SERIAL DATA

The AD1893 uses multirate digital signal processing techniques
to construct an output sample stream from the input sample
stream. The input word width is 4 to 16 bits for the AD1893.
Shorter input words are automatically zero-filled in the LSBs.
The output word width is 24 bits. The user can receive as many
of the output bits as desired. Internal arithmetic is performed
with 22-bit coefficients and 27-bit accumulation. The digital
samples are processed with unity gain.

The input and output control signals allow for considerable
flexibility for interfacing to a variety of DSP chips, AES/EBU
receivers and transmitters and for I2S compatible devices. Input
and output data can be independently right- or left- (with or
without a one bit clock delay) justified to the left/right clock
edge. In the right-justified mode, the MSB is delayed 16-bit
clock periods from the left/right clock edge transition. Input and
output data can also be independently justified to the word
clock rising edge. The data justification options are encoded on
two mode pins for both the input port and the output port. The
bit clocks can also be independently configured for rising edge
active or falling edge active operation.

The AD1893 SamplePort ASRC has on-chip digital coefficients
that correspond to a highly oversampled 0 Hz to 20 kHz low­pass filter with a flat passband, a very narrow transition band,
and a high degree of stopband attenuation. A subset of these
filter coefficients are dynamically chosen on the basis of the
filtered ratio between the input sample clock (LR_I) and the
output sample clock (LR_O), and these coefficients are then
used in an FIR convolver to perform the sample rate conversion.
Refer to the Theory of Operation section of this data sheet for a
more thorough functional description. The low-pass filter has
been designed so that full 20 kHz bandwidth is maintained
when the input and output sample clock frequencies are as low
as 44.1 kHz. If the output sample rate drops below the input
sample rate, the bandwidth of the input signal is automatically

AD1893

EXAMPLE

FREQUENCIES:

DAT 48kHz OR

CD 44.1kHz OR

BROADCAST 32kHz

OUTPUT SAMPLE CLOCK

OUTPUT SERIAL DATA

(continued on Page 4)

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD1893–SPECIFICATIONS

TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltage +3.0 V

Ambient Temperature 25 °C

Crystal Frequency 16 MHz
Load Capacitance 100 pF

All minimums and maximums tested except as noted.

PERFORMANCE1 (Guaranteed for V

= +3.3 V to +5.0 V ± 10%)

DD

Min Max Units

Dynamic Range (20 Hz to 20 kHz, –60 dB Input) 96 dB
Total Harmonic Distortion + Noise

(20 Hz to 20 kHz, Full-Scale Input, F
(1 kHz Full-Scale Input, F
(10 kHz Full-Scale Input, F

SOUT/FSIN

SOUT/FSIN

SOUT/FSIN

Between 0.7 and 1.4) –96 dB

Between 0.7 and 1.4) –95 dB

Between 0.51 and 1.99) –94 dB

Interchannel Phase Deviation 0 Degrees
Input and Output Sample Clock Jitter

(For ≤1 dB Degradation in THD+N with 10 kHz Full-Scale Input, Slow-Settling Mode) 10 ns

DIGITAL INPUTS (Guaranteed for V

= +3.0 V to +5.0 V ± 10%)

DD

Min Max Units

V

IH

V

IL(VDD

V

IL

I

IH

I

IH

I

IL

I

IL

V

OH

V

OH

V

OL

Input Capacitance

≥ +3.0 V) 0.8 V

(+2.7 V ≤ V

@ V

= +5.0 V, All Pins Except XTAL_I 4 µA

IH

@ V

= +5.0 V, XTAL_I Pin 6 µA

IH

@ V

= 0 V, All Pins Except XTAL_I 4 µA

IL

@ V

= 0 V, XTAL_I Pin 6 µA

IL

@ IOH = –4 mA (V
@ I

OH

@ IOL = 4 mA 0.4 V

< +3.0 V) 0.7 V

DD

≥ +3.0 V) 2.4 V

= –4 mA (+2.7 V ≤ V

DD

1

< +3.0 V) 2.2 V

DD

2.0 V

15 pF

DIGITAL TIMING (Guaranteed for V

t

CRYSTAL

F

CRYSTAL

t

PWL

t

PWH

F

LRI

t

RPWL

t

RS

t

BCLK

F

BCLK

t

BPWL

t

BPWH

t

WSI

t

WSO

t

LRSI

t

LRSO

t

DS

t

DH

t

DPD

t

DOH

Crystal Period 62.5 125 ns
Crystal Frequency (1/t
Crystal LO Pulsewidth 20 ns
Crystal HI Pulsewidth 20 ns
LR_I Frequency with 16 MHz Crystal

RESET LO Pulsewidth 125 ns
RESET Setup to Crystal Falling 15 ns

BCLK_I/O Period
BCLK_I/O Frequency (l/t
BCLK_I/O LO Pulsewidth 55 ns
BCLK_I/O HI Pulsewidth 55 ns
WCLK_I Setup to BCLK_I 15 ns
WCLK_O Setup to BCLK_O 40 ns
LR_I Setup to BCLK_I 15 ns
LR_O Setup to BCLK_O 55 ns
Data Setup to BCLK_I 0 ns
Data Hold from BCLK_I 35 ns
Data Propagation Delay from BCLK_O 90 ns
Data Output Hold from BCLK_O 15 ns

= +3.0 V to +5.0 V ± 10%) See Figures 26 through 28.

DD

) 16 MHz

CRYSTAL

1

1

1

)

BCLK

Min Max Units

10 56 kHz

120 ns

8.33 MHz

–2–

REV. A

AD1893

WARNING!

ESD SENSITIVE DEVICE

DIGITAL FILTER CHARACTERISTICS

1

Min Max Units

Passband Ripple (0 kHz to 20 kHz) 0.01 dB
Transition Band

2

4.1 kHz

Stopband Attenuation 110 dB

Group Delay (LR_I = 50 kHz) 700 3000 µs

POWER (F

= 48 kHz, F

SIN

= 44.1 kHz)

SOUT

Min Typ Max Units

Supplies

Voltage, V

DD

Operational Current, I
Operational Current, I
Power-Down Current, I
Power-Down Current, I

Dissipation

1

(VDD = +5.0 V) 30 40 mA

DD

(VDD = +3.0 V)

DD

(VDD = +5.0 V) 1.5 2.5 mA

DD

(VDD = +3.0 V)

DD

1

1

2.7 5.5 V

15 20 mA

0.5 1.0 mA

Operation (VDD = +5.0 V) 150 200 mW
Operation (V
Power-Down (V

= +3.0 V) 45 60 mW

DD

= +5.0 V) 7.5 12.5 mW

DD

Power-Down (VDD = +3.0 V) 1.5 3.0 mW

TEMPERATURE RANGE

Min Max Units

Specifications Guaranteed 0 +70 °C
Operational Guaranteed –40 +85 °C
Storage –60 +100 °C

ABSOLUTE MAXIMUM RATINGS

3

Min Max Units

to GND –0.3 7.0 V

V

DD

DC Input Voltage –0.3 V

+ 0.3 V

DD

Latch-Up Trigger Current –1000 +1000 mA

Soldering +300 °C

10 sec

NOTES

1

Guaranteed, Not Tested

2

Valid only when F

3

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Specifications subject to change without notice.

SOUT

≥ F

(i.e., upsampling), F

SIN

= 44.1 kHz.

SIN

ORDERING GUIDE

Model Temperature Range Package Descriptions Package Options

AD1893JN 0°C to +70°C Plastic DIP N-28
AD1893JST 0°C to +70°C LQFP ST-44

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1893 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A

–3–

AD1893

(continued from Page 1)

PRODUCT OVERVIEW (Continued)

limited to avoid alias distortion on the output signal. The
AD1893 dynamically alters the low-pass filter cutoff frequency
smoothly and slowly, so that real-time variations in the sample
rate ratio are possible without degradation of the audio quality.

The AD1893 has a pin selectable slow- or fast-settling mode.
This mode determines how quickly the ASRC adapts to a
change in either the input sample clock frequency (F
output sample clock frequency (F

). In the slow-settling

SOUT

mode, the control loop which computes the ratio between F
and F

settles in approximately 800 ms and begins to reject

SOUT

) or the

SIN

SIN

jitter above 3 Hz. The slow-settling mode offers the best signal
quality and the greatest jitter rejection. In the fast-settling mode,
the control loop settles in approximately 200 ms and begins to
reject jitter above 12 Hz. The fast-settling mode allows rapid,
real time sample rate changes to be tracked without error, at the
expense of some narrowband noise modulation products on the
output signal.

The AD1893 features short group delay processing. This feature
relates to the depth of the First-In, First-Out (FIFO) memory,
which buffers the input data samples before they are processed
by the FIR convolver. In the AD1893, the group delay is

approximately 700 µs. If the read and write pointers that

manage the FIFO cross (indicating underflow or overflow), the
AD1893 asserts the mute output (MUTE_O) pin HI for 128
output clock cycles. If MUTE_O is connected to the mute input
(MUTE_I) pin, as it normally should be, the serial output will
be muted (i.e., all bits zero) during this transient event.

The AD1893 includes an on-chip oscillator that only requires
the user provide an external crystal. By removing the need for
an external oscillator, the AD1893 lowers the total cost of own­ership to the end user. The AD1893 also includes a power­down mode, which is invoked with the PWRDWN pin.
Asserting this control signal HI will place the AD1893 into a
very low power dissipation in active and standby condition.

The AD1893 is fabricated in a 0.8 µm single poly, double metal

CMOS process and are packaged in a 0.6" wide 28-lead plastic
DIP and a 10 mm by 10 mm body size 44-lead LQFP. The
AD1893 operates from a +3 V to +5 V power supply over the

temperature range of 0°C to +70°C.

DEFINITIONS
Dynamic Range

The ratio of a near full-scale input signal to the integrated noise

in the passband (0 kHz to ≈20 kHz), expressed in decibels (dB).

Dynamic range is measured with a –60 dB input signal and
“60 dB” arithmetically added to the result.

Total Harmonic Distortion + Noise

Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the values
of the harmonics and noise to the rms value of a sinusoidal
input signal. It is usually expressed in percent (%) or decibels.

Interchannel Phase Deviation

Difference in input sampling times between stereo channels,
expressed as a phase difference in degrees between 1 kHz inputs.

Group Delay

Intuitively, the time interval required for a full-level input pulse
to appear at the converter’s output, at full level, expressed in
milliseconds (ms). More precisely, the derivative of radian
phase with respect to radian frequency at a given frequency.

Transport Delay

The time interval between when an impulse is applied to the
converter’s input and when the output starts to be affected by
this impulse, expressed in milliseconds (ms). Transport delay is
independent of frequency.

–4–

REV. A

DIP

AD1893

PIN CONFIGURATIONS

LQFP

XTAL_O

XTAL_I

DATA_I

BCLK_I

WCLK_I

BKPOL_I

MODE0_I

MODE1_I

RESET

AD1893 PIN LIST

LR_I

V

GND

NC

GND

1

2

3

4

5

6

7

DD

8

9

10

11

12

13

14

NC = NO CONNECT

FIFO

SERIAL IN

MULT

CLOCK

TRACKING

SERIAL OUT

ACCUM

COEF ROM

AD1893

28

27

26

25

24

23

22

21

20

19

18

17

16

15

SETSLW

PWRDWN

BCLK_O

WCLK_O

LR_O

DATA_O

V

DD

GND

NC

BKPOL_O

MODE0_O

MODE1_O

MUTE_O

MUTE_I

NC

1

BCLK_I

2

WCLK_I

3

LR_I

4

NC

5

V

6

DD

GND

7

NC

8

BKPOL_I

MODE0_I

NC = NO CONNECT

NC

9
10
11

NC

XTAL_I

DATA_I

44 39 38

43

NC

XTAL_O

404142

NC

AD1893

SERIAL IN

ACCUM

MULT

FIFO

CLOCK

TRACKING

NC

RESET

MODE1_I

NC

GND

NC

NC

SETSLW

36 35 34

37

SERIAL OUT

COEF ROM

NC

MUTE_I

PWRDWN

BCLK_O

21 2218 201912 13 15 16 1714

MUTE_O

MODE1_O

NC

NC

33
32
31
30
29
28
27

26
25
24
23

NC
WCLK_O

LR_O
DATA_O
NC
V

DD

GND
NC
BKPOL_O
MODE0_O
NC

Serial Input Interface

Pin Name DIP LQFP I/O Description

DATA_I 3 43 I Serial input, MSB first, containing two channels of 4 to 16 bits of twos-complement data per

channel.

BCLK_I 4 2 I Bit clock input for input data. Need not run continuously; may be gated or used in a burst fashion.
WCLK_I 5 3 I Word clock input for input data. This input is rising edge sensitive. (Not required in LR input

data clock triggered modes.)

LR_I 6 4 I Left/right clock input for input data. Must run continuously.

Serial Output Interface

Pin Name DIP LQFP I/O Description

DATA_O 23 30 O Serial output, MSB first, containing two channels of 4- to 24-bits of twos-complement data per

channel.

BCLK_O 26 35 I Bit clock input for output data. Need not run continuously; may be gated or used in a burst

fashion.

WCLK_O 25 32 I Word clock input for output data. This input is rising edge sensitive. (Not required in LR output

data clock triggered modes.)

LR_O 24 31 I Left/right clock input for output data. Must run continuously.

Input Control Signals

Pin Name DIP LQFP I/O Description

BKPOL_I 10 9 I Bit clock polarity. LO: Normal mode. Input data is sampled on rising edges of BCLK_I. HI:

Inverted mode. Input data is sampled on falling edges of BCLK_I.

MODE0_I 11 10 I Serial mode zero control for input port.

MODE1_I 12 13 I Serial mode one control for input port.

MODE0_I MODE1_I

0 0 Left-justified, no MSB delay, LR_I clock triggered.
0 1 Left-justified, MSB delay, LR_I clock triggered.
1 0 Right-justified, MSB delayed 16 bit clock periods from LR_I transition.

1 1 WCLK_I triggered, no MSB delay.

REV. A

–5–

AD1893

Output Control Signals

Pin Name DIP LQFP I/O Description

BKPOL_O 19 25 I Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK_O, changed

on falling. HI: Inverted mode. Output data is valid on falling edges of BCLK_O, changed on
rising.

MODE0_O 18 24 I Serial mode zero control for output port.

MODE1_O 17 21 I Serial mode one control for output port.

MODE0_O MODE1_O

0 0 Left-justified, no MSB delay, LR_O clock triggered.
0 1 Left-justified, MSB delay, LR_O clock triggered.
1 0 Right-justified, MSB delayed 16 bit clock periods from LR_O transition.

1 1 WCLK_O triggered, no MSB delay.

Miscellaneous

Pin Name DIP LQFP I/O Description

XTAL_O 1 40 O Crystal output. Connect to one side of nominal 16 MHz crystal for sampling frequencies

(FS word rates) from 8 kHz to 56 kHz.

XTAL_I 2 42 I Crystal input. Connect to other side of nominal 16 MHz crystal for sampling frequencies

(F

word rates) from 8 kHz to 56 kHz. Use this input to overdrive the on-chip oscillator

S

with an external clock source.

RESET 13 14 I Active LO reset. Set HI for normal chip operation.

MUTE_O 16 20 O Mute output. HI indicates that data is not currently valid due to read and write FIFO

memory pointer overlap. LO indicates normal operation.

MUTE_I 15 18 I Mute input. HI mutes the serial output to zeros (midscale). Normally connected to

MUTE_O. Reset LO for normal operation.

SETLSLW 28 38 I Settle slowly to changes in sample rates. HI: Slow-settling mode (≈800 ms). Less sensitive

to sample clock jitter. LO: Fast-settling mode (≈200 ms). Some narrow-band noise
modulation may result from jitter on the LR clocks. This signal may be asynchronous with

respect to the crystal frequency, and dynamically changed, but is normally pulled up or
pulled down on a static basis.

PWRDWN 27 36 I Power-down input. Set HI for inactive, low power dissipation state. Reset LO for normal

operation.

NC 9, 20 1, 5, 8, 11, No connect. Reserved. Do not connect.

12, 15, 17,
19, 22, 23,
26, 29, 33,
34, 37, 39,
41, 44

Power Supply Connections

Pin Name DIP LQFP I/O Description

V

DD

GND 8, 14, 21 7, 16, 27 I Digital ground. Pin 14 (DIP) and Pin 16 (LQFP) need not be decoupled.

7, 22 6, 28 I Positive digital voltage supply.

–6–

REV. A