Analog Devices AD1888 Datasheet

a

AC ’97 SoundMAX

AD1888

®

Codec

FEATURES
AC ’97 2.3 COMPATIBLE FEATURES
6 DAC Channels for 5.1 Surround
90 dB Dynamic Range
20-Bit PCM DACs
S/PDIF Output
Integrated Stereo Headphone Amplifiers
Phone, Aux, and Line-In
High Quality CD Input
Selectable MIC Input
Mono Output
External Amplifier Power-Down Control
Double Rate Audio (f

= 96 kHz)

S

Power Management Modes
48-Lead LQFP and 48-Lead LFCSP Packages

FUNCTIONAL BLOCK DIAGRAM

MIC1
MIC2

PHONE_IN

CD_L

CD_R
AUX_L
AUX_R

LINE_IN_L

LINE_IN_R

DIFF
AMP

G

ENHANCED FEATURES
Selectable Front and Rear MIC Inputs

with Preamp
Integrated PLL for System Clocking
Crystal-Free Operation
Variable Sample Rate 7 kHz to 96 kHz
Jack Sense (Auto Topology Switching)
Software Controlled VREF_OUT for MIC Bias
Software Enabled Outputs for Jack Sharing
Auto Down-Mix and Channel Spreading Modes

AD1888

PLL

16-BIT ⌺-⌬

G

M

ADC

16-BIT ⌺-⌬

G

M

ADC

ADC

SLOT

LOGIC

XTAL_IN

XTAL_OUT

ID0

ID1

GA

GA

GA

M

M

GA

M

M

GA

M

M M M M M M

HP_OUT_L

HP_OUT_R

M

AMONO_OUT

MZ

ALINE_OUT_L

MZ

ALINE_OUT_R

MZ

ACENTER_OUT

MZ

ALFE_OUT

HP

M

ASURR_L/

HP

M

ASURR_R/

GA

M

G = GAIN
A = ATTENUATION
M = MUTE
Z = HIGH-Z

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

RESET

AC '97

CONTROL

REGISTERS

GA

GA

M

GA

M

M

20-BIT ⌺-⌬

GA

M

M

M

M

M

M

DAC

20-BIT ⌺-⌬

GA

DAC

20-BIT ⌺-⌬

GA

DAC

20-BIT ⌺-⌬

GA

DAC

20-BIT ⌺-⌬

GA

DAC

20-BIT ⌺-⌬

GA

DAC

DAC

SLOT

LOGIC

AC '97 INTERFACE

SPDIF

TX

EAPD

JACK
SENSE
LOGIC

VOLTAGE

REFERENCE

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

SPDIF_OUT

EAPD

JS0

JS1

V

REF

V

REFOUT

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD1888–SPECIFICATIONS

STANDARD TEST CONDITIONS, UNLESS OTHERWISE
NOTED

Temperature 25°C
Digital Supply (DV
Analog Supply (AV
Sample Rate (f

) 3.3 V

DD

) 5.0 V

DD

) 48 kHz

S

Input Signal 1 kHz
Analog Output Pass Band 20 Hz to 20 kHz

DAC Test Conditions

Calibrated
–3 dB Attenuation Relative to Full Scale
0 dB Input
10 kΩ Output Load LINE_OUT, MONO_OUT,

CENTER_OUT, and LFE_OUT

32 Ω Output Load (HP_OUT)

ADC Test Conditions

Calibrated
0 dB Gain
Input –3.0 dB Relative to Full Scale

Parameter Min Typ Max Unit

ANALOG INPUT

Input Voltage (RMS Values Assume Sine Wave Input)

LINE_IN, CD, AUX, PHONE_IN 1 V rms

2.83 V p-p

MIC_IN with 30 dB Preamp 0.032 V rms

0.089 V p-p

MIC_IN with 20 dB Preamp 0.1 V rms

0.283 V p-p

MIC_IN with 10 dB Preamp 0.316 V rms

0.894 V p-p

MIC_IN with 0 dB Gain 1 V rms

2.83 V p-p

Input Impedance* 20 kΩ
Input Capacitance* 5 7.5 pF

MASTER VOLUME

Step Size (Line Out, Mono Out, Surround Out, Center, LFE) 1.5 dB
Output Attenuation Range Span* 46.5 dB
Mute Attenuation of 0 dB Fundamental* 80 dB

PROGRAMMABLE GAIN AMPLIFIER—ADC

Step Size (0 dB to 22.5 dB) 1.5 dB
PGA Gain Range Span 22.5 dB

ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS

Signal-to-Noise Ratio (SNR)

CD to LINE_OUT 90 dB
LINE, AUX, or PHONE to LINE_OUT* 90 dB
MIC1 or MIC2 (Note: MIC Gain of 0 dB) to LINE_OUT* 90 dB

Step Size All Mixer Inputs 1.5 dB
Input Gain/Attenuation Range: All Mixer Inputs 46.5 dB

DIGITAL DECIMATION AND INTERPOLATION FILTERS*

Pass Band 0 0.4  f

S

Hz
Pass-Band Ripple ± 0.09 dB
Transition Band 0.4  f
Stop Band 0.6  f

S

S

0.6  f

S

 Hz

Hz

Stop-Band Rejection –74 dB
Group Delay 16/f

S

sec
Group Delay Variation over Pass Band 0 µs

REV. 0–2–

AD1888

Parameter Min Typ Max Unit

ANALOG-TO-DIGITAL CONVERTERS

Resolution 16 Bits
Total Harmonic Distortion (THD) AV
Dynamic Range (–60 dB Input THD + N Referenced to FS, A-Weighted)

= 5.0 V 80 dB

AV

DD

Signal-to-Intermodulation Distortion* (CCIF Method) 84 dB
ADC Crosstalk*

Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) –85 dB

LINE_IN to Other –85 dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ± 10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ± 0.5 dB
ADC Offset Error* (0 dB Gain, HPF On) ± 10 mV

DIGITAL-TO-ANALOG CONVERTERS

Resolution 20 Bits
Total Harmonic Distortion (THD), LINE_OUT, AVDD = 5.0 V –80 dB
Total Harmonic Distortion (THD), HP_OUT, AV
Total Harmonic Distortion (THD), CENTER/LFE, AV
Dynamic Range (–60 dB Input THD + N Referenced to FS A-Weighted)

= 5.0 V, All Outputs 90 dB

AV

DD

Signal-to-Intermodulation Distortion* (CCIF Method) 88 dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ± 10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ± 0.7 dB
DAC Crosstalk (Input L, Zero R, Read LINE_OUT_R; Input R, –80 dB

Zero L, Read LINE_OUT_L, 10 kΩ Load)*
Total Audible Out-of-Band Energy* (Measured from 0.6  fS to 20 kHz) –40 dB

ANALOG OUTPUT

Full-Scale Output Voltage; LINE_OUT/MONO_OUT, CENTER_OUT,

LFE_OUT 1V rms

Output Impedance* 300 Ω
External Load Impedance*

(LINE_OUT, CENTER_OUT/LFE_OUT,

MONO_OUT) 10 kΩ
Output Capacitance* 15 pF
External Load Capacitance* 100 pF
Full-Scale Output Voltage; HP_OUT (0 dB Gain) 1 V rms
External Load Impedance*; HP_OUT 32 Ω
V

REF

(V

V

REF_OUT

V

REF_OUT

V

REF_OUT

= 0) 2.25 V

REFH

(V

= 1) 3.65 V

REFH

Current Drive 5mA

Mute Click (Muted Output Minus Unmuted Midscale DAC Output) ± 5mV

STATIC DIGITAL SPECIFICATIONS

High Level Input Voltage (VIH): Digital Inputs 0.65  DV
Low Level Input Voltage (V
High Level Output Voltage (V
Low Level Output Voltage (V

) 0.35  DV

IL

), IOH = 2 mA 0.9  DV

OH

), IOL = 2 mA 0.1  DV

OL

Input Leakage Current –10 +10 µA
Output Leakage Current –10 +10 µA

POWER SUPPLY

Power Supply Range, Analog (AVDD)4.755.25 V
Power Supply Range, Digital (DV
Power Dissipation 5 V/3.3 V 563 mW
Analog Supply Current 5 V (AV

DD

Digital Supply Current 3.3 V (DV
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*

(At Both Analog and Digital Supply Pins, Both ADCs and DACs) –40 dB

*Guaranteed but not tested.

Specifications subject to change without notice.

= 5.0 V –78 dB

DD

= 5.0 V –70 dB

DD

= 5.0 V –80 dB

DD

2.83 V p-p

2.05 2.25 2.45 V

DD

V
V
V
V

DD

DD

DD

)3.153.45 V

DD

)70mA

)53mA

DD

REV. 0

–3–

AD1888

Parameter PR[K:I]

POWER-DOWN STATES

2

1

PR[6:0]

1

DVDD Typ AVDD Typ Unit

Fully Active 000 000 0000 53 70 mA
ADC 000 000 0001 44 66 mA
FRONT DAC 000 000 0010 46 61 mA
SURROUND DAC 010 000 0000 46 61 mA
CENTER/LFE DAC 101 000 0000 46 61 mA
ADC + ALL DACs 111 000 0011 12 33 mA
Mixer 000 000 0100 52 44 mA
ADC + Mixer 000 000 0101 45 39 mA
ALL DACs + Mixer 111 000 0110 31 14 mA
ADC + ALL DACs + Mixer 111 000 0111 12 8 mA
Standby 111 011 1111 0 0 mA
Headphone Standby 000 100 0000 52 65 mA

NOTES

1

PR bits are controlled in Reg. 2Ah and 26h

2

Values presented with V

Specifications subject to change without notice.

REFOUT

loaded.

Parameter Min Typ Max Unit

CLOCK SPECIFICATIONS*

Input Clock Frequency (XTAL Mode or Clock Oscillator) 24.576 MHz
Input Clock Frequency (Reference Clock Mode) 14.31818 MHz
Input Clock Frequency (USB Clock Mode) 48.000 MHz
Recommended Clock Duty Cycle 40 50 60 %

*Guaranteed but not tested.
Specifications subject to change without notice.

TIMING PARAMETERS

(Guaranteed over Operating Temperature Range)

Parameter Symbol Min Typ Max Unit

RESET Active Low Pulse Width t
RESET Inactive to BIT_CLK Startup Delay t
SYNC Active High Pulse Width t
SYNC Low Pulse Width t
SYNC Inactive to BIT_CLK Startup Delay t

RST_LOW

RST2CLK

SYNC_HIGH

SYNC_LOW

SYNC2CLK

162.8 400,000 ns

162.8 ns

1.0 µs

1.3 µs

19.5 µs

BIT_CLK Frequency 12.288 MHz
BIT_CLK Frequency Accuracy 1.0 ppm
BIT_CLK Period t
BIT_CLK Output Jitter

1, 2

BIT_CLK High Pulse Width t
BIT_CLK Low Pulse Width t

CLK_PERIOD

CLK_HIGH

CLK_LOW

40 41.7 ns

39.7 41.4 ns

81.4 ns
750 ps

SYNC Frequency 48.0 kHz
SYNC Period t
Setup to Falling Edge of BIT_CLK t
Hold from Falling Edge of BIT_CLK t
BIT_CLK Rise Time t
BIT_CLK Fall Time t
SYNC Rise Time t
SYNC Fall Time t
SDATA_IN Rise Time t
SDATA_IN Fall Time t
SDATA_OUT Rise Time t
SDATA_OUT Fall Time t
End of Slot 2 to BIT_CLK, SDATA_IN Low t
Setup to RESET Inactive (SYNC, SDATA_OUT) t
Rising Edge of RESET to Hi-Z Delay t

SYNC_PERIOD

SETUP

HOLD

RISECLK

FALLCLK

RISESYNC

FALLSYNC

RISEDIN

FALLDIN

RISEDOUT

FALLDOUT

S2_PDOWN

SETUP2RST

OFF

4ns
3ns
246ns
246ns
246ns
246ns
246ns
246ns
246ns
246ns
0 1.0 µs
15 ns

20.8 µs

25 ns
Propagation Delay 15 ns
RESET Rise Time 50 ns
Output Valid Delay from BIT_CLK Rising 15 ns

NOTES

1

Guaranteed but not tested.

2

Output jitter directly dependent on crystal input jitter.

Specifications subject to change without notice.

REV. 0–4–

t

BIT_CLK

SDATA_OUT

SDATA_IN

SYNC

t

CO

t

SETUP

V

IH

V

IL

V

OH

V

OL

t

HOLD

t

TRI2ACTV

t

TRI2ACTV

RST2CLK

RESET

BIT_CLK

SDATA_IN

t

RST_LOW

Figure 1. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal)

AD1888

BIT_CLK

SYNC

BIT_CLK

SYNC

BIT_CLK

t

CLK_LOW

t

CLK_HIGH

t

CLK_PERIOD

t

SYNC_LOW

t

SYNC_HIGH

t

SYNC_PERIOD

Figure 3. Clock Timing

t

RISECLK

t

SYNC_HIGH

t

SYNC2CLK

Figure 2. Warm Reset Timing

Figure 5. AC-Link Low Power Mode Timing

t

FALLCLK

SLOT 1 SLOT 2

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

WRITE TO

0x26

BIT_CLK NOT TO SCALE

DATA

PR4

t

S2_PDOWN

REV. 0

SYNC

t

RISESYNC

SDATA_IN

t

RISEDIN

SDATA_OUT

t

RISEDOUT

Figure 4. Signal Rise and Fall Times

t

FALLSYNC

t

FALLDIN

t

FALLDOUT

–5–

Figure 6. AC-Link Low Power Mode Timing

RESET

SDATA_OUT

SDATA_IN, BIT_CLK,

EAPD, SPDIF_OUT

AND DIGITAL I/O

t

SETUP2RST

t

OFF

Hi-Z

Figure 7. ATE Test Mode

AD1888

ABSOLUTE MAXIMUM RATINGS*

Parameter Min Max Unit

Power Supplies
Digital (DVDD) –0.3 +3.6 V
Analog (AV

) –0.3 +6.0 V

DD

Input Current (Except Supply Pins) ± 10.0 mA
Analog Input Voltage (Signal Pins) –0.3 AV
Digital Input Voltage (Signal Pins) –0.3 DV

+ 0.3 V

DD

+ 0.3 V

DD

Ambient Temperature (Operating) 0 +70 °C
Storage Temperature –65 +150 °C

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD1888JST 0°C to 70°C 48-Lead LQFP, Tray Version ST-48
AD1888JST-REEL 0°C to 70°C 48-Lead LQFP, Reel Version ST-48
AD1888JSTZ* 0°C to 70°C 48-Lead LQFP, Tray Version ST-48
AD1888JSTZ-REEL* 0°C to 70°C 48-Lead LQFP, Reel Version ST-48
AD1888JCP 0°C to 70°C 48-Lead LFCSP, Tray Version CP-48
AD1888JCP-REEL 0°C to 70°C 48-Lead LFCSP, Reel Version CP-48

*Z = Lead Free

ENVIRONMENTAL CONDITIONS*

Ambient Temperature Rating

TCASE = Case Temperature in °C
PD = Power Dissipation in W

= Thermal Resistance (Junction-to-Ambient)



JA

= Thermal Resistance (Junction-to-Case)



JC

Package θ

JA

θ

JC

LQFP 50.1°C/W 17.8°C/W
LFCSP 50°C/W 25.88°C/W

*All measurements per EIA/JESD51 with 2S2P

test board per EIA/JESD51-7.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1888 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0–6–

PIN CONFIGURATION

48-Lead LQFP

AD1888

DVDD1

XTL_IN

XTL_OUT

DV

1

SS

SDATA_OUT

BIT_CLK

2

DV

SS

SDATA_IN

2

DV

DD

SYNC

RESET

NC

NC = NO CONNECT

3

3

SS

DD

SPDIF

EAPD

ID1

48 47 46 45 444342 41 40 39 38 37

1

2

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

AUX_L

AUX_R

PHONE_IN

ID0

AV

AD1888

TOP VIEW

(Not to Scale)

JS1

JS0

AV

NC

SURR_OUT_R/HP_OUT_R

CD_L

CD_R

CD_GND_REF

2

2

SS

DD

SURR_OUT_L/HP_OUT_L

AV

AV

MIC1

MIC2

MONO_OUT

LINE_IN_L

LINE_IN_R

36

35

34

33

32

31

30

29

28

27

26

25

LINE_OUT_R (FRONT_R)

LINE_OUT_L (FRONT_L)

AV

4

DD

AV

4

SS

LFE_OUT

CENTER_OUT

AFILT2

AFILT1

V

REFOUT

V

REF

AVSS1

AV

1

DD

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic I/O Function

DIGITAL INPUT/OUTPUT

2 XTL_IN I Crystal Input (24.576 MHz) or External Clock In (24.576 MHz,

14.31818 MHz, or 48000 MHz).
3 XTL_OUT O Crystal Output.
5 SDATA_OUT I AC-Link Serial Data Output. AD1888 input stream.
6 BIT_CLK O/I AC-Link Bit Clock. 12.288 MHz serial data clock. (Input pin for

Secondary mode only.)
8 SDATA_IN O AC-Link Serial Data Input. AD1888 output stream.
10 SYNC I AC-Link Frame Sync.
11 RESET I AC-Link Reset. AD1888 master H/W reset.
48 SPDIF O SPDIF Output.

CHIP SELECTS/CLOCK STRAPPING
45 ID0 IChip Select Input 0 (Active Low).

46 ID1 IChip Select Input 1 (Active Low).

JACK SENSE AND EAPD

47 EAPD O EAPD Output.
17 JS0 I Jack Sense 0 Input.
16 JS1 I Jack Sense 1 Input.

REV. 0

–7–

AD1888

Pin Number Mnemonic I/O Function

ANALOG INPUT/OUTPUT

13 PHONE_IN I Monaural Line-Level Input.
14 AUX_L I Auxiliary Input, Left Channel.
15 AUX_R I Auxiliary Input, Right Channel.
18 CD_L I CD Audio Left Channel.
19 CD_GND_REF I CD Audio Analog Ground Reference for Differential CD Input.
20 CD_ R I CD Audio Right Channel.
21 MIC1 I Rear Panel MIC Input.
22 MIC2 I Front Panel MIC Input.
23 LINE_IN_L I Line-In Left Channel.
24 LINE_IN_R I Line-In Right Channel.
31 CENTER_OUT O Center Channel Output.
32 LFE_OUT O Low Frequency Enhanced Output.
35 LINE_OUT_L O Line Out (Front) Left Channel.
36 LINE_OUT_R O Line Out (Front) Right Channel.
37 MONO_OUT O Monaural Output to Telephone Subsystem Speakerphone.
39 SURR_OUT_L/HP_OUT_L O Surround Front Headphone Left Channel Output.
41 SURR_OUT_R/HP_OUT_R O Surround Front Headphone Right Channel Output.

FILTER/REFERENCE

27 V
28 V

REF

REFOUT

29 AFILT1 O Antialiasing Filter Capacitor—ADC Right Channel.
30 AFILT2 O Antialiasing Filter Capacitor—ADC Left Channel.

POWER AND GROUND SIGNALS
1DV
4DV
7DV
9DV
25 AV
26 AV
33 AV
34 AV
38 AV
40 AV
43 AV

1IDigital VDD 3.3 V.

DD

1IDigital GND.

SS

2IDigital GND.

SS

2IDigital V

DD

1IAnalog V

DD

1IAnalog GND.

SS

4IAnalog GND.

SS

4IAnalog V

DD

2IAnalog V

DD

2IAnalog GND.

SS

3IAnalog V

DD

44 AVSS3IAnalog GND.

NO CONNECTS
12 NC No Connect.
42 NC No Connect.

OVoltage Reference Filter.
OVoltage Reference Output 5 mA Drive (intended for MIC bias).

3.3 V.

DD

5.0 V.

DD

5.0 V.

DD

5.0 V.

DD

5.0 V.

DD

REV. 0–8–

AD1888

Indexed Control Registers

Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0090h

02h Master Volume MM X LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 MMRM* X RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h

04h Headphone HPM X LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 HPRM* X RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h

Volume

06h Mono Volume MVM X X X X X X X X X MV5 MV4 MV2 MV2 MV1 MV0 8000h

0Ch Phone Volume PHM X X X X X X X X X X PHV4 PHV3 PHV2 PHV1 PHV0 8008h

0Eh MIC Volume MCM X X X X X X X X M20 X MCV4 MCV3 MCV2 MCV1 MCV0 8008h

10h Line-In Volume LVM X X LLV4 LLV3 LLV2 LLV1 LLV0 LVRM* XXRLV4 RLV3 RLV2 RLV1 RLV0 8808h

12h CD Volume CVM X X LCV4 LCV3 LCV2 LCV1 LCV0 CDRM* XXRCV4 RCV3 RCV2 RCV1 RCV0 8808h

16h AUX Volume AVM X X LAV4 LAV3 LAV2 LAV1 LAV0 AVRM* XXRAV4 RAV3 RAV2 RAV1 RAV0 8808h

18h PCM Out Vol OM X X LOV4 LOV3 LOV2 LOV1 LOV0 OMRM* XXROV4 ROV3 ROV2 ROV1 ROV0 8808h

1Ah Record Select X X X X X LS2 LS1 LS0 X X XXXRS2 RS1 RS0 0000h

1Ch Record Gain IM X X X LIM3 LIM2 LIM1 LIM0 IMRM* X XXRIM3 RIM2 RIM1 RIM0 8000h

20h General-Purpose X X X X DRSS1 DRSS0 X MS LPBK X XXXXXX 0000h

24h Audio Int. I4 X X X I0 X X X X X X X PG3 PG2 PG1 PG0 xxxxh

and Paging

26h Power-Down EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC NA

Ctrl/Stat

28h Ext’d Audio ID ID1 ID0 X X REV1 REV0 AMAP LDAC SDAC CDAC DSA1 DSA0 X SPDIF DRA VRA x3C7h

2Ah Ext’d Audio VFORCE X PRK PRJ PRI SPCV X ELDAC ESDAC ECDAC SP SA 1 SPSA0 X ESPDIF EDRA EVRA 0xx0h

Stat/Ctrl

2Ch PCM Front SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 BB80h

DAC Rate

2Eh PCM Surr SRS15 SRS14 SRS13 SRS12 SRS11 SRS10 SRS9 SRS8 SRS7 SRS6 SRS5 SRS4 SRS3 SRS2 SRS1 SRS0 BB80h

DAC Rate

30h PCM C/LFE SRCL15 SRCL14 SRCL13 SRCL12 SRCL11 SRCL10 SRCL9 SRCL8 SRCL7 SRCL6 SRCL5 SRCL4 SRCL3 SRCL2 SRCL1 SRCL0 BB80h

DAC Rate

32h PCM L/R SRA15 SRA14 SRA13 SRA13 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 BB80h

ADC Rate

36h Center/LFE LM X LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 CM X CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 8080h

Volume

38h Surround Volume MUTE_L X LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 MUTE_R X RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 8080h

3Ah SPDIF Control V X SPSR1 SPSR0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUD PRO 2000h

72h JACK SENSE JS1 JS1 JS0 JS JS JS X X JS1 JS0 JS1 JS0 JS1 JS0 JS1 JS0 0000h

74h Serial SLOT 16 REGM2 REGM1 REGM0 REGM3 DRF X CHEN X LBKS1 LBKS0 INTS X SPAL SPDZ SPLNK 1001h

Configuration

76h Misc Control DACZ

Bits

7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 4144h

7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5368h

NOTES
All registers not shown and bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written to.
Zeros should be written to reserved bits.
*For AC ’97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, Bit D7 has no effect.

SPRD DMX DMX MT2 MT1 MT0 TMR TMR MD MD ST ST INT INT

AC97NC

MSPLT LODIS CLDIS HPSEL DMIX1 DMIX0 SPRD X LOSEL S RU

VREFH

VREFD

MBG1 MBG0 0000h

REV. 0

–9–

AD1888

Reset Register (Index 00h)

Reg
No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0090h

NOTES
All registers not shown and bits containing an X are assumed to be reserved.
Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration).
Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement.

ID[9:0] Identify Capability. The ID decodes the capabilities of AD1888 based on the following:

Bit = 1 Function AD1888

ID0 Dedicated Mic PCM In Channel 0
ID1 Modem Line Codec Support 0
ID2 Bass and Treble Control 0
ID3 Simulated Stereo (Mono to Stereo) 0
ID4 Headphone Out Support 1
ID5 Loudness (Bass Boost) Support 0
ID6 18-Bit DAC Resolution 0
ID7 20-Bit DAC Resolution 1
ID8 18-Bit ADC Resolution 0
ID9 20-Bit ADC Resolution 0

SE[4:0] Stereo Enhancement. The AD1888 does not provide hardware 3D stereo enhancement. (All bits are zeros.)

Master Volume Register (Index 02h)

Reg
No. Name D15 D14 D131D12 D11 D10 D9 D8 D7 D6 D51D4 D3 D2 D1 D0 Default

02h Master MM X LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 MMRM2XRMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h

Volume

NOTES

1

Refer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and mute bit. Each volume subregister contains five bits,
generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 bits are
set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1.

2

For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved.

Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality:

For AC97NC = 0, the register controls the Line_out output Attenuators only.
For AC97NC = 1, the register controls the Line_out, Center, and LFE output Attenuators.

RMV[5:0] Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from

0 dB to a maximum attenuation of 46.5 dB.

MMRM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the MM bit. Otherwise this bit will always read 0 and will have no effect when set to 1.

LMV[5:0] Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB

to a maximum attenuation of 46.5 dB.

MM Headphones Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the

MSPLT bit in Register 76h is set to 1.

REV. 0–10–