Analog Devices AD1877 Datasheet

Single-Supply

a

FEATURES
Single 5 V Power Supply
Single-Ended Dual-Channel Analog Inputs
92 dB (Typ) Dynamic Range
90 dB (Typ) S/(THD+N)

0.006 dB Decimator Passband Ripple
Fourth-Order, 64-Times Oversampling ⌺⌬ Modulator
Three-Stage, Linear-Phase Decimator
256 ⴛ F
Less than 100 ␮W (Typ) Power-Down Mode
Input Overrange Indication
On-Chip Voltage Reference
Flexible Serial Output Interface
28-Lead SOIC Package

APPLICATIONS
Consumer Digital Audio Receivers
Digital Audio Recorders, Including Portables

Multimedia and Consumer Electronic Equipment
Sampling Music Synthesizers
Digital Karaoke Systems

PRODUCT OVERVIEW

The AD1877 is a stereo, 16-bit oversampling ADC based on
Sigma Delta (∑∆) technology intended primarily for digital
audio bandwidth applications requiring a single 5 V power supply.
Each single-ended channel consists of a fourth-order one-bit
noise shaping modulator and a digital decimation filter. An on­chip voltage reference, stable over temperature and time, defines
the full-scale range for both channels. Digital output data from
both channels are time-multiplexed to a single, flexible serial
interface. The AD1877 accepts a 256 × F
clock (F
port “master” and “slave” modes. In slave mode, all clocks must
be externally derived from a common source.

Input signals are sampled at 64 × F
switched-capacitors, eliminating external sample-and-hold ampli­fiers and minimizing the requirements for antialias filtering at the
input. With simplified antialiasing, linear phase can be preserved
across the passband. The on-chip single-ended to differential signal
converters save the board designer from having to provide them
externally. The AD1877’s internal differential architecture provides
increased dynamic range and excellent power supply rejection
characteristics. The AD1877’s proprietary fourth-order differen­tial switched-capacitor ∑∆ modulator architecture shapes the

*Protected by U.S. Patent Numbers 5055843, 5126653, and others pend ing.

or 384 ⴛ FS Input Clock

S

CD-R, DCC, MD and DAT

or a 384 × FS input

is the sampling frequency) and operates in both serial

S

S

onto internally buffered

S

16-Bit ⌺⌬ Stereo ADC

AD1877*

FUNCTIONAL BLOCK DIAGRAM

LRCK

WCLK

BCLK

DV

DD

DGND1

RDEDGE

S/M

384/256

AV

VINL

CAPL1

CAPL2

AGNDL

V

REF

1

2

3

THREE-STAGE FIR

4

1

5

6

7

8

9

DD

10

11

12

DIFFERENTIAL INPUT

13

L

14

SERIAL OUTPUT

DECIMATION

FILTER

D
A
C

SINGLE TO

CONVERTER

INTERFACE

D
A
C

VOLTAGE

REFERENCE

THREE-STAGE FIR

D
A
C

DIFFERENTIAL INPUT

CONVERTER

DIVIDER

DECIMATION

FILTER

SINGLE TO

AD1877

CLOCK

D
A
C

one-bit comparator’s quantization noise out of the audio pass­band. The high order of the modulator randomizes the modulator
output, reducing idle tones in the AD1877 to very low levels.
Because its modulator is single-bit, AD1877 is inherently
monotonic and has no mechanism for producing differential
linearity errors.

The input section of the AD1877 uses autocalibration to correct
any dc offset voltage present in the circuit, provided that the inputs
are ac coupled. The single-ended dc input voltage can swing
between 0.7 V and 3.8 V typically. The AD1877 antialias input
circuit requires four external 470 pF NPO ceramic chip filter
capacitors, two for each channel. No active electronics are
needed. Decoupling capacitors for the supply and reference pins
are also required.

The dual digital decimation filters are triple-stage, finite impulse
response filters for effectively removing the modulator’s high
frequency quantization noise and reducing the 64 × F
output data rate to an F

word rate. They provide linear phase

S

and a narrow transition band that properly digitizes 20 kHz signals
at a 44.1 kHz sampling frequency. Passband ripple is less than

0.006 dB, and stopband attenuation exceeds 90 dB.

(Continued on Page 6)

CLKIN

28

TAG

27

SOUT

26

DV

25

DD

24

DGND2

23

RESET

22

MSBDLY

21

RLJUST

20

AGND

VINR

19

CAPR1

18

CAPR2

17

AGNDR

16

V

15

REF

single-bit

S

2

R

REV. A

I

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD1877–SPECIFICATIONS

TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltages 5.0 V
Ambient Temperature 25 °C
Input Clock (F
Input Signal 991.768 Hz

Measurement Bandwidth 23.2 Hz to 19.998 kHz
Load Capacitance on Digital Outputs 50 pF
Input Voltage HI (V
Input Voltage LO (V
Master Mode, Data I
Device Under Test (DUT) bypassed and decoupled as shown in Figure 3.
DUT is antialiased and ac coupled as shown in Figure 2. DUT is calibrated.
Values in bold typeface are tested, all others are guaranteed but not tested.

ANALOG PERFORMANCE

Resolution 16 Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)

Without A-Weight Filter 87 92 dB

With A-Weight Filter 90 94 dB
Signal to (THD + Noise) 86.5 90 dB
Signal to THD 92 94 dB
Analog Inputs

Single-Ended Input Range (± Full Scale)* V

Input Impedance at Each Input Pin 32 kΩ
V

REF

DC Accuracy

Gain Error ±0.5 ⴞ2.5 %

Interchannel Gain Mismatch 0.01 dB

Gain Drift 115 ppm/°C

Midscale Offset Error (After Calibration) ± 3 ⴞ20 LSBs

Midscale Drift 15 ppm/°C
Crosstalk (EIAJ Method) –90 –99 dB

*VIN p-p = V

REF

) [256 × FS] 12.288 MHz

CLKIN

–0.5 dB Full Scale

) 2.4 V

IH

) 0.8 V

IL

2

S-Justified (Refer to Figure 14).

× 1.333.

Min Typ Max Unit

– 1.55 V

REF

REF

V

+ 1.55 V

REF

2.05 2.25 2.55 V

–2–

REV. A

AD1877

DIGITAL I/O

Min Typ Max Unit

Input Voltage HI (V
Input Voltage LO (V
Input Leakage (I
Input Leakage (I
Output Voltage HI (V
Output Voltage LO (V
Input Capacitance 15 pF

DIGITAL TIMING (Guaranteed over 0°C to 70°C, DVDD = AVDD = 5 V ± 5%. Refer to Figures 17–19.)

t

CLKIN

F

CLKIN

t

CPWL

t

CPWH

t

RPWL

t

BPWL

t

BPWH

t

DLYCKB

t

DLYBLR

t

DLYBWR

t

DLYBWF

t

DLYDT

t

SETLRBS

t

DLYLRDT

t

SETWBS

t

DLYBDT

) 2.4 V

IH

) 0.8 V

IL

@ VIH = 5 V) 10 µA

IH

@ VIL = 0 V) 10 µA

IL

@ IOH = –2 mA) 2.4 V

OH

@ IOL = 2 mA) 0.4 V

OL

Min Typ Max Unit

CLKIN Period 48 81 780 ns
CLKIN Frequency (1/t

) 1.28 12.288 20.48 MHz

CLKIN

CLKIN LO Pulsewidth 15 ns
CLKIN HI Pulsewidth 15 ns
RESET LO Pulsewidth 50 ns
BCLK LO Pulsewidth 15 ns
BCLK HI Pulsewidth 15 ns
CLKIN Rise to BCLK Xmit (Master Mode) 15 ns
BCLK Xmit to LRCK Transition (Master Mode) 15 ns
BCLK Xmit to WCLK Rise 10 ns
BCLK Xmit to WCLK Fall 10 ns
BCLK Xmit to Data/Tag Valid (Master Mode) 10 ns
LRCK Setup to BCLK Sample (Slave Mode) 10 ns
LRCK Transition to Data/TAG Valid (Slave Mode)
No MSB Delay Mode (for MSB Only) 40 ns
WCLK Setup to BCLK Sample (Slave Mode)
Data Position Controlled by WCLK Input Mode 10 ns
BCLK Xmit to DATA/TAG Valid (Slave Mode)
All Bits Except MSB in No MSB Delay Mode
All Bits in MSB Delay Mode 10 ns

POWER

Min Typ Max Unit

Supplies

Voltage, Analog and Digital 4.75 5 5.25 V
Analog Current 35 43 mA
Analog Current—Power Down (CLKIN Running) 6 26 µA
Digital Current 16 20 mA
Digital Current—Power Down (CLKIN Running) 13 39 µA

Dissipation

Operation—Both Supplies 255 315 mW
Operation—Analog Supply 175 215 mW
Operation—Digital Supply 80 100 mW
Power Down—Both Supplies (CLKIN Running) 95 325 µW
Power Down—Both Supplies (CLKIN Not Running) 5 µW
Power Supply Rejection (See TPC 5)

1 kHz 300 mV p-p Signal at Analog Supply Pins 76 dB
20 kHz 300 mV p-p Signal at Analog Supply Pins 71 dB
Stopband (≥0.55 × FS)—any 300 mV p-p Signal 80 dB

REV. A

–3–

AD1877

WARNING!

ESD SENSITIVE DEVICE

TEMPERATURE RANGE

Min Typ Max Unit

Specifications Guaranteed 25 °C
Functionality Guaranteed 0 70 °C
Storage –60 +100 °C

DIGITAL FILTER CHARACTERISTICS

Min Typ Max Unit

Decimation Factor 64
Passband Ripple 0.006 dB
Stopband
48 kHz F

44.1 kHz F

32 kHz F

Other F

Group Delay 36/F
Group Delay Variation 0 µs

NOTES

1

Stopband repeats itself at multiples of 64 × FS, where FS is the output word rate. Thus the digital filter will attenuate to 0 dB across the frequency spectrum except
for a range ± 0.55 × FS wide at multiples of 64 × FS.

Specifications subject to change without notice.

1

Attenuation 90 dB

(at Recommended Crystal Frequencies)

S

Passband 0 21.6 kHz

Stopband 26.4 kHz

(at Recommended Crystal Frequencies)

S

Passband 0 20 kHz

Stopband 24.25 kHz

(at Recommended Crystal Frequencies)

S

Passband 0 14.4 kHz

Stopband 17.6 kHz

S

Passband 0 0.45 F

Stopband 0.55 F

S

S

S

s

ABSOLUTE MAXIMUM RATINGS

Min Typ Max Unit

1 to DGND1 and DVDD2 to DGND2 0 6 V

DV

DD

AV

to AGND/AGNDL/AGNDR 0 6 V

DD

Digital Inputs DGND – 0.3 DV
Analog Inputs AGND – 0.3 AV

+ 0.3 V

DD

+ 0.3 V

DD

AGND to DGND –0.3 +0.3 V
Reference Voltage Indefinite Short Circuit to Ground
Soldering (10 sec) 300 °C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1877 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Package Package

Model Temperature Description Option

AD1877JR 0°C to 70°C SOIC R-28

–4–

REV. A

AD1877

PIN FUNCTION DESCRIPTIONS

Input/ Pin

Pin Output Name Description

1 I/O LRCK Left/Right Clock
2 I/O WCLK Word Clock
3 I/O BCLK Bit Clock
4I DV

1 5 V Digital Supply

DD

5 I DGND1 Digital Ground
6 I RDEDGE Read Edge Polarity Select
7I S/M Slave/Master Select
8 I 384/256 Clock Mode
9I AV
10 I V

DD

L Left Channel Input

IN

5 V Analog Supply

11 O CAPL1 Left External Filter Capacitor 1
12 O CAPL2 Left External Filter Capacitor 2
13 I AGNDL Left Analog Ground
14 O V
15 O V

L Left Reference Voltage Output

REF

R Right Reference Voltage Output

REF

16 I AGNDR Right Analog Ground
17 O CAPR2 Right External Filter Capacitor 2
18 O CAPR1 Ri
19 I V

R Right Channel Input

IN

ght External Filter

Capacitor 1

20 I AGND Analog Ground
21 I RLJUST Right/Left Justify
22 I MSBDLY Delay MSB One BCLK Period
23 I RESET Reset
24 I DGND2 Digital Ground
25 I DV

2 5 V Digital Supply

DD

26 O SOUT Serial Data Output
27 O TAG Serial Overrange Output
28 I CLKIN Master Clock

DEFINITIONS
Dynamic Range

The ratio of a full-scale output signal to the integrated output
noise in the passband (20 Hz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a –60 dB input signal
and is equal to (S/[THD+N]) 60 dB. Note that spurious har­monics are below the noise with a –60 dB input, so the noise
level establishes the dynamic range. The dynamic range is speci­fied with and without an A-Weight filter applied.

Signal to (Total Harmonic Distortion + Noise)

(S/(THD + N))

The ratio of the root-mean-square (rms) value of the fundamen­tal input signal to the rms sum of all other spectral components
in the passband, expressed in decibels (dB).

Signal to Total Harmonic Distortion (S/THD)

The ratio of the rms value of the fundamental input signal to the
rms sum of all harmonically related spectral components in the
passband, expressed in decibels.

Passband

The region of the frequency spectrum unaffected by the attenu­ation of the digital decimator’s filter.

Passband Ripple

The peak-to-peak variation in amplitude response from equal­amplitude input signal frequencies within the passband,
expressed in decibels.

Stopband

The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by “stopband
attenuation.”

Gain Error

With a near full-scale input, the ratio of actual output to
expected output, expressed as a percentage.

Interchannel Gain Mismatch

With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.

Gain Drift

Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.

Midscale Offset Error

Output response to a midscale dc input, expressed in least­significant bits (LSBs).

Midscale Drift

Change in midscale offset error with a change in temperature,
expressed as parts-per-million (ppm) per °C.

Crosstalk (EIAJ Method)

Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.

Power Supply Rejection

With no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.

Group Delay

Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds
(ms). More precisely, the derivative of radian phase with respect
to radian frequency at a given frequency.

Group Delay Variation

The difference in group delays at different input frequencies.
Specified as the difference between largest and the smallest
group delays in the passband, expressed in microseconds (µs).

REV. A

–5–

AD1877

(

Continued from Page 1

The flexible serial output port produces data in twos-comple­ment, MSB-first format. The input and output signals are TTL
compatible. The port is configured by pin selections. Each 16-bit
output word of a stereo pair can be formatted within a 32-bit
field of a 64-bit frame as either right-justified, I
Word Clock controlled or left-justified positions. Both 16-bit
samples can also be packed into a 32-bit frame, in left-justified

2

S-compatible positions.

and I

The AD1877 is fabricated on a single monolithic integrated circuit
using a 0.8 µm CMOS double polysilicon, double metal process,
and is offered in a plastic 28-lead SOIC package. Analog and
digital supply connections are separated to isolate the analog cir­cuitry from the digital supply and reduce digital crosstalk.

The AD1877 operates from a single 5 V power supply over the
temperature range of 0°C to 70°C, and typically consumes less
than 260 mW of power.

THEORY OF OPERATION
⌺⌬ Modulator Noise-Shaping

The stereo, internally differential analog modulator of the
AD1877 employs a proprietary feedforward and feedback archi­tecture that passes input signals in the audio band with a unity
transfer function yet simultaneously shapes the quantization
noise generated by the one-bit comparator out of the audio
band. See Figure 1. Without the ∑∆ architecture, this quantiza­tion noise would be spread uniformly from dc to one-half the
oversampling frequency, 64 × F

V

IN

SINGLE TO

DIFFERENTIAL

CONVERTER

Figure 1. Modulator Noise-Shaper (One Channel)

∑∆ architectures “shape” the quantization noise-transfer function
in a nonuniform manner. Through careful design, this transfer
function can be specified to high-pass filter the quantization
noise out of the audio band into higher frequency regions. The
AD1877 also incorporates a feedback resonator from the fourth
integrator’s output to the third integrator’s input. This resonator
does not affect the signal transfer function but allows the flexible
placement of a zero in the noise transfer function for more effec­tive noise shaping.

Oversampling by 64 simplifies the implementation of a high per­formance audio analog-to-digital conversion system. Antialias
requirements are minimal; a single pole of filtering will usually
suffice to eliminate inputs near F

A fourth-order architecture was chosen both to strongly shape
the noise out of the audio band and to help break up the idle
tones produced in all ∑∆ architectures. These architectures have
a tendency to generate periodic patterns with a constant dc input, a
response that looks like a tone in the frequency domain. These
idle tones have a direct frequency dependence on the input dc

ⴙV

)

ⴚV

2

S-compatible,

.

S

IN

DAC

MODULATOR
BITSTREAM
OUTPUT

DAC

IN

and its higher multiples.

S

offset and indirect dependence on temperature and time as it
affects dc offset. The AD1877 suppresses idle tones 20 dB or
better below the integrated noise floor.

The AD1877’s modulator was designed, simulated, and exhaus­tively tested to remain stable for any input within a wide tolerance
of its rated input range. The AD1877 is designed to internally
reset itself should it ever be overdriven, to prevent it from going
instable. It will reset itself within 5 µs at a 48 kHz sampling
frequency after being overdriven. Overdriving the inputs will
produce a waveform “clipped” to plus or minus full scale.

See TPCs 1 through 16 for illustrations of the AD1877’s
typical analog performance as measured by an Audio Precision
System One. Signal-to(distortion + noise) is shown under a
range of conditions. Note that there is a small variance between
the AD1877 analog performance specifications and some of the
performance plots. This is because the Audio Precision System
One measures THD and noise over a 20 Hz to 24 kHz band­width, while the analog performance is specified over a 20 Hz to
20 kHz bandwidth (i.e., the AD1877 performs slightly better
than the plots indicate). The power supply rejection (TPC 5)
graph illustrates the benefits of the AD1877’s internal differen­tial architecture. The excellent channel separation shown in
TPC 6 is the result of careful chip design and layout.

Digital Filter Characteristics

The digital decimator accepts the modulator’s stereo bitstream
and simultaneously performs two operations on it. First, the
decimator low-pass filters the quantization noise that the modu­lator shaped to high frequencies and filters any other out-of
audio-band input signals. Second, it reduces the data rate to an
output word rate equal to F

. The high frequency bitstream is

S

decimated to stereo 16-bit words at 48 kHz (or other desired

). The out-of-band one-bit quantization noise and other high

F

S

frequency components of the bitstream are attenuated by at
least 90 dB.

The AD1877 decimator implements a symmetric Finite Impulse
Response (FIR) filter which possesses a linear phase response.
This filter achieves a narrow transition band (0.1 × F

), high

S

stopband attenuation (> 90 dB), and low passband ripple
(< 0.006 dB). The narrow transition band allows the unattenu­ated digitization of 20 kHz input signals with F

as low as

S

44.1 kHz. The stopband attenuation is sufficient to eliminate
modulator quantization noise from affecting the output. Low
passband ripple prevents the digital filter from coloring the
audio signal. See TPC 7 for the digital filter’s characteristics.
The output from the decimator is available as a single serial
output, multiplexed between left and right channels.

Note that the digital filter itself is operating at 64 × F

. As a

S

consequence, Nyquist images of the passband, transition band,
and stopband will be repeated in the frequency spectrum at
multiples of 64 × F

. Thus the digital filter will attenuate to

S

greater than 90 dB across the frequency spectrum except for a
window ± 0.55 × F

wide centered at multiples of 64 × FS. Any

S

input signals, clock noise, or digital noise in these frequency
windows will not be attenuated to the full 90 dB. If the high
frequency signals or noise appear within the passband images
within these windows, they will not be attenuated at all, and
therefore input antialias filtering should be applied.

–6–

REV. A