ALTERA HardCopy III Service Manual

January 2011
HIII51001-3.2

HIII51001-3.2

1. HardCopy III Device Family Overview

This chapter provides an overview of features available in the HardCopy®III device
family. More details about these features can be found in their respective chapters.

HardCopy III devices are Altera’s low-cost, high-performance, low-power ASICs with
pin-outs, densities, and architectures that complement Stratix®III devices.
HardCopy III device features, such as phase-locked loops (PLLs), embedded memory,
and I/O elements (IOEs), are functionally and electrically equivalent to the Stratix III
FPGA features. The combination of the Quartus®II software for design, Stratix III
FPGAs for in-system prototype and design verification, and HardCopy III devices for
high-volume production, provides a complete, low-risk design solution to meet your
business needs.

HardCopy III devices improve on the successful and proven methodology of the
previous generations of HardCopy devices. Altera® HardCopy III devices use the
same base arrays across multiple customer designs for a given device density. They
are customized using only two metal and three via layers. The Quartus II software
provides a complete set of tools for designing the Stratix III FPGA prototypes and the
HardCopy III ASICs. HardCopy III devices are also supported through other
front-end design tools from Synopsys and Mentor Graphics®.

Based on a 0.9-V, 40-nm process, the HardCopy III family is an alternative to the
standard cell ASIC for low-cost, high-performance logic, digital signal processing
(DSP), and embedded designs.

This chapter contains the following sections:

■ “Features” on page 1–2

■ “Architectural Features” on page 1–9

■ “Software Support and Part Number Information” on page 1–13

© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or li ab ility aris ing out of the app lic atio n or us e of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

HardCopy III Device Handbook Volume 1: Device Interfaces and Integration
January 2011

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1–2 Chapter 1: HardCopy III Device Family Overview

Features

Features

HardCopy III devices offer the following features:

■ General

■ Fine-grained HCell architecture resulting in a low-cost, high-performance,

low-power ASIC

■ Fully tested production-quality samples typically available 14 weeks from the

date of your design submission

■ Design functionality the same as the Stratix III FPGA prototype

■ System performance and power

■ Core logic performance up to 50% faster than the Stratix III FPGA prototype

■ Power consumption reduction of typically 50% or greater from the Stratix III

FPGA prototype

■ Robust on-chip hot socketing and power sequencing support

■ Support for instant-on or instant-on-after-50 ms power-up modes

■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for

robust signal integrity

1 The actual performance and power consumption improvements described

in this data sheet are design-dependent.

■ Logic and Digital Signal Processing (DSP)

■ 2.7 to 7 million usable gates for both logic and DSP functions (as shown in

Table 1–1)

■ High-speed DSP functions supporting 9 × 9, 12 × 12, 18 × 18, and 36 × 36

multipliers, multiple accumulate functions, and finite impulse response (FIR)
filters

■ Internal memory

■ TriMatrix memory, consisting of three RAM block sizes to implement true

dual-port memory and first-in first-out (FIFO) buffers

■ Up to 16,272 Kbits RAM in embedded RAM blocks (including parity bits)

■ Memory logic array blocks (MLAB) implemented in HCell logic fabric

■ Clock resources PLLs

■ Up to 16 global clocks, 88 regional clocks, and 88 peripheral clocks per device

■ Clock control block supporting dynamic clock network enable/disable and

dynamic global clock network source selection

■ Up to 12 PLLs per device supporting PLL reconfiguration, clock switchover,

programmable bandwidth, clock synthesis, and dynamic phase shifting

HardCopy III Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation

Chapter 1: HardCopy III Device Family Overview 1–3

Features

■ I/O standards, external memory interface, and intellectual property (IP)

■ Support for numerous single-ended and differential I/O standards, such as

LVTTL, LVCMOS, PCI, PCI-X, SSTL, HSTL, and LVDS

■ High-speed differential I/O support with serializer/deserializer (SERDES) and

dynamic phase alignment (DPA) circuitry for 1.25 Gbps performance

■ Support for high-speed networking and communications bus standards,

including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSLI,
Rapid I/O, and NPSI

■ Memory interface support with dedicated DQS logic on all I/O banks

■ Dynamic On-Chip Termination (OCT) with auto-calibration support on all I/O

banks

■ Support for high-speed external memory interfaces, including DDR, DDR2,

DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 20 modular
I/O banks

■ Support for multiple intellectual property megafunctions from Altera

MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)

■ Nios

®

II embedded processor support

■ JTAG—IEEE 1149.1 boundary scan testing (BST) support

■ Packaging

■ Pin-compatible with Stratix III FPGA prototypes

■ Up to 880 user I/O pins available

■ Flip chip, space-saving FineLine BGA packages available (Table 1–3)

Table 1–1 lists the HardCopy III ASIC devices and available features.

Table 1–1. HardCopy III ASIC Family Features (Part 1 of 2)

HardCopy III

ASIC

Stratix III

FPGA

Prototype

ASIC

Equivalent

Gates (1)

M9K

Blocks

EP3SL110 2.7 M 275 12 4,203 Kb 288 4

EP3SL150 3.6 M 355 16 5,499 Kb 384 4

EP3SE110 5.8 M 639 16 8,055 Kb 896 4

HC325

EP3SL200 5.3 M 468 32 8,820 Kb 576 4

EP3SE260 6.9 M 864 32 12,384 Kb 768 4

EP3SL340 7.0 M 864 32 12,384 Kb 576 4

M144K
Blocks

Total Dedicated

RAM Bits

(not including

MLABs) (2)

18 × 18-Bit
Multipliers
(FIR Mode)

PLLs

January 2011 Altera Corporation HardCopy III Device Handbook Volume 1: Device Interfaces and Integration

1–4 Chapter 1: HardCopy III Device Family Overview

Features

Table 1–1. HardCopy III ASIC Family Features (Part 2 of 2)

HardCopy III

ASIC

HC335

Notes to Tab le 1 –1 :

(1) This is the number of ASIC equivalent gates available in the HardCopy III base array, shared between both adaptive logic module (ALM) logic

and DSP functions from a Stratix III FPGA prototype. The number of ASIC equivalent gates usable is bounded by the ALMs and DSP functions

in the companion Stratix III FPGA device.
(2) MLAB RAMs are implemented with HCells in the HardCopy III ASICs.
(3) This device has 12 PLLs in the F1517 package and 8 PLLs in the F1152 package.

Stratix III

FPGA

Prototype

EP3SL150 3.6 M 355 16 5,499 Kb 384 8

EP3SE110 5.8 M 639 16 8,055 Kb 896 8

EP3SL200 5.3 M 468 36 9,396 Kb 576 12 (3)

EP3SE260 6.9 M 864 48 14,688 Kb 768 12 (3)

EP3SL340 7.0 M 1,040 48 16,272 Kb 576 12 (3)

ASIC

Equivalent

Gates (1)

M9K

Blocks

M144K
Blocks

Total Dedicated

RAM Bits

(not including

MLABs) (2)

18 × 18-Bit
Multipliers
(FIR Mode)

PLLs

HardCopy III ASIC and Stratix III FPGA Mapping Paths

HardCopy III devices offer pin-to-pin compatibility with the Stratix III prototype,
making them drop-in replacements for the FPGAs. Therefore, the same system board
and software developed for prototyping and field trials can be retained, enabling the
lowest risk and fastest time-to-market for high-volume production.

HardCopy III devices also offer non-socket replacement mapping paths to smaller
standard or customized packages. For example, you can map the EP3SL110 device in
the 780-pin FBGA package to the HC325 device in the 484-pin FBGA standard
package, or to the 400-pin FBGA customized package. Because the pin-out for the two
packages are not the same, you need a separate board design for the Stratix III device
and the HardCopy III device.

The non-socket replacement offerings extend cost reduction further and allow for a
smaller foot print occupied by the HardCopy III device. The non-socket replacement
to a standard package is supported in the Quartus II software. The customized
package option is not visible in the Quartus II software. For more information, refer to

“HardCopy III Package Pro” on page 1–7.

For the non-socket replacement to a standard package, select I/Os in the Stratix III
device that can be mapped to the HardCopy III device. Not all I/Os in the Stratix III
device are available in the HardCopy III non-socket replacement device. Check the
pin-out information for both the Stratix III device and HardCopy III device to ensure
that the I/Os can be mapped, and select the companion device in the Quartus II
project setting during design development. By selecting the companion device, the
Quartus II software ensures that common resources and compatible I/Os are used
during the mapping from the Stratix FPGA to the HardCopy ASIC.

There are a number of FPGA prototype choices for each HardCopy III device, as listed
in Table 1–2. To obtain the best value and the lowest system cost, architect your
system to maximize silicon resource utilization.

HardCopy III Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation

Chapter 1: HardCopy III Device Family Overview 1–5

January 2011 Altera Corporation HardCopy III Device Handbook Volume 1: Device Interfaces and Integration

Features

Table 1–2. Stratix III FPGA Prototype to HardCopy III ASIC Mapping Paths (Note 1)

Stratix III FPGA Prototype and Package

HardCopy III

ASIC

HardCopy III

Package

EP3SL110 EP3SL150 EP3SE110 EP3SL200 EP3SE260 EP3SL340

F780 F780 F1152 F780 F1152 H780 F1152 F1517 H780 F1152 F1517 H1152 F1517

484-pin

HC325

FineLine BGA

780-pin

FineLine BGA

1152-pin

HC335

FineLine BGA

1517-pin

FineLine BGA

Notes to Ta bl e 1– 2:

(1) HardCopy III device migration paths are not supported for the EP3SL50, EP3SL70, EP3SE50, and EP3SE80 Stratix III devices.
(2) This mapping is a non-socket replacement path that requires a different board design for the Stratix III device and the HardCopy III device.
(3) The Hybrid FBGA package requires additional unused board space along the edges beyond the footprint, but its footprint is compatible with the regular FBGA package.

v (2) v (2) — v (2) — v (2) — —v (2) — —v (2) —

vv — v — v (3) — —v (3) — —v (2) —

— — v — v — v — —v — — —

— ——————v — — —

v

Three different FineLine BGA package substrate options are available for the HardCopy III devices:

■ Performance-optimized flip chip package (F)

■ Cost-optimized flip chip package (L, LA)

■ Low-cost wire bond package (W)

All three package types support direct replacement of the Stratix III FPGA prototype. The performance-optimized flip chip
package supports equivalent performance and the same number of I/Os as the corresponding FPGA prototype. The
cost-optimized flip chip package uses a substrate with fewer layers and no on-package decoupling (OPD) capacitors to offer a
low-cost package option. The performance is reduced from that of the FPGA prototype. However, the number of available
I/Os remains the same. The wire bond package offers another low-cost package option, but with the trade-off of reduced
performance and fewer available I/Os.

1 If you are going to use the low-cost wire bond package, make sure your design uses I/Os that are available in that package.

For HardCopy III non-socket replacement devices, only the performance-optimized flip chip package and the low-cost wire
bond package are supported.