Altera HardCopy II Clock Uncertainty Calculator User Manual

HardCopy II Clock Uncertainty Calculator

User Guide

101 Innovation Drive
San Jose, CA 95134
www.altera.com

Software Version: 7.1
Document Version: 1.0
Document Date: August 2007

Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des­ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporat ion in the U.S . and other co untries. All other product or service n ames are the proper ty of their respective holders. Al­tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera w arrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap­plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in­formation and before placing orders for products or services.

UG-01015-1.0

ii MegaCore Version a.b.c variable Altera Corporation
HardCopy II Clock Uncertainty Calculator User GuidePreliminary August 2007

Contents

Chapter 1. About HardCopy II Clock Uncertainty Calculator

Introduction ............................................................................................................................................ 1–1

General Description ............................................................................................................................... 1–2

PLL Extraction .................................................. ...................................................... .......................... 1–3

Clock Transfer Report ....... ............................................................................................................... 1–4

Intra-Clock Transfer ................................................................................................................... 1–5

Inter-Clock Transfer .................................................................................................................... 1–5

I/O Transfer ................................................................................................................................. 1–6

Clock Uncertainty Calculator Spreadsheet ................................................................................... 1–6

Instructions .................................................................................................................................. 1–6

Clock Uncertainty Calculator .................................................................................................... 1–7

Advanced Clock Uncertainty Calculator ............................................ ............................. ........ 1–7

Chapter 2. Launching the HardCopy II Clock Uncertainty Calculator

Release Information .................................................... ........................................................................... 2–1

Device Family Support ......................................................................................................................... 2–1

System and Software Requirements ................................................................................................... 2–2

Download and Install the HardCopy II Clock Uncertainty Calculator ........................... ........ 2–3

Installation of HardCopy II Clock Uncertainty Calculator ........................................................ 2–3

Running the Clock Uncertainty Calculator Flow .............................................................................. 2–3

PLL Settings Summary Extraction .................................................................................... ............. 2–3

Syntax ........................................................................................................................................... 2–3

Running get_pll.tcl on the Quartus II Tcl Console .......... ............................. .......................... 2–4

Running get_pll.tcl on the Command Line or UNIX ............................................................. 2–4

Report Clock Transfers Using the TimeQuest Timing Analyzer ........................... ................... 2–5

Run HardCopy II Clock Uncertainty Calculator Spreadsheet ........................ .......................... 2–6

Using the Clock Uncertainty Calculator .................................................................................. 2–6

Using the Advanced Clock Uncertainty Calculator ....... ....................................................... 2–8

Create Clock Uncertainty Timing Constraints on a SDC ........................................ ................. 2–11

Chapter 3. Design Case Exceptions

Multiple Clock Uncertainty on a Single Clock Transfer ............. ............................... ...................... 3–1

Various Clock Structures ....................... ................................................................................ ............... 3–2

Clock Gated in Core ......................................................................................................................... 3–2

Clock Divider ........................ ..................................................... ........................... ............................ 3–3

Ripple Clock ...................................................................................................................................... 3–3

Multiple Clock Networks ........................................................... ..................................................... 3–4

Multi-Cycle Clock ....................... ...................................................................................................... 3–4

Altera Corporation iii
August 2007

Contents

Appendix A. Clock Transfer Examples

Intra-Clock Domain with PLL ............................................................................................................ A–1

Intra-Clock Domain without PLL ...................................................................................................... A–3

Inter-Clock Domain with PLL ............................................................................................................ A–4

Inter-Clock Domain without PLL .................................................................................................... A–10

I/O Interface with PLL ...................................................................................................................... A–11

I/O Interface without PLL ................................................................................................................ A–12

Intra-Clock Domain with Cascaded PLLs ....................................................................................... A–14

Inter-Clock Domain with Cascaded PLLs ....................................................................................... A–16

I/O Interface with Cascaded PLLs .................................................................................................. A–29

iv Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide August 2007

About this User Guide

Revision History

Date/Version Changes Made Summary of Changes

August 2007, v1.0 N/A —

How to Contact

The following table shows the revision history for this User Guide.

For the most up-to-date information about Altera® products, refer to the
following table.

Altera

Contact (1)

Technical support Website www.altera.com/support
Technical training Website www.altera.com/training

Product literature Website www.altera.com/literature
Altera literature services Email [e-mail]
Non-technical support (General)

(Software Licensing)

Note to table:

(1) You can also contact your local Altera sales office or sales representative.

Contact
Method

Email [e-mail]

Email [e-mail]
Email [e-mail]

Address

Altera Corporation MegaCore Version a.b.c variable v
August 2007 HardCopy II Clock Uncertainty Calculator User Guide

Typographic Conventions

Typographic

This document uses the typographic conventions shown below.

Conventions

Visual Cue Meaning

Bold Type with Initial
Capital Letters

bold type External timing parameters, directory names, project names, disk drive names,

Italic Type with Initial Capital
Letters

Italic type Internal timing parameters and variables are shown in italic type.

Initial Capital Letters Keyboard ke ys and menu names are shown with initial capital letters. Examples:

“Subheading Title” References to sections within a document and titles of on-line help topics are

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,

1., 2., 3., and
a., b., c., etc.

● • Bullets are used in a list of items when the sequence of the items is not important.

■

v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.

c

w

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

Command names, dialog box titles, chec kbox options, and dialog bo x options are
shown in bold, initial capital letters. Example: Save As dialog box.

filenames, filename extensions, and software utility names are shown in bold
type. Examples: f

Document titles are shown in italic type with initial capital letters. Example: AN

75: High-Speed Board Design.

Examples: t

Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.

Delete key, the Options menu.

shown in quotation marks. Example: “Typographic Conventions.”

PIA

, \qdesigns directory, d: drive, chiptrip.gdf file.

MAX

, n + 1.

tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it displays is shown in Courier type. For
example:
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword
Courier.

Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.

A caution calls attention to a condition or possible situation that can damage or
destroy the product or the user’s work.

A warning calls attention to a condition or possible situation that can cause injury
to the user.

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an

SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

vi MegaCore Version a.b.c variable Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide August 2007

Chapter 1. About HardCopy II

Clock Uncertainty Calculator

Introduction

"Clock uncertainty" is the interval of confidence around the ideal clock
value, such that the measured value is always within the stated interval.
Common sources of clock uncertainty include clock jitter, duty cycle
distortion, and phase shift error. Due to these sources, clock uncerta int y
must be factored in to guard against deep submicron effects that are not
explicitly reflected in the timing models. The HardCopy II Clock
Uncertainty Calculator
HardCopy® II devices based on PLL phase error, PLL jitter, I/O buffer,
clock network noise, and core noise. Therefore, timing constraints that
consider clock uncertainty are required for the HardCopy II devices. You
must prepare the clock uncertainty timing constraints before starting
HardCopy II migration.

™

provides the clock uncertainty values for

Altera Corporation 1–1
August 2007

General Description

General
Description

Figure 1–1 shows the HardCopy II developm ent fl ow, including the

HardCopy II Clock Uncertainty Calculator flow.

Figure 1–1. Top-level Flow for HardCopy II Development Flow

FPGA
Quartus II
Database

Run Clock

Uncertainty

Calculator Flow (1)

(based on FPGA database)

Generate CU

Constraint File

Create HC II

Companion

Revision

Compile for

HardCopy II

Note to Figure 1–1:

(1) Initially, run clock uncertainty calculator flow on FPGA database; all subsequent

times are found in the HardCopy II database.

TimeQuest

Timing Analyzer

TQ

Analysis

Yes

Pass?

Yes

Done

TimeQuest

No

Calculator Flow (1)

(based on FPGA database)

Fix Timing

Violations

Recompile for

HardCopy II

Re-run Clock

Uncertainty

Generate

Revised CU

Constraint File

f Refer to the Quartus II Support of HardCopy Series Device chapter in the

Quartus II Handbook for more details.

®

After the Stratix
generated successfully, Altera® recommends that you run the clock
uncertainty (CU) calculator flow. Although the Stratix II FPGA database
may not be migrated to a HardCopy II companion device, the source used
to calculate the clock uncertainty in Strat ix II devices is same sour ce us ed
in the initial stage of HardCopy’s clock uncertainty calculati on. In
addition, creating and applying the clock uncertainty constraints during
the HardCopy II compilation and static timing analysis will increase
efficiency.

1–2 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide August 2007

II FPGA design is compiled and the database is

About HardCopy II Clock Uncertainty Calculator

xt

P
p

All timing violations that are reported during HardCopy II comp ilation
and static timing analysis must be resolved. When you have PLL setting
changes that cause new PLL jitter and/or static phase error on the design,
you are required to re-r un the clock uncertainty calculator flow to acquire
new clock uncertainty constraints.

Altera’s HardCopy II Clock Uncertainty Calculator flow can be separated
into three parts:

■ PLL extraction

■ Clock transfer report

■ Clock uncertainty calculator spreadsheet

Figure 1–2 shows PLL extraction, the clock transfer report, and the clock

uncertainty calculator spreadsheet within the HardCopy II Clock
Uncertainty Calculator flow.

Figure 1–2. HardCopy II Clock Uncertainty Calculator Flow

PLL Extraction

(Tcl Script)

LL_Names.txt
ll_settings_summary.txt

Clock Uncertainty

CU_Values.txt

PLL Extraction

Clock T r ansfer Report

(TimeQuest Timing Analyzer)

Calculator

Spreadsheet

Advanced Clock

Uncertainty Calculator

Spreadsheet

CU_Advanced_Values.t

All of the PLLs’ settings and names must be extracted to two separated
output files by using a Tcl script, get_pll.tcl. One of the output files,
pll_settings_summary.txt, contains the PLL settings summary, which is

Altera Corporation 1–3
August 2007 HardCopy II Clock Uncertainty Calculator User Guide

General Description

used as the input file for clock uncertainty calculators. The other file,
PLL_Names.txt, contains the PLL indices and the associated PLL names.
Even if the design does not contain a PLL, you still must run the Tcl script.

Clock Transfer Report

Before continuing on to the clock uncertainty calculator spreadsheet, you
must generate the clock transfer report using TimeQuest Timing
Analyzer. The clock transfer report covers the clock-to-clock transfer in
the design if a path exists between two registers that are clocked by two
clocks. The two clocks are source and destination clocks, and they may be
the same or different clocks. This report of clock transfer from the
TimeQuest Timing Analyzer is not an input file for the clock uncertainty
calculator, but rather provides useful information you may need when
setting the clock uncertainty timing constraints (SDC) for the design. For
example:

set_clock_uncertainty –setup –from clk_source –to
clk_destination 0.150

where clk_source is source clock name, and clk_destination is the
destination clock name.

Clock uncertainty is based on I/O buffer noise, clock network noise, core
noise, PLL jitter , or static phase error. Thus, the clock transfer information
plays an important role in the clock uncertainty calculator flow. There are
three types of clock transfers that clock uncertainty calculator flow
covers:

■ Intra-clock transfer

■ Inter-clock transfer

■ I/O transfer

f Refer to the TimeQuest Timing Analyzer chapter in volume 3 of the

Quartus II Handbook for more information about report clock transfer.

1–4 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide August 2007

About HardCopy II Clock Uncertainty Calculator

n

Clock

Source

n

Intra-Clock Transfer

Intra-clock transfer occurs when the source and destination clocks come
from the same PLL/I/O clock pin, as shown in Figure 1–3.

Figure 1–3. Intra-Clock Transfer

Source
Register

Destinatio
Register

INBUF

PLL

CLK11

CLK11

Source

Clock

Destination

Clock

Inter-Clock Transfer

Inter-clock transfer occurs when the source and destination clocks come
from different PLLs and I/O clock pins, as shown in Figure 1–4.

Figure 1–4. Inter-Clock T ransfer

INBUF

PLL5

PLL9

CLK2

CLK7

Source

Clock

Destination

Register

Destinatio
Register

Altera Corporation 1–5
August 2007 HardCopy II Clock Uncertainty Calculator User Guide

General Description

n

Register

A

I/O Transfer

I/O transfer occurs when the clock transfer from an off-chip to the
destination clock (input) or, clock transfer from the source clock to an
off-chip (output), as shown in Figures 1–5 and 1–6.

Figure 1–5. Input Transfer

DATA

Destinatio
Register

INBUF

PLL10

CLK5

Destination

Clock

Figure 1–6. Output Transfer

PLL7

INBUF

CLK2

Source

Clock

DAT

Source

Refer to Appendix A, Clock Transfer Examples for more examples of
clock transfer cases.

Clock Uncertainty Calculator Spreadsheet

The clock uncertainty calculator spreadsheet consists of three parts:

■ Instructions

■ Clock uncertainty calculator

■ Advanced Clock Uncertainty (ACU) calculator

Instructions

The clock uncertainty calculator spreadsheet is a Microsoft Excel-based
file. The first worksheet provides quick-start instructions for using the
calculators. Both the clock uncertainty and advanced clock uncertainty

1–6 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide August 2007

About HardCopy II Clock Uncertainty Calculator

calculators require the PLL settings summary file,
pll_settings_summary.txt, as input data to calculate the clock uncertainty
values.

Clock Uncertainty Calculator

The clock uncertainty calculator is on the second worksheet. It operates
with a single green button and supports all designs, except designs with
a cascading PLL structure. When the clock uncertainty values are
calculated, they are displayed on the spreadsheet, and simultaneously
written to a text file, CU_Values.txt. The clock uncertainty values are for
worst-case scenarios, and account for I/O buffer noise, clock network
noise, core noise, PLL jitter, and static phase error.

Advanced Clock Uncertainty Calculator

The advanced clock uncertainty calculator is different than the clock
uncertainty calculator. The clock uncertainty values from the advanced
clock uncertainty calculator are considered more precise than the clock
uncertainty calculator, because it accounts for each dedicated PLL’s
utilization within the design. The advanced clock uncertainty calculator
requires the input of PLLs’ indices for both the source and destination
clock. Therefore, entering the PLLs’ indices on the advanced clock
uncertainty calculator should be relied on for both the PLL_Names.txt file
and the clock transfer report to generate the clock uncertainty values.
Also, you should use this calculator if there are cascading PLLs in the
design. After clock uncertainty calculation, the clock uncertainty values
are displayed on the spreadsheet and written to a text file,
CU_Advanced_Values.txt.

Both the advanced clock uncertainty and clock uncertainty calculators
can calculate and display the setup and hold uncertainty results for
different types of clock transfers. You can apply these clock uncertainty
constraints to model jitter and noise to ensure integrity with clock signals.
When a clock uncertainty constraint exists for a clock signal, the
TimeQuest Timing Analyzer performs the most conservative setup and
hold checks. For a clock setup check, the setup uncertainty is subtracted
from the data time requirement. For the clock hold check, the hold
uncertainty is added to the data time requirement. Figure 1–7 on page 1–8
shows examples of clock sources with a clock setup uncertainty applied
and clock sources with clock hold uncertainty applied.

Altera Corporation 1–7
August 2007 HardCopy II Clock Uncertainty Calculator User Guide

General Description

S

D

0.0 ns

ty

ty

Figure 1–7. Clock Uncertainty Set-up and Hold Check

ource

Clock

estination

Clock

Clock hold check

with uncertainty

5.0 ns 10.0 ns

To obtain the clock uncertainty values from HardCopy II devices, you
should use the Altera HardCopy II Clock Uncertainty Calculator which
consists of the Tcl-based script for obtaining the PLL setting summary
and the Microsoft Excel-based spread sheet of clock uncertainty
calculators. Both utilities are packaged in the Altera HardCopy II Clock
Uncertainty Calculator, which is available on the Altera web
site (www.altera.com).

Clock steup check

with uncertainty

Clock Hold Uncertain

Clock Setup Uncertain

1–8 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide August 2007

Chapter 2. Launching the

HardCopy II Clock

Uncertainty Calculator

Release Information

Device Family Support

Table 2–1 provides information about the version of HardCopy® II Clock

Uncertainty Calculator spreadsheet docu m ented in this user guide.

Table 2–1. HardCopy II Clock Uncertainty Calculator Spreadsheet Version

Device Family

HardCopy II 2.2 and later

The HardCopy II Clock Uncertainty Calculator supports the following
HardCopy II devices in Commercial and Industry temperature ranges:

■ HC240

■ HC230

■ HC220

■ HC210

■ HC210W (Use HC210 clock uncertainty value for HC210W)

The HardCopy II Clock Uncertainty Calculator was developed for
calculating the clock uncertainties caused by clock jitter, duty cycle
distortion, and phase shift error. With different interfaces of the clock
transferring on the chip, you may have different outcomes for the clock
uncertainty.

As shown in Figure 2–1, the HardCopy II Clock Uncertainty Calculator
covers clock transfer at the following locations:

HardCopy II Clock Uncertainty

Calculator Spreadsheet Version

■ Within core

■ Between the core and I/O

■ Between the core and SERDES/DDR blocks

Altera Corporation 2–1

System and Software Requirements

Figure 2–1. HardCopy II Clock Uncertainty Calculator Coverage

Note to Figure 2–1:

(1) Transfer covered by DTW.
(2) Transfer covered by SERDES.
(3) Transfer covered by Altera HardCopy II Clock Uncertainty Calculator.

(2)

DDR (1)

S

E
R
D

E

S

CORE

HC230

DDR (1)

I

O

(3)

System and

The Altera® HardCopy II Clock Uncertainty Calculator spreadsheet
requires the following hardware and software:

Software
Requirements

2–2 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide

■ A PC running the Windows NT/2000/XP operating system

■ Microsoft Office 2003 SP-1 or higher

■ Quartus

®

II software version 6.0 or higher

Launching the HardCopy II Clock Uncertainty Calculator

Download and Install the HardCopy II Clock Uncertainty Calculator

The HardCopy II Clock Uncertainty Calculator includes a Tcl script for
PLL extraction and a clock uncertainty calculator spreadsheet, and is
available from the Altera web site (www.altera.com). After reading the
terms and conditions, and clicking I Agree, you can download the
package in .zip format to your hard drive.

Installation of HardCopy II Clock Uncertainty Calculator

After you download the .zip file of the HardCopy II Clock Uncertainty
Calculator package, unzip the file to extract the following files:

■ get_pll.tcl

■ HCII_CU_Calculator.Rev<version number>.xls

Copy or move these two files into the design’s Quartus II working
directory.

Running the Clock Uncertainty Calculator Flow

This section provides detailed procedures for the HardCopy II Clock
Uncertainty Calculator flow. It includes PLL extraction, clock transfer
report, and instructions for running the HardCopy II Clock Uncertainty
Calculator spreadsheet.

PLL Settings Summary Extraction

Before starting the PLL settings summary extraction, you should have the
generated FPGA design database ready in the Quartus II software. Even
if your design does not contain any PLLs, you must still run the design
through the Quartus II software. PLL settings summa ry extraction
requires the Tcl script, get_pll.tcl, within the working directory.

Syntax

Use the following syntax for the PLL settings summary extraction:

$QUARTUS_HOME/bin/quartus_sh –t get_pll.tcl

<project_name>

where $QUARTUS_HOME is the installation directory of the Quartus II
software.

Altera Corporation 2–3

HardCopy II Clock Uncertainty Calculator User Guide

Running the Clock Uncertainty Calculator Flow

Running get_pll.tcl on the Quartus II Tcl Console

Figure 2–2 shows the PLL settings summary extraction using the

Quartus II software.

Figure 2–2. Example for Getting PLL Settings on the Quartus II Tcl Console

Running get_pll.tcl on the Command Line or UNIX

Figure 2–3 shows the PLL settings summary extraction using the

command line or UNIX.

Figure 2–3. Example for Acquiring PLL Settings on UNIX Prompt

After you complete the PLL extraction, you will have generated two files,
pll_settings_summary.txt and PLL_Names.txt, in the working directory.
You should also check the log file to confirm that the PLL extraction job
has completed without any errors.

The pll_settings_summary.txt file contains PLL indices, PLL names,
feedback counter (M) values, charge pump current, loop filter resistances,
voltage controlled oscillator (V

) frequency, and phase frequency

CO

detector frequency, that are required for running the clock uncertainty
calculators. Y o u will need pll_settings_summary.txt to continue the
clock uncertainty calculator spreadsheet.

2–4 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide

Launching the HardCopy II Clock Uncertainty Calculator

1 If the above parameters in pll_settings_summary.txt changed

during the HardCopy II design development, you should re-run
the HardCopy II Clock Uncertainty Calculator and update the
clock uncertainty constraints.

PLL_Names.txt is an optional file for the clock uncertainty calculator
spreadsheet. However, it provides useful information when using the
advanced clock uncertainty calculator worksheet, as it helps to identify
the corresponding PLL index for each PLL name.

Report Clock Transfers Using the TimeQuest Timing Analyzer

After you confirm that all clock assignments are correct, run
report_clock_transfers, or, in the Tasks pane on the TimeQuest
Timing Analyzer’s GUI, double-click Report Clock Transfers. The
command generates a summary table with the number of paths between
each clock domain, as shown in Figure 2–4.

Figure 2–4. TimeQuest Timing Analyzer's Report Clock Transfers

Y ou can also use the report_clock_transfers command to generate
a report that details all clock-to-clock transfers in the design, as s hown in

Figure 2–5 on page 2–6. A clock-to-clock transfer is reported if a path

exists between two registers measured by two different clocks.

Altera Corporation 2–5

HardCopy II Clock Uncertainty Calculator User Guide