HardCopy II Device Handbook, Volume 1
Preliminary Information
101 Innovation Drive
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www.altera.com
H5V1-4.5
Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. Mentor Graphics and ModelSim are registered trademarks of Mentor Graphics
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specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and servic es at any time without
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version of device specifications before relying on any published information and before placing orders for products or services.
ii Altera Corporation
Preliminary
Contents
Chapter Revision Dates .......................................................................... vii
About this Handbook ............................................................................... ix
How to Contact Altera ............................................................................................................................. ix
Typographic Conventions ....................................................................................................................... ix
Section I. HardCopy II Device Family Data Sheet
Revision History .................................................................................................................................... 1–1
Chapter 1. Introduction to HardCopy II Devices
Introduction ............................................................................................................................................ 1–1
Feature Overview .................................................................................................................................. 1–1
Migration and Packaging Overview ................................................................................................... 1–4
Document Revision History ................................................................................................................. 1–5
Chapter 2. Description, Architecture, and Features
Introduction ............................................................................................................................................ 2–1
Functional Description .......................................................................................................................... 2–2
HardCopy II and Stratix II Similarities and Differences .................................................................. 2–4
HCells ...................................................................................................................................................... 2–6
Embedded Memory ............................................................................................................................... 2–8
PLLs and Clock Networks .................................................................................................................... 2–9
Enhanced and Fast PLLs ............................................................................................................... 2–11
Clock Networks .............................................................................................................................. 2–14
I/O Structure and Features ................................................................................................................ 2–14
General Purpose IOE ..................................................................................................................... 2–20
Memory Interface IOE ................................................................................................................... 2–22
High-Speed IOE .............................................................................................................................. 2–25
Power-Up Modes ................................................................................................................................. 2–27
Document Revision History ............................................................................................................... 2–28
Chapter 3. Boundary-Scan Support
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 3–1
Boundary-Scan Test (BST) on HardCopy II Devices ................................................................... 3–3
Document Revision History ................................................................................................................. 3–5
Altera Corporation iii
Preliminary
HardCopy Series Handbook, Volume 1
Chapter 4. DC and Switching Specifications and Operating Conditions
Introduction ............................................................................................................................................ 4–1
Absolute Maximum Ratings ................................................................................................................ 4–1
Recommended Operating Conditions ................................................................................................ 4–2
DC Electrical Characteristics ................................................................................................................ 4–3
I/O Standard Specifications ................................................................................................................. 4–4
Bus Hold Specifications ...................................................................................................................... 4–18
On-Chip Termination Specifications ................................................................................................ 4–19
Pin Capacitance .................................................................................................................................... 4–21
Maximum Input Clock Rates ............................................................................................................. 4–22
Maximum Output Clock Rates .......................................................................................................... 4–25
HighSpeed I/O Specifications ........................................................................................................... 4–35
PLL Timing Specifications .................................................................................................................. 4–39
External Memory Interface Specifications ....................................................................................... 4–42
Hot Socketing ....................................................................................................................................... 4–45
Electrostatic Discharge ........................................................................................................................ 4–46
Document Revision History ............................................................................................................... 4–49
Chapter 5. Quartus II Support for HardCopy II Devices
HardCopy II Device Support ............................................................................................................... 5–1
HardCopy II Design Benefits .......................................................................................................... 5–1
Quartus II Features for HardCopy II Planning ............................................................................ 5–2
HardCopy II Development Flow ......................................................................................................... 5–3
Designing the Stratix II FPGA First ............................................................................................... 5–4
Designing the HardCopy II Device First ...................................................................................... 5–6
HardCopy II Device Resource Guide ................................................................................................. 5–7
HardCopy II Companion Device Selection ..................................................................................... 5–10
HardCopy II Recommended Settings in the Quartus II Software ................................................ 5–12
Limit DSP and RAM to HardCopy II Device Resources .......................................................... 5–12
Enable Design Assistant to Run During Compile ..................................................................... 5–12
Timing Settings ............................................................................................................................... 5–13
Constraints for Clock Effect Characteristics ............................................................................... 5–15
Quartus II Software Features Supported for HardCopy II Designs ....................................... 5–17
Performing ECOs with Change Manager and Chip Planner ........................................................ 5–19
Migrating One-to-One Changes ................................................................................................... 5–20
Migrating Changes that must be Implemented Differently ..................................................... 5–21
Changes that Cannot be Migrated ............................................................................................... 5–22
Overall Migration Flow ...................................................................................................................... 5–22
Preparing the Revisions ................................................................................................................. 5–22
Applying ECO Changes ................................................................................................................ 5–23
Formal Verification of Stratix II and HardCopy II Revisions ....................................................... 5–24
HardCopy II Utilities Menu ............................................................................................................... 5–25
Companion Revisions .................................................................................................................... 5–26
Compiling the HardCopy II Companion Revision ................................................................... 5–28
Comparing HardCopy II and Stratix II Companion Revisions ............................................... 5–29
Generate HardCopy II Handoff Report ...................................................................................... 5–29
Archive HardCopy II Handoff Files ............................................................................................ 5–29
iv Altera Corporation
Preliminary
Contents
HardCopy II Advisor ..................................................................................................................... 5–30
HardCopy II Floorplan View ........................................................................................................ 5–33
Conclusion ............................................................................................................................................ 5–34
Document Revision History ............................................................................................................... 5–35
Chapter 6. Script-Based Design for HardCopy II Devices
Introduction ............................................................................................................................................ 6–1
Tcl Support in the Quartus II Software .............................................................................................. 6–1
Interactive Tcl Shell .......................................................................................................................... 6–2
Command-Line Processing ............................................................................................................. 6–5
The HardCopy II Design Flow ............................................................................................................ 6–6
Creating a New Project ......................................................................................................................... 6–8
Creating a Stratix II Prototype Project ........................................................................................... 6–8
Opening a Project ............................................................................................................................. 6–9
Closing a Project ............................................................................................................................... 6–9
New Project Example Script ......................................................................................................... 6–10
Making Global Assignments .............................................................................................................. 6–11
Initializing a HardCopy II Design ............................................................................................... 6–11
The Design Assistant ..................................................................................................................... 6–15
Example Tcl Script for Making Global Assignments ................................................................ 6–16
Pin Assignments ............................................................................................................................. 6–17
Setting I/O Type and Parameters ................................................................................................ 6–17
I/O Assignment Example Script .................................................................................................. 6–20
Assigning Timing Constraints ........................................................................................................... 6–20
Planning Design Timing Constraints .......................................................................................... 6–20
Specifying System Clocks .............................................................................................................. 6–21
Input/Output Timing .................................................................................................................... 6–22
Creating Timing Exceptions ......................................................................................................... 6–23
Example of TimeQuest SDC Constraints .................................................................................... 6–24
Example of Classic Timing Analyzer Tcl Script ......................................................................... 6–25
Compiling the Stratix II Prototype Design ...................................................................................... 6–25
Compiling the HardCopy II Design ................................................................................................. 6–27
Understanding Report Files ............................................................................................................... 6–28
Comparing FPGA and HardCopy Revisions .................................................................................. 6–29
Performing Static Timing Analysis ................................................................................................... 6–30
Static Timing Analysis in the Quartus II Software .................................................................... 6–30
Static Timing Analysis in Primetime ........................................................................................... 6–31
HardCopy II Example Tcl Script ....................................................................................................... 6–32
Top-Level Example Script demo_design.tcl ............................................................................... 6–32
Global Assignments Script global_assignments.tcl ................................................................... 6–33
Pin Assignments Script pin_assignments.tcl .............................................................................. 6–34
TimeQuest Constraint File demo_design.sdc ............................................................................ 6–34
Timing Assignments Script timing_assignments.tcl ................................................................. 6–35
Summary ............................................................................................................................................... 6–35
Document Revision History ............................................................................................................... 6–36
Altera Corporation v
Preliminary
HardCopy Series Handbook, Volume 1
Chapter 7. Timing Constraints for HardCopy II Devices
Introduction ............................................................................................................................................ 7–1
HardCopy II versus Stratix II Timing ........................................................................................... 7–2
Internal Register-to-Register Timing ............................................................................................. 7–2
I/O Path Timing ............................................................................................................................... 7–4
Clock Distribution Effects ............................................................................................................... 7–4
PLL Characteristics .......................................................................................................................... 7–5
HardCopy II Timing Closure Methodology ...................................................................................... 7–5
HardCopy II Timing Closure Flow ................................................................................................ 7–5
Using the TimeQuest Timing Analyzer ........................................................................................ 7–8
Using Classic Timing Analyzer .................................................................................................... 7–11
Quartus II Timing Related Checks and Settings ........................................................................ 7–11
Constraining Timing of HardCopy Series Devices ........................................................................ 7–14
Clock Definitions ............................................................................................................................ 7–15
Primary Input Port Timing ........................................................................................................... 7–17
Primary Output Port Timing ........................................................................................................ 7–18
Unsupported HardCopy II Timing Constraints for Classic Timing Analyzer ........................... 7–21
Conclusion ............................................................................................................................................ 7–22
Document Revision History ............................................................................................................... 7–23
Chapter 8. Migrating Stratix II Device Resources to HardCopy II Devices
Stratix II and HardCopy II Migration Options ................................................................................. 8–2
I/O Support and Planning ................................................................................................................... 8–5
HardCopy II I/O Banks .................................................................................................................. 8–7
User I/O Count Per IOE Type and Bank Location ...................................................................... 8–9
HardCopy II Supported I/O Standards ....................................................................................... 8–9
External Memory Interface Support ................................................................................................. 8–13
LVDS, SERDES, and DPA Compatibility ................................................................................... 8–14
Programmable Drive Strength Support ...................................................................................... 8–15
On-Chip Termination .......................................................................................................................... 8–17
On-Chip Series Termination ......................................................................................................... 8–18
On-Chip Series Termination without Calibration ..................................................................... 8–18
On-Chip Series Termination with Calibration ........................................................................... 8–19
Differential I/O Termination ........................................................................................................ 8–20
Stratix II and HardCopy II Companion Memory Blocks ............................................................... 8–21
M512 Options .................................................................................................................................. 8–22
M4K Utilization .............................................................................................................................. 8–24
M-RAM Compatibility .................................................................................................................. 8–24
PLL Planning and Utilization ............................................................................................................ 8–26
Global and Local Signals .................................................................................................................... 8–30
Stratix II ALM Adaptation into HardCopy II Logic ....................................................................... 8–31
HardCopy II DSP Implementation from Stratix II DSP Blocks .................................................... 8–33
JTAG BST and Extended Functions .................................................................................................. 8–35
Power Up and Configuration Compatibility ................................................................................... 8–36
Conclusion ............................................................................................................................................ 8–39
More Information ................................................................................................................................ 8–40
Document Revision History ............................................................................................................... 8–40
vi Altera Corporation
Preliminary
Chapter Revision Dates
The chapters in this book, HardCopy Series Handbook, Volume 1, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Introduction to HardCopy II Devices
Revised: September 2008
Part number: H51015-2.6
Chapter 2. Description, Architecture, and Features
Revised: September 2008
Part number: H51016-2.5
Chapter 3. Boundary-Scan Support
Revised: September 2008
Part number: H51017-2.4
Chapter 4. DC and Switching Specifications and Operating Conditions
Revised: September 2008
Part number: H51018-3.3
Chapter 5. Quartus II Support for HardCopy II Devices
Revised: September 2008
Part number: H51022-2.5
Chapter 6. Script-Based Design for HardCopy II Devices
Revised: September 2008
Part number: H51025-1.3
Chapter 7. Timing Constraints for HardCopy II Devices
Revised: September 2008
Part number: H51028-2.2
Chapter 8. Migrating Stratix II Device Resources to HardCopy II Devices
Revised: September 2008
Part number: H51024-1.4
Altera Corporation vii
Preliminary
HardCopy Series Handbook, Volume 1
viii Altera Corporation
Preliminary
About this Handbook
This handbook provides comprehensive information about the Altera®
HardCopy® devices.
How to Contact
For the most up-to-date information about Altera products, refer to the
following table.
Altera
Contact
Method
Website www.altera.com/training
Email custrain@altera.com
Email nacomp@altera.com
Email authorization@altera.com
Address
Typographic
Contact
Technical support Website www.altera.com/support/
Technical training
Product literature Website www.altera.com/literature
Altera literature services Email literature@altera.com
Non-technical (General)
(SoftwareLicensing)
Note to table:
(1) You can also contact your local Altera sales office or sales representative.
This document uses the typographic conventions shown below.
Conventions
Visual Cue Meaning
Bold Type with Initial
Capital Letters
bold type External timing parameters, directory names, project names, disk drive names,
Italic Type with Initial Capital
Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
filenames, filename extensions, and software utility names are shown in bold
type. Examples: f
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
, \qdesigns directory, d: drive, chiptrip.gdf file.
MAX
Altera Corporation ix
Preliminary
HardCopy Series Handbook, Volume 1
Visual Cue Meaning
Italic type Internal timing parameters and variables are shown in italic type.
Examples: t
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading” Title” References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
PIA
, n + 1.
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example:
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword
Courier.
1., 2., 3., and
a., b., c., etc.
● • Bullets are used in a list of items when the sequence of the items is not important.
■
v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.
c
w
r The angled arrow indicates you should press the Enter key.
f The feet direct you to more information on a particular topic.
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
A caution calls attention to a condition or possible situation that can damage or
destroy the product or the user’s work.
A warning calls attention to a condition or possible situation that can cause injury
to the user.
c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
x Altera Corporation
Preliminary
Section I. HardCopy II
Device Family Data Sheet
This section provides designers with the data sheet specifications
HardCopy® II devices. These cpaters contain feature definitions of the
internal architecture, configuration and JTAG boundary-scan testing
information, DC operationg conditions, AC timing parameters, a
reference to power consumption, and ordering information for
HardCopy II devices.
This section contains the following:
■ “Introduction to HardCopy II Devices” on page 1–1
■ “Description, Architecture, and Features” on page 2–1
■ “Boundary-Scan Support” on page 3–1
■ “DC and Switching Specifications and Operating Conditions” on
page 4–1
■ “Quartus II Support for HardCopy II Devices” on page 5–1
■ “Script-Based Design for HardCopy II Devices” on page 6–1
■ “Timing Constraints for HardCopy II Devices” on page 7–1
■ “Migrating Stratix II Device Resources to HardCopy II Devices” on
page 8–1
Revision History
Altera Corporation Section I–1
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Preliminary
Revision History HardCopy Series Handbook, Volume 1
Section I–2 Altera Corporation
Preliminary
H51015-2.6
1. Introduction to HardCopy II Devices
Introduction
Feature Overview
HardCopy® II devices are low-cost, high-performance structured ASICs
with pin-outs, densities, and architecture that complement Stratix®II
devices. HardCopy II device features, such as phase-locked loops (PLLs),
memory, and I/O elements (IOEs), are functionally and electrically
equivalent to the Stratix II FPGA features. The combination of Stratix II
FPGAs for in-system prototype and design verification, HardCopy II
devices for high-volume production, and the Quartus
design, provide a complete, low-risk design solution.
HardCopy II devices improve on the successful and proven methodology
of the two previous generations of HardCopy series devices. Altera
HardCopy II devices use the same base arrays across multiple designs for
a given device density and are customized using only two metal layers.
HardCopy II devices offer up to 90% cost reduction compared to Stratix II
FPGA prototypes.
The Quartus II software provides a complete set of tools, common for
both designing Stratix II FPGA prototypes and for quickly migrating the
design to a HardCopy II companion device. HardCopy II devices are also
supported through other front-end design tools from Synopsys,
Synplicity, and Mentor Graphics
HardCopy II structured ASICs are manufactured on a 1.2 V, 90 nm
all-layer-copper metal fabrication process (up to nine layers of metal).
HardCopy II devices offer the following features:
®
.
®
II software for
®
■ Fine-grained HCell architecture resulting in a low-cost,
high-performance, low-power structured ASIC
■ Customized using only two metal layers for fast turn-around times
and low non-recurring expenses (NRE)
■ Fully tested prototypes are available in approximately 10 to 12 weeks
from the date of your design submission
■ Support for instant-on or instant-on-after-50-ms power-up modes
■ Preserves the design functionality of a Stratix II FPGA prototype
■ 1,000,000 to 3,600,000 usable gates for both logic and DSP functions
Altera Corporation 1–1
September 2008 Preliminary
HardCopy Series Handbook, Volume 1
■ System performance up to 350 MHz
■ Up to 50% power reduction (dynamic and static) for typical designs
compared to Stratix II FPGA prototypes
1 The actual performance and power consumption improvements
■ Internal Memory
● Up to 8,847,360 RAM bits available (including parity bits)
● True dual-port memory, suitable for use in first-in-first-out
■ Phase-Locked Loops (PLLs)
● Up to 16 global clocks with 24 clocking resources per device
● Clock control block supports dynamic clock network
● Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per
■ I/O Standards and Intellectual Property (IP)
● Support for numerous single-ended and differential I/O
● High-speed differential I/O support on up to 116 channels with
● Support for high-speed networking and communications bus
● Support for high-speed external memory, including DDR and
● Support for multiple intellectual property megafunctions from
■ Packaging
● Pin-compatible with Stratix II FPGA prototypes
● Up to 951 user I/O pins available
● Available in wire bond and flip-chip space-saving
mentioned in this datasheet are design-dependent.
(FIFO) buffers
region
enable/disable and dynamic global clock network source
selection
device which provide identical features as the FPGA
counterparts, including spread spectrum, programmable
bandwidth, clock switchover, real-time PLL reconfiguration,
advanced multiplication, and phase shifting
standards such as LVTTL, LVCMOS, PCI, PCI-X, SSTL, HSTL,
and LVDS
dynamic phase alignment (DPA) circuitry for
1-Gigabit-per-second (Gbps) performance
standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransport™ technology, and SFI-4
DDR2 SDRAM, RLDRAM II, QDRII SRAM, and SDR SDRAM
Altera MegaCore® functions, and Altera Megafunction Partners
Program (AMPPSM) megafunctions
FineLine BGA packages (Table 1–3).
1–2 Altera Corporation
Preliminary September 2008
Feature Overview
The HardCopy II device family consists of five devices. Table 1–1
summarizes the features available in the HardCopy II devices.
Table 1–1. HardCopy II Device Family Features
Feature HC210W (1) HC210 HC220 HC230 HC240
ASIC equivalent gates (2) 1,000,000 1,000,000 1,900,000 2,900,000 3,600,000
M4K RAM blocks
(4 Kbits plus parity)
M-RAM blocks
(512 Kbits plus parity)
Total RAM bits
(including parity bits)
Enhanced PLLs 2 2 2 4 4
Fast PLLs 2 2 2 4 8
Maximum user I/O pins (4), (5) 308 334 494 698 951
Notes to Ta b l e 1 – 1:
(1) HC210W devices are in a wire bond package. All other HardCopy II devices and Stratix II FPGAs use a flip-chip
package. Devices in a wire bond package offer different performance and signal integrity characteristics compared
to devices in a flip-chip package.
(2) This is the number of ASIC equivalent gates available in the HardCopy II base array, shared between both adaptive
logic module (ALM) logic and DSP functions from a Stratix II FPGA prototype. Each Stratix II adaptive logic
module (ALM) is equal to approximately 30 ASIC equivalent gates. The number of ASIC equivalent gates usable
is bounded by the number of ALMs in the companion Stratix II FPGA device.
(3) Total number of usable M4K blocks is 768, which allows migration compatibility when prototyping with an
EP2S180 device. This may be different from the Quartus II software total physical M4K count of the HC240.
(4) The I/O pin counts include the dedicated CLK input pins, which can be used for clock signals or data inputs.
(5) The Quartus II I/O pin counts include an additional pin (PLLENA), which is not available as a general-purpose I/O
pin. The PLLENA pin can only be used to enable the PLLs.
190 190 408 614 768 (3)
00269
875,520 875,520 3,059,712 6,368,256 8,847,360
Altera Corporation 1–3
September 2008 Preliminary
HardCopy Series Handbook, Volume 1
Migration and Packaging Overview
HardCopy II devices offer pin-to-pin compatibility to the Stratix II
prototype, which makes them drop-in replacements for the FPGAs.
Therefore, the same system board and software developed for
prototyping and field trials can be retained, enabling the fastest
time-to-market for high-volume production. When migrating a specific
Stratix II FPGA to a HardCopy II device, there are a number of FPGA
prototype choices, as shown in Tab le 1 –2 . Depending on the design
resource needs, designers can choose an appropriate HardCopy II device.
Table 1–2. Stratix II FPGA to HardCopy II Migration Paths
HardCopy II
Device
HC210W
HC210 484-pin FineLine BGA
HC220 672-pin FineLine BGA
HC220 780-pin FineLine BGA
HC230 1,020-pin FineLine BGA
HC240 1,020-pin FineLine BGA
HC240 1,508-pin FineLine BGA
Notes to Ta b l e 1 – 2:
(1) The HC210W device uses a wire bond package while the Stratix II FPGA prototype device uses a pin-compatible
flip-chip package.
(2) Depending on design specific resource utilization, an opportunistic migration path may exist between this device
pair. Be sure to confirm your design is a potential candidate for such a path by fitting with the Quartus II software
and consulting an Altera applications engineer.
484-pin FineLine BGA (1)
Package
EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
vv
vv
Stratix II Device
v
v (2)
v (2)
v
v (2)
vv
v (2)
v
v
1–4 Altera Corporation
Preliminary September 2008
HardCopy II devices are available in the packages shown in Table 1–3.
Table 1–3. HardCopy II Package Options and I/O Pin Counts Notes (1), (2)
Document Revision History
Package
Typ e
484-Pin
FineLine BGA
(3)
Wire bond Flip-chip Flip-chip Flip-chip Flip-chip Flip-chip
484-Pin
FineLine BGA
(3)
672-Pin
FineLine BGA
780-Pin
FineLine BGA
1,020-Pin
FineLine BGA
1,508-Pin
FineLine BGA
Dimension
Pitch (mm) 1.00 1.00 1.00 1.00 1.00 1.00
Area (mm
Length × width
(mm × mm)
2
)
529 529 729 841 1,089 1,600
23 × 23 23 × 23 27 × 27 29 × 29 33 × 33 40 × 40
Device Maximum User I/O Pins
HC210W 308
HC210 334
HC220 492 494
HC230 698
HC240 742 951
Notes to Ta b l e 1 – 3:
(1) The Quartus II I/O pin counts include an additional pin (PLLENA) which is not available as a general-purpose I/O
pin. The PLLENA pin can only be used to enable the PLLs.
(2) The I/O pin counts include the dedicated CLK input pins, which can be used for clock signals or data inputs.
(3) The EP2S90 FPGA prototype uses a 484-pin hybrid FineLine BGA package. For more information, refer to the
Stratix II Device Handbook.
Document
Table 1–4 shows the revision history for this chapter.
Revision History
Table 1–4. Document Revision History (Part 1 of 2)
Date and Document
Version
September 2008,
v2.6
June 2007, v2.5 Minor text edits. —
Altera Corporation 1–5
September 2008 Preliminary
Updated chapter number and metadata. —
Changes Made Summary of Changes
HardCopy Series Handbook, Volume 1
Table 1–4. Document Revision History (Part 2 of 2)
Date and Document
Version
December 2006
v2.4
March 2006, v2.3
October 2005, v2.2. Updated graphics
July 2005, v2.2. Updated graphics
May 2005, v2.0
January 2005
v1.0
● Minor updates for the Quartus II software version 6.1.0
● Merged Table 1-3 and Table 1-4
● Added revision history
● Updated Table 1-1 and Table 1-3.
● Minor edits and clarifications throughout.
● Updated Table 1–1.
● Updated migration process time.
● Updated “Features” section.
Added document to the HardCopy Series Handbook.
Changes Made Summary of Changes
A minor update to the
chapter, due to changes in
the Quartus II software
version 6.1 release.
Merged Table 1-3 and Table
1-4.
1–6 Altera Corporation
Preliminary September 2008
H51016-2.5
2. Description, Architecture, and Features
Introduction
Altera® HardCopy®II devices feature an architecture that provides
high-density, high-performance, and low-power consumption suitable
for a variety of applications. HardCopy II devices are low-cost structured
ASICs with pin-outs, densities, and architecture that complement
®
Stratix
II FPGAs. HardCopy II devices make optimal use of die area and
core resources while offering features that are functionally equivalent to
the Stratix II FPGA. The combination of Stratix II FPGAs for in-system
prototype and design verification, HardCopy II devices for high-volume
®
production, and the Quartus
II design software, provide a complete,
seamless path from prototype to volume production. Table 2–1 provides
an overview of the HardCopy II device features.
Table 2–1. HardCopy II Family Overview (Part 1 of 2)
Feature HC210W (1) HC210 HC220 HC230 HC240
ASIC gates (2) 1,000,000 1,000,000 1,900,000 2,900,000 3,600,000
M4K RAM blocks (4k
bits plus parity)
M-RAM blocks (512k
bits plus parity)
Total RAM bits
(including parity bits)
Enhanced PLLs 2 2 2 4 4
Fast PLLs 2 2 2 4 8
Package (maximum
user I/O pins) (4), (5)
190 190 408 614 768 (3)
00 2 6 9
875,520 875,520 3,059,712 6,368,256 8,847,360
484-pin
FineLine
BGA (308)
484-pin
FineLine BGA
(334)
672-pin
FineLine BGA
(492)
780-pin
FineLine BGA
(494)
1,020-pin
FineLine BGA
(698)
1,020-pin
FineLine BGA
(742)
1,508-pin
FineLine BGA
(951)
Altera Corporation 2–1
September 2008 Preliminary
HardCopy Series Handbook, Volume 1
Table 2–1. HardCopy II Family Overview (Part 2 of 2)
Feature HC210W (1) HC210 HC220 HC230 HC240
FPGA prototype
options
Notes to Ta bl e 2 – 1 :
(1) HC210W devices use a wire bond package. All other HardCopy II devices and Stratix II FPGAs use a flip-chip
package. Devices in a wire bond package offer different performance and signal integrity characteristics compared
to devices in a flip-chip package.
(2) This is the number of ASIC gates available in the HardCopy II base array for both logic and DSP functions that can
be implemented in a Stratix II FPGA prototype.
(3) Total number of usable M4K blocks is 768, which allows migration compatibility when prototyping with an
EP2S180 device. This may be different from the Quartus II software total physical M4K count of the HC240.
(4) The I/O pin counts include the dedicated clock input pins, which can be used for clock signals or data inputs.
(5) The Quartus II I/O pin counts include an additional pin (PLLENA), which is not available as a general-purpose I/O
pin. The PLLENA pin can only be used to enable the PLLs.
EP2S30
EP2S60
EP2S90
EP2S30
EP2S60
EP2S90
EP2S60
EP2S90
EP2S130
EP2S90
EP2S130
EP2S180
EP2S180
Functional Description
The HardCopy II device family provides greater flexibility to design with
FPGA prototypes before moving to structured ASICs for production.
Before seamlessly migrating to the HardCopy II structured ASIC,
designers can prototype and test their design functionality using a
Stratix II FPGA. There are multiple options for the prototype FPGA,
allowing designers to choose the right HardCopy II device for volume
production and maximum cost savings. The Quartus II design software
includes features such as the Device Resource Guide, to help select the
optimal HardCopy II device based on the design requirements.
f For more information on the Device Resource Guide, refer to the
Quartus II Support for HardCopy II Devices chapter in the HardCopy Series
Handbook.
HardCopy II devices require minimal involvement from the designer in
the device migration process. Additionally, unlike ASICs, the designer is
not required to generate test benches, test vectors, or timing and
functional simulations since prototyping is performed using an FPGA.
HardCopy II devices consist of base arrays that are common to all designs
for a particular device density, with design-specific customization done
using two metal layers. The reprogrammable FPGA logic, routing,
memory, and FPGA configuration-related logic are stripped from
HardCopy II devices. Removing all programmable and configuration
resources and replacing them with direct metal connections results in
considerable die size reduction and cost savings. A fine-grain architecture
consisting of an array of HCells extends the die reduction and cost
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Preliminary September 2008
savings, which results in low-cost structured ASICs with
high-performance and low-power suitable for a wide variety of
applications.
The SRAM configuration cells of the Stratix II FPGAs are replaced in
HardCopy II devices with metal connections, which define the function
of logic, memory, phase-locked loop (PLL), and I/O elements (IOEs) in
the device. These resources are interconnected using metallization layers.
Once a HardCopy II device is manufactured, the functionality of the
device is fixed.
HardCopy II devices are manufactured using the same 90-nm process
technology and operate using the same core voltage (1.2 V) as Stratix II
FPGAs. Additionally, almost all architectural features in HardCopy II
devices are functionally equivalent to features found in the Stratix II
FPGA architecture. HardCopy II devices feature HCells, memory blocks,
PLLs, and IOEs (Figure 2–1).
Figure 2–1. Example Block Diagram of HC230 Device Note (1)
M4K RAM Blocks
of HCells
Array
Array
of HCells
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Array
of HCells
M4K RAM Blocks
IOE IOE
Fast
PLL
Fast
PLL
Array
of HCells
IOEs
M-RAM Block
Functional Description
Array
of HCells
Enhanced
Array
PLL
of HCells
Note to Figure 2–1:
(1) Figure 2–1 shows a graphical representation of the device floor plan. A detailed floor plan is available in the
Quartus II software.
Altera Corporation 2–3
September 2008 Preliminary
HardCopy Series Handbook, Volume 1
HardCopy II and Stratix II Similarities and Differences
HardCopy II devices preserve the functionality of Stratix II FPGAs.
Implementation of these architectural features in HardCopy II structured
ASICs matches Stratix II FPGA implementation, with a few exceptions.
Table 2–2 shows a qualitative comparison of HardCopy II device feature
implementation versus Stratix II FPGA feature implementation. Other
sections within this chapter provide details on similarities and differences
of a particular HardCopy II feature.
Table 2–2. HardCopy II Device vs. Stratix II FPGA Feature Implementation
Feature Equivalent Different
Logic blocks
DSP blocks
Memory
Clock networks
PLLs
I/O features
Configuration (1)
Note to Ta bl e 2 – 2 :
(1) HardCopy II structured ASICs do not need to be configured upon power-up.
The major similarities and differences between Stratix II FPGAs and
HardCopy II devices are highlighted below:
v
v
v
v
v
v
v
■ HardCopy II may result in a power reduction of up to 50% than an
equivalent Stratix II FPGAs operating at the same frequency. Power
consumption is design dependent and is a direct result of design
performance and resource utilization.
■ HardCopy II devices offer up to 100% performance improvement
when compared to Stratix II FPGA prototypes. The performance
improvement is achieved by efficient use of logic blocks, metal
interconnect optimization, die size reduction, and customized signal
buffering.
■ Logic blocks, known as HCells, are the basic building block of the
core logic in HardCopy II devices and replace Stratix II adaptive logic
modules (ALMs). HCells implement logic and DSP functions.
■ DSP block functions are implemented using HCells, instead of
dedicated DSP blocks.
■ M4K and M-RAM memory blocks can implement various types of
memory (the same as Stratix II FPGAs), with or without parity,
including true dual-port, simple dual-port, and single-port RAM,
ROM, and first-in first-out (FIFO) buffers.
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Preliminary September 2008
HardCopy II and Stratix II Similarities and Differences
■ Unlike Stratix II FPGAs, the HardCopy II M4K block contents cannot
be pre-loaded with a Memory Initialization File (.mif) when used as
RAM. When used as ROM, HardCopy II M4K blocks are initialized
to the ROM contents.
■ When used as RAM, and you select the non-registered output mode,
HardCopy II M4K and M-RAM blocks power up with outputs
unknown. In Stratix II FPGAs, M4K blocks power up with outputs
cleared, while M-RAM blocks power up with outputs unknown. If
registered outputs mode is selected, the outputs are cleared on both
the M4K and M-RAM blocks in HardCopy II.
■ The memory contents are unknown under both instances.
■ All HardCopy II clock network features are the same as in Stratix II
FPGAs.
■ Enhanced PLL and fast PLL implementations in HardCopy II
devices are the same as in Stratix II FPGAs.
■ All Stratix II I/O features and supported I/O standards are offered
in HardCopy II devices.
■ The Joint Test Action Group (JTAG) boundary scan order and length
in HardCopy II devices is different than that of the Stratix II FPGA.
Use a HardCopy II boundary-scan description language (BSDL) file
that describes the re-ordered and shortened boundary scan chain.
■ Unlike Stratix II devices, HardCopy II devices are customized using
two metal layers. Therefore, configuration circuitry is not required.
FPGA configuration emulation and other configuration modes,
including remote system upgrades and design security using
configuration bitstream encryption, are not supported in
HardCopy II devices.
■ Even though configuration is not required, the CRC_ERROR pin
function is supported by the HardCopy II using Quartus II software
version 6.0 and above. There is no need to recompile the Stratix II
design to eliminate this feature.
1 Only supplementary information to highlight HardCopy II
similarities and differences compared to the Stratix II FPGA
architecture and functionality is provided in this chapter. For
more information on similarities and differences of available
resources of the HardCopy II, refer to the Migrating Stratix II
Device Resources to HardCopy II Devices chapter of this Handbook.
In addition, the Stratix II Device Handbook has detailed
explanations of architectural features and functions that are
similar to the HardCopy II devices.
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HardCopy Series Handbook, Volume 1
HCells
HardCopy II devices are built using an array of fine-grained architecture
blocks called HCells. HCells are a collection of logic transistors based on
1.2 V, 90 nm process technology, similar to Stratix II devices. The
construction of logic using HCells allows flexible functionality such that
when HCells are combined, all viable logic combinations of Stratix II
functionality are replicated. These HCells constitute the array of HCells
area in Figure 2–1. Only HCells needed to implement the customer
design are assembled together, which optimizes HCell utilization. The
unused area of the HCell logic fabric is powered down, resulting in
significant power savings compared with the Stratix II FPGA prototype.
The Quartus II software uses the library of pre-characterized HCell
macros to place Stratix II ALM and DSP configurations into the
HardCopy II HCell-based logic fabric. An HCell macro defines how a
group of HCells are connected together within the array. HCell macros
can construct all combinations of combinational logic, adder, and register
functions that can be implemented by a Stratix II ALM. HCells not used
for ALM configurations can be used to implement DSP block functions.
Based on design requirements, the Quartus II software will chose the
appropriate HCell macros to implement the design functionality. For
example, Stratix II ALMs offer flexible look-up table (LUT) blocks,
registers, arithmetic blocks, and LAB-wide control signals. In
HardCopy II devices, if your design requires these architectural elements,
the Quartus II synthesis tool will map the design to the appropriate
HCells, resulting in improved design performance compared to the
Stratix II FPGA prototype.
Stratix II FPGAs have dedicated DSP blocks to implement various DSP
functions. Stratix II DSP blocks consist of a multiplier block, an
adder/subtractor/accumulator block, a summation block, input and
output interfaces, and input and output registers. In HardCopy II
devices, HCell macros implement Stratix II DSP block functionality with
area efficiency and performance on par with the dedicated DSP blocks in
Stratix II FPGAs.
There are eight HCell macros which implement the eight supported
modes of operation for the Stratix II DSP block:
■ 9 × 9 multiplier
■ 9 × 9 two-multiplier adder (9 × 9 complex multiply)
■ 9 × 9 four-multiplier adder
■ 18 × 18 multiplier
■ 18 × 18 two-multiplier adder (18 × 18 complex multiply)
■ 18 × 18 four-multiplier adder
■ 52-bit (18 × 18) multiplier-accumulator
■ 36 × 36 multiplier
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Preliminary September 2008
Only HCells that are required to implement the design’s DSP functions
Input
Registers
18 × 18
Multiplier
18 × 18
Multiplier
18 × 18
Multiplier
18 × 18
Multiplier
Input
Registers
Output
Registers
Output
Registers
Adder/
Subtractor/
Accumulator
Block
Input
Registers
18 × 18
Multiplier
Output
Registers
Used portions of the block
Unused portions of the block
Stratix II DSP Block HardCopy II HCell-Based Logic Fabric
These elements are implemented
using HCell macros.
Unused logic area can
be used to perform other
logic functions.
are enabled. HCells not needed for DSP functions can be used for ALM
configurations, which results in efficient logic usage. In addition to area
management, the placement of these HCell macros allows for optimized
routing and performance.
An example of efficient logic area usage can be seen when comparing the
18 × 18 multiplier implementation in Stratix II FPGAs using the dedicated
DSP block versus the implementation in HardCopy II devices using
HCells. If the Stratix II DSP function only calls for one 18 × 18 multiplier,
the other three 18 × 18 multipliers and the DSP block’s adder output block
are not used (Figure 2–2). In HardCopy II devices, the HCell-based logic
fabric that is not used for DSP functions can be used to implement other
combinational logic, adder, and register functions.
Figure 2–2. Stratix II DSP Block versus HardCopy II HCell 18 × 18-Bit Multiplier Implementation
HCells
Altera Corporation 2–7
September 2008 Preliminary
HardCopy II devices support all Stratix II DSP configurations (9 × 9,
18 × 18, and 36 × 36 multipliers) and all Stratix II DSP block features, such
as dynamic sign controls, dynamic addition/subtraction, saturation,
rounding, and dynamic input shift registers, except for dynamic mode
switching.
HardCopy Series Handbook, Volume 1
Dynamic mode switching allows the designer to set up each Stratix II
DSP block to dynamically switch between the following three modes:
■ Up to four 18-bit independent multipliers
■ Up to two 8-bit multiplier-accumulators
■ One 36-bit multiplier
Each half of a Stratix II DSP block has separate mode control signals.
Since DSP block functions are implemented in HardCopy II devices using
HCells, HardCopy II devices do not support dynamic mode switching. If
this feature is used, the Quartus II software flags the DSP implementation
and does not allow you to migrate the design. The fitter reports that all
HardCopy II devices are not compatible with the design. To migrate your
Stratix II design to a HardCopy II companion device, disable dynamic
switching in the DSP blocks.
f For more information on the Stratix II DSP operational modes, refer to
the Stratix II Device Handbook.
Embedded Memory
Table 2–3. HardCopy II Embedded Memory Resources
Feature HC210W HC210 HC220 HC230 HC240
M4K RAM blocks (4 Kbits) 190 190 408 614 768
M-RAM blocks (512 Kbits) 0 0 2 6 9
Total RAM bits (bits) 875,520 875,520 3,059,712 6,368,256 8,847,360
HardCopy II memory blocks can implement various types of memory
with or without parity, including true dual-port, simple dual-port, and
single-port RAM, ROM, and FIFO buffers. HardCopy II devices support
the same memory functions and features as Stratix II FPGAs.
Functionally, the memory in both devices are identical. However, the
number of available memory blocks differs based on density (Table 2–3).
Since device functionality is fixed in HardCopy II devices, M4K block
contents cannot be preloaded or initialized with a MIF when they are
configured as RAM. When the M4K blocks are used as ROM, they will
initialize to the design’s ROM contents.
When using the non-registered outputs mode for the HardCopy II M4K
memory block, the outputs power up uninitialized. When using the
registered outputs mode for the HardCopy II M4K memory blocks, the
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Preliminary September 2008
PLLs and Clock Networks
outputs are cleared on power up. The designer needs to take these into
consideration when designing logic that might evaluate the initial
power-up values of the memory block.
HardCopy II embedded memory consists of M4K and M-RAM memory
blocks and have a one-to-one mapping from Stratix II M4K and M-RAM
resources. Table 2–4 shows the size and features of the different RAM
blocks.
f For more information on the Stratix II memory block features, refer to
the Stratix II Device Handbook.
PLLs and Clock
Networks
Both HardCopy II enhanced and fast PLLs are feature rich, supporting
advanced capabilities such as clock switchover, reconfigurable phase
shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs are used
for general-purpose clock management, supporting multiplication,
division, phase shifting, and programmable duty cycle. In addition,
enhanced PLLs support external clock feedback mode, spread-spectrum
clocking, and counter cascading. Fast PLLs offer high speed outputs to
manage the high-speed differential I/O interfaces.
1 All Stratix II PLL features are supported by HardCopy II PLLs.
Similar to Stratix II FPGAs, HardCopy II devices also support a
power-down mode where unused clock networks can be disabled.
HardCopy II and Stratix II clock control blocks support dynamic
selection of the input clock from up to four possible sources, giving the
designer the flexibility to choose from multiple (up to four) clock sources.
Altera Corporation 2–9
September 2008 Preliminary
HardCopy Series Handbook, Volume 1
Table 2–4. HardCopy II Embedded Memory Features (Part 1 of 2) Notes (1), (2), (3)
Feature M4K Blocks M-RAM Blocks
Maximum performance (1), (4) 350 MHz 350 MHz
Total RAM bits (including parity bits) 4,608 589,824
Configurations 4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
Parity bits
Byte enable
Pack mode
Address clock enable
Single-port memory
Simple dual-port memory
True dual-port memory
Embedded shift register
ROM
FIFO buffer
Simple dual-port mixed width support
True dual-port mixed width support
Memory initialization file (.mif)
Mixed-clock mode
Power-up condition (2) Outputs unknown Outputs unknown
Register clears (3) Output registers only Output registers only
Same-port read-during-write New data available at positive clock
Mixed-port read-during-write Outputs set to unknown or old data Unknown output
Not supported, except in ROM
edge
vv
vv
vv
vv
vv
vv
vv
v
v
vv
vv
vv
mode
vv
New data available at positive clock
edge
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
Not supported
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Preliminary September 2008
PLLs and Clock Networks
Table 2–4. HardCopy II Embedded Memory Features (Part 2 of 2) Notes (1), (2), (3)
Feature M4K Blocks M-RAM Blocks
Note to Ta bl e 2 – 4 :
(1) Maximum performance information is preliminary until device characterization.
(2) The memory cells power up randomly, so reads before writes are not valid. Make sure you write to the memory
location before you read it.
(3) Even though the output register is cleared, the memory cells power up randomly. So reads before write are not
valid. Make sure you write to the memory location first before reading it.
(4) Violating the setup or hold time requirements on the address registers could corrupt the memory contents. This
applies to both read and write operations.
Enhanced and Fast PLLs
The number of PLLs available differs based on density (Table 2–5).
Table 2–5. HardCopy II PLLs
Feature HC210W HC210 HC220 HC230 HC240
Enhanced PLLs 22244
Fast PLLs 22248
The target HardCopy II device may not support the same number of
enhanced PLLs as the prototyping Stratix II FPGA. However, since
HardCopy II enhanced PLLs and fast PLLs offer a similar feature set
(Table 2–7 on page 2–13), a fast PLL could be used in place of an enhanced
PLL. The type of PLL used in the design should be chosen using the
Quartus II software to accommodate the resources available in the
HardCopy II device.
Table 2–6 shows which PLLs are available in each device density.
Figure 2–3 shows the location of each PLL. During the prototyping stage
using the FPGA, you must select the appropriate number of enhanced
and fast PLLs that will be used in your HardCopy II device. Use Ta bl e 2 –6
to ensure that the FPGA prototyping design uses the same PLL resources
available in the HardCopy II device.
Table 2–6. HardCopy II PLLs Available (Part 1 of 2) Note (1)
Fast PLLs Enhanced PLLs
Device
123478910561112
HC210W
HC210
Altera Corporation 2–11
September 2008 Preliminary
vv vv
vv vv
HardCopy Series Handbook, Volume 1
FPLL8CLK
CLK[3..0]
1
2
8
612
CLK[7..4]
PLLs
Table 2–6. HardCopy II PLLs Available (Part 2 of 2) Note (1)
Device
Fast PLLs Enhanced PLLs
123478910561112
HC220
HC230
HC240
Note to Ta bl e 2 – 6 :
(1) PLL performance in the HC210W device may differ from the Stratix II FPGA prototype.
vv vv
vv vv vvvv
vvvvvvvvvvvv
Figure 2–3. HardCopy II PLL Locations Notes (1), (2)
Notes to Figure 2–3:
(1) The PLLs may be located in the periphery or in the core of the device.
(2) This is the die-level top view of the device and is only a graphical representation of the PLL locations.
2–12 Altera Corporation
Preliminary September 2008
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