ALTERA HardCopy II Service Manual

HardCopy II Device Handbook, Volume 1

Preliminary Information

101 Innovation Drive
San Jose, CA 95134
www.altera.com

H5V1-4.5

Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des­ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. Mentor Graphics and ModelSim are registered trademarks of Mentor Graphics
Corporation. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and
foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current
specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and servic es at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service de­scribed herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest
version of device specifications before relying on any published information and before placing orders for products or services.

ii Altera Corporation

Preliminary

Contents

Chapter Revision Dates .......................................................................... vii

About this Handbook ............................................................................... ix

How to Contact Altera ............................................................................................................................. ix

Typographic Conventions ....................................................................................................................... ix

Section I. HardCopy II Device Family Data Sheet

Revision History .................................................................................................................................... 1–1

Chapter 1. Introduction to HardCopy II Devices

Introduction ............................................................................................................................................ 1–1

Feature Overview .................................................................................................................................. 1–1

Migration and Packaging Overview ................................................................................................... 1–4

Document Revision History ................................................................................................................. 1–5

Chapter 2. Description, Architecture, and Features

Introduction ............................................................................................................................................ 2–1

Functional Description .......................................................................................................................... 2–2

HardCopy II and Stratix II Similarities and Differences .................................................................. 2–4

HCells ...................................................................................................................................................... 2–6

Embedded Memory ............................................................................................................................... 2–8

PLLs and Clock Networks .................................................................................................................... 2–9

Enhanced and Fast PLLs ............................................................................................................... 2–11

Clock Networks .............................................................................................................................. 2–14

I/O Structure and Features ................................................................................................................ 2–14

General Purpose IOE ..................................................................................................................... 2–20

Memory Interface IOE ................................................................................................................... 2–22

High-Speed IOE .............................................................................................................................. 2–25

Power-Up Modes ................................................................................................................................. 2–27

Document Revision History ............................................................................................................... 2–28

Chapter 3. Boundary-Scan Support

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 3–1

Boundary-Scan Test (BST) on HardCopy II Devices ................................................................... 3–3

Document Revision History ................................................................................................................. 3–5

Altera Corporation iii

Preliminary

HardCopy Series Handbook, Volume 1

Chapter 4. DC and Switching Specifications and Operating Conditions

Introduction ............................................................................................................................................ 4–1

Absolute Maximum Ratings ................................................................................................................ 4–1

Recommended Operating Conditions ................................................................................................ 4–2

DC Electrical Characteristics ................................................................................................................ 4–3

I/O Standard Specifications ................................................................................................................. 4–4

Bus Hold Specifications ...................................................................................................................... 4–18

On-Chip Termination Specifications ................................................................................................ 4–19

Pin Capacitance .................................................................................................................................... 4–21

Maximum Input Clock Rates ............................................................................................................. 4–22

Maximum Output Clock Rates .......................................................................................................... 4–25

HighSpeed I/O Specifications ........................................................................................................... 4–35

PLL Timing Specifications .................................................................................................................. 4–39

External Memory Interface Specifications ....................................................................................... 4–42

Hot Socketing ....................................................................................................................................... 4–45

Electrostatic Discharge ........................................................................................................................ 4–46

Document Revision History ............................................................................................................... 4–49

Chapter 5. Quartus II Support for HardCopy II Devices

HardCopy II Device Support ............................................................................................................... 5–1

HardCopy II Design Benefits .......................................................................................................... 5–1

Quartus II Features for HardCopy II Planning ............................................................................ 5–2

HardCopy II Development Flow ......................................................................................................... 5–3

Designing the Stratix II FPGA First ............................................................................................... 5–4

Designing the HardCopy II Device First ...................................................................................... 5–6

HardCopy II Device Resource Guide ................................................................................................. 5–7

HardCopy II Companion Device Selection ..................................................................................... 5–10

HardCopy II Recommended Settings in the Quartus II Software ................................................ 5–12

Limit DSP and RAM to HardCopy II Device Resources .......................................................... 5–12

Enable Design Assistant to Run During Compile ..................................................................... 5–12

Timing Settings ............................................................................................................................... 5–13

Constraints for Clock Effect Characteristics ............................................................................... 5–15

Quartus II Software Features Supported for HardCopy II Designs ....................................... 5–17

Performing ECOs with Change Manager and Chip Planner ........................................................ 5–19

Migrating One-to-One Changes ................................................................................................... 5–20

Migrating Changes that must be Implemented Differently ..................................................... 5–21

Changes that Cannot be Migrated ............................................................................................... 5–22

Overall Migration Flow ...................................................................................................................... 5–22

Preparing the Revisions ................................................................................................................. 5–22

Applying ECO Changes ................................................................................................................ 5–23

Formal Verification of Stratix II and HardCopy II Revisions ....................................................... 5–24

HardCopy II Utilities Menu ............................................................................................................... 5–25

Companion Revisions .................................................................................................................... 5–26

Compiling the HardCopy II Companion Revision ................................................................... 5–28

Comparing HardCopy II and Stratix II Companion Revisions ............................................... 5–29

Generate HardCopy II Handoff Report ...................................................................................... 5–29

Archive HardCopy II Handoff Files ............................................................................................ 5–29

iv Altera Corporation

Preliminary

Contents

HardCopy II Advisor ..................................................................................................................... 5–30

HardCopy II Floorplan View ........................................................................................................ 5–33

Conclusion ............................................................................................................................................ 5–34

Document Revision History ............................................................................................................... 5–35

Chapter 6. Script-Based Design for HardCopy II Devices

Introduction ............................................................................................................................................ 6–1

Tcl Support in the Quartus II Software .............................................................................................. 6–1

Interactive Tcl Shell .......................................................................................................................... 6–2

Command-Line Processing ............................................................................................................. 6–5

The HardCopy II Design Flow ............................................................................................................ 6–6

Creating a New Project ......................................................................................................................... 6–8

Creating a Stratix II Prototype Project ........................................................................................... 6–8

Opening a Project ............................................................................................................................. 6–9

Closing a Project ............................................................................................................................... 6–9

New Project Example Script ......................................................................................................... 6–10

Making Global Assignments .............................................................................................................. 6–11

Initializing a HardCopy II Design ............................................................................................... 6–11

The Design Assistant ..................................................................................................................... 6–15

Example Tcl Script for Making Global Assignments ................................................................ 6–16

Pin Assignments ............................................................................................................................. 6–17

Setting I/O Type and Parameters ................................................................................................ 6–17

I/O Assignment Example Script .................................................................................................. 6–20

Assigning Timing Constraints ........................................................................................................... 6–20

Planning Design Timing Constraints .......................................................................................... 6–20

Specifying System Clocks .............................................................................................................. 6–21

Input/Output Timing .................................................................................................................... 6–22

Creating Timing Exceptions ......................................................................................................... 6–23

Example of TimeQuest SDC Constraints .................................................................................... 6–24

Example of Classic Timing Analyzer Tcl Script ......................................................................... 6–25

Compiling the Stratix II Prototype Design ...................................................................................... 6–25

Compiling the HardCopy II Design ................................................................................................. 6–27

Understanding Report Files ............................................................................................................... 6–28

Comparing FPGA and HardCopy Revisions .................................................................................. 6–29

Performing Static Timing Analysis ................................................................................................... 6–30

Static Timing Analysis in the Quartus II Software .................................................................... 6–30

Static Timing Analysis in Primetime ........................................................................................... 6–31

HardCopy II Example Tcl Script ....................................................................................................... 6–32

Top-Level Example Script demo_design.tcl ............................................................................... 6–32

Global Assignments Script global_assignments.tcl ................................................................... 6–33

Pin Assignments Script pin_assignments.tcl .............................................................................. 6–34

TimeQuest Constraint File demo_design.sdc ............................................................................ 6–34

Timing Assignments Script timing_assignments.tcl ................................................................. 6–35

Summary ............................................................................................................................................... 6–35

Document Revision History ............................................................................................................... 6–36

Altera Corporation v

Preliminary

HardCopy Series Handbook, Volume 1

Chapter 7. Timing Constraints for HardCopy II Devices

Introduction ............................................................................................................................................ 7–1

HardCopy II versus Stratix II Timing ........................................................................................... 7–2

Internal Register-to-Register Timing ............................................................................................. 7–2

I/O Path Timing ............................................................................................................................... 7–4

Clock Distribution Effects ............................................................................................................... 7–4

PLL Characteristics .......................................................................................................................... 7–5

HardCopy II Timing Closure Methodology ...................................................................................... 7–5

HardCopy II Timing Closure Flow ................................................................................................ 7–5

Using the TimeQuest Timing Analyzer ........................................................................................ 7–8

Using Classic Timing Analyzer .................................................................................................... 7–11

Quartus II Timing Related Checks and Settings ........................................................................ 7–11

Constraining Timing of HardCopy Series Devices ........................................................................ 7–14

Clock Definitions ............................................................................................................................ 7–15

Primary Input Port Timing ........................................................................................................... 7–17

Primary Output Port Timing ........................................................................................................ 7–18

Unsupported HardCopy II Timing Constraints for Classic Timing Analyzer ........................... 7–21

Conclusion ............................................................................................................................................ 7–22

Document Revision History ............................................................................................................... 7–23

Chapter 8. Migrating Stratix II Device Resources to HardCopy II Devices

Stratix II and HardCopy II Migration Options ................................................................................. 8–2

I/O Support and Planning ................................................................................................................... 8–5

HardCopy II I/O Banks .................................................................................................................. 8–7

User I/O Count Per IOE Type and Bank Location ...................................................................... 8–9

HardCopy II Supported I/O Standards ....................................................................................... 8–9

External Memory Interface Support ................................................................................................. 8–13

LVDS, SERDES, and DPA Compatibility ................................................................................... 8–14

Programmable Drive Strength Support ...................................................................................... 8–15

On-Chip Termination .......................................................................................................................... 8–17

On-Chip Series Termination ......................................................................................................... 8–18

On-Chip Series Termination without Calibration ..................................................................... 8–18

On-Chip Series Termination with Calibration ........................................................................... 8–19

Differential I/O Termination ........................................................................................................ 8–20

Stratix II and HardCopy II Companion Memory Blocks ............................................................... 8–21

M512 Options .................................................................................................................................. 8–22

M4K Utilization .............................................................................................................................. 8–24

M-RAM Compatibility .................................................................................................................. 8–24

PLL Planning and Utilization ............................................................................................................ 8–26

Global and Local Signals .................................................................................................................... 8–30

Stratix II ALM Adaptation into HardCopy II Logic ....................................................................... 8–31

HardCopy II DSP Implementation from Stratix II DSP Blocks .................................................... 8–33

JTAG BST and Extended Functions .................................................................................................. 8–35

Power Up and Configuration Compatibility ................................................................................... 8–36

Conclusion ............................................................................................................................................ 8–39

More Information ................................................................................................................................ 8–40

Document Revision History ............................................................................................................... 8–40

vi Altera Corporation

Preliminary

Chapter Revision Dates

The chapters in this book, HardCopy Series Handbook, Volume 1, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.

Chapter 1. Introduction to HardCopy II Devices

Revised: September 2008
Part number: H51015-2.6

Chapter 2. Description, Architecture, and Features

Revised: September 2008
Part number: H51016-2.5

Chapter 3. Boundary-Scan Support

Revised: September 2008
Part number: H51017-2.4

Chapter 4. DC and Switching Specifications and Operating Conditions

Revised: September 2008
Part number: H51018-3.3

Chapter 5. Quartus II Support for HardCopy II Devices

Revised: September 2008
Part number: H51022-2.5

Chapter 6. Script-Based Design for HardCopy II Devices

Revised: September 2008
Part number: H51025-1.3

Chapter 7. Timing Constraints for HardCopy II Devices

Revised: September 2008
Part number: H51028-2.2

Chapter 8. Migrating Stratix II Device Resources to HardCopy II Devices

Revised: September 2008
Part number: H51024-1.4

Altera Corporation vii

Preliminary

HardCopy Series Handbook, Volume 1

viii Altera Corporation

Preliminary

About this Handbook

This handbook provides comprehensive information about the Altera®
HardCopy® devices.

How to Contact

For the most up-to-date information about Altera products, refer to the
following table.

Altera

Contact
Method

Website www.altera.com/training

Email [e-mail]

Email [e-mail]

Email [e-mail]

Address

Typographic

Contact

Technical support Website www.altera.com/support/

Technical training

Product literature Website www.altera.com/literature

Altera literature services Email [e-mail]

Non-technical (General)

(SoftwareLicensing)

Note to table:

(1) You can also contact your local Altera sales office or sales representative.

This document uses the typographic conventions shown below.

Conventions

Visual Cue Meaning

Bold Type with Initial
Capital Letters

bold type External timing parameters, directory names, project names, disk drive names,

Italic Type with Initial Capital
Letters

Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.

filenames, filename extensions, and software utility names are shown in bold
type. Examples: f

Document titles are shown in italic type with initial capital letters. Example: AN 75:

High-Speed Board Design.

, \qdesigns directory, d: drive, chiptrip.gdf file.

MAX

Altera Corporation ix

Preliminary

HardCopy Series Handbook, Volume 1

Visual Cue Meaning

Italic type Internal timing parameters and variables are shown in italic type.

Examples: t

Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:

Delete key, the Options menu.

“Subheading” Title” References to sections within a document and titles of on-line help topics are

shown in quotation marks. Example: “Typographic Conventions.”

PIA

, n + 1.

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,

tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For
example:
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword
Courier.

1., 2., 3., and
a., b., c., etc.

● • Bullets are used in a list of items when the sequence of the items is not important.

■

v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.

c

w

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.

A caution calls attention to a condition or possible situation that can damage or
destroy the product or the user’s work.

A warning calls attention to a condition or possible situation that can cause injury
to the user.

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an

SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

x Altera Corporation

Preliminary

Section I. HardCopy II

Device Family Data Sheet

This section provides designers with the data sheet specifications
HardCopy® II devices. These cpaters contain feature definitions of the
internal architecture, configuration and JTAG boundary-scan testing
information, DC operationg conditions, AC timing parameters, a
reference to power consumption, and ordering information for
HardCopy II devices.

This section contains the following:

■ “Introduction to HardCopy II Devices” on page 1–1

■ “Description, Architecture, and Features” on page 2–1

■ “Boundary-Scan Support” on page 3–1

■ “DC and Switching Specifications and Operating Conditions” on

page 4–1

■ “Quartus II Support for HardCopy II Devices” on page 5–1

■ “Script-Based Design for HardCopy II Devices” on page 6–1

■ “Timing Constraints for HardCopy II Devices” on page 7–1

■ “Migrating Stratix II Device Resources to HardCopy II Devices” on

page 8–1

Revision History

Altera Corporation Section I–1

Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.

Preliminary

Revision History HardCopy Series Handbook, Volume 1

Section I–2 Altera Corporation

Preliminary

H51015-2.6

1. Introduction to HardCopy II Devices

Introduction

Feature Overview

HardCopy® II devices are low-cost, high-performance structured ASICs
with pin-outs, densities, and architecture that complement Stratix®II
devices. HardCopy II device features, such as phase-locked loops (PLLs),
memory, and I/O elements (IOEs), are functionally and electrically
equivalent to the Stratix II FPGA features. The combination of Stratix II
FPGAs for in-system prototype and design verification, HardCopy II
devices for high-volume production, and the Quartus
design, provide a complete, low-risk design solution.

HardCopy II devices improve on the successful and proven methodology
of the two previous generations of HardCopy series devices. Altera
HardCopy II devices use the same base arrays across multiple designs for
a given device density and are customized using only two metal layers.
HardCopy II devices offer up to 90% cost reduction compared to Stratix II
FPGA prototypes.

The Quartus II software provides a complete set of tools, common for
both designing Stratix II FPGA prototypes and for quickly migrating the
design to a HardCopy II companion device. HardCopy II devices are also
supported through other front-end design tools from Synopsys,
Synplicity, and Mentor Graphics

HardCopy II structured ASICs are manufactured on a 1.2 V, 90 nm
all-layer-copper metal fabrication process (up to nine layers of metal).
HardCopy II devices offer the following features:

®

.

®

II software for

®

■ Fine-grained HCell architecture resulting in a low-cost,

high-performance, low-power structured ASIC

■ Customized using only two metal layers for fast turn-around times

and low non-recurring expenses (NRE)

■ Fully tested prototypes are available in approximately 10 to 12 weeks

from the date of your design submission

■ Support for instant-on or instant-on-after-50-ms power-up modes

■ Preserves the design functionality of a Stratix II FPGA prototype

■ 1,000,000 to 3,600,000 usable gates for both logic and DSP functions

Altera Corporation 1–1
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

■ System performance up to 350 MHz

■ Up to 50% power reduction (dynamic and static) for typical designs

compared to Stratix II FPGA prototypes

1 The actual performance and power consumption improvements

■ Internal Memory

● Up to 8,847,360 RAM bits available (including parity bits)

● True dual-port memory, suitable for use in first-in-first-out

■ Phase-Locked Loops (PLLs)

● Up to 16 global clocks with 24 clocking resources per device

● Clock control block supports dynamic clock network

● Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per

■ I/O Standards and Intellectual Property (IP)

● Support for numerous single-ended and differential I/O

● High-speed differential I/O support on up to 116 channels with

● Support for high-speed networking and communications bus

● Support for high-speed external memory, including DDR and

● Support for multiple intellectual property megafunctions from

■ Packaging

● Pin-compatible with Stratix II FPGA prototypes

● Up to 951 user I/O pins available

● Available in wire bond and flip-chip space-saving

mentioned in this datasheet are design-dependent.

(FIFO) buffers

region

enable/disable and dynamic global clock network source
selection

device which provide identical features as the FPGA
counterparts, including spread spectrum, programmable
bandwidth, clock switchover, real-time PLL reconfiguration,
advanced multiplication, and phase shifting

standards such as LVTTL, LVCMOS, PCI, PCI-X, SSTL, HSTL,
and LVDS

dynamic phase alignment (DPA) circuitry for
1-Gigabit-per-second (Gbps) performance

standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransport™ technology, and SFI-4

DDR2 SDRAM, RLDRAM II, QDRII SRAM, and SDR SDRAM

Altera MegaCore® functions, and Altera Megafunction Partners
Program (AMPPSM) megafunctions

FineLine BGA packages (Table 1–3).

1–2 Altera Corporation

Preliminary September 2008

Feature Overview

The HardCopy II device family consists of five devices. Table 1–1
summarizes the features available in the HardCopy II devices.

Table 1–1. HardCopy II Device Family Features

Feature HC210W (1) HC210 HC220 HC230 HC240

ASIC equivalent gates (2) 1,000,000 1,000,000 1,900,000 2,900,000 3,600,000

M4K RAM blocks
(4 Kbits plus parity)

M-RAM blocks
(512 Kbits plus parity)

Total RAM bits
(including parity bits)

Enhanced PLLs 2 2 2 4 4

Fast PLLs 2 2 2 4 8

Maximum user I/O pins (4), (5) 308 334 494 698 951

Notes to Ta b l e 1 – 1:

(1) HC210W devices are in a wire bond package. All other HardCopy II devices and Stratix II FPGAs use a flip-chip

package. Devices in a wire bond package offer different performance and signal integrity characteristics compared
to devices in a flip-chip package.

(2) This is the number of ASIC equivalent gates available in the HardCopy II base array, shared between both adaptive

logic module (ALM) logic and DSP functions from a Stratix II FPGA prototype. Each Stratix II adaptive logic
module (ALM) is equal to approximately 30 ASIC equivalent gates. The number of ASIC equivalent gates usable
is bounded by the number of ALMs in the companion Stratix II FPGA device.

(3) Total number of usable M4K blocks is 768, which allows migration compatibility when prototyping with an

EP2S180 device. This may be different from the Quartus II software total physical M4K count of the HC240.
(4) The I/O pin counts include the dedicated CLK input pins, which can be used for clock signals or data inputs.
(5) The Quartus II I/O pin counts include an additional pin (PLLENA), which is not available as a general-purpose I/O

pin. The PLLENA pin can only be used to enable the PLLs.

190 190 408 614 768 (3)

00269

875,520 875,520 3,059,712 6,368,256 8,847,360

Altera Corporation 1–3
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

Migration and Packaging Overview

HardCopy II devices offer pin-to-pin compatibility to the Stratix II
prototype, which makes them drop-in replacements for the FPGAs.
Therefore, the same system board and software developed for
prototyping and field trials can be retained, enabling the fastest
time-to-market for high-volume production. When migrating a specific
Stratix II FPGA to a HardCopy II device, there are a number of FPGA
prototype choices, as shown in Tab le 1 –2 . Depending on the design
resource needs, designers can choose an appropriate HardCopy II device.

Table 1–2. Stratix II FPGA to HardCopy II Migration Paths

HardCopy II

Device

HC210W

HC210 484-pin FineLine BGA

HC220 672-pin FineLine BGA

HC220 780-pin FineLine BGA

HC230 1,020-pin FineLine BGA

HC240 1,020-pin FineLine BGA

HC240 1,508-pin FineLine BGA

Notes to Ta b l e 1 – 2:

(1) The HC210W device uses a wire bond package while the Stratix II FPGA prototype device uses a pin-compatible

flip-chip package.
(2) Depending on design specific resource utilization, an opportunistic migration path may exist between this device

pair. Be sure to confirm your design is a potential candidate for such a path by fitting with the Quartus II software

and consulting an Altera applications engineer.

484-pin FineLine BGA (1)

Package

EP2S30 EP2S60 EP2S90 EP2S130 EP2S180

vv
vv

Stratix II Device

v

v (2)
v (2)

v

v (2)

vv

v (2)

v
v

1–4 Altera Corporation

Preliminary September 2008

HardCopy II devices are available in the packages shown in Table 1–3.

Table 1–3. HardCopy II Package Options and I/O Pin Counts Notes (1), (2)

Document Revision History

Package

Typ e

484-Pin

FineLine BGA

(3)

Wire bond Flip-chip Flip-chip Flip-chip Flip-chip Flip-chip

484-Pin

FineLine BGA

(3)

672-Pin

FineLine BGA

780-Pin

FineLine BGA

1,020-Pin

FineLine BGA

1,508-Pin

FineLine BGA

Dimension

Pitch (mm) 1.00 1.00 1.00 1.00 1.00 1.00

Area (mm

Length × width
(mm × mm)

2

)

529 529 729 841 1,089 1,600

23 × 23 23 × 23 27 × 27 29 × 29 33 × 33 40 × 40

Device Maximum User I/O Pins

HC210W 308

HC210 334

HC220 492 494

HC230 698

HC240 742 951

Notes to Ta b l e 1 – 3:

(1) The Quartus II I/O pin counts include an additional pin (PLLENA) which is not available as a general-purpose I/O

pin. The PLLENA pin can only be used to enable the PLLs.
(2) The I/O pin counts include the dedicated CLK input pins, which can be used for clock signals or data inputs.
(3) The EP2S90 FPGA prototype uses a 484-pin hybrid FineLine BGA package. For more information, refer to the

Stratix II Device Handbook.

Document

Table 1–4 shows the revision history for this chapter.

Revision History

Table 1–4. Document Revision History (Part 1 of 2)

Date and Document

Version

September 2008,
v2.6

June 2007, v2.5 Minor text edits. —

Altera Corporation 1–5
September 2008 Preliminary

Updated chapter number and metadata. —

Changes Made Summary of Changes

HardCopy Series Handbook, Volume 1

Table 1–4. Document Revision History (Part 2 of 2)

Date and Document

Version

December 2006
v2.4

March 2006, v2.3

October 2005, v2.2. Updated graphics

July 2005, v2.2. Updated graphics

May 2005, v2.0

January 2005
v1.0

● Minor updates for the Quartus II software version 6.1.0

● Merged Table 1-3 and Table 1-4

● Added revision history

● Updated Table 1-1 and Table 1-3.

● Minor edits and clarifications throughout.

● Updated Table 1–1.

● Updated migration process time.

● Updated “Features” section.

Added document to the HardCopy Series Handbook.

Changes Made Summary of Changes

A minor update to the

chapter, due to changes in

the Quartus II software

version 6.1 release.

Merged Table 1-3 and Table

1-4.

1–6 Altera Corporation

Preliminary September 2008

H51016-2.5

2. Description, Architecture, and Features

Introduction

Altera® HardCopy®II devices feature an architecture that provides
high-density, high-performance, and low-power consumption suitable
for a variety of applications. HardCopy II devices are low-cost structured
ASICs with pin-outs, densities, and architecture that complement

®

Stratix

II FPGAs. HardCopy II devices make optimal use of die area and
core resources while offering features that are functionally equivalent to
the Stratix II FPGA. The combination of Stratix II FPGAs for in-system
prototype and design verification, HardCopy II devices for high-volume

®

production, and the Quartus

II design software, provide a complete,
seamless path from prototype to volume production. Table 2–1 provides
an overview of the HardCopy II device features.

Table 2–1. HardCopy II Family Overview (Part 1 of 2)

Feature HC210W (1) HC210 HC220 HC230 HC240

ASIC gates (2) 1,000,000 1,000,000 1,900,000 2,900,000 3,600,000

M4K RAM blocks (4k
bits plus parity)

M-RAM blocks (512k
bits plus parity)

Total RAM bits
(including parity bits)

Enhanced PLLs 2 2 2 4 4

Fast PLLs 2 2 2 4 8

Package (maximum
user I/O pins) (4), (5)

190 190 408 614 768 (3)

00 2 6 9

875,520 875,520 3,059,712 6,368,256 8,847,360

484-pin

FineLine

BGA (308)

484-pin

FineLine BGA

(334)

672-pin

FineLine BGA

(492)

780-pin

FineLine BGA

(494)

1,020-pin

FineLine BGA

(698)

1,020-pin

FineLine BGA

(742)

1,508-pin

FineLine BGA

(951)

Altera Corporation 2–1
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

Table 2–1. HardCopy II Family Overview (Part 2 of 2)

Feature HC210W (1) HC210 HC220 HC230 HC240

FPGA prototype
options

Notes to Ta bl e 2 – 1 :

(1) HC210W devices use a wire bond package. All other HardCopy II devices and Stratix II FPGAs use a flip-chip

package. Devices in a wire bond package offer different performance and signal integrity characteristics compared
to devices in a flip-chip package.

(2) This is the number of ASIC gates available in the HardCopy II base array for both logic and DSP functions that can

be implemented in a Stratix II FPGA prototype.

(3) Total number of usable M4K blocks is 768, which allows migration compatibility when prototyping with an

EP2S180 device. This may be different from the Quartus II software total physical M4K count of the HC240.
(4) The I/O pin counts include the dedicated clock input pins, which can be used for clock signals or data inputs.
(5) The Quartus II I/O pin counts include an additional pin (PLLENA), which is not available as a general-purpose I/O

pin. The PLLENA pin can only be used to enable the PLLs.

EP2S30
EP2S60
EP2S90

EP2S30
EP2S60
EP2S90

EP2S60
EP2S90

EP2S130

EP2S90
EP2S130
EP2S180

EP2S180

Functional Description

The HardCopy II device family provides greater flexibility to design with
FPGA prototypes before moving to structured ASICs for production.
Before seamlessly migrating to the HardCopy II structured ASIC,
designers can prototype and test their design functionality using a
Stratix II FPGA. There are multiple options for the prototype FPGA,
allowing designers to choose the right HardCopy II device for volume
production and maximum cost savings. The Quartus II design software
includes features such as the Device Resource Guide, to help select the
optimal HardCopy II device based on the design requirements.

f For more information on the Device Resource Guide, refer to the

Quartus II Support for HardCopy II Devices chapter in the HardCopy Series
Handbook.

HardCopy II devices require minimal involvement from the designer in
the device migration process. Additionally, unlike ASICs, the designer is
not required to generate test benches, test vectors, or timing and
functional simulations since prototyping is performed using an FPGA.

HardCopy II devices consist of base arrays that are common to all designs
for a particular device density, with design-specific customization done
using two metal layers. The reprogrammable FPGA logic, routing,
memory, and FPGA configuration-related logic are stripped from
HardCopy II devices. Removing all programmable and configuration
resources and replacing them with direct metal connections results in
considerable die size reduction and cost savings. A fine-grain architecture
consisting of an array of HCells extends the die reduction and cost

2–2 Altera Corporation

Preliminary September 2008

savings, which results in low-cost structured ASICs with
high-performance and low-power suitable for a wide variety of
applications.

The SRAM configuration cells of the Stratix II FPGAs are replaced in
HardCopy II devices with metal connections, which define the function
of logic, memory, phase-locked loop (PLL), and I/O elements (IOEs) in
the device. These resources are interconnected using metallization layers.
Once a HardCopy II device is manufactured, the functionality of the
device is fixed.

HardCopy II devices are manufactured using the same 90-nm process
technology and operate using the same core voltage (1.2 V) as Stratix II
FPGAs. Additionally, almost all architectural features in HardCopy II
devices are functionally equivalent to features found in the Stratix II
FPGA architecture. HardCopy II devices feature HCells, memory blocks,
PLLs, and IOEs (Figure 2–1).

Figure 2–1. Example Block Diagram of HC230 Device Note (1)

M4K RAM Blocks

of HCells

Array

Array

of HCells

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

Array

of HCells

M4K RAM Blocks

IOE IOE

Fast
PLL

Fast
PLL

Array

of HCells

IOEs

M-RAM Block

Functional Description

Array

of HCells

Enhanced

Array

PLL

of HCells

Note to Figure 2–1:

(1) Figure 2–1 shows a graphical representation of the device floor plan. A detailed floor plan is available in the

Quartus II software.

Altera Corporation 2–3
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

HardCopy II and Stratix II Similarities and Differences

HardCopy II devices preserve the functionality of Stratix II FPGAs.
Implementation of these architectural features in HardCopy II structured
ASICs matches Stratix II FPGA implementation, with a few exceptions.

Table 2–2 shows a qualitative comparison of HardCopy II device feature

implementation versus Stratix II FPGA feature implementation. Other
sections within this chapter provide details on similarities and differences
of a particular HardCopy II feature.

Table 2–2. HardCopy II Device vs. Stratix II FPGA Feature Implementation

Feature Equivalent Different

Logic blocks

DSP blocks

Memory

Clock networks

PLLs

I/O features

Configuration (1)

Note to Ta bl e 2 – 2 :

(1) HardCopy II structured ASICs do not need to be configured upon power-up.

The major similarities and differences between Stratix II FPGAs and
HardCopy II devices are highlighted below:

v
v
v
v

v
v

v

■ HardCopy II may result in a power reduction of up to 50% than an

equivalent Stratix II FPGAs operating at the same frequency. Power
consumption is design dependent and is a direct result of design
performance and resource utilization.

■ HardCopy II devices offer up to 100% performance improvement

when compared to Stratix II FPGA prototypes. The performance
improvement is achieved by efficient use of logic blocks, metal
interconnect optimization, die size reduction, and customized signal
buffering.

■ Logic blocks, known as HCells, are the basic building block of the

core logic in HardCopy II devices and replace Stratix II adaptive logic
modules (ALMs). HCells implement logic and DSP functions.

■ DSP block functions are implemented using HCells, instead of

dedicated DSP blocks.

■ M4K and M-RAM memory blocks can implement various types of

memory (the same as Stratix II FPGAs), with or without parity,
including true dual-port, simple dual-port, and single-port RAM,
ROM, and first-in first-out (FIFO) buffers.

2–4 Altera Corporation

Preliminary September 2008

HardCopy II and Stratix II Similarities and Differences

■ Unlike Stratix II FPGAs, the HardCopy II M4K block contents cannot

be pre-loaded with a Memory Initialization File (.mif) when used as
RAM. When used as ROM, HardCopy II M4K blocks are initialized
to the ROM contents.

■ When used as RAM, and you select the non-registered output mode,

HardCopy II M4K and M-RAM blocks power up with outputs
unknown. In Stratix II FPGAs, M4K blocks power up with outputs
cleared, while M-RAM blocks power up with outputs unknown. If
registered outputs mode is selected, the outputs are cleared on both
the M4K and M-RAM blocks in HardCopy II.

■ The memory contents are unknown under both instances.

■ All HardCopy II clock network features are the same as in Stratix II

FPGAs.

■ Enhanced PLL and fast PLL implementations in HardCopy II

devices are the same as in Stratix II FPGAs.

■ All Stratix II I/O features and supported I/O standards are offered

in HardCopy II devices.

■ The Joint Test Action Group (JTAG) boundary scan order and length

in HardCopy II devices is different than that of the Stratix II FPGA.
Use a HardCopy II boundary-scan description language (BSDL) file
that describes the re-ordered and shortened boundary scan chain.

■ Unlike Stratix II devices, HardCopy II devices are customized using

two metal layers. Therefore, configuration circuitry is not required.
FPGA configuration emulation and other configuration modes,
including remote system upgrades and design security using
configuration bitstream encryption, are not supported in
HardCopy II devices.

■ Even though configuration is not required, the CRC_ERROR pin

function is supported by the HardCopy II using Quartus II software
version 6.0 and above. There is no need to recompile the Stratix II
design to eliminate this feature.

1 Only supplementary information to highlight HardCopy II

similarities and differences compared to the Stratix II FPGA
architecture and functionality is provided in this chapter. For
more information on similarities and differences of available
resources of the HardCopy II, refer to the Migrating Stratix II
Device Resources to HardCopy II Devices chapter of this Handbook.
In addition, the Stratix II Device Handbook has detailed
explanations of architectural features and functions that are
similar to the HardCopy II devices.

Altera Corporation 2–5
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

HCells

HardCopy II devices are built using an array of fine-grained architecture
blocks called HCells. HCells are a collection of logic transistors based on

1.2 V, 90 nm process technology, similar to Stratix II devices. The
construction of logic using HCells allows flexible functionality such that
when HCells are combined, all viable logic combinations of Stratix II
functionality are replicated. These HCells constitute the array of HCells
area in Figure 2–1. Only HCells needed to implement the customer
design are assembled together, which optimizes HCell utilization. The
unused area of the HCell logic fabric is powered down, resulting in
significant power savings compared with the Stratix II FPGA prototype.

The Quartus II software uses the library of pre-characterized HCell
macros to place Stratix II ALM and DSP configurations into the
HardCopy II HCell-based logic fabric. An HCell macro defines how a
group of HCells are connected together within the array. HCell macros
can construct all combinations of combinational logic, adder, and register
functions that can be implemented by a Stratix II ALM. HCells not used
for ALM configurations can be used to implement DSP block functions.

Based on design requirements, the Quartus II software will chose the
appropriate HCell macros to implement the design functionality. For
example, Stratix II ALMs offer flexible look-up table (LUT) blocks,
registers, arithmetic blocks, and LAB-wide control signals. In
HardCopy II devices, if your design requires these architectural elements,
the Quartus II synthesis tool will map the design to the appropriate
HCells, resulting in improved design performance compared to the
Stratix II FPGA prototype.

Stratix II FPGAs have dedicated DSP blocks to implement various DSP
functions. Stratix II DSP blocks consist of a multiplier block, an
adder/subtractor/accumulator block, a summation block, input and
output interfaces, and input and output registers. In HardCopy II
devices, HCell macros implement Stratix II DSP block functionality with
area efficiency and performance on par with the dedicated DSP blocks in
Stratix II FPGAs.

There are eight HCell macros which implement the eight supported
modes of operation for the Stratix II DSP block:

■ 9 × 9 multiplier

■ 9 × 9 two-multiplier adder (9 × 9 complex multiply)

■ 9 × 9 four-multiplier adder

■ 18 × 18 multiplier

■ 18 × 18 two-multiplier adder (18 × 18 complex multiply)

■ 18 × 18 four-multiplier adder

■ 52-bit (18 × 18) multiplier-accumulator

■ 36 × 36 multiplier

2–6 Altera Corporation

Preliminary September 2008

Only HCells that are required to implement the design’s DSP functions

Input

Registers

18 × 18

Multiplier

18 × 18

Multiplier

18 × 18

Multiplier

18 × 18

Multiplier

Input

Registers

Output

Registers

Output

Registers

Adder/

Subtractor/

Accumulator

Block

Input

Registers

18 × 18

Multiplier

Output

Registers

Used portions of the block

Unused portions of the block

Stratix II DSP Block HardCopy II HCell-Based Logic Fabric

These elements are implemented

using HCell macros.

Unused logic area can

be used to perform other

logic functions.

are enabled. HCells not needed for DSP functions can be used for ALM
configurations, which results in efficient logic usage. In addition to area
management, the placement of these HCell macros allows for optimized
routing and performance.

An example of efficient logic area usage can be seen when comparing the
18 × 18 multiplier implementation in Stratix II FPGAs using the dedicated
DSP block versus the implementation in HardCopy II devices using
HCells. If the Stratix II DSP function only calls for one 18 × 18 multiplier,
the other three 18 × 18 multipliers and the DSP block’s adder output block
are not used (Figure 2–2). In HardCopy II devices, the HCell-based logic
fabric that is not used for DSP functions can be used to implement other
combinational logic, adder, and register functions.

Figure 2–2. Stratix II DSP Block versus HardCopy II HCell 18 × 18-Bit Multiplier Implementation

HCells

Altera Corporation 2–7
September 2008 Preliminary

HardCopy II devices support all Stratix II DSP configurations (9 × 9,
18 × 18, and 36 × 36 multipliers) and all Stratix II DSP block features, such
as dynamic sign controls, dynamic addition/subtraction, saturation,
rounding, and dynamic input shift registers, except for dynamic mode
switching.

HardCopy Series Handbook, Volume 1

Dynamic mode switching allows the designer to set up each Stratix II
DSP block to dynamically switch between the following three modes:

■ Up to four 18-bit independent multipliers

■ Up to two 8-bit multiplier-accumulators

■ One 36-bit multiplier

Each half of a Stratix II DSP block has separate mode control signals.
Since DSP block functions are implemented in HardCopy II devices using
HCells, HardCopy II devices do not support dynamic mode switching. If
this feature is used, the Quartus II software flags the DSP implementation
and does not allow you to migrate the design. The fitter reports that all
HardCopy II devices are not compatible with the design. To migrate your
Stratix II design to a HardCopy II companion device, disable dynamic
switching in the DSP blocks.

f For more information on the Stratix II DSP operational modes, refer to

the Stratix II Device Handbook.

Embedded Memory

Table 2–3. HardCopy II Embedded Memory Resources

Feature HC210W HC210 HC220 HC230 HC240

M4K RAM blocks (4 Kbits) 190 190 408 614 768

M-RAM blocks (512 Kbits) 0 0 2 6 9

Total RAM bits (bits) 875,520 875,520 3,059,712 6,368,256 8,847,360

HardCopy II memory blocks can implement various types of memory
with or without parity, including true dual-port, simple dual-port, and
single-port RAM, ROM, and FIFO buffers. HardCopy II devices support
the same memory functions and features as Stratix II FPGAs.

Functionally, the memory in both devices are identical. However, the
number of available memory blocks differs based on density (Table 2–3).

Since device functionality is fixed in HardCopy II devices, M4K block
contents cannot be preloaded or initialized with a MIF when they are
configured as RAM. When the M4K blocks are used as ROM, they will
initialize to the design’s ROM contents.

When using the non-registered outputs mode for the HardCopy II M4K
memory block, the outputs power up uninitialized. When using the
registered outputs mode for the HardCopy II M4K memory blocks, the

2–8 Altera Corporation

Preliminary September 2008

PLLs and Clock Networks

outputs are cleared on power up. The designer needs to take these into
consideration when designing logic that might evaluate the initial
power-up values of the memory block.

HardCopy II embedded memory consists of M4K and M-RAM memory
blocks and have a one-to-one mapping from Stratix II M4K and M-RAM
resources. Table 2–4 shows the size and features of the different RAM
blocks.

f For more information on the Stratix II memory block features, refer to

the Stratix II Device Handbook.

PLLs and Clock
Networks

Both HardCopy II enhanced and fast PLLs are feature rich, supporting
advanced capabilities such as clock switchover, reconfigurable phase
shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs are used
for general-purpose clock management, supporting multiplication,
division, phase shifting, and programmable duty cycle. In addition,
enhanced PLLs support external clock feedback mode, spread-spectrum
clocking, and counter cascading. Fast PLLs offer high speed outputs to
manage the high-speed differential I/O interfaces.

1 All Stratix II PLL features are supported by HardCopy II PLLs.

Similar to Stratix II FPGAs, HardCopy II devices also support a
power-down mode where unused clock networks can be disabled.
HardCopy II and Stratix II clock control blocks support dynamic
selection of the input clock from up to four possible sources, giving the
designer the flexibility to choose from multiple (up to four) clock sources.

Altera Corporation 2–9
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

Table 2–4. HardCopy II Embedded Memory Features (Part 1 of 2) Notes (1), (2), (3)

Feature M4K Blocks M-RAM Blocks

Maximum performance (1), (4) 350 MHz 350 MHz

Total RAM bits (including parity bits) 4,608 589,824

Configurations 4K × 1

2K × 2

1K × 4
512 × 8
512 × 9

256 × 16
256 × 18
128 × 32
128 × 36

Parity bits

Byte enable

Pack mode

Address clock enable

Single-port memory

Simple dual-port memory

True dual-port memory

Embedded shift register

ROM

FIFO buffer

Simple dual-port mixed width support

True dual-port mixed width support

Memory initialization file (.mif)

Mixed-clock mode

Power-up condition (2) Outputs unknown Outputs unknown

Register clears (3) Output registers only Output registers only

Same-port read-during-write New data available at positive clock

Mixed-port read-during-write Outputs set to unknown or old data Unknown output

Not supported, except in ROM

edge

vv
vv
vv
vv
vv
vv
vv
v
v
vv
vv
vv

mode

vv

New data available at positive clock
edge

64K × 8

64K × 9
32K × 16
32K × 18
16K × 32
16K × 36

8K × 64

8K × 72
4K × 128
4K × 144

Not supported

2–10 Altera Corporation

Preliminary September 2008

PLLs and Clock Networks

Table 2–4. HardCopy II Embedded Memory Features (Part 2 of 2) Notes (1), (2), (3)

Feature M4K Blocks M-RAM Blocks

Note to Ta bl e 2 – 4 :

(1) Maximum performance information is preliminary until device characterization.
(2) The memory cells power up randomly, so reads before writes are not valid. Make sure you write to the memory

location before you read it.

(3) Even though the output register is cleared, the memory cells power up randomly. So reads before write are not

valid. Make sure you write to the memory location first before reading it.

(4) Violating the setup or hold time requirements on the address registers could corrupt the memory contents. This

applies to both read and write operations.

Enhanced and Fast PLLs

The number of PLLs available differs based on density (Table 2–5).

Table 2–5. HardCopy II PLLs

Feature HC210W HC210 HC220 HC230 HC240

Enhanced PLLs 22244

Fast PLLs 22248

The target HardCopy II device may not support the same number of
enhanced PLLs as the prototyping Stratix II FPGA. However, since
HardCopy II enhanced PLLs and fast PLLs offer a similar feature set
(Table 2–7 on page 2–13), a fast PLL could be used in place of an enhanced
PLL. The type of PLL used in the design should be chosen using the
Quartus II software to accommodate the resources available in the
HardCopy II device.

Table 2–6 shows which PLLs are available in each device density.
Figure 2–3 shows the location of each PLL. During the prototyping stage

using the FPGA, you must select the appropriate number of enhanced
and fast PLLs that will be used in your HardCopy II device. Use Ta bl e 2 –6
to ensure that the FPGA prototyping design uses the same PLL resources
available in the HardCopy II device.

Table 2–6. HardCopy II PLLs Available (Part 1 of 2) Note (1)

Fast PLLs Enhanced PLLs

Device

123478910561112

HC210W

HC210

Altera Corporation 2–11
September 2008 Preliminary

vv vv
vv vv

HardCopy Series Handbook, Volume 1

FPLL8CLK

CLK[3..0]

1
2

8

612

CLK[7..4]

PLLs

Table 2–6. HardCopy II PLLs Available (Part 2 of 2) Note (1)

Device

Fast PLLs Enhanced PLLs

123478910561112

HC220

HC230

HC240

Note to Ta bl e 2 – 6 :

(1) PLL performance in the HC210W device may differ from the Stratix II FPGA prototype.

vv vv
vv vv vvvv
vvvvvvvvvvvv

Figure 2–3. HardCopy II PLL Locations Notes (1), (2)

Notes to Figure 2–3:

(1) The PLLs may be located in the periphery or in the core of the device.
(2) This is the die-level top view of the device and is only a graphical representation of the PLL locations.

2–12 Altera Corporation

Preliminary September 2008

PLLs and Clock Networks

PLL functionality in HardCopy II devices remains the same as in Stratix II
FPGA PLLs. Therefore, the HardCopy II PLLs support PLL
reconfiguration (the PLL can be dynamically configured in user mode).

HardCopy II enhanced and fast PLLs support a one-to-one mapping from
Stratix II PLL resources. Ta bl e 2 –7 shows the features of the different
PLLs. For more information on the Stratix II PLL features, refer to the
Stratix II Device Handbook.

Table 2–7. HardCopy II PLL Features

Feature Enhanced PLL Fast PLL

Clock multiplication and division m/(n × post-scale counter) (1) m/(n × post-scale counter) (2)

Phase shift Down to 125-ps increments (3) Down to 125-ps increments (3)

Clock switchover vv (4)
PLL reconfiguration vv
Reconfigurable bandwidth vv
Spread-spectrum clocking v
Programmable duty cycle vv

Number of clock outputs per PLL (5) 64

Number of dedicated external clock outputs
per PLL

Number of feedback clock inputs per PLL 1 (7)

Three differential or six singled­ended

(6)

Notes to Ta bl e 2 – 7 :

(1) For enhanced PLLs, m and n range from 1 to 512 and post-scale counters range from 1 to 512 with 50% duty cycle.

For non-50% duty-cycle clock outputs, post-scale counters range from 1 to 256.

(2) For fast PLLs, n can range from 1 to 4. The post-scale and m counters range from 1 to 32. For non-50% duty-cycle

clock outputs, post-scale counters range from 1 to 16.

(3) The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by eight. The

supported phase shift range is from 125 to 250 ps. HardCopy II devices can shift all output frequencies in
increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide

parameters. For non-50% duty cycle clock outputs post-scale counters range from 1 to 256.
(4) HardCopy II fast PLLs only support manual clock switchover.
(5) The clock outputs can be driven to internal clock networks or to a pin.
(6) The PLL clock outputs of the fast PLLs can drive to any I/O pin to be used as an external clock output. For

high-speed differential I/O pins, the device uses a data channel to generate the transmitter output clock

(txclkout).
(7) If the design uses external feedback input pins, you will lose one (or two, if f

clock output pin.

is differential) dedicated external

BIN

Altera Corporation 2–13
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

Clock Networks

There are 16 clock pins (CLK[15..0]) in HardCopy II devices that can
drive either the global- or regional-clock networks. The CLK pins can
drive clock ports or data inputs.

HardCopy II devices provide 16 dedicated global-clock networks and
32 regional-clock networks; the same as in Stratix II FPGAs. These clocks
are organized to provide 24 unique clock sources per device quadrant
with low skew and delay. This clocking scheme provides up to 48 unique
clock domains within the entire HardCopy II device. Table 2–8 lists the
clock resources and features available in HardCopy II devices.

Table 2–8. Clock Network Resources and Features Available in HardCopy II Devices

Resources and Features Availability

Number of global clock networks 16

Number of regional clock networks 32

Global clock input sources Clock input pins, PLL outputs, logic array

Regional clock input sources Clock input pins, PLL outputs, logic array

Number of unique clock sources in a quadrant 24 (16 global clocks and 8 regional clocks)

Number of unique clock sources in the entire device 48 (16 global clocks and 32 regional clocks)

Power-down mode Global- and regional-clock networks,

dual-regional-clock region

Clocking regions for high fan-out applications Quadrant region, dual-regional, entire device via global-

or regional-clock networks

HardCopy II devices also support the same features as the Stratix II clock
control block, which is available for each global- and regional-clock
network. The control block has two functions:

■ Clock source selection (dynamic selection for global clocks):

You user can either dynamically select between two PLL outputs,
between two clock pins (CLKp or CLKn), or a combination of the
clock pins or PLL outputs.

■ Clock power-down (dynamic clock enable or disable):

In HardCopy II devices, you can dynamically turn the clock off or on
in user-mode.

I/O Structure and Features

2–14 Altera Corporation

Preliminary September 2008

The structure and features of the HardCopy II IOE remains the same as in
Stratix II. Any feature implemented in Stratix II IOEs can be migrated to
Hardcopy II IOEs.

I/O Structure and Features

The IOE feature set in HardCopy II devices can be classified in one of
three categories:

■ General purpose IOEs—The most commonly used I/O type in

designs.

■ Memory Interface IOEs—Includes features to interface with

common external memory standards.

■ High-speed IOEs—Supports high-speed data transmission and

reception.

All I/O pins in Stratix II FPGAs support general-purpose I/O standards,
which includes the LVTTL and LVCMOS I/O standards. In Stratix II
FPGAs, the PCI clamping diode and memory interfaces are supported on
the top and bottom I/O pins, while high-speed interfaces are supported
on the left and right side I/O pins of the device.

The new general purpose IOEs in HardCopy II devices are a cost saving
and area efficient advantage. The complex memory interface and the
high-speed IOE circuitry is removed to save die area while still offering
the more commonly-used features. The memory interface IOE supports
all the features available in the general purpose IOE. The high-speed IOE
also supports all the same features and I/O standards as the general
purpose IOE, except for the PCI clamping diode (supported on the
bottom general purpose IOEs in HC210 and HC220 devices).

In order to increase the I/O area efficiency of HardCopy II devices, the
features available on any given IOE depends on the location.

Table 2–9 shows which I/O standards are supported by the different IOE

types.

Table 2–9. HardCopy II Supported I/O Standards (Part 1 of 3)

Level (V) Memory

V

I/O Standard Type

CCIO

Input Output

3.3-V LVTTL/
LV CM O S

2.5-V LVTTL/
LV CM O S

1.8-V LVTTL/
LV CM O S

1.5-V LVCMOS Single-ended 1.8/1.5 1.5

SSTL-2 class I Voltage

Altera Corporation 2–15
September 2008 Preliminary

Single-ended 3.3/2.5 3.3

Single-ended 3.3/2.5 2.5

Single-ended 1.8/1.5 1.8

2.5 2.5

referenced

Interface

IOEs

vvv
vvv
vvv

vvv
v

General

Purpose IOEs

High-Speed

IOEs

HardCopy Series Handbook, Volume 1

Table 2–9. HardCopy II Supported I/O Standards (Part 2 of 3)

V

Level (V) Memory

I/O Standard Type

SSTL-2 class II Voltage

referenced

SSTL-18 class I Voltage

referenced

SSTL-18 class II Voltage

referenced

1.8-V HSTL class I Voltage
referenced

1.8-V HSTL class II Voltage
referenced

1.5-V HSTL Class I Voltage
referenced

1.5-V HSTL Class II Voltage
referenced

PCI/PCI-X Single-ended 3.3 3.3

Differential SSTL-2
class I and II input

Differential SSTL-2
class I and II output

Differential SSTL-18
class I and II input

Differential SSTL-18
class I and II output

1.8-V differential

HSTL class I and II
input

1.8-V differential

HSTL class I and II
output

1.5-V differential

HSTL class I and II
input

1.5-V differential

HSTL class I and II
output

LVDS Differential 2.5 2.5 (5) (4), (6)

HyperTransport™
technology

Pseudo

differential (1)

Pseudo

differential (1)

Pseudo

differential (1)

Pseudo

differential (1)

Pseudo

differential (1)

Pseudo

Differential (1)

Pseudo

differential (1)

Pseudo

Differential (1)

Differential 2.5 2.5 (5) (4), (6)

CCIO

Input Output

2.5 2.5

1.8 1.8

1.8 1.8

1.8 1.8

1.8 1.8

1.5 1.5

1.5 1.5

3.3/2.5/

1.8/1.5

2.5 (3)

3.3/2.5/

1.8/1.5

1.8 (3)

3.3/2.5/

1.8/1.5

1.8 (3)

3.3/2.5/

1.8/1.5

1.5 (3)

Interface

IOEs

v
v
v
v
v
v
v

v (2) v (2)

(3)

(3)

(3)

(3)

General

Purpose IOEs

High-Speed

IOEs

v
v

2–16 Altera Corporation

Preliminary September 2008

I/O Structure and Features

Table 2–9. HardCopy II Supported I/O Standards (Part 3 of 3)

V

Level (V) Memory

I/O Standard Type

LVPECL Differential 3.3/2.5/

Notes to Ta bl e 2 – 9 :

(1) Pseudo-differential HSTL and SSTL inputs only use the positive-polarity input in the speed path. The negative

input is not connected internally. Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with

the second output programmed as inverted. This is similar to a Stratix II device implementation.
(2) The PCI clamping diode is only supported on the I/O pins on the top and bottom sides of the device.
(3) This I/O standard is only supported on the DQS, CLK and PLL_FB input pins or on the PLL_OUT output pins.
(4) This I/O standard is only supported on the bottom CLK and PLL_FB input pins or on the bottom PLL_OUT output

pins.
(5) This I/O standard is only supported on the CLK and PLL_FB input pins or on the PLL_OUT output pins.
(6) Also supported on CLK9 and CLK11 pins.
(7) This I/O standard is only supported on CLK and PLL_FB input pins.
(8) LVPECL input I/O standard is supported on the top and bottom CLK and PLL_FB input pins. LVPECL output I/O

standard is supported on the top and bottom PLL_OUT output pins. LVPECL support is similar to Stratix II devices.

CCIO

Input Output

(8) (8) (8)

1.8/1.5

Interface

IOEs

General

Purpose IOEs

High-Speed

IOEs

The three types of IOEs are located in different areas of the device and are
described in the following sections. HardCopy II devices have eight I/O
banks, just as in Stratix II FPGAs. Figures 2–4 through 2–6 show which
I/O type each bank supports.

Altera Corporation 2–17
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

s

s

Figure 2–4. I/O Type Support in HC210 and HC220 Devices Notes (1), (2)

Bank 2

High-Speed IOEs

Bank 1

High-Speed IOEs

PLL 1

PLL 2

Bank 3

Memory Interface IOEs

I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/

LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V

HSTL, 1.5-V HSTL & PCI/PCI-X I/O standards.

CLK, PLL_FB input pins & PLL_OUT output

pins support differential SSTL, differential HSTL,

LVDS & HyperTransport technology. CLK & PLL_FB

pins support LVPECL. DQS input pins support

differential SSTL and differential HSTL I/O standards.

I/O Banks 1 & 2 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS, 1.5-V
LVCMOS, LVDS & HyperTransport Technology

I/O banks 7 & 8 support 3.3-V, 2.5-V, 1.8-V LVTTL/

LVCMOS, 1.5-V LVCMOS & PCI/PCI-X I/O standards.

CLK, PLL_FB input pins & PLL_OUT output

pins support differential SSTL, differential HSTL,

LVDS & HyperTransport technology. CLK &

Bank 8

General Purpose IOEs

Bank 9

PLL_FB pins support LVPECL.

PLL 6

Bank 10

PLL 5

Bank 4

Memory Interface IOEs

I/O Banks 5 & 6 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS
&1.5-V LVCMOS

Bank 7

General Purpose IOEs

Bank 5
General-Purpose IOE

Bank 6
General-Purpose IOE

2–18 Altera Corporation

Preliminary September 2008

Figure 2–5. I/O Type Support in HC230 Devices Notes (1), (2)

s

s

Bank 11

PLL 11

Bank 9

PLL 5

Bank 2

High-Speed IOEs

PLL 7

Bank 3

Memory Interface IOEs

I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/
LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V

pins support differential SSTL, differential HSTL,

LVDS & HyperTransport technology. CLK & PLL_FB

differential SSTL and differential HSTL I/O standards.

HSTL, 1.5-V HSTL & PCI/PCI-X I/O standards.

CLK, PLL_FB input pins & PLL_OUT output

pins support LVPECL. DQS input pins support

Bank 4

Memory Interface IOEs

I/O Structure and Features

Bank 5
General-Purpose IOE

Bank 1

High-Speed IOEs

PLL 1

PLL 2

PLL 8

I/O Banks 1 & 2 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS, 1.5-V
LVCMOS, LVDS & HyperTransport Technology

I/O banks 7 & 8 support 3.3-V, 2.5-V, 1.8-V LVTTL/

LVCMOS, 1.5-V LVCMOS & PCI/PCI-X I/O standards.

CLK, PLL_FB input pins, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HST,

LVDS & HyperTransport technology. CLK & PLL_FB

differential SSTL and differential HSTL I/O standards.

Bank 8

Memory Interface IOEs

& PLL_OUT output

pins support differential SSTL, differential HSTL,

pins support LVPECL. DQS input pins support

PLL 6PLL 12

Bank 12 Bank 10

I/O Banks 5 & 6 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS
&1.5-V LVCMOS

Bank 7

Memory Interface IOEs

Bank 6
General-Purpose IOE

Altera Corporation 2–19
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

s

s

Figure 2–6. I/O Type Support in HC240 Devices Notes (1), (2)

Bank 11

PLL 11

Bank 9

PLL 5

Bank 2

High-Speed IOEs

PLL 7

Bank 3

Memory Interface IOEs

I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/
LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V

HSTL, 1.5-V HSTL & PCI/PCI-X I/O standards.

pins support differential SSTL, differential HSTL,

LVDS & HyperTransport technology. CLK & PLL_FB

differential SSTL and differential HSTL I/O standards.

CLK, PLL_FB input pins & PLL_OUT output

pins support LVPECL. DQS input pins support

Bank 4

Memory Interface IOEs

PLL 10

Bank 5
High-Speed IOE

I/O Banks 5 & 6 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS,

1.5-V LVCMOS, LVDS &

HyperTransport Technology

PLL 6PLL 12

Bank 7

Memory Interface IOEs

PLL 4

PLL 3

PLL 9

Bank 6
High-Speed IOE

Bank 1

High-Speed IOEs

PLL 1

PLL 2

PLL 8

I/O Banks 1 & 2 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS,

1.5-V LVCMOS, LVDS &
HyperTransport Technology

I/O banks 7 & 8 support 3.3-V, 2.5-V, 1.8-V LVTTL/

LVCMOS, 1.5-V LVCMOS & PCI/PCI-X I/O standards.

CLK, PLL_FB input pins SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HST,

LVDS & HyperTransport technology. CLK & PLL_FB

differential SSTL and differential HSTL I/O standards.

Bank 8

Memory Interface IOEs

& PLL_OUT output

pins support differential SSTL, differential HSTL,

pins support LVPECL. DQS input pins support

Bank 12 Bank 10

Notes to Figures 2–4 through 2–6:

(1) In addition to supporting external memory interfaces, memory interface IOEs have the same features as general

purpose IOEs. In addition to supporting high-speed I/O interfaces, high-speed IOEs have the same features as
general purpose IOEs, except for the PCI clamping diode and LVPECL clock input support.

(2) This is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. It is a graphical

representation only.

1 When planning I/O placement for designs targeting

HardCopy II devices, care should be taken to ensure the same
I/O standards are supported in the same HardCopy II I/O
banks as in the Stratix II I/O banks.

General Purpose IOE

The general purpose IOEs in HC210 and HC220 devices are located on the
right side and at the bottom of the device. The general purpose IOEs in
HC230 devices are located on the right side of the device. (Directions are
based on a top view of the silicon die.) HC240 devices do not have general
purpose IOEs. The general purpose IOE functionality is supported in the
memory interface IOEs for these devices. The high-speed IOEs also

2–20 Altera Corporation

Preliminary September 2008

I/O Structure and Features

provide the same features as the general purpose IOEs except for the PCI
clamping diode. In Stratix II FPGAs, all IOEs support the general purpose
IOE features except the PCI diode, which is only supported on the top
and bottom I/O pins.

The general purpose IOE has many features, including:

■ Dedicated single-ended I/O buffers

■ 3.3-V, 64-bit, 66 MHz PCI compliance

■ 3.3-V, 64-bit, 133 MHz PCI-X 1.0 compliance

■ JTAG boundary-scan test (BST) support

■ On-chip driver series termination (non-calibrated)

■ Output drive strength control

■ Tri-state buffers

■ Bus-hold circuitry

■ Programmable pull-up resistors

■ Open-drain outputs

■ PCI clamping diode (supported on the bottom I/O pins only)

■ Double data rate (DDR) registers

General purpose IOEs support the following I/O standards:

■ 3.3-V LVTTL/LVCMOS

■ 2.5-V LVTTL/LVCMOS

■ 1.8-V LVTTL/LVCMOS

■ 1.5-V LVCMOS

■ 3.3-V PCI

■ 3.3-V PCI-X mode 1

The general purpose CLK and PLL_FB input pins and the PLL_OUT
output pins support the following I/O standards:

■ LV DS

■ HyperTransport technology

■ LVPECL (on input clocks and PLL_OUT only)

The programmable drive strengths available vary depending on the I/O
standard being used and are listed in Table 2–10.

Table 2–10. Programmable Drive Strength Support for General-Purpose
IOEs (Part 1 of 2)

I/O Standard Programmable Drive Strength Options (mA)

3.3-V LVTTL 4, 8, 12

3.3-V LVCMOS 4, 8

2.5-V LVTTL/LVCMOS 4, 8, 12

Altera Corporation 2–21
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

Table 2–10. Programmable Drive Strength Support for General-Purpose
IOEs (Part 2 of 2)

1.8 V LVTTL/LVCMOS 2, 4, 6, 8

1.5 V LVCMOS 2, 4

General purpose IOEs support non-calibrated on-chip series termination.
50- and 25-Ω on-chip series termination is available for 3.3-V or 2.5-V I/O
standards. 50-Ω on-chip series termination is available for 1.8- and 1.5-V
I/O standards (pending characterization).

Memory Interface IOE

Memory interface IOEs in HC210 and HC220 devices are located on the
top of the device. Memory interface IOEs in HC230 and HC240 devices
are located on the top and the bottom of the device. In Stratix II FPGAs,
the top and bottom IOEs support the memory interface IOE features.

The memory interface IOE has many features, including:

■ Dedicated single-ended I/O buffers

■ 3.3-V, 64-bit, 66 MHz PCI compliance

■ 3.3-V, 64-bit, 133 MHz PCI-X 1.0 compliance

■ JTAG BST support

■ On-chip driver series termination

■ V

REF

■ Output drive strength control

■ Tri-state buffers

■ Bus-hold circuitry

■ Programmable pull-up resistors

■ Open-drain outputs

■ PCI clamping diode

■ DQ and DQS I/O pins

■ Double data rate (DDR) registers

I/O Standard Programmable Drive Strength Options (mA)

pins

The following I/O standards are supported when using the memory
interface IOEs and can be used to interface to external memory, including
DDR and DDR2 SDRAM, and QDRII, RLDRAM II, and SDR SRAM:

■ 3.3-V LVTTL/LVCMOS

■ 2.5-V LVTTL/LVCMOS

■ 1.8-V LVTTL/LVCMOS

■ 1.5-V LVCMOS

■ 3.3-V PCI

■ 3.3-V PCI-X mode 1

2–22 Altera Corporation

Preliminary September 2008

I/O Structure and Features

■ SSTL-2 class I and II

■ SSTL-18 class I and II

■ 1.8-V HSTL class I and II

■ 1.5-V HSTL class I and II

The memory interface DQS, CLK, and PLL_FB input pins and the
PLL_OUT output pins support the following I/O standards:

■ LV TT L/ LV CM OS

■ SSTL-2 class I and II

■ SSTL-18 class I and II

■ 1.8-V HSTL class I and II

■ 1.5-V HSTL class I and II

■ Differential SSTL-2 class I and II

■ Differential SSTL-18 class I and II

■ 1.8-V differential HSTL class I and II

■ 1.5-V differential HSTL class I and II

■ LVDS (not supported on DQS pins)

■ HyperTransport technology (not supported on DQS pins)

■ LVPECL on input clocks and PLL_OUT only (not supported on DQS

pins)

Pseudo-differential HSTL and SSTL inputs are supported on clock and
DQS pins, while outputs are supported on dedicated PLL_OUT and DQS
pins. Pseudo-differential HSTL and SSTL I/O standards use two
single-ended outputs with the second output programmed as inverted.
Pseudo-differential HSTL and SSTL inputs treat differential inputs as two
single-ended HSTL and SSTL inputs and only decode one of them. This
I/O support is the same as in Stratix II FPGAs.

The functionality of all DQS circuitry in HardCopy II devices is the same
as in Stratix II FPGAs. Table 2–11 shows the number of DQS/DQ groups
supported in each HardCopy II device density and package.

Table 2–11. DQS and DQ Bus Mode Support (Part 1 of 2)

Device Package

HC210W 484-pin FineLine BGA

(Wire Bond)

HC210 484-pin FineLine BGA 4 2 0 0

HC220 672-pin FineLine BGA 9 4 2 0

780-pin FineLine BGA 9 4 2 0

HC230 1,020-pin FineLine BGA 36 18 8 4

Altera Corporation 2–23
September 2008 Preliminary

Number of ×4

Groups

42 0 0

Number of ×8/×9

Groups

Number of

×16/×18 Groups

Number of

×32/×36 Groups

HardCopy Series Handbook, Volume 1

Table 2–11. DQS and DQ Bus Mode Support (Part 2 of 2)

Device Package

HC240 1,020-pin FineLine BGA 36 18 8 4

1,508-pin FineLine BGA 36 18 8 4

Number of ×4

Groups

Number of ×8/×9

Groups

Number of

×16/×18 Groups

Number of

×32/×36 Groups

The programmable drive strengths available vary depending on the I/O
standard used. The options are listed in Table 2–12.

Table 2–12. Programmable Drive Strength Support for Memory Interface
IOEs

I/O Standard Programmable Drive Strength Options (mA)

3.3-V LVTTL 4, 8, 12, 16, 20, 24

3.3-V LVCMOS 4, 8, 12, 16, 20, 24

2.5-V LVTTL/LVCMOS 4, 8, 12, 16

1.8-V LVTTL/LVCMOS 2, 4, 6, 8, 10, 12

1.5-V LVCMOS 2, 4, 6, 8

SSTL-2 class I 8, 12

SSTL-2 class II 16, 20, 24

SSTL-18 class I 4, 6, 8, 10, 12

SSTL-18 class II 8, 16, 18, 20

1.8-V HSTL class I 4, 6, 8, 10, 12

1.8-V HSTL class II 16, 18, 20

1.5-V HSTL class I 4, 6, 8, 10, 12

1.5-V HSTL class II 16, 18, 20

Memory interface IOEs support both non-calibrated and calibrated
on-chip series termination. 50- and 25-Ω on-chip series termination is
available for 3.3-, 2.5-, or 1.8-V I/O standards. 50-Ω on-chip series
termination is available for 1.5- or 1.2-V I/O standards (pending
characterization).

1 If on-chip series termination is enabled, programmable drive

strength support is not available.

2–24 Altera Corporation

Preliminary September 2008

I/O Structure and Features

High-Speed IOE

High-speed IOEs in HC210, HC220, and HC230 devices are located on the
left side of the device. High-speed IOEs in HC240 devices are located on
the left and right sides of the device. (Directions are based on a top view
of the silicon die.) Unlike Stratix II left and right side I/O pins,
HardCopy II left and right side I/O pins do not support SSTL or HSTL
I/O standards or the PCI clamping diode. In Stratix II FPGAs, the right
and left IOEs support the high-speed IOE features.

The high-speed IOE has many features, including:

■ Dedicated single-ended I/O buffers

■ Differential I/O buffer

■ JTAG BST support

■ On-chip driver series termination (non-calibrated)

■ On-chip termination for differential I/O standards

■ Output drive strength control

■ Tri-state buffers

■ Bus-hold circuitry

■ Programmable pull-up resistors

■ Open-drain outputs

■ Transmit serializer

■ Receive deserializer

■ Dynamic phase alignment (DPA)

■ Double data rate (DDR) registers

The following I/O standards are supported when using high-speed IOEs:

■ 3.3-V LVTTL/LVCMOS

■ 2.5-V LVTTL/LVCMOS

■ 1.8-V LVTTL/LVCMOS

■ 1.5-V LVCMOS

■ LV DS

■ HyperTransport technology

Altera Corporation 2–25
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

The SERDES and DPA circuitry and functionality is the same in
HardCopy II devices as in Stratix II FPGAs. HardCopy II devices support
differential I/O standards at rates up to 1 Gbps when using DPA, and at
rates up to 840 Mbps when not using DPA. Table 2–13 provides the
number of differential channels per HardCopy II device.

Table 2–13. Number of Differential Channels in HardCopy II Devices Notes (1), (2)

HC210W HC210 HC220 HC230 HC240

Channel

484-Pin

FineLine

BGA (Wire-

Bond)

Transmitter
channels

Receiver
channels

Notes to Ta bl e 2 – 1 3 :

(1) The pin count does not include dedicated PLL input and output pins.
(2) The total number of receiver channels includes the non-dedicated clock channels that can optionally be used as

data channels.

13 19 29 29 44 88 116

17 21 31 31 46 92 116

484-Pin

FineLine

BGA

672-Pin

FineLine

BGA

780-Pin

FineLine

BGA

1,020-Pin

FineLine

BGA

1,020-Pin

FineLine

BGA

1,508-Pin

FineLine

BGA

HardCopy II high-speed IOEs, which are on the left and/or right sides of
the device, support fewer programmable drive strengths than Stratix II
side IOEs. The programmable drive strengths available vary depending
on the I/O standard being used. The options are listed in Table 2–14.

Table 2–14. Programmable Drive Strength Support for High-Speed IOEs

I/O Standard Programmable Drive Strength Options (mA)

3.3-V LVTTL 4, 8, 12

3.3-V LVCMOS 4, 8

2.5-V LVTTL/LVCMOS 4, 8, 12

1.8-V LVTTL/LVCMOS 2, 4, 6, 8

1.5-V LVCMOS 2, 4

High-speed IOEs support non-calibrated on-chip series termination and
differential termination on the receiver channels. 50- and 25-Ω on-chip
series termination is available for 3.3- or 2.5-V I/O standards. 50-Ω
on-chip series termination is available for 1.8- and 1.5-V I/O standards
(pending characterization).

2–26 Altera Corporation

Preliminary September 2008

Power-Up Modes

Power-Up
Modes

The functionality of structured ASICs is determined before they are
produced. Therefore, they do not require programmability. HardCopy II
structured ASICs follow the same principle, enabling traditional
ASIC-like power up. Although prototyping FPGAs require configuration
upon power up, the HardCopy II structured ASICs do not need to be
configured. HardCopy II devices do not support configuration and
designers should take this into account in the prototyping-to-production
development process. The HardCopy II device does not require a
configuration device, but you must ensure that the nCE pin is low and
that the nCONFIG and nSTATUS pins are high after power up.

1 HardCopy II devices do not support FPGA configuration

emulation and other configuration modes, including remote
system upgrades and design security using configuration
bitstream encryption.

HardCopy II devices support both instant on and instant on after 50 ms
power-up modes. In the instant on power-up mode, the HardCopy II
device is available for use shortly after the device powers up to a safe
operating voltage. The on-chip power-on reset (POR) circuit will reset all
registers. The nCE, nCONFIG, and nSTATUS signals must be at the
appropriate logic levels for the CONF_DONE output to be tristated once the
POR has elapsed. This option is similar to an ASIC’s functionality upon
power up and is the most likely scenario in production.

In the instant on after 50 ms power-up mode, the HardCopy II device
behaves similarly to the instant on mode, except that there is an
additional delay of 50 ms, during which time the device will be held in
reset. The CONF_DONE output is pulled low during this time, and then
tri-stated after the 50 ms have elapsed.

f For more information about which power-up modes HardCopy II

devices support, refer to the Power-Up Modes and Configuration Emulation
in HardCopy Series Devices chapter in the HardCopy Series Handbook.

Altera Corporation 2–27
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

Document

Table 2–15 shows the revision history for this chapter.

Revision History

Table 2–15.Document Revision History

Date and Document

Version

September 2008,
v2.5

June 2007, v2.4

December 2006
v2.3

March 2006, v2.2 ● Updated Table 2–1, Table 2–9, Table 2–13.

October 2005, v2.1 Updated graphics. —

May 2005, v2.0

January 2005,
v1.0

Updated chapter number and metadata. —

● Added Note 4 to Table 2–4.—

● Updated Table 2–1, Table 2–4, and Table 2–11.

● Added revision history.

● Updated Figure 2–5 and Figure 2–6.

● Added Table 2–1.

● Updated HCell information for DSP functions in the

Functional Description section.

● Updated Table 2–9.

● Updated Figures 2–4, 2–5, and 2–6.

Added document to the HardCopy Series Handbook. —

Changes Made Summary of Changes

—

—

—

2–28 Altera Corporation

Preliminary September 2008

H51017-2.4

3. Boundary-Scan Support

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support

All HardCopy®II structured ASICs provide Joint Test Action Group
(JTAG) boundary-scan test (BST) circuitry that complies with the IEEE
Std. 1149.1-1990 specification. The BST architecture offers the capability
to efficiently test components on printed circuit boards (PCBs) with tight
lead spacing by testing pin connections, without using physical test
probes, and capturing functional data while a device is in normal
operation. Boundary-scan cells in a device can force signals onto pins, or
capture data from pin or core logic signals. Forced test data is serially
shifted into the boundary-scan cells. Captured data is serially shifted out
and externally compared to expected results.

A device using the JTAG interface uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. The TCK pin has an internal weak
pull-down resistor, while the TDI, TMS, and TRST pins have weak
internal pull-up resistors. The TDO output is powered by V
HardCopy II devices support the JTAG instructions shown in Tab le 3 –1 .

Table 3–1. HardCopy II JTAG Instructions (Part 1 of 2)

JTAG Instruction Instruction Code Description

SAMPLE/PRELOAD 00 0000 0101

EXTEST (1) 00 0000 1111

BYPASS 11 1111 1111 Places the 1-bit BYPASS register

Allows a snapshot of signals at the
device pins to be captured and
examined during normal device
operation, and permits an initial data
pattern to be output at the device
pins.

Allows the external circuitry and
board-level interconnects to be
tested by forcing a test pattern at the
output pins and capturing test results
at the input pins.

between the
which allows the BST data to pass
synchronously through selected
devices to adjacent devices during
normal device operation.

TDI and TDO pins,

CCIO

.

Altera Corporation 3–1
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

Table 3–1. HardCopy II JTAG Instructions (Part 2 of 2)

JTAG Instruction Instruction Code Description

USERCODE 00 0000 0111 Selects the 32-bit USERCODE

IDCODE 00 0000 0110 Selects the IDCODE register and

HIGHZ (1) 00 0000 1011 Places the 1-bit BYPASS register

CLAMP (1) 00 0000 1010 Places the 1-bit BYPASS register

Note to Ta bl e 3 – 1 :

(1) Bus hold and weak pull-up resistor features override the high-impedance state of

HIGHZ, CLAMP, and EXTEST.

register and places it between the

TDI and TDO pins, allowing the
USERCODE to be serially shifted out

TDO.

of

places it between
allowing the
shifted out of

between the
which allows the BST data to pass
synchronously through selected
devices to adjacent devices during
normal device operation, while
tri-stating all of the I/O pins.

between the
which allows the BST data to pass
synchronously through selected
devices to adjacent devices during
normal device operation while
holding I/O pins to a state defined by
the data in the boundary-scan
register.

TDI and TDO,

IDCODE to be serially

TDO.

TDI and TDO pins,

TDI and TDO pins,

f The BSDL files for HardCopy II devices are different from the

corresponding Stratix
BSDL files for IEEE Std. 1149.1- compliant Hardcopy II devices, visit the
Altera website at www.altera.com.

The HardCopy II device instruction register length is 10 bits and the
USERCODE register length is 32 bits. The USERCODE registers are not
reprogrammable and are mask-programmed. The designer can choose an
appropriate 32 bit sequence which will be programmed into the
USERCODE registers.

3–2 Altera Corporation

Preliminary September 2008

®

II FPGAs. For more information, or to receive

Tables 3–2 and 3–3 show the boundary-scan register length and device

IDCODE information for HardCopy II devices.

Table 3–2. HardCopy II Boundary-Scan Register Length

Table 3–3. 32-Bit HardCopy II Device IDCODE

Device

HC210W

HC210

HC220

HC230

HC240

Version
(4 Bits)

0000 0010 0000 1100 0001 000 0110 1110 1

0000 0010 0000 1100 0010 000 0110 1110 1

0000 0010 0000 1100 0011 000 0110 1110 1

0000 0010 0000 1100 0100 000 0110 1110 1

0000 0010 0000 1100 0101 000 0110 1110 1

Part Number (16 Bits)

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support

Device Boundary-Scan Register Length

HC210W 1050

HC210 1050

HC220 1530

HC230 2154

HC240 2910

IDCODE (32 Bits) (1)

Manufacturer Identity

(11 Bits)

LSB (1 Bit) (2)

Notes to Ta bl e 3 – 3 :

(1) The most significant bit (MSB) is on the left.
(2) The least significant bit (LSB) of IDCODE is always 1.

Boundary-Scan Test (BST) on HardCopy II Devices

In order to run the boundary-scan test on HardCopy II devices, you need
two files:

1. The generic HardCopy II BSDL file you can download from the
Altera website at www.altera.com.

2. The PIN file for your design from the Quartus II software.

With these two files, you must run through a tool called the
BSDLCustomizer.

Altera Corporation 3–3
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

TDO

TCK

t

JPZX

t

JPCO

t

JPH

t

JPXZ

t

JCP

t

JPSU

t

JCL

t

JCH

TDI

BSDLCustomizer is a TCL script which is used to modify the BSDL file’s
port definitions and boundary-scan chain groups’ attributes according to
the design and pin assignments from the Quartus II software PIN file.

Once you run the generic BSDL file and your PIN file through the
BSDLCustomizer tool, a modified BSDL file is created which should be
used for the boundary-scan test.

Before running the boundary scan test on your board make sure that the
nCONFIG pin is externally pulled low and that the nSTATUS pin is low.

For more information on the BSDLCustomizer tool, refer to the
BSDLCustomizer User Guide that you can download with the
BSDLCustomizer tool from the Altera website at www.altera.com.

Figure 3–1 shows the timing requirements for the JTAG signals.

Figure 3–1. HardCopy II JTAG Waveforms

Table 3–4 shows the JTAG timing parameters and values for HardCopy II

devices.

Table 3–4. HardCopy II JTAG Timing Parameters and Values (Part 1 of 2)

Symbol Parameter Min Max Unit

t

JCP

t

JCH

t

JCL

t

JPSU

TCK clock period

TCK clock high time

TCK clock low time

JTAG port setup time 3 ns

3–4 Altera Corporation

Preliminary September 2008

30 ns

13 ns

13 ns

Document Revision History

Table 3–4. HardCopy II JTAG Timing Parameters and Values (Part 2 of 2)

Symbol Parameter Min Max Unit

t

JPH

t

JPCO

t

JPZX

t

JPXZ

t

JSSU

t

JSH

JTAG port hold time 5 ns

JTAG port clock to output 11 ns

JTAG port high impedance to
valid output

JTAG port valid output to high
impedance

Capture register setup time 4 ns

Capture register hold time 5 ns

14 ns

14 ns

f For more information on JTAG or boundary-scan testing, refer to AN 39:

IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.

1 Like Stratix II FPGAs, HardCopy II devices support the

SignalTap® II embedded logic analyzer, which monitors design
operation over a period of time through the JTAG interface. The
SignalTap II logic analyzer is a useful feature during the FPGA
prototyping phase, but should be removed if not needed once
the design has been migrated to a HardCopy II device.
HardCopy II is a mask programmed device, and the Signal Tap
logic cannot be eliminated after the HardCopy II device is
fabricated.

Document

Table 3–5 shows the revision history for this chapter.

Revision History

Table 3–5. Document Revision History (Part 1 of 2)

Date and Document

Version

September 2008,
v2.4

June 2007, v2.3

December 2006
v2.2

October 2005, v2.1 Updated graphics. —

Altera Corporation 3–5
September 2008 Preliminary

Updated chapter number and metadata. —

● Added resource information

● Figure 3–1 changes

● New section on Boundar y-Scan Test (BST) on HardCopy

II devices.

● Minor updates for Quartus II 6.1.0 software version

● Added revision history

Changes Made Summary of Changes

—

Updated for Quartus II 6.1

software version.

HardCopy Series Handbook, Volume 1

Table 3–5. Document Revision History (Part 2 of 2)

Date and Document

Version

May 2005, v2.0 Updated Table 3-2. —

January 2005
v1.0

Added document to the HardCopy Series Handbook. —

Changes Made Summary of Changes

3–6 Altera Corporation

Preliminary September 2008

H51018-3.3

4. DC and Switching

Specifications and Operating

Conditions

Introduction

Absolute Maximum Ratings

This chapter provides preliminary information on absolute maximum
ratings, recommended operating conditions, DC electrical characteristics,

®

and other specifications for HardCopy

II devices.

HardCopy II devices are offered in both commercial and industrial
grades. All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless otherwise noted, the
parameter values in this chapter apply to all HardCopy II devices.

Table 4–1 contains the absolute maximum ratings for the HardCopy II

device family.

Table 4–1. HardCopy II Device Absolute Maximum Ratings Notes (1), (2), (3)

Symbol Parameter Conditions Minimum Maximum Unit

V

CCINT

V

CCIO

V

CCPD

V

CCA

V

CCD

V

I

I

OUT

T

STG

T

J

Notes to Ta b l e 4 – 1:

(1) Refer to the Operating Requirements for Altera Devices Data Sheet for more information.
(2) Conditions beyond those listed in Ta bl e 4– 1 may cause permanent damage to a device. Additionally, device

operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
(3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
(4) During transitions, the inputs may overshoot to the voltage shown in Ta bl e 4– 2 based upon the input duty cycle.

The DC case is equivalent to a 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input

currents less than 100 mA and periods shorter than 20 ns.

Supply voltage With respect to ground -0.5 1.8 V

Supply voltage With respect to ground -0.5 4.6 V

Supply voltage With respect to ground -0.5 4.6 V

Analog power supply for

PLLs

Digital power supply for

PLLs

DC input voltage(4) — -0.5 4.6 V

DC output current, per pin — -25 40 mA

Storage temperature No bias -65 150

Junction temperature Ball-grid array (BGA)

With respect to ground -0.5 1.8 V

With respect to ground -0.5 1.8 V

-55 125

packages under bias

°C

°C

Altera Corporation 4–1
September 2008 Preliminary

HardCopy Series Handbook, Volume 1

Table 4–2. Maximum Duty Cycles in Voltage Transitions

Recommended

VIN (V)

4 100%

4.1 90%

4.2 50%

4.3 30%

4.4 17%

4.5 10%

Table 4–3 contains the HardCopy II device family’s recommended

operating conditions.

Maximum Duty Cycles

Operating
Conditions

Table 4–3. HardCopy II Device Recommended Operating Conditions Note (1) (Part 1 of 2)

Symbol Parameter Conditions Minimum Maximum Unit

V

V

V

V

V

V

V

CCINT

CCIO

CCPD

CCA

CCD

I

O

Supply voltage for internal

logic and input buffers

Supply voltage for output

buffers, 3.3-V operation

Supply voltage for output

buffers, 2.5-V operation

Supply voltage for output

buffers, 1.8-V operation

Supply voltage for output

buffers, 1.5-V operation

Supply voltage for pre-drivers

as well as configuration and

JTAG I/O buffers

Analog power supply for PLLs 100 µs ≤ rise time ≤ 100 ms (3) 1.15 1.25 V

Digital power supply for PLLs 100 µs ≤ rise time ≤ 100 ms (3) 1.15 1.25 V

Input voltage (4), (5) -0.5 4.0 V

Output voltage — 0 V

100 µs ≤ rise time ≤ 100 ms (2) 1.15 1.25 V

100 µs ≤ rise time ≤ 100 ms (2), (6) 3.135

(3.0)

100 µs ≤ rise time ≤ 100 ms (2) 2.375 2.625 V

100 µs ≤ rise time ≤ 100 ms (2) 1.71 1.89 V

100 µs ≤ rise time ≤ 100 ms (2) 1.425 1.575 V

100 µs ≤ rise time ≤ 100 ms (3) 3.135 3.465 V

3.465
(3.6)

CCIO

V

V

4–2 Altera Corporation

September 2008

DC Electrical Characteristics

Table 4–3. HardCopy II Device Recommended Operating Conditions Note (1) (Part 2 of 2)

Symbol Parameter Conditions Minimum Maximum Unit

T

J

Notes to Ta b l e 4 – 3:

(1) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
(2) Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(3) V

CCPD

time, the HardCopy II device will not power up successfully.

(4) During transitions, the inputs may overshoot to the voltage shown in Ta bl e 4– 2 based upon the input duty cycle.

The DC case is equivalent to a 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.

(5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V

are powered.

(6) V

CCIO

Operating junction

temperature

must ramp-up from 0 V to 3.3 V within 100 µs to 100 ms. If V

maximum and minimum conditions for PCI and PCI-X are shown in parentheses.

For commercial use 0 85 °C

For industrial use -40 100 °C

is not ramped up within this specified

CCPD

CCINT

, V

CCPD

, and V

CCIO

DC Electrical

Table 4–4 shows the HardCopy II device family’s DC electrical

characteristics.

Characteristics

Table 4–4. HardCopy II Device DC Operating Conditions Note (1) (Part 1 of 2)

Symbol Parameter Conditions Device Minimum Typical Maximum Unit

I

I

I

OZ

I

CCINT0

I

CCPD0

Input pin leakage
current

Tri-stated I/O pin
leakage current

V

supply current

CCINT

(standby)

V

supply current

CCPD

(standby)

VI = V

CCIO

max to

0 V (2)

VO = V

CCIO

max to

0 V (2)

VI = ground, no
load, no toggling
inputs

= 25° C

T

J

VI = ground, no
load, no toggling
inputs

= 25° C

T

J

= 3.3 V

V

CCPD

all

-10 — 10 µA

-10 — 10 µA

all

HC210W — 0.09 (3) (5) A

HC210 — 0.09 (3) (5) A

HC220 — 0.19 (3) (5) A

HC230 — 0.34 (3) (5) A

HC240 — 0.52 (3) (5) A

HC210W — 3 (3) (5) mA

HC210 — 3 (3) (5) mA

HC220 — 4 (3) (5) mA

HC230 — 5 (3) (5) mA

HC240 — 5 (3) (5) mA

Altera Corporation 4–3
September 2008

HardCopy Series Handbook, Volume 1

Table 4–4. HardCopy II Device DC Operating Conditions Note (1) (Part 2 of 2)

Symbol Parameter Conditions Device Minimum Typical Maximum Unit

I

CCIO0

V

supply current

CCIO

(standby)

VI = ground, no
load, no toggling
inputs

= 25° C

T

J

(4) Value of I/O pin

R

CONF

pull-up resistor
before and during
configuration

Recommended value

V

= 0; V

I

V

= 0; V

I

V

= 0; V

I

V

= 0; V

I

V

= 0; V

I

= 3.3 V — 10 25 50 kΩ

CCIO

= 2.5 V — 15 35 70 kΩ

CCIO

= 1.8 V — 30 50 100 kΩ

CCIO

= 1.8 V — 40 75 150 kΩ

CCIO

= 1.2 V — 50 90 170 kΩ

CCIO

———12kΩ
of I/O pin external
pull-down resistor
before and during
configuration

Notes to Ta b l e 4 – 4:

(1) Typical values are for TA = 25° C, V
(2) This value is specified for normal device operation. The value may vary during power-up. This applies for all

V

settings (3.3-, 2.5-, 1.8-, and 1.5-V).

CCIO

(3) This specification is preliminary and pending further device characterization.
(4) Pin pull-up resistor values will lower if an external source drives the pin higher than V
(5) Maximum values depend on the actual TJ and design utilization. See the PowerPlay Early Power Estimator or the

Quartus II PowerPlay Power Analyzer feature for maximum values.

= 1.2 V, and V

CCINT

HC210W — 3 (3) (5) mA

HC210 — 3 (3) (5) mA

HC220 — 3 (3) (5) mA

HC230 — 3 (3) (5) mA

HC240 — 3 (3) (5) mA

—

—

—

= 1.5-, 1.8-, 2.5-, and 3.3-V.

CCIO

.

CCIO

I/O Standard

Tables 4–5 through 4–27 show the HardCopy II device family’s I/O

standard specifications.

Specifications

Table 4–5. LVTTL Specifications (Part 1 of 2)

Symbol Parameter Conditions Minimum Maximum Unit

V

(1) Output-supply voltage — 3.135 3.465 V

CCIO

V

IH

V

IL

V

OH

4–4 Altera Corporation

High-level input voltage — 1.7 4.0 V

Low-level input voltage — -0.3 0.8 V

High-level output voltage IOH = -4 mA (2), (3) 2.4 — V

September 2008

I/O Standard Specifications

Table 4–5. LVTTL Specifications (Part 2 of 2)

Symbol Parameter Conditions Minimum Maximum Unit

V

OL

Notes to Ta b l e 4 – 5:

(1) HardCopy II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,

JESD8-B.
(2) Drive strength is programmable according to values in Table 2–10, Table 2–12, and Ta b le 2 –1 4 .
(3) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

HardCopy II Device Family Data Sheet section of volume 1 of the HardCopy Series Handbook for more information.

Low-level output voltage IOL = 4 mA (2), (3) —0.45V

Table 4–6. LVCMOS Specifications

Symbol Parameter Conditions Minimum Maximum Unit

V

(1) Output-supply voltage — 3.135 3.465 V

CCIO

V

IH

V

IL

V

OH

V

OL

Notes to Ta b l e 4 – 6:

(1) HardCopy II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,

(2) Drive strength is programmable according to values in Tables 2–10, 2–12, and 2–14.
(3) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

High-level input voltage — 1.7 4.0 V

Low-level input voltage — -0.3 0.8 V

High-level output voltage V

Low-level output voltage V

= 3.0, IOH = -0.1 mA (2), (3) V

CCIO

= 3.0, IOL = 0.1 mA (2), (3) —0.2V

CCIO

– 0.2 — V

CCIO

JESD8-B.

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

Table 4–7. 2.5-V I/O Specifications (Part 1 of 2)

Symbol Parameter Conditions Minimum Maximum Unit

V

(1) Output-supply voltage — 2.375 2.625 V

CCIO

V

IH

V

IL

V

OH

Altera Corporation 4–5
September 2008

High-level input voltage — 1.7 4.0 V

Low-level input voltage — -0.3 0.7 V

High-level output voltage IOH = -1 mA (2), (3) 2.0 — V

HardCopy Series Handbook, Volume 1

Table 4–7. 2.5-V I/O Specifications (Part 2 of 2)

Symbol Parameter Conditions Minimum Maximum Unit

V

OL

Notes to Ta b l e 4 – 7:

(1) HardCopy II devices V

EIA/JEDEC Standard.
(2) Drive strength is programmable according to values in Tables 2–10, 2–12, and 2–14.
(3) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

Low-level output voltage IOL = 1 mA (2), (3) —0.4V

voltage-level support of 2.5 ± -5% is narrower than defined in the normal range of the

CCIO

Table 4–8. 1.8-V I/O Specifications

Symbol Parameter Conditions Minimum Maximum Unit

V

(1) Output-supply voltage — 1.71 1.89 V

CCIO

V

IH

V

IL

V

OH

V

OL

Notes to Ta b l e 4 – 8:

(1) HardCopy II devices V

(2) Drive strength is programmable according to values in Tables 2–10, 2–12, and 2–14.
(3) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

High-level input voltage — 0.65 × V

CCIO

Low-level input voltage — -0.3 0.35 × V

High-level output voltage IOH = -2 to -8 mA (2), (3) V

– 0.45 — V

CCIO

2.25 V

CCIO

Low-level output voltage IOL = 2 to 8 mA (2), (3) —0.45V

voltage-level support of 1.8 ± -5% is narrower than defined in the normal range of the

CCIO

EIA/JEDEC Standard.

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

V

Table 4–9. 1.5-V I/O Specifications (Part 1 of 2)

Symbol Parameter Conditions Minimum Maximum Unit

V

(1) Output-supply voltage — 1.425 1.575 V

CCIO

V

IH

V

IL

V

OH

4–6 Altera Corporation

High-level input voltage — 0.65 × V

CCIO

V

+ 0.3 V

CCIO

Low-level input voltage — -0.3 0.35 × V

High-level output voltage IOH = -2 mA (2), (3) 0.75 × V

CCIO

—V

September 2008

CCIO

V

I/O Standard Specifications

Table 4–9. 1.5-V I/O Specifications (Part 2 of 2)

Symbol Parameter Conditions Minimum Maximum Unit

V

OL

Notes to Ta b l e 4 – 9:

(1) HardCopy II devices V

EIA/JEDEC Standard.
(2) Drive strength is programmable according to values in Tables 2–10, 2–12, and 2–14.
(3) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

Low-level output voltage IOL = 2 mA (2), (3) — 0.25 × V

voltage-level support of 1.5 ± -5% is narrower than defined in the normal range of the

CCIO

CCIO

Figure 4–1 and Figure 4–2 show receiver input and transmitter

waveforms, respectively, for all differential I/O LVPECL and
HyperTransport technology.

Figure 4–1. Receiver Input Waveforms for Differential I/O Standards

Single-Ended Waveform

Positive Channel (p) = V

V

ID

V

CM

Negative Channel (n) = V

Ground

V

IH

IL

Differential Waveform (Mathematical Function of Positive & Negative Channel)

V

ID

V

ID (Peak-to-peak)

V

ID

p − n = 0 V

Altera Corporation 4–7
September 2008

HardCopy Series Handbook, Volume 1

Single-Ended Waveform

Differential Waveform (Mathematical Function of Positive & Negative Channel)

Positive Channel (p) = V

OH

Negative Channel (n) = V

OL

Ground

V

OD

V

OD

V

OD

p − n = 0 V

V

CM

Table 4–10. 2.5-V LVDS I/O Specifications

V

CCIO

V

ID

V

ICM

V

OD

V

OCM

R

L

Notes to Table 4–10:

(1) IOEs = I/O elements.
(2) For information on which I/O banks support high-speed IOEs, refer to the Description, Architecture, and Features

Figure 4–2. Transmiter Output Waveforms for Differential I/O Standards

Symbol Parameter Conditions Minimum Typical Maximum Unit

I/O supply voltage for I/O banks
that support high-speed IOEs (1),

(2)

Input differential voltage swing
(single-ended)

Input common mode voltage — 200 1,250 1,800 mV

Output differential voltage
(single-ended)

Output common mode voltage RL = 100 Ω 1.125 — 1.375 V

Receiver differential input discrete
resistor (external to HardCopy II
devices)

chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook.

— 2.375 2.5 2.625 V

—

— 100 350 900 mV

RL = 100 Ω 250 — 450 mV

— 90 100 110 Ω

4–8 Altera Corporation

September 2008

I/O Standard Specifications

Table 4–11. 3.3-V LVDS I/O Specifications Note (1)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

ID

V

ICM

V

OD

V

OCM

R

L

Notes to Ta b l e 4 – 11 :

(1) Like Stratix II devices, 3.3-V LVDS is supported by the top and bottom clock input differential buffers, and by the

(2) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V

Output and feedback pins in PLL

— 3.135 3.3 3.465 V

banks 9, 10, 11, and 12 (2)

Input differential voltage swing

— 100 350 900 mV

(single-ended)

Input common mode voltage — 200 1,250 1,800 mV

Output differential voltage

RL = 100 Ω 250 — 710 mV

(single-ended)

Output common mode voltage RL = 100 Ω 0.84 — 1.570 V

Receiver differential input discrete

— 90 100 110 Ω
resistor (external to HardCopy II
devices)

PLL clock output and feedback pins.

The PLL clock output and feedback differential buffers are powered by VCC_PLLOUT. For differential clock output
and feedback operation, connect VCC_PLLOUT to 3.3 V.

CCINT

, not V

CCIO

.

Table 4–12. LVPECL Specifications (Part 1 of 2) Note (1)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

I/O supply voltage for I/O
banks that support high­speed IOEs (2)

V

(peak-

ID

to-peak)

Input differential voltage
swing
(single-ended)

V

ICM

Input common mode
voltage

V

OD

Output differential voltage
(single-ended)

V

OCM

Output common mode
voltage

Altera Corporation 4–9
September 2008

— 3.135 3.3 3.465 V

— 300 600 1,000 mV

RL = 100 Ω 1.0 — 2.5 mV

RL = 100 Ω 525 — 970 mV

RL = 100 Ω 1.650 — 2.275 V

HardCopy Series Handbook, Volume 1

Table 4–12. LVPECL Specifications (Part 2 of 2) Note (1)

Symbol Parameter Conditions Minimum Typical Maximum Unit

R

L

Receiver differential input
discrete resistor (external to
HardCopy II devices)

Notes to Table 4–12:

(1) Like Stratix II devices, LVPECL is supported by the top and bottom clock input differential buffers, and by the PLL

clock output and feedback pins.

(2) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V

The PLL clock output and feedback differential buffers are powered by VCC_PLLOUT. For differential clock output
and feedback operation, connect VCC_PLLOUT to 3.3 V.

— 90 100 110 Ω

, not V

CCINT

CCIO

Table 4–13. HyperTransport Technology Specifications

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

I/O supply voltage for I/O
banks that support
high-speed IOEs (1), (2)

Output and feedback pins in
PLL banks 9, 10, 11, and 12

V

(peak-

ID

to-peak)

V

ICM

V

OD

Input differential voltage
swing (single-ended)

Input common mode voltage — 385 600 845 mV

Output differential voltage
(single-ended)

ΔV

OD

Change in VOD between high
and low

V

OCM

Output common mode
voltage

ΔV

OCM

Change in V

OCM

between

high and low

R

L

Receiver differential input
discrete resistor (external to
HardCopy II devices)

Notes to Table 4–13:

(1) For information on which I/O banks support high-speed IOEs, refer to the Description, Architecture, and Features

chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook.

(2) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V

The PLL clock output and feedback differential buffers are powered by VCC_PLLOUT. For differential clock output
and feedback operation, connect VCC_PLLOUT to 3.3 V.

— 2.375 2.5 2.625 V

— 3.135 3.3 3.465 V

— 300 600 900 mV

RL = 100 Ω 400 600 820 mV

RL = 100 Ω —— 75mV

RL = 100 Ω 440 600 780 V

RL = 100 Ω —— 50mV

— 90 100 110

CCINT

, not V

Ω

CCIO

.

.

4–10 Altera Corporation

September 2008

I/O Standard Specifications

Table 4–14. 3.3-V PCI Specifications

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

V

V

V

V

CCIO

IH

IL

OH

OL

Output-supply voltage — 3 3.3 3.6 V

High-level input voltage — 0.5 × V

CCIO

Low-level input voltage — -0.3 — 0.3 × V

High-level output voltage I

Low-level output voltage I

= -500 µA 0.9 × V

OUT

= 1,500 µA — — 0.1 × V

OUT

CCIO

—V

+ 0.5 V

CCIO

CCIO

——V

CCIO

Table 4–15. PCI-X Mode 1 Specifications

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

V

V

V

V

V

CCIO

IH

IL

IPU

OH

OL

Output-supply voltage — 3 — 3.6 V

High-level input voltage — 0.5 × V

CCIO

—V

+ 0.5 V

CCIO

Low-level input voltage — -0.3 — 0.35 × VCCIO V

Input pull-up voltage — 0.7 × V

High-level output voltage I

Low-level output voltage I

= -500 µA 0.9 × V

OUT

= 1,500 µA — — 0.1 × V

OUT

CCIO

CCIO

——V

——V

CCIO

V

V

V

Table 4–16. SSTL-18 Class I Specifications (Part 1 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

REF

V

TT

V

IH(DC)

V

IL(DC)

V

IH(AC)

V

IL(AC)

V

OH

Altera Corporation 4–11
September 2008

Output-supply voltage — 1.71 1.8 1.89 V

Reference voltage — 0.855 0.9 0.945 V

Termination voltage — V

High-level DC input voltage — V

Low-level DC input voltage — — — V

High-level AC input voltage — V

Low-level AC input voltage — — — V

– 0.04 VREF V

REF

+ 0.125 — — V

REF

+ 0.25 — — V

REF

+ 0.04 V

REF

– 0.125 V

REF

– 0.25 V

REF

High-level output voltage IOH = -6.7 mA (1), (2) VTT + 0.475 — — V

HardCopy Series Handbook, Volume 1

Table 4–16. SSTL-18 Class I Specifications (Part 2 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

OL

Notes to Table 4–16:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown

(2) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

Low-level output voltage IOL = 6.7 mA (1), (2) ——V

– 0.475 V

TT

in the I/O Structure and Features section located in the Description, Architecture, and Features chapter in volume 1 of
the HardCopy Series Devices Handbook.

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

Table 4–17. SSTL-18 Class II Specifications

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

REF

V

TT

V

IH(DC)

V

IL(DC)

V

IH(AC)

V

IL(AC)

V

OH

V

OL

Notes to Table 4–17:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown

(2) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

Output-supply voltage — 1.71 1.8 1.89 V

Reference voltage — 0.855 0.9 0.945 V

Termination voltage — V

High-level DC input voltage — V

Low-level DC input voltage — — — V

High-level AC input voltage — V

Low-level AC input voltage — — — V

High-level output voltage IOH = -13.4 mA (1), (2) V

– 0.04 V

REF

+ 0.125 — — V

REF

+ 0.25 — — V

REF

– 0.28 — — V

TT

REFVREF

+ 0.04 V

– 0.125 V

REF

– 0.25 V

REF

Low-level output voltage IOL = 13.4 mA (1), (2) ——0.28V

in the I/O Structure and Features section located in the Description, Architecture, and Features chapter in volume 1 of
the HardCopy Series Devices Handbook.

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

Table 4–18. SSTL-18 Differential Specifications (Part 1 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

SWING(DC)

4–12 Altera Corporation

Output-supply voltage — 1.71 1.8 1.89 V

DC differential input voltage — 0.25 — — V

September 2008

I/O Standard Specifications

Table 4–18. SSTL-18 Differential Specifications (Part 2 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

X(AC)

V

SWING(AC)

V

ISO

ΔV

ISO

V

OX(A C)

AC differential input cross point
voltage

—(V

) – 0.175 — (V

CCIO/2

CCIO/2

0.175

) +

AC differential input voltage — 0.5 — — V

Input clock signal offset voltage — — 0.5 ×

V

CCIO

Input clock signal offset voltage

— — ± 200 — V

—V

variation

AC differential cross point
voltage

—(V

) – 0.125 — (V

CCIO/2

CCIO/2

0.125

) +

Table 4–19. SSTL-2 Class I Specifications

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

TT

V

REF

V

IH (DC)

V

IL (DC)

V

IH (AC)

V

IL (AC)

V

OH

V

OL

Output-supply voltage — 2.375 2.5 2.625 V

Termination voltage — V

– 0.04 V

REF

REF

V

+ 0.04 V

REF

Reference voltage — 1.188 1.25 1.313 V

High-level input voltage — V

Low-level input voltage — -0.3 — V

High-level input voltage — V

Low-level input voltage — — — V

High-level output

IOH = -8.1 mA (1), (2) VTT + 0.57 — — V

+ 0.18 — 3.0 V

REF

– 0.18 V

REF

+ 0.35 — — V

REF

– 0.35 V

REF

voltage

Low-level output

IOL = 8.1 mA (1), (2) ——V

– 0.57 V

TT

voltage

V

V

Notes to Table 4–19:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown

in the I/O Structure and Features section of the Description, Architecture, and Features chapter in volume 1 of the

HardCopy Series Devices Handbook.

(2) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

Altera Corporation 4–13
September 2008

HardCopy Series Handbook, Volume 1

Table 4–20. SSTL-2 Class II Specifications

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

TT

V

REF

V

IH (DC)

V

IL (DC)

V

IH (AC)

V

IL (AC)

V

OH

V

OL

Notes to Table 4–20:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown

(2) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

Output-supply voltage — 2.375 2.5 2.625 V

Termination voltage — V

– 0.04 V

REF

REF

V

+ 0.04 V

REF

Reference voltage — 1.188 1.25 1.313 V

High-level input voltage — V

Low-level input voltage — -0.3 — V

High-level input voltage — V

Low-level input voltage — — — V

High-level output

IOH = -16.4 mA (1), (2) VTT + 0.76 — — V

+ 0.18 — V

REF

+ 0.35 — — V

REF

+ 0.3 V

CCIO

– 0.18 V

REF

– 0.35 V

REF

voltage

Low-level output

IOL = 16.4 mA (1), (2) ——V

– 0.76 V

TT

voltage

in the I/O Structure and Features section located in the Description, Architecture, and Features chapter in volume 1 of
the HardCopy Series Devices Handbook.

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

Table 4–21. SSTL-2 Differential Specifications

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

SWING (DC)

V

X (AC)

V

SWING (AC)

V

ISO

ΔV

ISO

V

OX (A C)

4–14 Altera Corporation

Output-supply voltage — 2.375 2.5 2.625 V

DC differential input voltage — 0.36 — — V

AC differential input cross point

—(V

CCIO/2

) – 0.2 — (V

CCIO/2

) + 0.2 V

voltage

AC differential input voltage — 0.7 — — V

Input clock signal offset voltage — — 0.5 ×

V

CCIO

Input clock signal offset voltage

— — ±200 — V

—V

variation

AC differential output cross point

—(V

CCIO/2

) – 0.2 — (V

CCIO/2

) + 0.2 V

voltage

September 2008

I/O Standard Specifications

Table 4–22. 1.5-V HSTL Class I Specifications

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

REF

V

TT

V

IH (DC)

V

IL (DC)

V

IH (AC)

V

IL(AC)

V

OH

V

OL

Notes to Table 4–22:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown

(2) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

Output-supply voltage — 1.425 1.5 1.575 V

Input reference voltage — 0.713 0.75 0.788 V

Termination voltage — 0.713 0.75 0.788 V

DC high-level input voltage — V

DC low-level input voltage — -0.3 — V

AC high-level input voltage — V

AC low-level input voltage — — — V

High-level output voltage IOH = 8 mA (1), (2) V

+ 0.1 — — V

REF

– 0.1 V

REF

+ 0.2 — — V

REF

– 0.2 V

REF

– 0.4 — — V

CCIO

Low-level output voltage IOL = -8 mA (1), (2) ——0.4V

in the I/O Structure and Features section located in the Description, Architecture, and Features chapter in volume 1 of
the HardCopy Series Devices Handbook.

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

Table 4–23. 1.5-V HSTL Class II Specifications (Part 1 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

REF

V

TT

V

IH (DC)

V

IL (DC)

V

IH (AC)

V

IL (AC)

V

OH

Altera Corporation 4–15
September 2008

Output-supply voltage — 1.425 1.5 1.575 V

Input reference voltage — 0.713 0.75 0.788 V

Termination voltage — 0.713 0.75 0.788 V

DC high-level input voltage — V

DC low-level input voltage — -0.3 — V

AC high-level input voltage — V

AC low-level input voltage — — — V

High-level output voltage IOH = 16 mA (1), (2) V

+ 0.1 — — V

REF

– 0.1 V

REF

+ 0.2 — — V

REF

– 0.2 V

REF

– 0.4 — — V

CCIO

HardCopy Series Handbook, Volume 1

Table 4–23. 1.5-V HSTL Class II Specifications (Part 2 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

OL

Notes to Table 4–23:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown

(2) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

Low-level output voltage IOL = -16 mA (1), (2) ——0.4V

inthe I/O Structure and Features section of the Description, Architecture, and Features chapter in volume 1 of the
HardCopy Series Devices Handbook.

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

Table 4–24. 1.5-V Differential HSTL Specifications

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

DIF (DC)

V

CM (DC)

V

DIF (AC)

V

OX (A C)

I/O supply voltage — 1.425 1.5 1.575 V

DC input differential voltage — 0.2 — — V

DC common mode input voltage — 0.68 — 0.9 V

AC differential input voltage — 0.4 — — V

AC differential cross point

—0.68—0.9V

voltage

Table 4–25. 1.8-V HSTL Class I Specifications (Part 1 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

REF

V

TT

V

IH (DC)

V

IL (DC)

V

IH( AC)

V

IL (AC)

V

OH

4–16 Altera Corporation

Output-supply voltage — 1.71 1.8 1.89 V

Input reference voltage — 0.85 0.9 0.95 V

Termination voltage — 0.85 0.9 0.95 V

DC high-level input voltage — V

DC low-level input voltage — -0.3 — V

AC high-level input — V

AC low-level input voltage — — — V

High-level output voltage IOH = 8 mA (1), (2) V

+ 0.1 — — V

REF

– 0.1 V

REF

+ 0.2 — — V

REF

– 0.2 V

REF

– 0.4 — — V

CCIO

September 2008

I/O Standard Specifications

Table 4–25. 1.8-V HSTL Class I Specifications (Part 2 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

OL

Notes to Table 4–25:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown

(2) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

Low-level output voltage IOL = -8 mA (1), (2) ——0.4V

in the I/O Structure and Features section located in the Description, Architecture, and Features chapter of the HardCopy
Series Devices Handbook.

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

Table 4–26. 1.8-V HSTL Class II Specifications

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

REF

V

TT

V

IH (DC)

V

IL (DC)

V

IH (AC)

V

IL (AC)

V

OH

V

OL

Notes to Table 4–26:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown

(2) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the

Output-supply voltage — 1.71 1.8 1.89 V

Input reference voltage — 0.85 0.9 0.95 V

Termination voltage — 0.85 0.9 0.95 V

DC high-level input voltage — V

DC low-level input voltage — -0.3 — V

AC high-level input voltage — V

AC low-level input voltage — — — V

High-level output voltage IOH = 16 mA (1), (2) V

+ 0.1 — — V

REF

– 0.1 V

REF

+ 0.2 — — V

REF

– 0.2 V

REF

– 0.4 — — V

CCIO

Low-level output voltage IOL= -16 mA (1), (2) ——0.4V

in the I/O Structure and Features section located in the Description, Architecture, and Features chapter in volume 1 of
the HardCopy Series Devices Handbook.

HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information.

Table 4–27. 1.8-V Differential HSTL Specifications (Part 1 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

CCIO

V

DIF (DC)

V

CM (DC)

Altera Corporation 4–17
September 2008

I/O supply voltage — 1.71 1.8 1.89 V

DC input differential voltage — 0.2 — V

+ 0.6 V V

CCIO

DC common mode input voltage — 0.78 — 1.12 V

HardCopy Series Handbook, Volume 1

Table 4–27. 1.8-V Differential HSTL Specifications (Part 2 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

V

DIF (AC)

V

OX (A C)

AC differential input voltage — 0.4 — V

+ 0.6 V V

CCIO

AC differential cross point voltage — 0.68 — 0.9 V

Bus Hold

Table 4–28 shows the HardCopy II device family’s bus hold

specifications.

Specifications

Table 4–28. Bus Hold Parameters

Parameter Conditions

V

Low
sustaining
current

High
sustaining
current

Low overdrive
current

High overdrive
current

Bus-hold
trip point

> VIL

IN

(maximum)

V

< VIH

IN

(minimum)

CCIO

CCIO

<

IN

<

IN

0 V < V
V

0 V < V
V

— 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00 V

V

Level

CCIO

1.5 V 1.8 V 2.5 V 3.3 V

Min Max Min Max Min Max Min Max

Unit

25 — 30 — 50 — 70 — µA

-25 — -30 — -50 — -70 — µA

— 160 — 200 — 300 — 500 µA

— -160 — -200 — -300 — -500 µA

4–18 Altera Corporation

September 2008

On-Chip Termination Specifications

On-Chip
Termination

Table 4–29 defines the specification for internal termination specification

when using series or differential on-chip termination for HC210W
devices only.

Specifications

Table 4–29. Series On-Chip Termination Specification for I/O Banks Supporting Memory Interface IOEs for
HC210W Notes (1), (2), (3)

Resistance Tolerance

Symbol Description Conditions

25 Ω RS

3.3/2.5

50 Ω R

3.3/2.5

25 Ω R

1.8

50 Ω R

1.8

50 Ω R

1.5

Notes to Table 4–29:

(1) For information on which I/O banks support memory interface IOEs, refer to the Description, Architecture, and

(2) The resistance tolerances for calibrated SOCT and POCT are at the time of initial of calibration. If the temperature

(3) This table applies only to the HC210W device.

Internal series termination with

V

= 3.3/2.5 V ± 10 ± 15 %

CC IO

calibration (25-Ω setting)

Internal series termination

V

= 3.3/2.5 V ± 30 ± 30 %

CC IO

without calibration (25-Ω setting)

Internal series termination with

S

V

= 3.3/2.5 V ± 10 ± 15 %

CC IO

calibration (50-Ω setting)

Internal series termination

V

= 3.3/2.5 V ± 30 ± 30 %

CC IO

without calibration (50-Ω setting)

Internal series termination with

S

V

= 1.8 V ± 10 ± 15 %

CC IO

calibration (25-Ω setting)

Internal series termination

V

= 1.8 V ± 30 ± 30 %

CC IO

without calibration (25-Ω setting)

Internal series termination with

S

V

= 1.8 V ± 10 ± 15 %

CC IO

calibration (50-Ω setting)

Internal series termination

V

= 1.8 V ± 30 ± 30 %

CC IO

without calibration (50-Ω setting)

Internal series termination with

S

V

= 1.5 V ± 13 ± 15 %

CC IO

calibration (50-Ω setting)

Internal series termination

V

= 1.5 V ± 36 ± 36 %

CC IO

without calibration (50-Ω setting)

Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook.

or voltage changes over time, the tolerance may also change.

Commercial

Max

Industrial

Max

Unit

Altera Corporation 4–19
September 2008

HardCopy Series Handbook, Volume 1

Tables 4–30 and 4–31 define the specification for internal termination

specification when using series or differential on-chip termination.

Table 4–30. Series On-Chip Termination Specification for I/O Banks Supporting Memory Interface IOEs

Notes (1), (2), (3)

Resistance Tolerance

Symbol Description Conditions

25 Ω RS

3.3/2.5

50 Ω R

3.3/2.5

25 Ω R

1.8

50 Ω R

1.8

50 Ω R

1.5

Notes to Table 4–30:

(1) For information on which I/O banks support memory interface IOEs, refer to the Description, Architecture, and

(2) The resistance tolerances for calibrated SOCT and POCT are at the time of initial calibration. If the temperature or

(3) This table applies only to HC210, HC220, HC230 and HC240 devices.

Internal series termination with

V

= 3.3/2.5 V ±5 ±10 %

CC IO

calibration (25-Ω setting)

Internal series termination

V

= 3.3/2.5 V ± 30 ± 30 %

CC IO

without calibration (25-Ω setting)

Internal series termination with

S

V

= 3.3/2.5 V ± 5 ± 10 %

CC IO

calibration (50-Ω setting)

Internal series termination

V

= 3.3/2.5 V ± 30 ± 30 %

CC IO

without calibration (50-Ω setting)

Internal series termination with

S

V

= 1.8V ±5 ±10 %

CC IO

calibration (25-Ω setting)

Internal series termination

V

= 1.8 V ± 30 ± 30 %

CC IO

without calibration (25-Ω setting)

Internal series termination with

S

V

= 1.8V ±5 ±10 %

CC IO

calibration (50-Ω setting)

Internal series termination

V

= 1.8 V ± 30 ± 30 %

CC IO

without calibration (50-Ω setting)

Internal series termination with

S

V

= 1.5 V ±8 ±10 %

CC IO

calibration (50-Ω setting)

Internal series termination

V

= 1.5 V ± 36 ± 36 %

CC IO

without calibration (50-Ω setting)

Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook.

voltage changes over time, the tolerance may also change.

Commercial

Max

Industrial

Max

Unit

4–20 Altera Corporation

September 2008

Pin Capacitance

Table 4–31. Series and Differential On-Chip Termination Specification for I/O Banks Supporting
High-Speed and General Purpose IOEs Notes (1), (3), (4)

Resistance Tolerance

Symbol Description Conditions

25 Ω RS

3.3/2.5

50 Ω R

3.3/2.5/1.8

50 Ω R

1.5

(2) Internal differential termination for

R

D

Notes to Table 4–31:

(1) For information on which I/O banks support high-speed IOEs, refer to the Description, Architecture, and Features

(2) RD is only supported on high-speed IOEs.
(3) The resistance tolerances for calibrated SOCT and POCT are at the time of initial calibration. If the temperature or

(4) This table applies only to HC210, HC220, HC230, and HC240 devices.

Internal series termination without

V

= 3.3/2.5 V ± 30 ± 30 %

CCIO

calibration (25-Ω setting)

Internal series termination without

S

calibration (50-Ω setting)

Internal series termination without

S

V

=

CCIO

3.3/2.5/1.8 V

V

= 1.5 V ± 36 ± 36 %

CCIO

calibration (50-Ω setting)

—±20±25%

LVDS or HyperTransport technology

chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook.

voltage changes over time, the tolerance may also change.

Commercial

Max

Industrial

Max

Unit

± 30 ± 30 %

Pin Capacitance

Table 4–32 shows the HardCopy II device family’s pin capacitance.

Table 4–32. HardCopy II Device Capacitance Note (1) (Part 1 of 2)

HC210, HC220,

Symbol Parameter HC210W

Typical

C

GPIO

Input capacitance on I/O pins in I/O
banks supporting general-purpose
IOEs.

C

MIIO

Input capacitance on I/O pins in I/O
banks supporting memory interface
IOEs.

C

HSIO

Input capacitance on I/O pins in I/O
banks supporting high-speed IOEs.

C

CLKTB

Input capacitance on top/bottom clock
input pins CLK[4..7] and CLK[12..15].

Altera Corporation 4–21
September 2008

5.7 5.0 pF

5.7 5.0 pF

7.2 6.1 pF

6.0 6.0 pF

HC230, HC240

Typical

Unit

HardCopy Series Handbook, Volume 1

Table 4–32. HardCopy II Device Capacitance Note (1) (Part 2 of 2)

HC210, HC220,

Symbol Parameter HC210W

Typical

C

CLKLR

C

CLKLR+

C

OUTFB

Note to Table 4–32:

(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement

Input capacitance on left/right clock
inputs CLK0, CLK2, CLK8, CLK10.

Input capacitance on left/right clock
inputs CLK1, CLK3, CLK9, and CLK11.

Input capacitance on dual-purpose clock
output/feedback pins in PLL banks 9, 10,
11, and 12.

accuracy is within ± 0.5 pF.

4.3 6.1 pF

4.2 3.3 pF

6.9 6.7 pF

HC230, HC240

Typical

Unit

Maximum Input

Tables 4–33 and 4–34 show the maximum input clocking rates of

HardCopy II I/Os.

Clock Rates

Table 4–33. HardCopy II Maximum Input Clock Rates of HC210, HC220, HC230 and HC240 Devices (Part
1 of 2)

Memory

I/OStandard

Interface

IOEs

LVTTL 500 500 500 500 500 500 500 MHz

2.5 V 500 500 500 500 500 500 500 MHz

1.8 V 500 500 500 500 500 500 500 MHz

1.5 V 500 500 500 500 500 500 500 MHz

LVCMOS 500 500 500 500 500 500 500 MHz

SSTL2 class I 500 — — — 500 — 500 MHz

SSTL2 class II 500 — — — 500 — 500 MHz

SSTL18 class I 500 — — — 500 — 500 MHz

SSTL18 class II 500 — — — 500 — 500 MHz

1.5 V HSTL class I 500 — — — 500 — 500 MHz

1.5 V HSTL class II 500 — — — 500 — 500 MHz

1.8 V HSTL class I 500 — — — 500 — 500 MHz

1.8 V HSTL class II 500 — — — 500 — 500 MHz

PCI (1) 500 — 500 — 500 — 500 MHz

High

Speed

IOEs

General

Purpose

IOEs

CLK

[0..3,

8..11]

CLK

[4..7,

12..15]

FPLL_CLK PLL_FB Unit

4–22 Altera Corporation

September 2008

Maximum Input Clock Rates

Table 4–33. HardCopy II Maximum Input Clock Rates of HC210, HC220, HC230 and HC240 Devices (Part
2 of 2)

Memory

I/OStandard

Interface

IOEs

PCI-X (1) 500 — 500 — 500 — 500 MHz

Differential SSTL2 class I

(2), (3)

Differential SSTL2 class II

(2), (3)

Differential SSTL18 class I

(2), (3)

Differential SSTL18 class II

(2), (3)

1.8-V Differential HSTL
class I (2), (3)

1.8-V Differential HSTL
class II (2), (3)

1.5-V Differential HSTL
class I (2), (3)

1.5-V Differential HSTL
class II (2), (3)

LVDS — 520 — 717 450 717 450 MHz

LVPECL — — — — 450 — 450 MHz

HyperTransport — 520 — 717 — 717 — MHz

Notes to Table 4–33:

(1) The PCI clamping diode is only supported on the top and bottom I/O pins.
(2) This I/O standard is only supported on the DQS, CLK, and PLL_FB input pins.
(3) For HC210 and HC220, differential HSTL/SSTL input is supported on top/bottom PLL_FB, the top clock pins and

DQS pins located on the top I/Os.

500 — — — 500 — 500 MHz

500 — — — 500 — 500 MHz

500 — — — 500 — 500 MHz

500 — — — 500 — 500 MHz

500 — — — 500 — 500 MHz

500 — — — 500 — 500 MHz

500 — — — 500 — 500 MHz

500 — — — 500 — 500 MHz

High

Speed

IOEs

General

Purpose

IOEs

CLK

[0..3,

8..11]

CLK

[4..7,

12..15]

FPLL_CLK PLL_FB Unit

Altera Corporation 4–23
September 2008

HardCopy Series Handbook, Volume 1

Table 4–34. HardCopy II Maximum Input Clock Rates of HC210W Devices Note (3) (Part 1 of 2)

Memory

I/O Standard

Interface

IOEs

LVTTL 350 350 350 350 350 350 350 MHz

2.5-V LVTTL/LVCMOS 350 350 350 350 350 350 350 MHz

1.8-V LVTTL/LVCMOS 350 350 350 350 350 350 350 MHz

1.5-V LVTTL/LVCMOS 270 270 270 270 270 270 270 MHz

LVCMOS 350 350 350 350 350 350 350 MHz

SSTL2 class I 350 — — — 350 — 350 MHz

SSTL2 class II 350 — — — 350 — 350 MHz

SSTL18 class I 350 — — — 350 — 350 MHz

SSTL18 class II 350 — — — 350 — 350 MHz

1.5-V HSTL class I 350 — — — 350 — 350 MHz

1.5-V HSTL class II 350 — — — 350 — 350 MHz

1.8-V HSTL class I 350 — — — 350 — 350 MHz

1.8-V HSTL class II 350 — — — 350 — 350 MHz

PCI (1) 315 — 315 — 315 — 315 MHz

PCI-X (1) 315 — 315 — 315 — 315 MHz

Differential SSTL2 class I (2) — — — — 350 — 350 MHz

Differential SSTL2 class II (2) — — — — 350 — 350 MHz

Differential SSTL18 class I (2) — — — — 350 — 350 MHz

Differential SSTL18 class II (2) — — — — 350 — 350 MHz

1.8-V differential HSTL class I

(2)

1.8-V differential HSTL class II

(2)

1.5-V differential HSTL class I

(2)

1.5-V differential HSTL class II

(2)

LVDS — 320 — 320 320 320 320 MHz

LVPECL — — — — 320 — 320 MHz

— — — — 350 — 350 MHz

— — — — 350 — 350 MHz

— — — — 350 — 350 MHz

— — — — 350 — 350 MHz

High

Speed

IOEs

General

Purpose

IOEs

CLK

[0..3,

8..11]

CLK

[4..7,

12..15]

FPLL_C

LK

PLL_FB Unit

4–24 Altera Corporation

September 2008

Maximum Output Clock Rates

Table 4–34. HardCopy II Maximum Input Clock Rates of HC210W Devices Note (3) (Part 2 of 2)

Memory

I/O Standard

Interface

IOEs

HyperTransport — 320 — 320 — 320 — MHz

Notes to Table 4–34:

(1) The PCI clamping diode is only supported on the top and bottom I/O pins.
(2) For HC210W, differential HSTL/SSTL input is supported on the top clock pins, the DQS pins on the top I/O banks and

top/bottom PLL_FB input pins.

(3) These numbers are preliminary and pending further silicon characterization.

Maximum

Tables 4–35 and 4–36 show the maximum output toggle rates of

HardCopy II I/O's for all available drive strengths.

High

Speed

IOEs

General

Purpose

IOEs

CLK

[0..3,

8..11]

CLK

[4..7,

12..15]

FPLL_C

LK

PLL_FB Unit

Output Clock
Rates

Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices

Note (1) (Part 1 of 5)

I/O Standard

3.3-V LVTTL 4 mA 225 225 225 225 225 225 225 MHz

3.3-V LVCMOS 4 mA 250 250 250 250 250 250 250 MHz

Drive

Strength

8 mA 355 355 355 355 355 355 355 MHz

12 mA 475 475 475 475 475 475 475 MHz

16 mA 594 — — — — 594 594 MHz

20 mA 700 — — — — 700 700 MHz

24 mA (3) 794 — — — — 794 794 MHz

8 mA 480 480 480 480 480 480 480 MHz

12 mA 710 — — — — 710 710 MHz

16 mA 925 — — — — 925 925 MHz

20 mA 985 — — — — 985 985 MHz

24 mA (3) 1040 — — — — 1040 1040 MHz

Memory

Interface

IOEs

High

Speed

IOEs

General Purpose

IOEs

Bottom

Column

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

Altera Corporation 4–25
September 2008

HardCopy Series Handbook, Volume 1

Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices

Note (1) (Part 2 of 5)

I/O Standard

2.5-V
LVT T L /
LV CM O S

1.8-V
LVT T L /
LV CM O S

1.5-V
LVT T L /
LV CM O S

SSTL2
class I

SSTL2
class II

SSTL18
class I

SSTL18
class II

Drive

Strength

4 mA 194 194 194 194 194 194 194 MHz

8 mA 380 380 380 380 380 380 380 MHz

12 mA 575 575 575 575 575 575 575 MHz

16 mA (3) 845 — — — — 845 845 MHz

2 mA 109 109 109 109 109 109 109 MHz

4 mA 250 250 250 250 250 250 250 MHz

6 mA 390 390 390 390 390 390 390 MHz

8 mA 570 570 570 570 570 570 570 MHz

10 mA 805 — — — — 805 805 MHz

12 mA (3) 1040 — — — — 1040 1040 MHz

2 mA 200 200 200 200 200 200 200 MHz

4 mA 370 370 370 370 370 370 370 MHz

6 mA 430 — — — — 430 430 MHz

8mA (3) 495 — — — — 495 495 MHz

8 mA 300 — — — — 300 300 MHz

12 mA (3) 400 — — — — 400 400 MHz

16 mA 350 — — — — 350 350 MHz

20 mA 350 — — — — 350 350 MHz

24 mA (3) 400 — — — — 400 400 MHz

4 mA 150 — — — — 150 150 MHz

6 mA 250 — — — — 250 250 MHz

8 mA 300 — — — — 300 300 MHz

10 mA 400 — — — — 400 400 MHz

12 mA (3) 550 — — — — 550 550 MHz

8 mA 200 — — — — 200 200 MHz

16 mA 350 — — — — 350 350 MHz

18 mA 400 — — — — 400 400 MHz

20 mA (3) 500 — — — — 500 500 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom

Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

General Purpose

4–26 Altera Corporation

September 2008

Maximum Output Clock Rates

Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices

Note (1) (Part 3 of 5)

I/O Standard

1.8-V HSTL
class I

1.8-V HSTL
class II

1.5-V HSTL
class I

1.5-V HSTL
class II

PCI (4) — 790 — 790 — — 790 790 MHz

PCI-X (4) — 790 — 790 — — 790 790 MHz

LVDS — — 717 — — — — 400 MHz

HyperTransport — — 717 — — — — — MHz

LVPECL — — — — — — — 400 MHz

Differential
SSTL2 class I

(5)

Differential
SSTL2 class II

(5)

Drive

Strength

4 mA 300 — — — — 300 300 MHz

6 mA 450 — — — — 450 450 MHz

8 mA 600 — — — — 600 600 MHz

10 mA 650 — — — — 650 650 MHz

12 mA (3) 700 — — — — 700 700 MHz

16 mA 500 — — — — 500 500 MHz

18 mA 500 — — — — 500 500 MHz

20 mA (3) 550 — — — — 550 550 MHz

4 mA 300 — — — — 300 300 MHz

6 mA 500 — — — — 500 500 MHz

8 mA 650 — — — — 650 650 MHz

10 mA 700 — — — — 700 700 MHz

12 mA (3) 700 — — — — 700 700 MHz

16 mA 600 — — — — 600 600 MHz

18 mA 600 — — — — 600 600 MHz

20 mA (3) 650 — — — — 650 650 MHz

8 mA 300 — — — — 300 300 MHz

12 mA (3) 400 — — — — 400 400 MHz

16 mA 350 — — — — 350 350 MHz

20 mA (3) 350 — — — — 350 350 MHz

24 mA (3) 400 — — — — 400 400 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom

Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

General Purpose

Altera Corporation 4–27
September 2008

HardCopy Series Handbook, Volume 1

Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices

Note (1) (Part 4 of 5)

I/O Standard

Differential
SSTL18 class I

(5)

Differential
SSTL18 class II

(5)

1.8-V differential
HSTL class I

(5)

1.8-V differential
HSTL class II

(5)

1.5-V differential
HSTL class I

(5)

Drive

Strength

4 mA 150 — — — — 150 150 MHz

6 mA 250 — — — — 250 250 MHz

8 mA 300 — — — — 300 300 MHz

10 mA 400 — — — — 400 400 MHz

12 mA (3) 550 — — — — 550 550 MHz

8 mA 200 — — — — 200 200 MHz

16 mA 350 — — — — 350 350 MHz

18 mA 400 — — — — 400 400 MHz

20 mA (3) 500 — — — — 500 500 MHz

4 mA 300 — — — — 300 300 MHz

6 mA 450 — — — — 450 450 MHz

8 mA 600 — — — — 600 600 MHz

10 mA 650 — — — — 650 650 MHz

12 mA (3) 700 — — — — 700 700 MHz

16 mA 500 — — — — 500 500 MHz

18 mA 500 — — — — 500 500 MHz

20 mA (3) 550 — — — — 550 550 MHz

4 mA 300 — — — — 300 300 MHz

6 mA 500 — — — — 500 500 MHz

8 mA 650 — — — — 650 650 MHz

10 mA 700 — — — — 700 700 MHz

12 mA (3) 700 — — — — 700 700 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom

Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

General Purpose

4–28 Altera Corporation

September 2008

Maximum Output Clock Rates

Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices

Note (1) (Part 5 of 5)

I/O Standard

1.5-V differential
HSTL class II

(5)

Notes to Table 4–35:

(1) The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology

on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from
0 to 5 pF.

(2) CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and are excluded from this table.

(3) This is the default setting in the Quartus® II software if supported by the pin location.
(4) The PCI clamping diode is only supported on the top and bottom I/O pins.
(5) Like Stratix II devices, differential HSTL and SSTL is supported only on the column CLK, PLL_OUT and memory

interface DQS IOE pins. For HC210 and HC220, only the top column clock pins support Differential HSTL and SSTL.

Drive

Strength

16 mA 600 — — — — 600 600 MHz

18 mA 600 — — — — 600 600 MHz

20 mA (3) 650 — — — — 650 650 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom

Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices Notes (1), (6) (Part 1 of 4)

General Purpose

General Purpose

I/O Standard

3.3-V LVTTL 4 mA 100 100 100 100 100 100 100 MHz

3.3-V LVCMOS 4 mA 175 175 175 175 175 175 175 MHz

Drive

Strength

8 mA 170 170 170 170 170 170 170 MHz

12 mA 230 230 230 230 230 230 230 MHz

16 mA 240 — — — — 240 240 MHz

20 mA 280 — — — — 280 280 MHz

24 mA (3) 300 — — — — 300 300 MHz

8 mA 230 230 230 230 230 230 230 MHz

12 mA 260 — — — — 260 260 MHz

16 mA 270 — — — — 270 270 MHz

20 mA 290 — — — — 290 290 MHz

24 mA (3) 310 — — — — 310 310 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom
Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

Altera Corporation 4–29
September 2008

HardCopy Series Handbook, Volume 1

Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices Notes (1), (6) (Part 2 of 4)

I/O Standard

2.5-V
LVT T L / LV C M OS

1.8-V
LVT T L / LV C M OS

1.5-V
LVT T L / LV C M OS

SSTL2 class I 8 mA 210 — — — — 210 210 MHz

SSTL2 class II 16 mA 245 — — — — 245 245 MHz

SSTL18 class I 4 mA 105 — — — — 105 105 MHz

SSTL18 class II 8 mA 140 — — — — 140 140 MHz

Drive

Strength

4 mA 136 136 136 136 136 136 136 MHz

8 mA 230 230 230 230 230 230 230 MHz

12 mA 370 370 370 370 370 370 370 MHz

16 mA (3) 405 — — — — 405 405 MHz

2mA77777777777777MHz

4 mA 150 150 150 150 150 150 150 MHz

6 mA 180 180 180 180 180 180 180 MHz

8 mA 200 200 200 200 200 200 200 MHz

10 mA 250 — — — — 250 250 MHz

12 mA (3) 290 — — — — 290 290 MHz

2mA60606060606060MHz

4 mA 110 110 110 110 110 110 110 MHz

6 mA 150 — — — — 150 150 MHz

8mA (3) 190 — — — — 190 190 MHz

12 mA (3) 280 — — — — 280 280 MHz

20 mA 245 — — — — 245 245 MHz

24 mA (3) 280 — — — — 280 280 MHz

6 mA 175 — — — — 175 175 MHz

8 mA 210 — — — — 210 210 MHz

10 mA 220 — — — — 220 220 MHz

12 mA (3) 230 — — — — 230 230 MHz

16 mA 220 — — — — 220 220 MHz

18 mA 220 — — — — 220 220 MHz

20 mA (3) 350 — — — — 350 350 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom
Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

General Purpose

4–30 Altera Corporation

September 2008

Maximum Output Clock Rates

Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices Notes (1), (6) (Part 3 of 4)

I/O Standard

1.8-V HSTL class I 4 mA 210 — — — — 210 210 MHz

1.8-V HSTL class II16 mA 190 — — — — 190 190 MHz

1.5-V HSTL class I 4 mA 150 — — — — 150 150 MHz

1.5-V HSTL class II16 mA 170 — — — — 170 170 MHz

PCI (4) — 315 — 315 — — 315 315 MHz

PCI-X (4) — 315 — 315 — — 315 315 MHz

LVDS — — 320 — — — — 280 MHz

HyperTransport — — 320 — — — — — MHz

LVPECL — — — — — — — 280 MHz

Differential SSTL2
class I (5)

Differential SSTL2
class II (5)

Differential
SSTL18 class I (5)

Drive

Strength

6 mA 210 — — — — 210 210 MHz

8 mA 220 — — — — 220 220 MHz

10 mA 250 — — — — 250 250 MHz

12 mA (3) 270 — — — — 270 270 MHz

18 mA 200 — — — — 200 200 MHz

20 mA (3) 210 — — — — 210 210 MHz

6 mA 160 — — — — 160 160 MHz

8 mA 170 — — — — 170 170 MHz

10 mA 180 — — — — 180 180 MHz

12 mA (3) 190 — — — — 190 190 MHz

18 mA 170 — — — — 170 170 MHz

20 mA (3) 170 — — — — 170 170 MHz

8 mA 210 — — — — 210 210 MHz

12 mA (3) 280 — — — — 280 280 MHz

16 mA 245 — — — — 245 245 MHz

20 mA 245 — — — — 245 245 MHz

24 mA (3) 280 — — — — 280 280 MHz

4 mA 105 — — — — 105 105 MHz

6 mA 175 — — — — 175 175 MHz

8 mA 210 — — — — 210 210 MHz

10 mA 220 — — — — 220 220 MHz

12 mA (3) 230 — — — — 230 230 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom
Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

General Purpose

Altera Corporation 4–31
September 2008

HardCopy Series Handbook, Volume 1

Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices Notes (1), (6) (Part 4 of 4)

I/O Standard

Differential
SSTL18 class II (5)

1.8-V differential
HSTL class I (5)

1.8-V differential
HSTL class II (5)

1.5-V differential
HSTL class I (5)

1.5-V differential
HSTL class II (5)

Notes to Table 4–36:

(1) The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology on

row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from 0 to
5pF.

(2) CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and excluded from this table.
(3) This is the default setting in the Quartus II software if supported by the pin location.
(4) The PCI clamping diode is only supported on the top and bottom I/O pins.
(5) Like Stratix II devices, differential HSTL and SSTL is supported only on the column CLK, PLL_OUT and memory

interface DQS IOE pins. For HC210 and HC220, only the top column clock pins support Differential HSTL and SSTL.

(6) These numbers are preliminary and pending further silicon characterization.

Drive

Strength

8 mA 140 — — — — 140 140 MHz

16 mA 220 — — — — 220 220 MHz

18 mA 220 — — — — 220 220 MHz

20 mA (3) 220 — — — — 220 220 MHz

4 mA 210 — — — — 210 210 MHz

6 mA 210 — — — — 210 210 MHz

8 mA 220 — — — — 220 220 MHz

10 mA 250 — — — — 250 250 MHz

12 mA (3) 270 — — — — 270 270 MHz

16 mA 190 — — — — 190 190 MHz

18 mA 200 — — — — 200 200 MHz

20 mA (3) 210 — — — — 210 210 MHz

4 mA 150 — — — — 150 150 MHz

6 mA 160 — — — — 160 160 MHz

8 mA 170 — — — — 170 170 MHz

10 mA 180 — — — — 180 180 MHz

12 mA (3) 190 — — — — 190 190 MHz

16 mA 170 — — — — 170 170 MHz

18 mA 170 — — — — 170 170 MHz

20 mA (3) 170 — — — — 170 170 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom
Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

General Purpose

4–32 Altera Corporation

September 2008

Maximum Output Clock Rates

Tables 4–37 and 4–38 show the maximum output toggle rates of

HardCopy II I/Os using OCT.

Table 4–37. HardCopy II Maximum Output Clock Rate for HC210, HC220, HC230 and HC240 Devices (OCT)

Note (1) (Part 1 of 2)

I/O Standard

3.3-V LVTTL OCT 50 Ω 400 400 400 400 400 400 400 MHz

2.5-V LVTTL OCT 50 Ω 350 350 350 350 350 350 350 MHz

1.8-V LVTTL OCT 50 Ω 550 550 550 550 550 550 550 MHz

3.3-V LVCMOS OCT 50 Ω 350 350 350 350 350 350 350 MHz

1.5-V LVCMOS OCT 50 Ω 450 450 450 450 450 450 450 MHz

SSTL-2 Class I OCT 50 Ω 500 — — — — 500 500 MHz

SSTL-2 Class II OCT 25 Ω 550 — — — — 550 550 MHz

SSTL-18 Class I OCT 50 Ω 400 — — — — 400 400 MHz

SSTL-18 Class II OCT 25 Ω 500 — — — — 500 500 MHz

1.5-V HSTL
Class I

1.8-V HSTL
Class I

1.8-V HSTL
Class II

Differential
SSTL-2 Class I

(3)

Differential
SSTL-2 Class II

(3)

Differential
SSTL-18 Class I

(3)

Differential
SSTL-18 Class II

(3)

1.8-V Differential
HSTL Class I (3)

1.8-V Differential
HSTL Class II (3)

Drive

Strength

OCT 50 Ω 550 — — — — 550 550 MHz

OCT 50 Ω 600 — — — — 600 600 MHz

OCT 50 Ω 500 — — — — 500 500 MHz

OCT 50 Ω 500 — — — — 500 500 MHz

OCT 25 Ω 550 — — — — 550 550 MHz

OCT 50 Ω 400 — — — — 400 400 MHz

OCT 25 Ω 500 — — — — 500 500 MHz

OCT 50 Ω 600 — — — — 600 600 MHz

OCT 25 Ω 500 — — — — 500 500 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom

Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

General Purpose

Altera Corporation 4–33
September 2008

HardCopy Series Handbook, Volume 1

Table 4–37. HardCopy II Maximum Output Clock Rate for HC210, HC220, HC230 and HC240 Devices (OCT)

Note (1) (Part 2 of 2)

I/O Standard

1.5-V Differential
HSTL Class I (3)

Notes to Table 4–37:

(1) The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology

on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from

0 to 5 pF.
(2) CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and excluded from this table.
(3) Like Stratix II devices, differential HSTL and SSTL is supported only on the column CLK, PLL_OUT and memory

interface DQS IOE pins. For HC210 and HC220, only the top column clock pins support Differential HSTL and

SSTL.

Drive

Strength

OCT 50 Ω 550 — — — — 550 550 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom

Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

Table 4–38. HardCopy II Maximum Output Clock Rate for HC210W using OCT Notes (1), (4) (Part 1 of 2)

General Purpose

General Purpose

I/O Standard

3.3-V LVTTL OCT 50 Ω 280 280 280 280 280 280 280 MHz

2.5-V LVTTL OCT 50 Ω 245 245 245 245 245 245 245 MHz

1.8-V LVTTL OCT 50 Ω 290 290 290 290 290 290 290 MHz

3.3-V LVCMOS OCT 50 Ω 245 245 245 245 245 245 245 MHz

1.5-V LVCMOS OCT 50 Ω 190 190 190 190 190 190 190 MHz

SSTL-2 Class I OCT 50 Ω 280 — — — — 280 280 MHz

SSTL-2 Class II OCT 25 Ω 280 — — — — 280 280 MHz

SSTL-18 Class I OCT 50 Ω 230 — — — — 230 230 MHz

SSTL-18 Class II OCT 25 Ω 220 — — — — 220 220 MHz

1.5-V HSTL
Class I

1.8-V HSTL
Class I

1.8-V HSTL
Class II

Drive

Strength

OCT 50 Ω 190 — — — — 190 190 MHz

OCT 50 Ω 270 — — — — 270 270 MHz

OCT 50 Ω 210 — — — — 210 210 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom

Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

4–34 Altera Corporation

September 2008

HighSpeed I/O Specifications

Table 4–38. HardCopy II Maximum Output Clock Rate for HC210W using OCT Notes (1), (4) (Part 2 of 2)

I/O Standard

Differential
SSTL-2 Class I

(3)

Differential
SSTL-2 Class II

(3)

Differential
SSTL-18 Class I

(3)

Differential
SSTL-18 Class II

(3)

1.8-V Differential
HSTL Class I (3)

1.8-V Differential
HSTL Class II (3)

1.5-V Differential
HSTL Class I (3)

Notes to Table 4–38:

(1) The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology

on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from

0 to 5 pF.
(2) CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and excluded from this table.
(3) Like Stratix II devices, differential HSTL and SSTL is supported only on the column CLK, PLL_OUT and memory

interface DQS IOE pins. For HC210 and HC220, only the top column clock pins support differential HSTL and SSTL.
(4) These numbers are preliminary and pending further silicon characterization.

Drive

Strength

OCT 50 Ω 280 — — — — 280 280 MHz

OCT 25 Ω 280 — — — — 280 280 MHz

OCT 50 Ω 230 — — — — 230 230 MHz

OCT 25 Ω 220 — — — — 220 220 MHz

OCT 50 Ω 270 — — — — 270 270 MHz

OCT 25 Ω 210 — — — — 210 210 MHz

OCT 50 Ω 190 — — — — 190 190 MHz

Memory

Interface

IOEs

High

Speed

IOEs

Bottom

Column

IOEs

Right

Row

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT Unit

General Purpose

HighSpeed I/O

Table 4–39 provides high-speed timing specifications definitions.

Specifications

Table 4–39. HighSpeed Timing Specifications and Definitions (Part 1 of 2)

HighSpeed Timing Specifications Definitions

t

C

f

HSCLK

J De-serialization factor (width of parallel data bus).

Altera Corporation 4–35
September 2008

Highspeed receiver/transmitter input and output clock period.

Highspeed receiver/transmitter input and output clock frequency.

HardCopy Series Handbook, Volume 1

Table 4–39. HighSpeed Timing Specifications and Definitions (Part 2 of 2)

HighSpeed Timing Specifications Definitions

W PLL multiplication factor

t

RISE

t

FAL L

Timing unit interval (TUI) The timing budget allowed for skew, propagation delays, and data

f

HSDR

f

HSDRDPA

Channel-to-channel skew (TCCS) The timing difference between the fastest and slowest output edges,

Sampling window (SW) The period of time during which the data must be valid in order to

Input jitter (peak-to-peak) Peak-to-peak input jitter on highspeed PLLs.

Output jitter (peak-to-peak) Peak-to-peak output jitter on highspeed PLLs.

t

DUTY

t

LOCK

Low-to-high transmission time.

High-to-low transmission time.

sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC/w).

Maximum/minimum LVDS data transfer rate (f

Maximum/minimum LVDS data transfer rate (f

= 1/TUI), non-DPA.

HSDR

= 1/TUI), DPA.

HSDRDPA

including tCO variation and clock skew. The clock is included in the
TCCS measurement.

capture it correctly. The setup and hold times determine the ideal strobe
position within the sampling window.

Duty cycle on highspeed transmitter output clock.

Lock time for highspeed transmitter and receiver PLLs.

Table 4–40 shows the high-speed I/O timing specifications for HC210W

F484 WireBond devices.

Table 4–40. HardCopy II High-Speed I/O Specifications for HC210W Device Notes (1), (2) (Part 1 of 2)

Symbol Conditions Min Typ Max Unit

f

(clock frequency)

HSCLK

= f

f

HSCLK

HSDR

/ W

W = 2 to 32 (LVDS, HyperTransport technology)

(3)

W = 1 (SERDES bypass, LVDS only) 16 — 320 MHz

W = 1 (SERDES used, LVDS only) 150 — 320 MHz

(data rate) J = 4 to 10 (LVDS, HyperTransport technology) 150 — 640 Mbps

f

HSDR

J = 2 (LVDS, HyperTransport technology) (4) — 640 Mbps

J = 1 t(LVDS only) (4) — 320 Mbps

(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology) 150 — 640 Mbps

f

HSDRDPA

TCCS All differential standards — — 240 ps

SW All differential standards 400 — — ps

Output jitter — — — (5) ps

4–36 Altera Corporation

16 — 320 MHz

September 2008

HighSpeed I/O Specifications

Table 4–40. HardCopy II High-Speed I/O Specifications for HC210W Device Notes (1), (2) (Part 2 of 2)

Symbol Conditions Min Typ Max Unit

Output t

RISE

Output t

FAL L

t

DUTY

DPA run length — — — — — 6,400 UI

DPA jitter tolerance
(peak-to-peak)

DPA lock time Standard Training

Parallel Rapid I/O 10010000 25% (5) ——

Miscellaneous 10101010 100% (5) ——

Notes to Table 4–40:

(1) These numbers are preliminary and pending further silicon characterization.
(2) When J = 4 to 10, the SERDES block is used.

When J = 1 or 2, the SERDES block is bypassed.
(3) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input

clock frequency × W ≤ 640.
(4) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and

the clock routing resource (global, regional, or local) used. The I/O differential buffer and input register do not

have a minimum toggle rate.
(5) Contact the Altera Applications Group for more information.

All differential I/O standards — — (5) ps

All differential I/O standards — — (5) ps

———455055%

———(5) —— UI

Pattern

Transition

Density

— — — Number of

repetitions

——————

SPI4 0000000000

10% (5) ——

1111111111

— 10010000 50% (5) ——

— 10101010 — (5) ——

Table 4–41 shows the high-speed I/O timing specifications for HC210,

HC220, HC230 and HC240 HardCopy II devices.

Table 4–41. HardCopy II High-Speed I/O Specifications for HC210, HC220, HC230 and HC240 Devices

Note (1) (Part 1 of 2)

Symbol Conditions Min Typ Max Unit

f

(clock frequency)

HSCLK

= f

f

HSCLK

HSDR

/ W

W = 2 to 32 (LVDS, HyperTransport technology)

(2)

W = 1 (SERDES bypass, LVDS only) 16 — 500 MHz

W = 1 (SERDES used, LVDS only) 150 — 717 MHz

Altera Corporation 4–37
September 2008

16 — 520 MHz

HardCopy Series Handbook, Volume 1

Table 4–41. HardCopy II High-Speed I/O Specifications for HC210, HC220, HC230 and HC240 Devices

Note (1) (Part 2 of 2)

Symbol Conditions Min Typ Max Unit

f

(data rate) J = 4 to 10 (LVDS, HyperTransport technology) 150 — 1,040 Mbps

HSDR

J = 2 (LVDS, HyperTransport technology) (3) — 760 Mbps

J = 1 (LVDS only) (3) — 500 Mbps

(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology) 150 — 1,040 Mbps

f

HSDRDPA

TCCS All differential standards — — 200 ps

SW All differential standards 330 — — ps

Output jitter — — — 190 ps

Output t

RISE

Output t

FAL L

t

DUTY

DPA run length — — — 6,400 UI

DPA jitter tolerance
(peak-to-peak)

DPA lock time Standard Training

Parallel Rapid I/O 10010000 25% 256 — —

All differential I/O standards — — 160 ps

All differential I/O standards — — 180 ps

—455055%

—0.44——UI

Pattern

Transition

Density

— — — Number of

——————

SPI4 0000000000

10% 256 — —

1111111111

— 10010000 50% 256 — —

Miscellaneous 10101010 100% 256 — —

— 10101010 — 256 — —

repetitions

Notes to Table 4–41:

(1) When J = 4 to 10, the SERDES block is used.

When J = 1 or 2, the SERDES block is bypassed.
(2) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input

clock frequency × W ≤ 1,040.
(3) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and

the clock routing resource (global, regional, or local) used. The I/O differential buffer and input register do not

have a minimum toggle rate.

4–38 Altera Corporation

September 2008

PLL Timing Specifications

PLL Timing
Specifications

Tables 4–42 and 4–43 describe the HardCopy II PLL specifications when

operating in both the commercial junction temperature range (0° to 85° C)
and the industrial junction temperature range (–40° to 100° C), except for
the clock switchover feature. Like the Stratix II devices, the clock
switchover feature is only supported from the 0° to 100° C junction
temperature range.

Table 4–42. HardCopy II Enhanced PLL Specifications (Part 1 of 2)

Name Description Min Typ Max Unit

f

IN

f

INPFD

f

INDUTY

f

EINDUTY

t

INJITTER

t

OUTJITTER

t

FCOMP

f

OUT

t

OUTDUTY

f

SCANCLK

t

CONFIGEPLL

f

OUT_EXT

Input clock frequency for HC210,

2 — 500 MHz

HC220, HC230 and HC240 devices

Input clock frequency for the

2 — 320 (1) MHz

HC210W device

Input frequency to the PFD 2 — 420 MHz

Input clock duty cycle 40 — 60 %

External feedback input clock duty

40 — 60 %

cycle

Input or external feedback clock

—0.5 — ns
input jitter tolerance in terms of
period jitter. Bandwidth ≤ 0.85 MHz

Input or external feedback clock

—1 — ns
input jitter tolerance in terms of
period jitter. Bandwidth > 0.85 MHz

Dedicated clock output period jitter
for HC210, HC220, HC230 and
HC240 devices

——250ps for ≥ 100 MHz

outclk

25 mUI for < 100 MHz

outclk

Dedicated clock output period jitter
for HC210W device

——300ps for ≥ 100 MHz

outclk

30 mUI for < 100 MHz

outclk

External feedback compensation

— — 10 ns
time

Output frequency for internal global

1.5 (2) — 550 MHz

or regional clock

Duty cycle for external clock output

45 50 55 %

(when set to 50%).

Scanclk frequency — — 100 MHz

Time required to reconfigure scan

— 174/f

SCANCLK

—ns

chains for enhanced PLLs

PLL external clock output

1.5 (2) — (1) MHz

frequency

(pp)

(pp)

ps or

mUI

ps or

mUI

Altera Corporation 4–39
September 2008

HardCopy Series Handbook, Volume 1

Table 4–42. HardCopy II Enhanced PLL Specifications (Part 2 of 2)

Name Description Min Typ Max Unit

t

LOCK

Time required for the PLL to lock
from the time it is enabled or the
end of device configuration

t

DLOCK

Time required for the PLL to lock
dynamically after automatic clock
switchover between two identical
clock frequencies

f

SWITCHOVER

Frequency range where the clock
switchover performs properly

f

CLKW

f

VCO

PLL closed loop bandwidth 0.13 1.2 16.9 MHz

PLL VCO operating range for
HC210, HC220, HC230 and HC240
devices

PLL VCO operating range for
HC210W devices

f

SS

Spread spectrum modulation
frequency

% spread Percent down spread for a given

clock frequency

t

PLL_PSERR

t

ARESET

Accuracy of PLL phase shift — — ± 15 ps

Minimum pulse width on ARESET
signal.

t

ARESET_RECONFIG

Minimum pulse width on the areset
signal when using PLL
reconfiguration. Reset the PLL after
scan done goes high.

—0.03 1 ms

—— 1 ms

4 — 500 MHz

300 — 1,040 MHz

300 — 840 MHz

100 — 500 MHz

0.4 0.5 0.6 %

10 (3) ——ns

500 (4) ——ns

500 — — ns

Notes to Table 4–42:

(1) Limited by I/O f
(2) If the counter cascading feature of the PLL is used, there is no minimum output clock frequency.
(3) Applicable when the PLL input clock has been running continuously for at least 10 µs.
(4) Applicable when the PLL input clock has stopped toggling or has been running continuously for less than 10 µs.

MAX

.

4–40 Altera Corporation

September 2008

PLL Timing Specifications

Table 4–43. HardCopy II Fast PLL Specifications (Part 1 of 2)

Name Description Min Typ Max Unit

f

IN

f

INPFD

f

INDUTY

t

INJITTER

f

VCO

f

OUT

f

OUT_IO

t

CONFIGPLL

f

CLBW

t

LOCK

t

PLL_PSERR

t

ARESET

Input clock frequency for HC210, HC220,

16 — 717 MHz

HC230 and HC240 devices

Input clock frequency for the HC210W

16 — 320 (1) MHz

device

Input frequency to the PFD 16 — 500 MHz

Input clock duty cycle 40 — 60 %

Input clock jitter tolerance in terms of period

—0.5—ns

jitter. Bandwidth ≤ 2MHz

Input clock jitter tolerance in terms of period

—1—ns

jitter. Bandwidth > 0.2 MHz

Upper VCO frequency range for HC210,

300 — 1,040 MHz

HC220, HC230 and HC240 devices

Upper VCO frequency range for HC210W

300 — 840 MHz

devices

Lower VCO frequency range for HC210,

150 — 520 MHz

HC220, HC230 and HC240 devices

Lower VCO frequency range for HC210W

150 — 420 MHz

device

PLL output frequency to GCLK or RCLK 4.6875 — 550 MHz

PLL output frequency to LVDS or DPA clock

150 — 1,040 MHz
for HC210, HC220, HC230 and HC240
devices

PLL output frequency to LVDS or DPA clock

150 — 840 MHz
for HC210W devices

PLL clock output frequency to regular I/O pin 4.6875 — (1) MHz

Time required to reconfigure scan chains for

—75/f

SCANCLK

—ns

fast PLLs

PLL closed loop bandwidth 1.16 5 28 MHz

Time required for the PLL to lock from the

—0.031ms
time it is enabled or the end of the device
configuration

Accuracy of PLL phase shift — — ± 30 ps

Minimum pulse width on areset signal. 10 — — ns

(pp)

(pp)

Altera Corporation 4–41
September 2008

HardCopy Series Handbook, Volume 1

Table 4–43. HardCopy II Fast PLL Specifications (Part 2 of 2)

Name Description Min Typ Max Unit

t

ARESET_RECONFIG

Note to Table 4–43:

(1) Limited by I/O f

Minimum pulse width on the areset signal
when using PLL reconfiguration. Reset the
PLL after scan done goes high.

MAX

.

500 — — ns

External

Table 4–44 summarizes the maximum clock rate that HardCopy II devices

can support with external memory devices.

Memory
Interface
Specifications

Table 4–44. HardCopy II Maximum Clock Rate Support for External Memory Interfaces Note (1)

HardCopy II Device

Memory Standards

DDR 150 133 200 200 MHz

DDR2 (7) 150 133 267 233 MHz

QDRII (6) 150 133 250 233 (5) MHz

RLDRAMII (6) 150 133 250 (4) 233 (4) MHz

Notes to Table 4–44:

(1) HardCopy II devices do not support PLL-based external memory interface except for SDR SDRAMs which do not

require the DLL.
(2) HC210W supports memory interface on the top I/O banks.
(3) HC210 and HC220 support memory interface on the top I/O banks. HC230 and HC240 support memory interface

on the top and bottom I/O banks.
(4) You will need to under-clock a 300 MHz memory device.
(5) You will need to under-clock a 250 MHz memory device.
(6) Based on a DDIO scheme with the 1.8-V HSTL I/O standard.
(7) Based on the PLL dedicated scheme. Use the same F

write-side is limited by the new tDS/tH specification.

Wire Bond Package

HC210W (2)

HC210 / HC220 / HC230 / HC240 (3)

specification for Static-PHY and Auto-PHY since the

MAX

Flip Chip Package

Com (C) Ind (I)Com (C) Ind (I)

Unit

4–42 Altera Corporation

September 2008

External Memory Interface Specifications

Tables 4–45 through 4–51 contain HardCopy II device specifications for

the dedicated circuitry used for interfacing with external memory
devices.

Table 4–45. DLL Frequency Range Specifications

Frequency Mode Frequency Range Resolution (Degrees)

0 100 to 175 30

1 150 to 230 22.5

2 200 to 310 30

3 240 to 350 36

Table 4–46 lists the maximum delay in the fast timing model for the

HardCopy II DQS delay buffer. Multiply the number of delay buffers that
you are using in the DQS logic block to get the maximum delay
achievable in your system. For example, if you implement a 90° phase
shift at 200 MHz, you use three delay buffers in mode 2. The maximum
achievable delay from the DQS block is then 3 × .416 ps = 1.248 ns.

Table 4–46. DQS Delay Buffer Maximum Delay in Fast Timing Model

DLL Frequency Mode Maximum Delay Per Delay Buffer Unit

0 0.833 ns

1, 2, 3 0.416 ns

Table 4–47. DQS Period Jitter Specifications for DLL-Delayed Clock
(tDQS_JITTER) Note (1)

Number of DQS Delay Buffer

Stages (2)

1 80 110 ps

2 110 130 ps

3 130 180 ps

4 160 210 ps

Notes to Ta b l e 4 – 47 :

(1) Peak-to-peak period jitter on the phase shifted DQS clock.
(2) Delay stages used for requested DQS phase shift are reported in your project’s

Compilation Report in the Quartus II software.

Altera Corporation 4–43
September 2008

Commercial Industrial Unit

HardCopy Series Handbook, Volume 1

Table 4–48. DQS Phase Jitter Specifications for DLL-Delayed Clock (tDQS
PHASE_JITTER) Note (1)

Number of DQS Delay Buffer

Stages (2)

130ps

260ps

390ps

4 120 ps

Notes to Ta b l e 4 – 48 :

(1) Peak-to-peak phase jitter on the phase shifted DDS clock (digital jitter is caused

by DLL tracking).

(2) Delay stages used for requested DQS phase shift are reported in your project’s

Compilation Report in the Quartus II software.

DQS Phase Jitter Unit

Table 4–49. DQS Phase-Shift Error Specifications for DLL-Delayed Clock
(tDQS_PSERR) Note (1)

Number of DQS Delay Buffer

Stages (2))

130ps

260ps

390ps

4 120 ps

HC210, HC220, HC230 HC240 Unit

Notes to Ta b l e 4 – 49 :

(1) This error specification is the absolute maximum and minimum error. For

example, skew on three delay buffer stages with an HC240 device is 105 ps or
±52.5ps.

(2) Delay stages used for requested DQS phase shift are reported in your project’s

Compilation Report in the Quartus II software.

4–44 Altera Corporation

September 2008

Hot Socketing

Table 4–50. DQS Bus Clock Skew Adder Specifications
(tDQS_CLOCK_SKEW_ADDER) Note (1)

Mode DQS Clock Skew Adder Unit

×4 DQ per DQS 40 ps

×9 DQ per DQS 70 ps

×18 DQ per DQS 75 ps

×36 DQ per DQS 95 ps

Note to Table 4–50:

(1) This skew speci fication is the absolute maximum and minimum skew. For example,

skew on a ×4 DQ group is 40 ps or ± 20 ps.

Table 4–51. DQS Phase Offset Delay Per Stage Note (1)

HardCopy II Devices Min Max Unit

All 9 14 ps

Note to Table 4–51

(1) The delay settings are linear. The valid settings for phase offset are -64 to +63 for

frequency mode 0 and -32 to +31 for frequency modes 1, 2, and 3. The typical
value equals the average of the minimum and maximum values.

Hot Socketing

HardCopy II devices offer hot socketing, which is also known as hot
plug-in or hot swap, and power sequencing support without the use of
any external devices. You can insert or remove a HardCopy II device in a
system during system operation without causing undesirable effects to
the running system bus or the board that was inserted into the system.

The hot socketing feature in HardCopy II devices allow:

■ The device can be driven before power-up without any damage to

the device itself.

■ I/O pins remain tri-stated during power-up, so they do no disrupt

bus operation when HardCopy II I/Os are inserted in the system.

■ Signal pins do not drive the V

■ External input signals to I/O pins of the device do not internally

power the V

CCIO

or V

power supplies of the device via internal

CCINT

CCIO

, V

CCPD

, or V

power supplies.

CCINT

paths within the device.

Altera Corporation 4–45
September 2008

HardCopy Series Handbook, Volume 1

In a hot socketing situation, a device’s output buffers are turned off
during system power-up or power-down. To simplify board design,
HardCopy II devices support any power-up or power-down sequence

and V

(V

CCIO

signals into the device before or during power-up or power-down
without damaging the device.

). For mixed-voltage environments, you can drive

CCINT

Electrostatic Discharge

You can power up or power down the V

CCIO

and V

CCINT

pins in any
sequence. The power supply ramp rates can range from 100 ns to 100 ms.
All VCC supplies must power down within 100 ms of each other to
prevent the I/O pins from driving out. During hot socketing, the I/O pin
capacitance is less than 15 pF and the clock pin capacitance is less than
20 pF.

■ The hot socketing DC specification is | I

■ The hot socketing AC specification is | I

| < 300 µA.

IOPIN

| < 8 mA for 10 ns

IOPIN

or less.

1 The DC specification applies when all VCC supplies to the

device are stable in the powered-up or powered-down
conditions. The AC specification applies when the device is
being powered up or powered down in any of the conditions
mentioned above.

Electrostatic discharge (ESD) protection is a design practice that is
integrated in Altera FPGAs and structured ASIC devices. HardCopy II
devices are no exception, and they are designed with ESD protection on
all I/O and power pins.

4–46 Altera Corporation

September 2008

Electrostatic Discharge

Figure 4–3 shows a typical HardCopy II CMOS I/O buffer structure

which will be used to explain ESD protection.

Figure 4–3. Transistor-Level Diagram of HardCopy II Device I/O Buffers

The CMOS output drivers in the I/O pins intrinsically provide
electrostatic discharge protection. There are two cases to consider for ESD
voltage strikes: positive voltage zap and negative voltage zap.

A positive ESD voltage zap occurs when a positive voltage is present on
an I/O pin due to an ESD charge event. This can cause the N+
(Drain)/PSubstrate junction of the N-channel drain to break down and
the N+ (Drain)/P-Substrate/N+ (Source) intrinsic bipolar transistor turns
on to discharge ESD current from I/O pin to GND.

Altera Corporation 4–47
September 2008

HardCopy Series Handbook, Volume 1

The dashed line (see Figure 4–4) shows the ESD current discharge path
during a positive ESD zap.

Figure 4–4. ESD Protection During Positive Voltage Zap

When the I/O pin receives a negative ESD zap at the pin that is less than

-0.7 V (0.7 V is the voltage drop across a diode), the intrinsic
P-Substrate/N+ drain diode is forward biased. Hence, the discharge
ESD current path is from GND to the I/O pin, as shown in Figure 4–5.

Figure 4–5. ESD Protection During Negative Voltage Zap

4–48 Altera Corporation

September 2008