ALTERA HardCopy Service Manual

HardCopy Series Handbook, Volume 1
101 Innovation Drive San Jose, CA 95134 www.alter a.com
Preliminary Information
H5V1-4.5
Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des­ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. Mentor Graphics and ModelSim are registered trademarks of Mentor Graphics Corporation. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service de­scribed herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services
.
ii Altera Corporation
Preliminary

Contents

Chapter Revision Dates ........................................................................... ix
About this Handbook ............................................................................... xi
How to Contact Altera ........ ..................................................................................................................... xi
Typographic Conventions ....................................................................................................................... xi
Section I. HardCopy Stratix Device Family Data Sheet
Revision History .................................................................................................................................... 1–1
Chapter 1. Introduction to HardCopy Stratix Devices
Introduction ............................................................................................................................................ 1–1
Features ................................................................................................................................................... 1–2
Document Revision History ............................................ ..................................................................... 1–4
Chapter 2. Description, Architecture, and Features
Introduction ............................................................................................................................................ 2–1
HardCopy Stratix and Stratix FPGA Differences ............................................................................. 2–2
Logic Elements ....................................................................................................................................... 2–4
Embedded Memory ......................... ...................................................................................................... 2–4
DSP Blocks .............................................................................................................................................. 2–6
PLLs and Clock Networks ............................................................................... ..................................... 2–6
I/O Structure and Features .................................................................................................................. 2–6
Power-Up Modes in HardCopy Stratix Devices ... ............................................................................ 2–7
Hot Socketing ......................................................................................................................................... 2–8
HARDCOPY_ FPGA_ PROTOTYPE Devices ..................................................................................... 2–9
Document Revision History ............................................ ................................................................... 2–10
Chapter 3. Boundary-Scan Support
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 3–1
Document Revision History ............................................ ..................................................................... 3–4
Chapter 4. Operating Conditions
Recommended Operating Conditions ................................................................................................ 4–1
Power Consumption ............................................................ ............................................................... 4–15
Timing Closure .................................................................................................................................... 4–15
External Timing Parameters ......................................................................................................... 4–16
HardCopy Stratix External I/O Timing ...................................................................................... 4–17
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HardCopy Series Handbook, Volume 1
Maximum Input and Output Clock Rates .................................................................................. 4–23
High-Speed I/O Specification ........................................................................................................... 4–28
PLL Specifications ................................................................................................................................ 4–30
Electrostatic Discharge ........................................................................................................................ 4–33
Positive Voltage Zap ................................................................... ................................................... 4–34
Negative Voltage Zap ............................................... ..................................................................... 4–35
Document Revision History ............................................ ................................................................... 4–36
Chapter 5. Quartus II Support for HardCopy Stratix Devices
Introduction ............................................................................................................................................ 5–1
Features ................................................................................................................................................... 5–2
HARDCOPY_FPGA_PROTOTYPE, HardCopy Stratix and Stratix Devices ................................ 5–3
HardCopy Design Flow ............................................................................................... ......................... 5–5
The Design Flow Steps of the One Step Process ....................................................... ................... 5–6
How to Design HardCopy Stratix Devices ........................................................................................ 5–7
Tcl Support for HardCopy Migration ......................................................................................... 5–11
Design Optimization and Performance Estimation ........................................................................ 5–12
Design Optimization ............................................................... ....................................................... 5–12
Performance Estimation ................................................................................................................ 5–12
Buffer Insertion ............................................................................................................................... 5–16
Placement Constraints ................................................................................................................... 5–16
Location Constraints ........................................................................................................................... 5–17
LAB Assignments .......................................................................... ................................................. 5–17
LogicLock Assignments ................................................................................................................ 5–18
Checking Designs for HardCopy Design Guidelines .................................................................... 5–19
Altera Recommended HDL Coding Guidelines ........................................................................ 5–19
Design Assistant .............................................................................. ............................................... 5–19
Reports and Summary ................................................................................................................... 5–20
Generating the HardCopy Design Database ................................................................................... 5–21
Static Timing Analysis ........................................................................................................................ 5–23
Early Power Estimation ................ ...................................................................................................... 5–23
HardCopy Stratix Early Power Estimation ................................................................................ 5–23
HardCopy APEX Early Power Estimation ................................................................................. 5–24
Tcl Support for HardCopy Stratix ..................................................................................................... 5–24
Targeting Designs to HardCopy APEX Devices ............................................................................. 5–25
Conclusion ............................................................................................................................................ 5–25
Related Documents ............................... .............................................................................................. 5–26
Document Revision History ............................................ ................................................................... 5–26
Chapter 6. Design Guidelines for HardCopy Stratix Performance Improvement
Introduction ............................................................................................................................................ 6–1
Background Information ...................................................................................................................... 6–1
Planning Stratix FPGA Design for HardCopy Stratix Design Conversion ................................... 6–2
Partitioning Your Design ................................................................................................................ 6–2
Physical Synth esis Optimization .................................................................................................... 6–3
Using LogicLock Regions in HardCopy Stratix Designs ................................................................. 6–4
Recommended LogicLock Settings for HardCopy Stratix Designs .......................................... 6–5
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Contents
Using Design Space Explorer for HardCopy Stratix Designs ......................................................... 6–6
Recommended DSE Settings for HardCopy Stratix Designs ..................................................... 6–7
Performance Improvement Example .................................................................................................. 6–8
Initial Design Example Settings . .................................................................................................... 6–8
Using Analysis and Synthesis Settings for Performance Improvement ................................ 6–11
Using Fitter Assignments and Physical Synthesis Optimizations for Performance
Improvement .................................................................................................................................. 6–13
Design Space Ex plorer ................................................................................................................... 6–15
Back-Annotation and Location Assignment Adjustments ....................................................... 6–17
Conclusion ............................................................................................................................................ 6–21
Document Revision History ............................................ ................................................................... 6–22
Section II. HardCopy APEX Device Family Data Sheet
Revision History .................................................................................................................................... 6–1
Chapter 7. Introduction to HardCopy APEX Devices
Introduction ............................................................................................................................................ 7–1
Features... ................................................................................................................................................ 7–1
...and More Features .............................................................................................................................. 7–2
Document Revision History ............................................ ..................................................................... 7–5
Chapter 8. Description, Architecture, and Features
Introduction ............................................................................................................................................ 8–1
Differences Between HardCopy APEX and APEX 20K FPGAs ..................................................... 8–5
Power-up Mode and Configuration Emulation ................................................................................ 8–5
Speed Grades ................................................................................................... ....................................... 8–6
Quartus II-Generated Output Files ..................................................................................................... 8–6
Document Revision History ............................................ ..................................................................... 8–7
Chapter 9. Boundary-Scan Support
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 9–1
Document Revision History ............................................ ..................................................................... 9–3
Chapter 10. Operating Conditions
Recommended Operating Conditions .............................................................................................. 10–1
Document Revision History ............................................ ................................................................. 10–15
Section III. General HardCopy Series Design Considerations
Revision History .................................................................................................................................. 10–1
Chapter 11. Design Guidelines for HardCopy Series Devices
Introduction .......................................................................................................................................... 11–1
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HardCopy Series Handbook, Volume 1
Design Assistant Tool ......................................................................................................................... 11–1
Asynchronous Clock Domains ................................ .......................................................................... 11–2
Transferring Data between Two Asynchronous Clock Domains ........................................... 11–4
Gated Clocks ......................................................................................................................................... 11–7
Preferred Clock Gating Circuit ..................................................................................................... 11–7
Alternative Clock Gating Circuits ................................................................................................ 11–9
Inverted Clocks ............................................................................................................................. 11–11
Clocks Driving Non-Clock Pins .................................................................. ............................... 11–11
Clock Signals Should Use Dedicated Clock Resources .......................................................... 11–13
Mixing Clock Edges ..................................................................................................................... 11–14
Combinational Loops ...... .................................................................................................................. 11–16
Intentional Delays .............................................................................................................................. 11–18
Ripple Counters ................................................................................................................................. 11–20
Pulse Generators ................................................................................................................................ 11–21
Combinational Oscillator Circuits ................................................................................................... 11–24
Reset Circuitry .................................................................................................................................... 11–25
Gated Reset .................................................................................................................................... 11–25
Asynchronous Reset Synchronization ...................................................................................... 11–26
Synchronizing Reset Signals Across Clock Domains .............................................................. 11–27
Asynchronous RAM .......................................................................................................................... 11–30
Conclusion .......................................................................................................................................... 11–31
Document Revision History ............................................ ................................................................. 11–31
Chapter 12. Power-Up Modes and Configuration Emulation in HardCopy Series Devices
Introduction .......................................................................................................................................... 12–1
HardCopy Power-Up Options ........................................................................................................... 12–1
Instant On Options ......................................................................................................................... 12–2
Configuration Emulation of FPGA Configuration Sequence .................................................. 12–9
Power-Up Options Summary When Designing With HardCopy Series Devices .................... 12–15
Power-Up Option Selection and Examples ................................................................................... 12–17
Replacing One FPGA With One HardCopy Series Device .................................................... 12–18
Replacing One or More FPGAs With One or More HardCopy Series Devices in a Multiple-
Device Configuration Chain ....................... ................................................................................ 12–19
Replacing all FPGAs with HardCopy Series Devices in a Multiple-Device Configuration Chain
......... .................................................................................................................................................12–21
FPGA to HardCopy Configuration Migration Examples ............................................................ 12–21
HardCopy Series Device Replacing a Stand-Alone FPGA ..................................................... 12–21
HardCopy Series Device Replacing an FPGA in a Cascaded Configuration Chain .......... 12–23
HardCopy Series Device Replacing an FPGA Configured Using a Microprocessor ......... 12–25
HardCopy Stratix Device Replacing FPGA Configured in a JTAG Chain .......................... 12–28
HardCopy II Device Replacing Stratix II Device Configured With a Microprocessor ...... 12–30
Conclusion .......................................................................................................................................... 12–32
Document Revision History ............................................ ................................................................. 12–33
vi Altera Corporation
Preliminary
Contents
Section IV. HardCopy Design Center Migration Process
Revision History .................................................................................................................................. 12–1
Chapter 13. Back-End Design Flow for HardCopy Series Devices
Introduction .......................................................................................................................................... 13–1
HardCopy II Back-End Design Flow ................................................................... ............................. 13–1
Device Netlist Generation ........... .................................................................................................. 13–2
Design for Testability Insertion .................................................................................................... 13–3
Clock Tree and Global Signal Insertion ...................................................................................... 13–3
Formal Verification of the Processed Netlist .............................................................................. 13–3
Timing and Signal Integrity Driven Place and Route ............................................................... 13–3
Parasitic Extraction and Timing Analysis ................................................................................... 13–4
Layout Verification ...................................... .................................................................................. 13–4
Design Signoff ................................................................................................................................. 13–4
HardCopy Stratix and HardCopy APEX Migration Flow ............................................................. 13–5
Netli st Generation .......................................................................................................................... 13–6
Testability Audit ............................................................................................................................. 13–6
Placement ........................................................................................................................................ 13–6
Test Vector Generation ................ .................................................................................................. 13–7
Routing ............................................................................................................................................ 13–7
Extracted Delay Calculation ......................................................................................................... 13–7
Static Timing Analysis and Timing Closure .............................................................................. 13–7
Formal Verification ........................................................................................................................ 13–8
Physical Verification ...................................................................................................................... 13–8
Manufacturing .............................................................................................. .................... ................... 13–8
Testing ................................................................................................................................................... 13–9
Unused Resources ........................................................................................................ ..................... 13–11
Conclusion .......................................................................................................................................... 13–12
Document Revision History ............................................ ................................................................. 13–12
Chapter 14. Back-End Timing Closure for HardCopy Series Devices
Introduction .......................................................................................................................................... 14–1
Timing Analysis of HardCopy Prototype Device ..................................................................... 14–1
Cell Structure ........................................................................................................................................ 14–2
HardCopy II .................................................................................................................................... 14–2
HardCopy Stratix, HardCopy APEX ........................................................................................... 14–2
Clock Tree Structure ............................................................................................................................ 14–3
HardCopy II .................................................................................................................................... 14–3
HardCopy Stratix ........................................................................................................................... 14–3
HardCopy APEX ............................................................................................................................ 14–3
Importance of Timing Constraints ........................................................................................... ......... 14–4
Correcting Timing Violations ....................................................................................................... 14–4
Hold-Time Violations .................................................................................................................... 14–5
Setup-Ti me Violations ... .............................................................................................................. 14–10
Timing ECOs ...................................................................................................................................... 14–15
Conclusion .......................................................................................................................................... 14–17
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Preliminary
HardCopy Series Handbook, Volume 1
Document Revision History ............................................ ................................................................. 14–17
viii Altera Corporation
Preliminary

Chapter Revision Dates

The chapters in this book, HardCopy Series Handbook, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Introduction to HardCopy Stratix Devices
Revised: September 2008 Part number: H51001-2.3
Chapter 2. Description, Architecture, and Features
Revised: September 2008 Part number: H51002-3.3
Chapter 3. Boundary-Scan Support
Revised: September 2008 Part number: H51004-3.3
Chapter 4. Operating Conditions
Revised: September 2008 Part number: H51005-3.3
Chapter 5. Quartus II Support for HardCopy Stratix Devices
Revised: September 2008 Part number: H51014-3.3
Chapter 6. Design Guidelines for HardCopy Stratix Performance Improvement
Revised: September 2008 Part number: H51027-1.3
Chapter 7. Introduction to HardCopy APEX Devices
Revised: September 2008 Part number: H51006-2.2
Chapter 8. Description, Architecture, and Features
Revised: September 2008 Part number: H51007-2.2
Chapter 9. Boundary-Scan Support
Revised: September 2008 Part number: H51009-2.2
Altera Corporation ix
Preliminary
HardCopy Series Handbook
Chapter 10. Operating Conditions
Revised: September 2008 Part number: H51010-2.2
Chapter 11. Design Guidelines for HardCopy Series Devices
Revised: September 2008 Part number: H51011-3.3
Chapter 12. Power-Up Modes and Configuration Emulation in HardCopy Series Devices
Revised: September 2008 Part number: H51012-2.4
Chapter 13. Back-End Design Flow for HardCopy Series Devices
Revised: September 2008 Part number: H51019-1.3
Chapter 14. Back-End Timing Closure for HardCopy Series Devices
Revised: September 2008 Part number: H51013-2.3
x Altera Corporation
Preliminary

About this Handbook

How to Contact Altera

Typographic Conventions

This handbook provides comprehensive information about the Altera® HardCopy
®
devices.
For the most up-to-date information about Altera products, refer to the following table.
Contact
Technical support Website www.altera.com/support/
Technical training
Product literature Website www.altera.com/literature
Altera literature services Email literat ure@altera.com
Non-technical (General)
(SoftwareLicensing)
Note to table:
(1) You can also contact your local Altera sales office or sales representative.
Contact Method
Website www.altera.com/training
Email custrain@altera.com
Email nacomp@altera.com
Email authorization@altera.com
Address
This document uses the typographic conventions shown below.
Visual Cue Meaning
Bold Type with Initial Capital Lett ers
bold type External timing parameters, directory names, project names, disk drive names,
Italic Type with Initial Capital Letters
Altera Corporation xi
Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.
filenames, filename extensions, and software utility names are shown in bold type. Examples: f
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
, \qdesigns directory, d: dri ve, chiptrip.gdf file.
MAX
Preliminary
HardCopy Series Handbook, Volume 1
Visual Cue Meaning
Italic t ype Internal timing parameters and variables are shown in italic type.
Examples: t
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file.
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading” Title” References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
PIA
, n + 1.
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., rese tn.
Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesign s\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL key wo r d SUBDES IGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c., etc.
Bullets are used in a list of items when the sequence of the items is not important.
v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention.
c
w
r The angled arrow indicates you should press the Enter key.
f The feet direct you to more information on a particular topic.
Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.
A caution calls attention to a condition or possible situation that can damage or destroy the product or the user’s work.
A warning calls attention to a condition or possible situation that can cause injury to the user.
xii Altera Corporation
Preliminary
Section I. HardCopy Stratix
Device Family Data Sheet

Revision History

This section provides designers with the data sheet specifications for HardCopy
definitions of the internal architecture, JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, and a reference to power consumption for HardCopy Stratix structured ASICs.
This section contains the following:
Chapter 1, Introduction to HardCopy Stratix Devices
Chapter 2, Description, Architecture, and Features
Chapter 3, Boundary-Scan Support
Chapter 4, Operating Conditions
Chapter 5, Quartus II Support for HardCopy Stratix Devices
Chapter 6, Design Guidelines for HardCopy Stratix Performance
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook.
®
Stratix structured ASICs. The chapters contain feature
Improvement
Altera Corporation Section I–1
Preliminary
Revision History HardCopy Series Handbook, Volume 1
Section I–2 Altera Corporation
Preliminary
H51001-2.4

1. Introduction to HardCopy Stratix Devices

Introduction

HardCopy® Stratix® structured ASICs, Altera’s second-generation HardCopy structured ASICs, are low-cost, high-performance devices with the same architecture as the high-density Stratix FPGAs. The combination of Stratix FPGAs for prototyping and design verification, HardCopy Stratix devices for high-volume production, and the
Quartus complete and powerful alternative to ASIC design and development.
HardCopy Stratix devices are architecturally equivalent and have the same features as the corresponding Stratix FPGA. They offer pin-to-pin compatibility using the same package as the corresponding Stratix FPGA prototype. Designers can prototype their design to verify functionality with Stratix FPGAs before seamlessly migrating the proven design to a HardCopy Stratix structured ASIC.
The Quartus II software provides a complete set of inexpensive and easy-to-use tools for designing HardCopy Stratix devices. Using the successful and proven methodology from HardCopy APEX™ devices, Stratix FPGA designs can be seamlessly and quickly migrated to a low-cost ASIC alternative. Desi gners can use the Quartus II software to design HardCopy Stratix devices to obtain an average of 50% higher performance and up to 40% lower power consumption than can be achieved in the corresponding Stratix FPGAs. The migration process is fully automated, requires minimal customer involvement, and takes approximately eight weeks to deliver fully tested HardCopy Stratix prototypes.
®
II design software beginning with version 3.0, provide a
The HardCopy Stratix devices use the same base arrays across multiple designs for a given device density and are customized using the top two metal layers. The HardCopy Stratix family consists of the HC1S25, HC1S30, HC1S40, HC1S60, and HC1S80 devices. Table 1–1 provides the details of the HardCopy Stratix devices.
Altera Corporation 1–1 September 2008 Preliminary
HardCopy Series Handbook, Volume 1
Table 1–1. HardCopy Stratix Devices and Features
Device LEs (1) M512 Blocks M4K Blocks
HC1S25 25,660 224 138 2 10 6
HC1S30 32,470 295 171 2 (4) 12 6
HC1S40 41,250 384 183 2 (4) 14 6
HC1S60 57,120 574 292 6 18 12
HC1S80 79,040 767 364 6 (4) 22 12
Notes to Tab l e 1 –1 :
(1) LE: logic elements. (2) DSP: digital signal processing. (3) PLLs: phase-locked loops. (4) In HC1S30, HC1S40, and HC1S80 devices, there are fewer M-RAM blocks than in the equivalent Stratix FPGA. All
other resources are identical to the Stra tix counterpart.

Features

HardCopy Stratix devices are manufactured on the same 1.5-V, 0.13 μm all-layer-copper metal fabrication process (up to eight layers of metal) as
M-RAM
Blocks
DSP Blocks (2) PLLs (3)
the Stratix FPGAs.
Preserves the functionality of a configured Stratix device
Pin-compatible with the Stratix counterparts
On average, 50% faster than their Stratix equivalents
On average, 40% less power consumption than their Stratix
equivalents
25,660 to 79,040 LEs
Up to 5,658,408 RAM bits available
TriMatrix memory architecture consisting of three RAM block sizes
to implement true dual-port memory and first-in-first-out (FIFO) buffers
Embedded high-speed DSP blocks provide dedicated
implementation of multipliers, multiply-accumulate functions, and finite impulse response (FIR) filters
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device
which provide identical features as the FPGA counterparts, including spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, advanced multiplication, and phase shifting
Supports numerous single-ended and differential I/O standards
Supports high-speed networking and communications bus
standards including RapidIO™, UTOPIA IV, CSIX, HyperTransport technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4
Differential on-chip termination support for LVDS
1–2 Altera Corporation
Preliminary September 2008
Features
Supports high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM, DDR fast-cycle RAM (FCRAM), and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) megafunctions from
Available in space-saving flip-chip FineLine BGA
®
Altera
MegaCore® functions, and Altera Megafunction Partners
Program (AMPP
SM
) megafunctions
®
and wire-bond
packages (Tables 1–2 and 1–3)
Optional emulation of original FPGA configuration sequence
Optional instant-on power-up
1 The actual performance and power consumption improvements
over the Stratix equivalents mentioned in this data sheet are design-dependent.
Table 1–2. HardCopy Stratix Device Package Options and I/O Pin Counts
Note (1)
Device
HC1S25 473
HC1S30 597
HC1S40 613 (4)
HC1S60 782
HC1S80 782
Notes to Tab l e 1 –2 :
(1) Quartus II I/O pi n counts include one additional pin, PLLENA, which is not a
general-purpose I/O pin. PLLENA can only be used to enable the PLLs. (2) This device uses a wire-bond package. (3) This device uses a flip-chip package. (4) In the Stratix EP 1S40F7 80 FPGA, the I/O pins U12 and U18 are general-purpose
I/O pins. In the F PGA prototype,
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE, and in the HardCopy Stratix
HC1S40F 780 device, U12 and U18 must be connected to ground. The
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE and HC1S40F780 pin-outs are
identical.
672-Pin
FineLine BGA (2)
780-Pin
FineLine BGA (3)
1,020-Pin
FineLine BGA (3)
Altera Corporation 1–3 September 2008 Preliminary
HardCopy Series Handbook, Volume 1
Table 1–3. HardCopy Stratix Device Package Sizes
Document
Device
Pitch (mm) 1.00 1.00 1.00
Area (mm2)
Length × width
(mm × mm)
672-Pin
FineLine BGA
729 841 1,089
27 × 27 29 × 29 33 × 33
Table 1–4 shows the revision history for this chapter.
780-Pin
FineLine BGA
Revision History
Table 1–4. Document Revision History
Date and Document
Version
September 2008 v2.4
June 2007 v2.3 Updated Introduction section.
December 2006 v2.2
March 2006 Formerly chapter 5; no content change.
October 2005 v2.1 Minor edits
January 2005 v2.0 Minor edits
June 2003 v1.0 Initial release of Chapter 5, Introduction to HardCopy Stratix
Revised chapter number and metadata.
Updated Table 1–2.
Updated revision history.
Devices, in the HardCopy Device Handbook.
Changes Made Summary of Changes
1,020-Pin
FineLine BGA
1–4 Altera Corporation
Preliminary September 2008
H51002-3.4

2. Description, Architecture, and Features

Introduction

HardCopy® Stratix® structured ASICs provide a comprehensive alternative to ASICs. The HardCopy Stratix device family is fully
supported by the Quartus intellectual property (IP) portfolio, provides a complete path from prototype to volume production. Designers can now procure devices, tools, and Altera
As shown in Figure 2–1, HardCopy Stratix devices preserve their Stratix FPGA counterpart’s architecture, but the programmability for logic, memory, and interconnect is removed. HardCopy Stratix devices are also manufactured in the same process technology and process voltage as Stratix FPGAs. Removing all configuration and programmable routing resources and replacing it with direct metal interconnect results in considerable die size reduction and the ensuing cost savings.
Figure 2–1. HardCopy Stratix Device Architecture
M512 RAM Blocks for Dual-Port Memory, Shift Registers, & FIFO Buffers
IOEs
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DSP Blocks for Multiplication and Full Implementation of FIR Filters
DSP
Block
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®
II des ign software, and, combined with a vast
®
IP for their high-volume applications.
M4K RAM Blocks for True Dual-Port Memory & Other Embedded Memory Functions
IOEs Support DDR, PCI, GTL+, SSTL-3, SSTL-2, HSTL, LVDS, LVPECL, PCML, HyperTransport & other I/O Standards
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M-RAM Block
Altera Corporation 2–1 September 2008

HardCopy Stratix and Stratix FPGA Differences

The HardCopy Stratix family consists of base arrays that are common to all designs for a particular device density. Design-specific customization is done within the top two metal layers. The base arrays use an area-efficient sea-of-logic-elements (SOLE) core an d extend the flexibility of high-density Stratix FPGAs to a cost-effective, high-volume production solution. With a seamless migration process employed in numerous successful designs, functionality-verified Stratix FPGA designs can be migrated to fixed-function HardCopy Stratix devices with minimal risk and guaranteed first-time success.
The SRAM configuration cells of the original Stratix devices are replaced in HardCopy Stratix devices by metal connects, which define the function of each logic element (LE), digital signal processing (DSP) block, phase-locked loop (PLL), embedded memory, and I/O cell in the device. These resources are interconnected using metallization layers. Once a HardCopy Stratix device has been manufactured, the functionality of the dev ic e i s fixe d an d n o re -p ro gr am mi ng is po ss ib le . H ow ev er, as is th e c as e with Stratix FPGAs, the PLLs can be dynamically configured in HardCopy Stratix devices.
HardCopy Stratix and Stratix FPGA Differences
To ensure HardCopy Stratix device functionality and performance, designers should thoroughly test the original Stratix FPGA-based design for satisfactory results before committing the design for migration to a HardCopy Stratix device. Unlike Stratix FPGAs, HardCopy Stratix devices are customized at the time of manufacturing and therefore do not have programmability support.
Since HardCopy Stratix devices are customized within the top two metal layers, no configuration circuitry is required. Refer to “Power-Up Modes
in HardCopy Stratix Devices” on page 2–7 for more information.
Depending on the design, HardCopy Stratix devices can provide, on average, a 50% performance improvement over equivalent Stratix FPGAs. The performance improvement is achieved by die size reduction, metal interconnect optimization, and customized signal buffering. HardCopy Stratix devices consume, on average, 40% less power than their equivalent Stratix FPGAs.
1 Designers can use the Quartus II software to design HardCopy
Stratix devices, estimate performance and power consumption, and maximize system throughput.
2–2 Altera Corporation
September 2008
Description, Architecture, and Features
Table 2–1 illustrates the differences between HardCopy Stratix and
Stratix devices.
Table 2–1. HardCopy Stratix and Stratix Device Comparison (Part 1 of 2)
HardCopy Stratix Stratix
Customized device. All reprogrammability support is removed and no configuration is required.
Average of 50% performance improvement over corresponding FPGA (1).
Average of 40% less power consumption compared to corresponding FPGA (1).
Contact Altera for information regarding specific IP support.
Double data rate (DDR) SDRAM maximum operating frequency is pending characterization.
All routing connections are direct and all unused routing is removed.
HC1S30 and HC1S40 devices have two M-RAM blocks. HC1S80 devices have six M-RAM blocks.
It is not possible to initialize M512 and M4K RAM contents during power-up.
The contents of memory output registers are unknown after power-on reset (POR).
HC1S30 and HC1S40 devices have six PLLs.
PLL dynamic reconfiguration uses ROM for information. This reconfiguration is performed in the back-end and does not affect the migration fl ow.
The I/O elements (IOEs) are equivalent but not identical to FPGA IOEs due to slight design optimizations for HardCopy devices.
Re-programmable with configuration is required upon power-up.
High-performance FPGA.
Standard FPGA power consumption.
IP support for all devices is available.
DDR SDRAM can operate at 200 MHz for -5 speed grade devices.
MultiTrack™ routing stitches together routing resources to provide a path.
EP1S30 and EP1S40 devices have four M-RAM blocks. EP1S80 devices have nine M-RAM blocks.
The contents of M512 and M4K RAM blocks can be preloaded during configuration with data specified in a mem ory initia lization file (.m if).
The contents of memory output registers are initialized to '0' after POR.
HC1S30 devices have 10 PLLs. HC1S40 devices have 12 PLLs.
PLL dynamic reconfiguration uses a MIF to initialize a RAM resource with information.
The IOEs are optimized for the FPGA architecture.
Altera Corporation 2–3 September 2008

Logic Elements

Table 2–1. HardCopy Stratix and Stratix Device Comparison (Part 2 of 2)
HardCopy Stratix Stratix
The I/O drive strength for single-ended I/O pins are slightly different and is modeled in the HardCopy Stratix IBIS models.
In the HC1S40 780-pin FineLine BGA® device, the I/O pins U12 and U18 must be connected to ground.
The BSDL file describes re-ordered Joint Test Action Group (JTAG) boundary-scan chains.
Note t o Table 2–1:
(1) Performance and power consumption are design dependant.
The I/O drive strength for single-ended I/O pins are found in Stratix IBIS models.
In the HC1S40 780-pin FineLine BGA device, the I/O pins U12 and U18 are available as general-purpose I/O pins.
The JTAG boundary-scan chain is defined in the BSDL file.
Logic Elements

Embedded Memory

Logic is implemented in HardCopy Stratix devices using the same architectural units as the Stratix device family. The basic unit is the logic element (LE) with logic array blocks (LAB) consisting of 10 LEs. The implementation of LEs and LABs is identical to the Stratix device family.
In the HardCopy Stratix device family, all extraneous routing resources not essential to the specific design are removed for performance and die size efficiency. Therefore, the MultiTrack interconnect for routing implementation between LABs and other device resources in the Stratix device family is no longer necessary in the HardCopy Stratix device family.
Table 2–2 illustrates the differences between HardCopy Stratix and
Stratix logic.
Table 2–2. HardCopy Stratix and Stratix Logic Comparison
HardCopy Stratix Stratix
All routing connections are direct and all unused routing is removed.
MultiTrack routing stitches routing resources together to provide a path.
TriMatrix™ memory blocks from Stratix devices, including M512, M4K, and M-RAM memory blocks, are available in HardCopy Stratix devices. Embedded memory is seamlessly implemented in the equivalent resource.
2–4 Altera Corporation
September 2008
Description, Architecture, and Features
Although memory resource implementation is equivalent, the number of specific M-RAM blocks are not necessarily the same between corresponding Stratix and HardCopy Stratix devices. Table 2–3 shows the number of M-RAM blocks available in each device.
Table 2–3. HardCopy Stratix and Stratix M-RAM Block Comparison
HardCopy Stratix Stratix
Device M-RAM Blocks Device M-RAM Blocks
HC1S25 2 EP1S25 2
HC1S30 2 EP1S30 4
HC1S40 2 EP1S40 4
HC1S60 6 EP1S60 6
HC1S830 6 EP1S830 9
In HardCopy Stratix devices, it is not possible to preload RAM contents using a MIF after powering up; the output registers of memory blocks will have unknown values. This occurs because there is no configuration process that is executed.
1 Violating the setup or hold time requirements on address
registers could corrupt the memory contents. This requirement applies to both read and write operations.
Table 2–4 illustrates the differences between HardCopy Stratix and
Stratix memory.
Table 2–4. HardCopy Stratix and Stratix Memory Comparison
HardCopy Stratix Stratix
HC1S30 and HC1S40 devices have two M-RAM blocks. HC1S80 devices have six M-RAM blocks.
It is not possible to initialize M512 and M4k RAM contents during power-up.
The contents of memory output registers are unknown after POR.
Altera Corporation 2–5 September 2008
EP1S30 and EP1S40 devices have four M-RAM blocks. EP1S80 devices have nine M-RAM blocks.
The contents of M512 and M4K RAM blocks can be preloaded during configuration with data specified in a MIF.
The contents of memory output registers are initialized to ‘0’ after POR.

DSP Blocks

DSP Blocks

PLLs and Clock Networks

DSP blocks in HardCopy Stratix devices are architecturally identical to those in Stratix devices. The number of DSP blocks available in HardCopy Stratix devices matches the number of DSP blocks available in the corresponding Stratix device.
The PLLs in HardCopy Stratix devices are identical to those in Stratix devices. The clock networks are also implemented exactly as they are in Stratix devices. The number of PLLs can vary between corresponding Stratix and HardCopy Stratix devices. Ta b l e 2 –5 shows the number of PLLs available in each device.
Table 2–5. HardCopy Stratix and Stratix PLL Comparison
HardCopy Stratix Stratix
Device PLLs Device PLLs
HC1S25 6 EP1S25 6
HC1S30 6 EP1S30 10
HC1S40 6 EP1S40 12
HC1S60 12 EP1S60 12
EP1S830 12 EP1S830 12
Table 2–6 illustrates the differences between HardCopy Stratix and
Stratix PLLs.
Table 2–6. HardCopy Stratix and Stratix PLL Differences
HardCopy Stratix Stratix
HC1S30 and HC1S40 devices have six PLLs.
PLL dynamic reconfiguration uses ROM for information. This reconfiguration is performed in the back-end and does not affect the migration fl ow.

I/O Structure and Features

2–6 Altera Corporation
The HardCopy Stratix IOEs are equivalent, but not identical to, the Stratix FPGA IOEs. This is due to the reduced die size, layout difference, and metal customization of the HardCopy Stratix device. The differences are minor but may be relevant to customers designing with tight DC and switching characteristics. However, no signal integrity concerns are introduced with HardCopy Stratix IOEs.
HC1S30 devices have 10 PLLs. HC1S40 devices have12 PLLs.
PLL dynamic reconfiguration uses a MIF to initialize a RAM resource with information.
September 2008
Description, Architecture, and Features
When designing with very tight timing constraints (for example, DDR or quad data rate [QDR]), or if using the programmable drive strength option, Altera recommends verifying final drive strength using updated IBIS models located on the Altera website at www.alter a.com. Differential I/O standards are unaffected.
I/O pin placement and VREF pin placement rules are identical between HardCopy Strati x and Stratix devices. Unused pin settings will carry o ver from Stratix device settings and are implemented as tri-stated outputs driving ground or outputs driving V
CC
.
In Stratix EP1S40 780-pin FineLine BGA FPGAs, the I/O pins U12 and U18 are available as general-purpose I/O pins. In the FPGA prototype, EP1S40F780_HARDCOPY_FPGA_PROTOTYPE, and in the Hardcopy Stratix HC1S40 780-pin FineLine BGA device, the I/O pins U12 and U18 must be connected to ground. HC1S40 780-pin FineLine BGA and EP1S40F780_HARDCOPY_FPGA_PROTOTYPE pin-outs are identical.
Table 2–7 illustrates the differences between HardCopy Stratix and
Stratix I/O pins.
Table 2–7. HardCopy Stratix and Stratix I/O Pin Comparison
HardCopy Stratix Stratix

Power-Up Modes in HardCopy Stratix Devices

The IOEs are equivalent, but not identical to, the FPGA IOEs due to slight design optimizations for HardCopy devices.
The I/O drive strength for single-ended I/O pins are slightly different and are found in the HardCopy Stratix IBIS models.
In the HC1S40 780-pin FineLine BGA device, the I/O pins U12 and U18 must be connected to ground.
Designers do not need to configure HardCopy Stratix devices, unlike their FPGA counterparts. However, to facilitate seamless migration, configuration can be emulated in HardCopy Stratix devices.
The modes in which a HardCopy Stratix device can be made ready for operation after power-up are: instant on, instant on after 50 ms, and
IOEs are optimized for the FPGA architecture.
The I/O drive strength for single-ended I/O pins are found in Stratix IBIS models.
In the EP1S40 780-pin FineLine BGA device, the I/O pins U12 and U18 are available as general-purpose I/O pins.
configuration emulation. These modes are briefly described below.
Altera Corporation 2–7 September 2008

Hot Socketing

In instant on mode, the HardCopy Stratix device is available for use
shortly after the device receives power. The on-chip POR circuit resets all registers. The CONF_DONE output is tri-stated once the POR has elapsed. No configuration device or configuration data is necessary.
In instant on after 50 ms mode, the HardCopy Stratix device
performs in a fashion similar to the instant on mode, except that there is an additional delay of 50 ms, during which time the device is held in reset stage. The CONF_DONE output is pulled low during this time, and then tri-stated after the 50 ms have elapsed. No configuration device or configuration data is necessary for this option.
In configuration emulation mode, the HardCopy series device
emulates the behavi or of an APEX or Stratix FPGA during its configuration phase. When this mode is used, the HardCopy device uses a configuration emulation circuit to receive configuration bit streams. When all the configuration data is received, the HardCopy series device transitions into an initialization phase and releases the CONF_DONE pin to be pulled high. Pulling the CONF_DONE pin high signals that the HardCopy series device is ready for normal operation. If the optional open-drain INIT_DONE output is used, the normal operation is delayed until this signal is released by the HardCopy series device.
1 HardCopy II and some HardCopy Stratix devices do not
support configuration emulation mode.
Instant on and instant on after 50 ms modes are the recommended power-up modes because these modes are similar to an ASIC’s functionality upon power-up. No changes to th e existing board design or the configuration software are required.
All three modes provide significant benefits to system designers. They enable seamless migration of the design from the FPGA device to the HardCopy device with no changes to the existing board design or the configuration software. The pull-up resistors on nCONFIG, nSTATUS, and CONF_DONE should be left on the printed circuit board.
f For more information, refer to the HardCopy Series Configuration
Emulation chapter in the HardCopy Series Handbook.
Hot Socketing
2–8 Altera Corporation
HardCopy Stratix devices support hot socketing without any external components. In a hot socketing situation, a device’s output buffers are turned off during system power up or power down. To simplify board design, HardCopy Stratix devices support any power-up or power-down sequence (V
CCIO
and V
). For mixed-voltage environments, you can
CCINT
September 2008
Description, Architecture, and Features
drive signals into the device before or during power up or power down without damaging the device. HardCopy Stratix devices do not drive out until they have attained proper operating conditions.

HARDCOPY_ FPGA_ PROTOTYPE Devices

You can power up or power down the V
CCIO
and V
CCINT
pi ns in any
sequence. The power supply ramp rates can range from 100 ns to 100 ms. During hot socketing, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is less than 20 pF.
The hot socketing DC specification is | I
The hot socketing AC specification is | I
| < 300 µA.
IOPIN
| < 8 mA for 10 ns or
IOPIN
less. This specification takes into account the pin capacitance only. Additional capacitance for trace, connector, and loading needs to be taken into consideration separately. I
is the current at any user
IOPIN
I/O pin on the device.
1 The DC specifi cation applies when all V
supplies to the device
CC
are stable in the powered-up or powered-down conditions. For the AC specification, the peak current duration due to power-up transients is 10 ns or less.
HARDCOPY_FPGA_PROTOTYPE devices are Stratix FPGAs available for designers to prototype their HardCopy Stratix designs and perform in-system verification before migration to a HardCopy Stratix device. The HARDCOPY_FPGA_PROTOTYPE devices have the same available resources as in the final HardCopy Stratix devices.
The Quartus II software version 4.1 and later contains the latest timing models. For designs with tight timing constraints, Altera strongly recommends compiling the design with the Quartus II software version 4.1 or later. To properly verify I/O features, it is important to design with the HARDCOPY_FPGA_PROTOTYPE device option prior to migrating to a HardCopy Stratix device.
Altera Corporation 2–9 September 2008

Document Revision History

1 Some HARDCOPY_FPGA_PROTOTYPE devices, as indicated
in Table 2–8, have fewer M-RAM blocks compared to the equivalent Stratix FPGAs. The selective removal of these resources provides a significant price benefit to designers using HardCopy Stratix devices.
Table 2–8. M-RAM Block Comparison Between Various Devices
Number
HARDCOPY_FPGA_PROTOTYPE
Devices
HardCopy Stratix Devices Stratix Devices
of LEs
Device M-RAM Blocks Device M-RAM Blocks Device M-RAM Blocks
25,660 EP1S25 2 HC1S25 2 EP1S25 2
32,470 EP1S30 2 HC1S30 2 EP1S30 4
41,250 EP1S40 2 HC1S40 2 EP1S40 4
57,120 EP1S60 6 HC1S60 6 EP1S60 6
79,040 EP1S830 6 HC1S830 6 EP1S830 9
f For more information about how the various features in the Quartus II
software can be used for designing HardCopy Stratix devices, refer to the Quartus II Support for HardCopy Stratix Devices chapter of the HardCopy Series Handbook.
HARDCOPY_FPGA_PROTOTYPE FPGA devices have the identical speed grade as the equivalent Stratix FPGAs. However, HardCopy Stratix devices are customized and do not have any speed grading. HardCopy Stratix devices, on an average, can be 50% faster than their equivalent HARDCOPY_FPGA_PROTOTYPE devices. The actual improvement is design-dependent.
Document
Table 2–9 shows the revision history for this chapter.
Revision History
Table 2–9. Document Revision History (Part 1 of 2)
Date and Document
Version
September 2008 v3.4
June 2007 v3.3 Updated Table 2–1.
2–10 Altera Corporation
Revised chapter number and metadata.
Added note to the “Embedded Memory” section.
Updated the “Hot Socketing” section.
Changes Made Summary of Changes
September 2008
Table 2–9. Document Revision History (Part 2 of 2)
Description, Architecture, and Features
Date and Document
Version
December 2006
Updated revision history.
Changes Made Summary of Changes
v3.2
March 2006 Formerly chapter 6; no content change.
October 2005 v3.1 Minor edits
Updated graphics
May 2005 v3.0
January 2005 v2.0
Added Table 6-1
Added the Logic Elements section
Added the Embedded Memory section
Added the DSP Blocks section
Added the PLLs and Clock Networks section
Added the I/O Structure and Features section
Added summary of I/O and timing differences between
Stratix FPGAs and HardCopy Stratix devices
Removed section on Quartus II support of HardCopy
Minor edits.
Minor update.
Minor update.
Stratix devices
Added “Hot Socketing” section
August 2003
Edited section headings’ hierarchy. Minor edits.
v1.1
June 2003 v1.0
Initial release of Chapter 6, Description, Architecture and Features, in the HardCopy Device Handbook
Altera Corporation 2–11 September 2008
Document Revision History
2–12 Altera Corporation
September 2008
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