Altera GPIO User Manual

2014.08.18

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Altera GPIO IP Core User Guide

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The Altera GPIO megafunction IP core supports General Purpose I/O (GPIO) components and features.
GPIOs are I/Os used in general applications not specific to transceivers, memory-like interfaces or LVDS.

The Altera GPIO IP core features the following components:

• Double data rate input/output (DDIO)—A digital component that doubles, or halves the data-rate of a
communication channel.

• Delay chains— configure the delay chains to perform specific delay and assist in I/O timing closure.

• I/O buffers—connect the pads to the FPGA.

Note: The actual implementations and features of DDIO, delay chains, and I/O buffers vary from family

to family.

The Altera GPIO IP core is only available for Arria 10 devices. For Arria V, Cyclone V, and Stratix V
devices, follow the steps in IP Migration for Arria V, Cyclone V, and Stratix V on page 1 to migrate
your IP.

Related Information

• Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) Megafunctions

User Guide

• I/O Buffer (ALTIOBUF) Megafunction User Guide

IP Migration for Arria V, Cyclone V, and Stratix V

The Altera GPIO IP core supports the IP migration flow which allows you to migrate your Arria V,
Cyclone V, and Stratix V devices IP into the Altera GPIO IP core in Arria 10 devices.

This IP migration flow configures the new IP to match the settings of the old one and allow you to
regenerate. Some IP cores only support this migration in specific modes.

If your IP core is in a mode that is not supported, you may need to run the Altera GPIO IP Parameter
Editor and configure it manually.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

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9001:2008
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Migrating Your IP

Migrating Your IP

To use the IP migration flow:

1. Open your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, or ALTIOBUF IP in the IP

Parameter Editor.

2. In the Currently selected device family, select Arria 10.

3. Click Finish to open the Altera GPIO IP Parameter Editor.

4. The Altera GPIO IP Parameter Editor will be configured similarly to the old settings.

5. If there are any incompatible settings between the two, select new supported settings.

6. Click Finish in the Altera GPIO IP Parameter Editor to regenerate the IP.

7. Replace your old IP core instantiation in RTL with the newly generated IP.

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Note:

The port names of the new IP core may not match the old ones, so simply changing the IP name in
the instantiation is not sufficient.

Resource Utilization and Performance

For details about the resource usage and performance of your design, refer to the compilation reports in
the Quartus II software.

To view the compilation reports in the Quartus II software, follow these steps:

1. On the Processing menu, click Start Compilation to run a full compilation.

2. After compiling the design, on the Processing menu, click Compilation Report.

3. In the Table of Contents browser, expand the Fitter folder by clicking the “+” icon.

4. To view the resource usage information, under Fitter, expand Resource section, and select Resource
Usage Summary.

5. To view the resource utilization information, under Fitter, expand Resource section, and select
Resource Utilization by Entity.

Note:

Related Information

The performance of the Altera GPIO IP core depends on the I/O constraints and clock phases.
To validate timing for Altera GPIO configuration, Altera recommends using the TimeQuest
Timing Analyzer.

• The Quartus II TimeQuest Timing Analyzer

Parameter Settings

The following table lists the parameter settings for the Altera GPIO IP core.

Table 1: Altera GPIO Parameter Settings

Name Values Description

General

Data Direction Input, Output,

Altera Corporation

Bidir

This setting specifies the data direction for the
Altera GPIO IP core.

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Parameter Settings

Name Values Description

Data width 1 to 128 Specifies the data width.
Use legacy top-level port names Turn on, Turn off Reverts to ports used in Arria V, Cyclone V, and

Stratix V devices. For example, dout becomes

dataout_h and dataout_l and din becomes
datain_h and datain_l.

Buffer

Use differential buffer Turn on, Turn off Allows the use of differential buffer.
Use pseudo-differential buffer Turn on, Turn off Allows the use of pseudo-differential buffer. This

option is only available when you enable the Use
differential buffer option.

Use bus-hold circuitry Turn on, Turn off Allows the use of bus-hold circuitry.
Use open-drain output Turn on, Turn off Allows the use of open-drain output.
Enable output enable port Turn on, Turn off Allows the use of OE input. This option is

available only when you set the Data Direction
option to output.

When you set the Data Direction option to
input and bidir, this option is disabled.

3

Enable seriestermination/
paralleltermination ports

Turn on, Turn off Allows the use of the seriestermination/

paralleltermination ports of the output

buffer.

Registers

Register mode none, Simple

register, DDIO

This setting specifies the register mode for the
Altera GPIO IP core. The values for this
parameter are:

• none—specifies a simple wire connection

from/to the buffer.

• Simple register—specifies that the DDIO is

used as a simple register in single data-rate
mode (SDR). The Fitter may pack this register
in the I/O.

• DDIO— specifies that the IP core uses the

DDIO.

Enable synchronous clear / preset
port

Enable asynchronous clear /
preset port

None, Clear, Preset Specifies how to implement synchronous reset

port.

None, Clear, Preset Specifies how to implement asynchronous reset

port.

Enable clock enable port Specifies whether the DDIO will have the clock

enable port exposed.

Half Rate Logic Turn on, Turn off Allows the Altera GPIO IP core to use half rate

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logic (half-rate DDIO).

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Buffer

OEIN[1:0]

DATAIN[3:0]

Output

Path

GPIO

OE

Path

Input Path

DATAOUT[3:0]

Core

PAD

ACLR_N
APRE_N

DATAOUT[0]

DATAOUT[2]

DATAOUT[1]

DATAOUT[3]

CLK_HR

CLK_FR

DDIO

IN

DDIO

IN

DDIO

IN

Delay

Element

HR FR

B

A

1

3

2

4

Overview

Name Values Description

Separate input/output Clocks Turn on, Turn off Allows the Altera GPIO to use separate clocks for

input and output data paths.

Overview

The following figure shows the high-level view of a single-ended GPIO.

Figure 1: Single-Ended GPIO

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Input Path

The following figure shows the simplified view of a single-ended GPIO input path.

Figure 2: Input Path (Simplified View)

The pad sends data to the input buffer, and the input buffer feeds the delay element.

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Input Path Waveform

5

Note: The Altera GPIO megafunction does not support dynamic calibration of the input path. For

applications requiring dynamic calibration of the input path, refer to the Altera PHYLite

Megafunction User Guide.

After data goes to the output of the delay element, programmable bypass multiplexers select the features
and paths to use. Each input path contains two stages of DDIOs, which are full-rate and half-rate.

Note: When you set the Register mode option to Simple register, the full-rate DDIO works as a simple

register.

Note: When you set the Register mode option to Simple register, the Fitter chooses whether to pack the

register in the I/O or implement the register in the core, depending on the area and timing trade­offs.

Use the input path in four modes:

• Bypass—data goes from the delay element to the core, bypassing all DDIOs.

• Packed Register—the full-rate DDIO operates as a register, bypassing half-rate DDIOs.

• Double data rate Input/Output (DDIO) mode with full-rate conversion—The full-rate DDIO operates
as a regular DDIO, bypassing half-rate DDIOs.

• DDIO mode with half-rate conversion—The full-rate DDIO operates as a regular DDIO. Half-rate
DDIOs converts data for full-rate to half-rate.

All DDIOs share the same asynchronous clear and preset signals when used. Half-rate and full-rate
DDIOs connect to separate clocks. When you use half-rate and full-rate DDIOs, the full-rate clock must
run at twice the half-rate frequency. Use different phase relationships to meet timing requirements.

Input Path Waveform

The following figure shows the waveforms for an input path in DDIO mode with half-rate conversion.
This configuration uses all the blocks and refers to the same labels shown in Figure 2.

Note:

The actual timing relationship between different signals may vary depending on the specific design,
delays, and phases that you choose for the full-rate and half-rate clocks.

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Output Path

Figure 3: Input Path Waveform

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The pad receives data. DDIO IN (1) (refer to Figure 2) captures data on the rising and falling edges of
CLK_FR, and sends data at SDR (refer to signals (A) and (B) in the waveform). DDIO IN (2) and DDIO
IN (3) (refer to Figure 2) halves the data rate and DATAOUT[3:0] presents data as a half-rate bus.

Notice how going from full-rate clock at double data rate to half-rate clock at single data rate, data rate has
been divided by four and the bus size has increased by the same ratio. The overall throughput through the
Altera GPIO IP core remained unchanged.

Output Path

The following figure shows the simplified view of a single-ended GPIO output path.

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PAD

ACLR_N
APRE_N

DATAOUT[0]

DATAOUT[2]

DATAOUT[1]

DATAOUT[3]

CLK_HR

CLK_FR

DDIO

OUT

DDIO

OUT

DDIO

OUT

Delay

Element

HR FR

OE

from Output

Enable Path

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Figure 4: Output Path (Simplified View)

Output Path

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The simplified view of a GPIO output path is similar to the input path (refer to Figure 2). The output
delay element sends data to the pad through the output buffer.

Note:

The Altera GPIO IP core does not support dynamic calibration of the input path. For applications
requiring dynamic calibration of the output path, refer to the Altera PHYLite Megafunction User

Guide.

Note: When you set the Register mode option to Simple register, the full-rate DDIO works as a simple

register.

Note: When you set the Register Mode option to Simple register, the Fitter chooses whether to pack the

register in the I/O or implement the register in the core, depending on the area and timing trade­offs.

You can select a combination of half-rate, full-rate DDIOs, and simple register using programmable
bypass multiplexers to implement the following four output modes:

• Bypass—data goes from the core straight to the delay element, bypassing all DDIOs.

• Packed Register—full-rate DDIO operates as a register, bypassing half-rate DDIOs.

• DDIO output mode, Full-Rate—full-rate DDIO operates as a regular DDIO, bypassing half-rate
DDIOs.

• DDIO output, Half-Rate—full-rate DDIO operates as a regular DDIO. Half-rate DDIOs convert data
from full-rate to half-rate.

All DDIOs share the same asynchronous clear and preset signals when used. Half-rate and full-rate
DDIOs connect to separate clocks. When you use half-rate and full-rate DDIOs, the full-rate clock must
run at twice the half-rate frequency. You can use different phase relationships to meet timing require‐
ments.

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