Altera Floating-Point User Manual

Floating-Point IP Cores User Guide

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TOC-2

About Floating-Point IP Cores...........................................................................1-1

List of Floating-Point IP Cores.................................................................................................................. 1-1

Installing and Licensing IP Cores..............................................................................................................1-2

Design Flow.................................................................................................................................................. 1-2

IP Catalog and Parameter Editor...................................................................................................1-3

Specifying IP Core Parameters and Options................................................................................1-4

Specifying IP Core Parameters and Options (Legacy Parameter Editors)...............................1-8

Upgrading IP Cores.....................................................................................................................................1-9

Migrating IP Cores to a Different Device...................................................................................1-12

Floating-Point IP Cores General Features..............................................................................................1-12

IEEE-754 Standard for Floating-Point Arithmetic............................................................................... 1-13

Floating-Point Formats.................................................................................................................1-13

Special Case Numbers...................................................................................................................1-14

Rounding.........................................................................................................................................1-15

Non-IEEE-754 Standard Format.............................................................................................................1-15

Floating-Points IP Cores Output Latency..............................................................................................1-16

Floating-Point IP Cores Design Example Files......................................................................................1-16

VHDL Component Declaration.............................................................................................................. 1-18

VHDL LIBRARY-USE Declaration.........................................................................................................1-18

ALTERA_FP_MATRIX_INV IP Core................................................................2-1

ALTERA_FP_MATRIX_INV Features....................................................................................................2-1

ALTERA_FP_MATRIX_INV Output Latency....................................................................................... 2-1

ALTERA_FP_MATRIX_INV Resource Utilization and Performance................................................2-1

ALTERA_FP_MATRIX_INV Functional Description..........................................................................2-2

Cholesky Decomposition Function...............................................................................................2-3

Triangular Matrix Inversion...........................................................................................................2-5

Matrix Multiplication......................................................................................................................2-5

Matrix Inversion Operation........................................................................................................... 2-5

ALTERA_FP_MATRIX_INV Design Example: Matrix Inverse of Single-Precision Format

Numbers.................................................................................................................................................. 2-6

ALTERA_FP_MATRIX_INV Design Example: Understanding the Simulation Results..... 2-7

Sample Matrix Data.....................................................................................................................................2-8

ALTERA_FP_MATRIX_INV Signals.....................................................................................................2-10

ALTERA_FP_MATRIX_INV Parameters.............................................................................................2-11

ALTERA_FP_MATRIX_MULT IP Core............................................................3-1

ALTERA_FP_MATRIX_MULT Features................................................................................................3-1

ALTERA_FP_MATRIX_MULT Output Latency...................................................................................3-1

ALTERA_FP_MATRIX_MULT Resource Utilization and Performance........................................... 3-1

ALTERA_FP_MATRIX_MULT Functional Description......................................................................3-2

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TOC-3

ALTERA_FP_MATRIX_MULT Signals.................................................................................................. 3-4

ALTERA_FP_MATRIX_MULT Parameters...........................................................................................3-5

ALTERA_FP_ACC_CUSTOM IP Core..............................................................4-1

ALTERA_FP_ACC_CUSTOM Features..................................................................................................4-1

ALTERA_FP_ACC_CUSTOM Output Latency.....................................................................................4-1

ALTERA_FP_ACC_CUSTOM Resource Utilization and Performance............................................. 4-1

ALTERA_FP_ACC_CUSTOM Signals.................................................................................................... 4-3

ALTERA_FP_ACC_CUSTOM Parameters.............................................................................................4-4

ALTFP_ADD_SUB IP Core................................................................................5-1

ALTFP_ADD_SUB Features......................................................................................................................5-1

ALTFP_ADD_SUB Output Latency.........................................................................................................5-1

ALTFP_ADD_SUB Truth Table................................................................................................................5-1

ALTFP_ADD_SUB Resource Utilization and Performance................................................................. 5-2

ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers..................5-3

ALTFP_ADD_SUM Design Example: Understanding the Simulation Results......................5-3

ALTFP_ADD_SUB Signals........................................................................................................................ 5-4

ALTFP_ADD_SUB Parameters.................................................................................................................5-6

ALTFP_DIV IP Core...........................................................................................6-1

ALTFP_DIV Features..................................................................................................................................6-1

ALTFP_DIV Output Latency.....................................................................................................................6-1

ALTFP_DIV Truth Table........................................................................................................................... 6-2

ALTFP_DIV Resource Utilization and Performance.............................................................................6-3

ALTFP_DIV Design Example: Division of Single-Precision.................................................................6-4

ALTFP_DIV Design Example: Understanding the Simulation Results...................................6-4

ALTFP_DIV Signals....................................................................................................................................6-6

ALTFP_DIV Parameters.............................................................................................................................6-7

ALTFP_MULT IP Core....................................................................................... 7-1

ALTFP_MULT IP Core Features...............................................................................................................7-1

ALTFP_MULT Output Latency................................................................................................................ 7-1

ALTFP_MULT Truth Table.......................................................................................................................7-1

ALTFP_MULT Resource Utilization and Performance.........................................................................7-2

ALTFP_MULT Design Example: Multiplication of Double-Precision Format Numbers................7-3

ALTFP_MULT Design Example: Understanding the Simulation Waveform........................7-3

Parameters.....................................................................................................................................................7-4

ALTFP_MULT Signals................................................................................................................................7-5

ALTFP_SQRT......................................................................................................8-1

ALTFP_SQRT Features...............................................................................................................................8-1

Output Latency.............................................................................................................................................8-1

ALTFP_SQRT Truth Table........................................................................................................................ 8-2

ALTFP_SQRT Resource Utilization and Performance..........................................................................8-3

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TOC-4

ALTFP_SQRT Design Example: Square Root of Single-Precision Format Numbers........................8-3

ALTFP_SQRT Design Example: Understanding the Simulation Results................................8-3

ALTFP_SQRT Signals.................................................................................................................................8-4

ALTFP_SQRT Parameters..........................................................................................................................8-6

ALTFP_EXP IP Core...........................................................................................9-1

ALTFP_EXP Features..................................................................................................................................9-1

Output Latency.............................................................................................................................................9-1

ALTFP_EXP Truth Table........................................................................................................................... 9-1

ALTFP_EXP Resource Utilization and Performance.............................................................................9-2

ALTFP_EXP Design Example: Exponential of Single-Precision Format Numbers...........................9-2

ALTFP_EXP Design Example: Understanding the Simulation Results...................................9-3

ALTFP_EXP Signals....................................................................................................................................9-4

ALTFP_EXP Parameters.............................................................................................................................9-6

ALTFP_INV IP Core.........................................................................................10-1

ALTFP_INV Features............................................................................................................................... 10-1

Output Latency...........................................................................................................................................10-1

ALTFP_INV Truth Table.........................................................................................................................10-1

ALTFP_INV Resource Utilization and Performance...........................................................................10-2

ALTFP_INV Design Example: Inverse of Single-Precision Format Numbers ................................10-2

ALTFP_INV Design Example: Understanding the Simulation Results.................................10-3

Ports.............................................................................................................................................................10-4

Parameters.................................................................................................................................................. 10-5

ALTFP_INV_SQRT IP Core.............................................................................11-1

ALTFP_INV_SQRT Features...................................................................................................................11-1

Output Latency...........................................................................................................................................11-1

ALTFP_INV_SQRT Truth Table............................................................................................................11-1

ALTFP_INV_SQRT Resource Utilization and Performance..............................................................11-2

ALTFP_INV_SQRT Design Example: Inverse Square Root of Single-Precision Format

Numbers ...............................................................................................................................................11-2

ALTFP_INV_SQRT Design Example: Understanding the Simulation Results ...................11-3

Ports.............................................................................................................................................................11-4

Parameters.................................................................................................................................................. 11-5

ALTFP_LOG......................................................................................................12-1

ALTFP_LOG Features...............................................................................................................................12-1

Output Latency...........................................................................................................................................12-1

ALTFP_LOG Truth Table........................................................................................................................ 12-1

ALTFP_LOG Resource Utilization and Performance..........................................................................12-2

ALTFP_LOG Design Example: Natural Logarithm of Single-Precision Format Numbers ...........12-2

ALTFP_LOG Design Example: Understanding the Simulation Results................................12-3

Signals..........................................................................................................................................................12-4

Parameters.................................................................................................................................................. 12-6

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TOC-5

ALTFP_ATAN IP Core..................................................................................... 13-1

Output Latency...........................................................................................................................................13-1

ALTFP_ATAN Features........................................................................................................................... 13-1

ALTFP_ATAN Resource Utilization and Performance.......................................................................13-1

Ports.............................................................................................................................................................13-2

ALTFP_ATAN Parameters...................................................................................................................... 13-2

ALTFP_SINCOS IP Core.................................................................................. 14-1

ALTFP_SINCOS Features........................................................................................................................14-1

Output Latency...........................................................................................................................................14-1

ALTFP_SINCOS Resource Utilization and Performance....................................................................14-1

ALTFP_SINCOS Signals...........................................................................................................................14-2

ALTFP_SINCOS Parameters................................................................................................................... 14-3

ALTFP_ABS IP Core.........................................................................................15-1

ALTFP_ABS Features................................................................................................................................15-1

ALTFP_ABS Output Latency...................................................................................................................15-1

ALTFP_ABS Resource Utilization and Performance...........................................................................15-1

ALTFP_ABS Design Example: Absolute Value of Multiplication Results........................................ 15-2

ALTFP_ABS Design Example: Understanding the Simulation Results.................................15-2

ALTFP_ABS Signals..................................................................................................................................15-3

ALTFP_ABS Parameters...........................................................................................................................15-5

ALTFP_COMPARE IP Core.............................................................................16-1

ALTFP_COMPARE Features.................................................................................................................. 16-1

ALTFP_COMPARE Output Latency......................................................................................................16-1

ALTFP_COMPARE Resource Utilization and Performance..............................................................16-1

ALTFP_COMPARE Design Example: Comparison of Single-Precision Format Numbers...........16-2

ALTFP_COMPARE Design Example: Understanding the Simulation Results ...................16-2

ALTFP_COMPARE Signals.....................................................................................................................16-3

ALTFP_COMPARE Parameters..............................................................................................................16-4

ALTFP_CONVERT IP Core............................................................................. 17-1

ALTFP_CONVERT Features...................................................................................................................17-1

ALTFP_CONVERT Conversion Operations........................................................................................ 17-1

ALTFP_CONVERT Output Latency......................................................................................................17-2

ALTFP_CONVERT Resource Utilization and Performance.............................................................. 17-3

ALTFP_CONVERT Design Example: Convert Double-Precision Floating-Point Format

Numbers................................................................................................................................................17-6

ALTFP_CONVERT Design Example: Understanding the Simulation Results....................17-6

ALTFP_CONVERT Signals..................................................................................................................... 17-8

ALTFP_CONVERT Parameters............................................................................................................17-10

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TOC-6

ALTERA_FP_FUNCTIONS IP Core................................................................18-1

ALTERA_FP_FUNCTIONS Features.................................................................................................... 18-1

ALTERA_FP_FUNCTIONS Output Latency........................................................................................18-2

ALTERA_FP_FUNCTIONS Target Frequency....................................................................................18-2

ALTERA_FP_FUNCTIONS Combined Target....................................................................................18-2

ALTERA_FP_FUNCTIONS Resource Utilization and Performance................................................18-3

ALTERA_FP_FUNCTIONS Signals.....................................................................................................18-24

ALTERA_FP_FUNCTIONS Parameters............................................................................................. 18-25

Document Revision History...............................................................................A-1

Document Revision History......................................................................................................................A-1

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2014.12.19

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101 Innovation Drive, San Jose, CA 95134

About Floating-Point IP Cores

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The Altera® floating-point megafunction IP cores enable you to perform floating-point arithmetic in FPGAs through optimized parameterizable functions for Altera device architectures.

You can customize the IP cores by configuring various parameters to accommodate your needs.

List of Floating-Point IP Cores

This table lists the Floating-Point IP cores.

Table 1-1: List of IP Cores

IP Core Name Function Overview

Operator Functions ALTFP_ADD_SUB Adder/Subtractor ALTFP_DIV Divider ALTFP_MULT Multiplier ALTFP_SQRT Square Root Algebraic and Trancendental Functions ALTFP_EXP Exponential ALTFP_INV Inverse ALTFP_INV_SQRT Inverse Square Root ALTFP_LOG Natural Logarithm Trigonometric Functions ALTFP_ATAN Arctangent ALTFP_SINCOS Trigonometric Sine/Cosine Other Functions ALTFP_ABS Absolute value ALTFP_COMPARE Comparator ALTFP_CONVERT Converter

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO 9001:2008 Registered

acds

quartus - Contains the Quartus II software ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

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Installing and Licensing IP Cores

IP Core Name Function Overview

ALTERA_FP_ACC_CUSTOM An Application Specific Accumulator ALTERA_FP_FUNCTIONS A Collection of Floating-Point Functions Complex Functions ALTFP_MATRIX_INV Matrix Inverse ALTFP_MATRIX_MULT Matrix Multiplier

Related Information

Introduction to Altera IP Cores

Provides general information about Altera IP cores

Installing and Licensing IP Cores

The Altera IP Library provides many useful IP core functions for production use without purchasing an additional license. You can evaluate any Altera® IP core in simulation and compilation in the Quartus® II software using the OpenCore® evaluation feature. Some Altera IP cores, such as MegaCore® functions, require that you purchase a separate license for production use. You can use the OpenCore Plus feature to evaluate IP that requires purchase of an additional license until you are satisfied with the functionality and performance. After you purchase a license, visit the Self Service Licensing Center to obtain a license number for any Altera product.

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Figure 1-1: IP Core Installation Path

The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is

Note:

<home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

Design Flow

Use the IP Catalog and parameter editor to define and instantiate complex IP cores. Using the GUI ensures that you set all IP core ports and parameters properly.

If you are an expert user, and choose to configure the IP core directly through parameterized instantiation in your design, refer to the port and parameter details. The details of these ports and parameters are hidden in the parameter editor.

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Search and filter IP for your target device

Double-click to customize, right-click for information

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IP Catalog and Parameter Editor

The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate files representing your custom IP variation.

Note: The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In

Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.

The IP Catalog lists IP cores available for your design. Double-click any IP core to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your project. You can also parameterize an IP variation without an open project.

Use the following features to help you quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families.

• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access

partner IP information on the Altera website.

• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, andor view links to documentation.

IP Catalog and Parameter Editor

1-3

Figure 1-2: Quartus II IP Catalog

The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes

Note:

exclusive system interconnect, video and image processing, and other system-level IP that are not

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View IP port and parameter details

Apply preset parameters for specific applications

Specify your IP variation name and target device

Legacy parameter editors

1-4

Using the Parameter Editor

available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer to Creating a System with Qsys in the Quartus II Handbook.

Using the Parameter Editor

The parameter editor helps you to configure IP core ports, parameters, and output file generation options.

• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values for specific applications.

• View port and parameter descriptions, and links to documentation.

• Generate testbench systems or example designs (where provided).

Figure 1-3: IP Parameter Editors

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Specifying IP Core Parameters and Options

The parameter editor GUI allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Quartus II software. Refer to Specifying IP Core Parameters and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.

2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys. Click OK.

3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters.

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View IP port and parameter details

Apply preset parameters for specific applications

Specify your IP variation name and target device

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Files Generated for Altera IP Cores

• Optionally select preset parameter values if provided for your IP core. Presets specify initial

parameter values for specific applications.

• Specify parameters defining the IP core functionality, port configurations, and device-specific

features.

• Specify options for processing the IP core files in other EDA tools.

4. Click Generate HDL, the Generation dialog box appears.

5. Specify output file generation options, and then click Generate. The IP variation files generate

according to your specifications.

6. To generate a simulation testbench, click Generate > Generate Testbench System.

7. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > HDL Example.

8. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.

9. After generating and instantiating your IP variation, make appropriate pin assignments to connect

ports.

Figure 1-4: IP Parameter Editor

1-5

Files Generated for Altera IP Cores

The Quartus software generates the following IP core output file structure.

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<your_testbench>_tb.csv <your_testbench>_tb.spd

<your_ip>.cmp - VHDL component declaration file

<your_ip>.ppf - XML I/O pin information file <your_ip>.qip - Lists IP synthesis files <your_ip>.sip - Lists files for simulation

<your_ip>.v or .vhd

Top-level IP synthesis file

<your_ip>.v or .vhd Top-level simulation file

<simulator_setup_scripts>

<your_ip>.qsys - System or IP integration file

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file <your_ip>_inst.v or .vhd - Sample instantiation template

<your_ip>_generation.rpt - IP generation report <your_ip>.debuginfo - Contains post-generation information

<your_ip>.html - Connection and memory map data <your_ip>.bsf - Block symbol schematic <your_ip>.spd - Combines individual simulation scripts

<your_ip>_tb.qsys

Testbench system file

<your_ip>.sopcinfo - Software tool-chain integration file

<EDA tool setup

scripts>

<your_ip>

IP variation files

<testbench>_tb

testbench system

sim

Simulation files

synth

IP synthesis files

sim

simulation files

Simulator scripts

<testbench>_tb

<ip subcores> n

Subcore libraries

sim

Subcore

Simulation files

synth

Subcore

synthesis files

<your_ip> n

IP variation files

testbench files

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Files Generated for Altera IP Cores

Figure 1-5: IP Core Generated Files

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Table 1-2: IP Core Generated Files

File Name Description

<my_ip>.qsys

<system>.sopcinfo Describes the connections and IP component parameterizations in

The Qsys system or top-level IP variation file. <my_ip> is the name that you give your IP variation.

your Qsys system. You can parse its contents to get requirements when you develop software drivers for IP components.

Downstream tools such as the Nios II tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.

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Files Generated for Altera IP Cores

File Name Description

<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that

contains local generic and port definitions that you can use in VHDL design files.

1-7

<my_ip>.html

A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.

<my_ip>_generation.rpt IP or Qsys generation log file. A summary of the messages during IP

generation.

<my_ip>.debuginfo Contains post-generation information. Used to pass System Console

and Bus Analyzer Toolkit information about the Qsys interconnect. The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect.

<my_ip>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Quartus software.

<my_ip>.csv Contains information about the upgrade status of the IP component. <my_ip>.bsf A Block Symbol File (.bsf) representation of the IP variation for use

in Quartus Block Diagram Files (.bdf).

<my_ip>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<my_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for

IP components created for use with the Pin Planner.

<my_ip>_bb.v You can use the Verilog black-box (_bb.v) file as an empty module

declaration for use as a black box.

<my_ip>.sip Contains information required for NativeLink simulation of IP

components. You must add the .sip file to your Quartus project.

<my_ip>_inst.v or _inst.vhd HDL example instantiation template. You can copy and paste the

contents of this file into your HDL file to instantiate the IP variation.

<my_ip>.regmap If IP contains register information, .regmap file generates.

The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This enables register display views and user customizable statistics in the System Console.

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Specifying IP Core Parameters and Options (Legacy Parameter Editors)

File Name Description

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<my_ip>.svd

<my_ip>.v

<my_ip>.vhd

mentor/

aldec/

/synopsys/vcs

/synopsys/vcsmx

Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system.

During synthesis, the .svd files for slave interfaces visible to System Console masters are stored in the .sof file in the debug section. System Console reads this section, which Qsys can query for register map information. For system slaves, Qsys can access the registers by name.

HDL files that instantiate each submodule or child IP core for synthesis or simulation.

Contains a ModelSim® script msim_setup.tcl to set up and run a simulation.

Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation.

Contains a shell script vcs_setup.sh to set up and run a VCS

simulation. Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to

set up and run a VCS MX® simulation.

/cadence

Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.

/submodules Contains HDL files for the IP core submodule. <child IP cores>/ For each generated child IP core directory, Qsys generates /synth and /

sim sub-directories.

Specifying IP Core Parameters and Options (Legacy Parameter Editors)

Some IP cores use a legacy version of the parameter editor for configuration and generation. Use the following steps to configure and generate an IP variation using a legacy parameter editor.

The legacy parameter editor generates a different output file structure than the latest parameter

Note:

editor. Refer to Specifying IP Core Parameters and Options for configuration of IP cores that use the latest parameter editor.

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Legacy parameter editors

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Figure 1-6: Legacy Parameter Editors

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1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.

2. Specify a top-level name and output HDL file type for your IP variation. This name identifies the IP core variation files in your project. Click OK.

3. Specify the parameters and options for your IP variation in the parameter editor. Refer to your IP core user guide for information about specific IP core parameters.

4. Click Finish or Generate (depending on the parameter editor version). The parameter editor generates the files for your IP variation according to your specifications. Click Exit if prompted when generation is complete. The parameter editor adds the top-level .qip file to the current project automatically.

Note:

Upgrading IP Cores

IP core variants generated with a previous version of the Quartus II software may require upgrading before use in the current version of the Quartus II software. Click Project > Upgrade IP Components to identify and upgrade IP core variants.

The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or unsupported for specific IP cores in your design. You must upgrade IP cores that require it before you can compile the IP variation in the current version of the Quartus II software. Many Altera IP cores support automatic upgrade.

To manually add an IP variation generated with legacy parameter editor to a project, click Project > Add/Remove Files in Project and add the IP variation .qip file.

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Upgrading IP Cores

The upgrade process renames and preserves the existing variation file (.v, .sv, or .vhd) as <my_variant>_

BAK.v, .sv, .vhd in the project directory.

Table 1-3: IP Core Upgrade Status

IP Core Status Corrective Action

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Required Upgrade IP Components

Optional Upgrade IP Components

You must upgrade the IP variation before compiling in the current version of the Quartus II software.

Upgrade is optional for this IP variation in the current version of the Quartus II software. You can upgrade this IP variation to take advantage of the latest development of this IP core. Alternatively you can retain previous IP core characteristics by declining to upgrade.

Upgrade Unsupported Upgrade of the IP variation is not supported in the current version of the

Quartus II software due to IP core end of life or incompatibility with the current version of the Quartus II software. You are prompted to replace the obsolete IP core with a current equivalent IP core from the IP Catalog.

Before you begin

• Archive the Quartus II project containing outdated IP cores in the original version of the Quartus II software: Click Project > Archive Project to save the project in your previous version of the Quartus II software. This archive preserves your original design source and project files.

• Restore the archived project in the latest version of the Quartus II software: Click Project > Restore Archived Project. Click OK if prompted to change to a supported device or overwrite the project database. File paths in the archive must be relative to the project directory. File paths in the archive must reference the IP variation .v or .vhd file or .qsys file (not the .qip file).

1. In the latest version of the Quartus II software, open the Quartus II project containing an outdated IP core variation. The Upgrade IP Components dialog automatically displays the status of IP cores in your project, along with instructions for upgrading each core. Click Project > Upgrade IP

Components to access this dialog box manually.

2. To simultaneously upgrade all IP cores that support automatic upgrade, click Perform Automatic

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Upgrade. The Status and Version columns update when upgrade is complete. Example designs provided with any Altera IP core regenerate automatically whenever you upgrade the IP core.

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Displays upgrade status for all IP cores in the Project

Upgrades all IP core that support “Auto Upgrade” Upgrades individual IP cores unsupported by “Auto Upgrade”

Checked IP cores support “Auto Upgrade”

Successful “Auto Upgrade”

Upgrade unavailable

Double-click to individually migrate

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Figure 1-7: Upgrading IP Cores

Upgrading IP Cores

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Example 1-1: Upgrading IP Cores at the Command Line

You can upgrade IP cores that support auto upgrade at the command line. IP cores that do not support automatic upgrade do not support command line upgrade.

• To upgrade a single IP core that supports auto-upgrade, type the following command:

quartus_sh –ip_upgrade –variation_files <my_ip_filepath/my_ip>.<hdl> <qii_project>

Example: quartus_sh -ip_upgrade -variation_files mega/pll25.v hps_testx

• To simultaneously upgrade multiple IP cores that support auto-upgrade, type the following command:

quartus_sh –ip_upgrade –variation_files “<my_ip_filepath/my_ip1>.<hdl>; <my_ip_filepath/my_ip2>.<hdl>” <qii_project>

Example: quartus_sh -ip_upgrade -variation_files "mega/pll_tx2.v;mega/pll3.v" hps_testx

IP cores older than Quartus II software version 12.0 do not support upgrade.

Note:

Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core. The Altera IP Release Notes reports any verifica‐ tion exceptions for Altera IP cores. Altera does not verify compilation for IP cores older than the previous two releases.

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Migrating IP Cores to a Different Device

Related Information

Altera IP Release Notes

Migrating IP Cores to a Different Device

IP migration allows you to target the latest device families with IP originally generated for a different device. Some Altera IP cores require individual migration to upgrade. The Upgrade IP Components dialog box prompts you to double-click IP cores that require individual migration.

1. To display IP cores requiring migration, click Project > Upgrade IP Components. The Description field prompts you to double-click IP cores that require individual migration.

2. Double-click the IP core name, and then click OK after reading the information panel. The parameter editor appears showing the original IP core parameters.

3. For the Currently selected device family, turn off Match project/default, and then select the new target device family.

4. Click Finish, and then click Finish again to migrate the IP variation using best-effort mapping to new parameters and settings. Click OK if you are prompted that the IP core is unsupported for the current device. A new parameter editor opens displaying best-effort mapped parameters.

5. Click Generate HDL, and then confirm the Synthesis and Simulation file options. Verilog is the parameter editor default HDL for synthesis files. If your original IP core was generated for VHDL, select VHDL to retain the original output HDL format.

6. To regenerate the new IP variation for the new target device, click Generate. When generation is complete, click Close.

7. Click Finish to complete migration of the IP core. Click OK if you are prompted to overwrite IP core files. The Device Family column displays the migrated device support. The migration process replaces <my_ip>.qip with the <my_ip>.qsys top-level IP file in your project.

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Note:

If migration does not replace <my_ip>.qip with <my_ip>.qsys, click Project > Add/Remove Files in Project to replace the file in your project.

8. Review the latest parameters in the parameter editor or generated HDL for correctness. IP migration

may change ports, parameters, or functionality of the IP core. During migration, the IP core's HDL generates into a library that is different from the original output location of the IP core. Update any assignments that reference outdated locations. If your upgraded IP core is represented by a symbol in a supporting Block Design File schematic, replace the symbol with the newly generated <my_ip>.bsf after migration.

Note:

The migration process may change the IP variation interface, parameters, and functionality. This may require you to change your design or to re-parameterize your variant after the Upgrade IP Components dialog box indicates that migration is complete. The Description field identifies IP cores that require design or parameter changes.

Related Information

Altera IP Release Notes

Floating-Point IP Cores General Features

All Altera floating-point IP cores offer the following features:

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IEEE-754 Standard for Floating-Point Arithmetic

• Support for floating-point formats.

• Input support for not-a-number (NaN), infinity, zero, and normal numbers.

• Optional asynchronous input ports including asynchronous clear (aclr) and clock enable (clk_en).

• Support for round-to-nearest-even rounding mode.

• Compute results of any mathematical operations according to the IEEE-754 standard compliance with a maximum of 1 unit in the last place (u.l.p.) error. This assumption is applied to all floating-point IP cores excluding complex matrix multiplication and inverse operations (for example, ALTFP_MATRIX_MULTI and ALFP_MATRIX_INV), where a slight increase in errors is observed due to the accumulation of errors during the mathematical operation.

Altera floating-point IP cores do not support denormal number inputs. If the input is a denormal value, the IP core forces the value to zero and treats the value as a zero before going through any operation.

Related Information

FFT MegaCore Function User Guide

Altera also offers the single-precision floating-point option in the FFT MegaCore.

IEEE-754 Standard for Floating-Point Arithmetic

The floating-point IP cores implement the following representations in the IEEE-754 standard:

1-13

• Floating-point numbers

• Special values (zero, infinity, denormal numbers, and NaN bit combinations)

• Single-precision, double-precision, and single-extended precision formats for floating-point numbers

Floating-Point Formats

All floating-point formats have binary patterns. In Figure 1–1, S represents a sign bit, E represents an exponent field, and M is the mantissa (part of a logarithm, or fraction) field.

For a normal floating-point number, a leading 1 is always implied, for example, binary 1.0011 or decimal 1.1875 is stored as 0011 in the mantissa field. This format saves the mantissa field from using an extra bit to represent the leading 1. However, the leading bit for a denormal number can be either 0 or 1. For zero, infinity, and NaN, the mantissa field does not have an implied leading 1 nor any explicit leading bit.

Figure 1-8: IEEE-754 Floating-Point Format

This figure shows a floating-point format.

Single-Precision Format

The single-precision format contains the following binary patterns:

• The MSB holds the sign bit.

• The next 8 bits hold the exponent bits.

• 23 LSBs hold the mantissa.

The total width of a floating-point number in the single-precision format is 32 bits. The bias for the single-precision format is 127.

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S E M

31 30 23 22 0

S E M

63 62 52 51 0

1-14

Double-Precision Format

Figure 1-9: Single-Precision Representation

This figure shows a single-precision representation.

Double-Precision Format

The double-precision format contains the following binary patterns:

• The MSB holds the sign bit.

• The next 11 bits hold the exponent bits.

• 52 LSBs hold the mantissa.

The total width of a floating-point number in the double-precision format is 64 bits. The bias for the double-precision format is 1023.

Figure 1-10: Double-Precision Representation

This figure shows a double-precision representation.

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Single-Extended Precision Format

The single-extended precision format contains the following binary patterns:

• The MSB holds the sign bit.

• The exponent and mantissa fields do not have fixed widths.

• The minimum exponent field width is 11 bits and must be less than the width of the mantissa field.

• The width of the mantissa field must be a minimum of 31 bits.

The sum of the widths of the sign bit, exponent field, and mantissa field must be a minimum of 43 bits and a maximum of 64 bits. The bias for the single-extended precision format is unspecified in the IEEE-754 standard. In these IP cores, a bias of 2(WIDTH_EXP–1)–1 is assumed for the single-extended precision format.

Special Case Numbers

The following table lists the special case numbers defined by the IEEE-754 standard and the data bit representations.

Table 1-4: Special Case Numbers in IEEE-754 Representation

Meaning Sign Field Exponent Field Mantissa Field

Zero Don’t care All 0’s All 0’s

Positive Denormalized 0 All 0’s Non-zero

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Sign bit

Integer bits

31 0

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Rounding

Meaning Sign Field Exponent Field Mantissa Field

Negative Denormalized 1 All 0’s Non-zero

Positive Infinity 0 All 1’s All 0’s

Negative Infinity 1 All 1’s All 0’s

Not-a-Number (NaN) Don’t care All 1’s Non-zero

The IEEE-754 standard defines four types of rounding modes, which are:

• round-to-nearest-even

• round-toward-zero

• round-toward-positive-infinity

• round-toward-negative-infinity

Altera floating-point IP cores support only the most commonly used rounding mode, which is the roundto-nearest-even mode (TO_NEAREST). With round-to-nearest-even, the IP core rounds the result to the nearest floating-point number. If the result is exactly halfway between two floating-point numbers, the IP core rounds the result so that the LSB becomes a zero, which is even.

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Non-IEEE-754 Standard Format

Only the ALTFP_CONVERT and ALTERA_FP_FUNCTIONS (when the convert function is selected) support the fixed point format.

The fixed-point data type is similar to the conventional integer data type, except that the fixed-point data carries a predetermined number of fractional bits. If the width of the fraction is 0, the data becomes a normal signed integer.

The notation for fixed-point format numbers in this user guide is Qm.f, where Q designates that the number is in Q format notation, m is the number of bits used to indicate the integer portion of the number, and f is the number of bits used to indicate the fractional portion of the number.

For example, Q4.12 describes a number with 4 integer bits and 12 fractional bits in a 16-bit word. The following figures show the difference between the signed-integer format and the fixed-point format

for a 32-bit number.

Figure 1-11: Signed-Integer Format

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Sign bit

Integer bits

31 0

Fraction bits

1-16

Floating-Points IP Cores Output Latency

Figure 1-12: Fixed-Point Format

Floating-Points IP Cores Output Latency

The IP cores measure the output latency in clock cycles and is different for each IP core. In some IP cores, the precision modes determine the number of clock cycles between the input and output result. When you select a mode, the options for latency are fixed for that mode.

For specific details about latency options, refer to the Output Latency section of your selected IP core in this user guide.

Floating-Point IP Cores Design Example Files

The design examples for each IP core in this user guide use the IP Catalog and parameter editor to define custom IP variations.

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Simulate the designs in the ModelSim®-Altera software to generate a waveform display of the device behavior. You must be familiar with the ModelSim-Altera software before trying out the design examples.

Table 1-5: Design Files for Floating-Point IP Cores

Floating-Point IP Cores Design Files

ALTFP_ADD_SUB

ALTFP_DIV

ALTFP_MULT

ALTFP_SQRT

ALTFP_EXP

ALTFP_INV

• altfp_add_sub_DesignExample.zip (Quartus II design files)

• altfp_add_sub_ex_msim.zip (ModelSim-Altera files)

• altfp_div_DesignExample.zip (Quartus II design files)

• altfp_div_ex_msim.zip (ModelSim-Altera files)

• altfp_mult_DesignExample.zip (Quartus II design files)

• altfp_mult_ex_msim.zip (ModelSim-Altera files)

• altfp_sqrt_DesignExample.zip (Quartus II design files)

• altfp_sqrt_ex_msim.zip (ModelSim-Altera files)

• altfp_exp_DesignExample.zip (Quartus II design files)

• altfp_exp_ex_msim.zip (ModelSim-Altera files)

• altfp_inv_DesignExample.zip (Quartus II design files)

• altfp_inv_ex_msim.zip (ModelSim-Altera files)

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Floating-Point IP Cores Design Example Files

Floating-Point IP Cores Design Files

1-17

ALTFP_INV_SQRT

• altfp_inv_sqrt_DesignExample.zip (Quartus II design files)

• altfp_inv_sqrt_ex_msim.zip (ModelSim-Altera files)

ALTFP_LOG

• altfp_log_DesignExample.zip (Quartus II design files)

• altfp_log_ex_msim.zip (ModelSim-Altera files)

ALTFP_ATAN Not Available ALTFP_SINCOS Not Available ALTFP_ABS

• altfp_mult_abs_DesignExample.zip (Quartus II design files)

• altfp_mult_abs_ex_msim.zip (ModelSim-Altera files)

ALTFP_COMPARE

• altfp_compare_DesignExample.zip (Quartus II design files)

• altfp_compare_ex_msim.zip (ModelSim-Altera files)

ALTFP_CONVERT

• altfp_convert_DesignExample.zip (Quartus II design files)

• altfp_convert_float2int_msim.zip (ModelSim-Altera files)

ALTERA_FP_ACC_CUSTOM Not Available ALTERA_FP_FUNCTIONS Not Available ALTERA_FP_MATRIX_INV

• altfp_matrix_inv_DesignExample.zip (Quartus II design files)

• altfp_matrix_inv_ex_msim.zip (ModelSim-Altera files)

ALTERA_FP_MATRIX_

Not Available

MULT

Related Information

• ALTERA_FP_MATRIX_INV Design Example: Matrix Inverse of Single-Precision Format

Numbers on page 2-6

• ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers on page 53

• ALTFP_DIV Design Example: Division of Single-Precision on page 6-4

• ALTFP_MULT Design Example: Multiplication of Double-Precision Format Numbers on page 73

• ALTFP_SQRT Design Example: Square Root of Single-Precision Format Numbers on page 8-3

• ALTFP_EXP Design Example: Exponential of Single-Precision Format Numbers on page 9-2

• ALTFP_INV Design Example: Inverse of Single-Precision Format Numbers on page 10-2

This design example uses the ALTFP_INV IP core to compute the inverse of single-precision format numbers. This example uses the parameter editor in the Quartus II software.

• ALTFP_INV_SQRT Design Example: Inverse Square Root of Single-Precision Format Numbers on page 11-2

• ALTFP_LOG Design Example: Natural Logarithm of Single-Precision Format Numbers on page 12-2

• ALTFP_ABS Design Example: Absolute Value of Multiplication Results on page 15-2

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VHDL Component Declaration

• ALTFP_COMPARE Design Example: Comparison of Single-Precision Format Numbers on page 16-2

• ALTFP_CONVERT Design Example: Convert Double-Precision Floating-Point Format Numbers on page 17-6

• Floating-Point IP Cores Design Examples Provides the design example files for the Floating-Point IP cores

• ModelSim-Altera Software Support Provides information about installation, usage, and troubleshooting

VHDL Component Declaration

The VHDL component declaration is located in the <Quartus II installation directory>\libraries\vhdl\altera_mf\

altera_mf_components.vhd

VHDL LIBRARY-USE Declaration

The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.

LIBRARY altera_mf;

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USE altera_mf_altera_mf_components.all;

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ALTERA_FP_MATRIX_INV IP Core

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ALTERA_FP_MATRIX_INV Features

The ALTERA_FP_MATRIX_INV IP core offers the following features:

• Inversion of a matrix.

• Support for floating-point format in single precision.

• Support for VHDL and Verilog HDL languages.

• Support for matrix sizes up to are 4 × 4, 6 × 6, 8 × 8, 16 ×16, 32 × 32, and 64 × 64.

• Use of control signal, load.

• Use of handshaking signals: busy, outvalid, and done.

ALTERA_FP_MATRIX_INV Output Latency

The ALTERA_FP_MATRIX_INV IP core does not have a fixed output latency. Instead, it uses handshaking signals to interface with external circuitry.

ALTERA_FP_MATRIX_INV Resource Utilization and Performance

This table lists the resource utilization and performance information for the ALTERA_FP_MATRIX_INV IP core. The information was derived using the Quartus II software version 10.0

ISO 9001:2008 Registered

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ALTERA_FP_MATRIX_INV Functional Description

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Table 2-1: ALTERA_FP_MATRIX_INV Resource Utilization and Performance for the Stratix IV Device Family

Precision

Single

Logic usage

Matrix

Size

Blocks

Adapti

Logic

Modul

(ALMs)

DSP

Usage

(18 x

DSPs)

M9K M144K Memor

y (Bits)

Latenc

Throug

hput

(kb/s)

4× 4 2 21159 222 139 — 19919 PendingPendingPendin

Giga

Floatin

Point

Operat

ions

per

Secon

(GFLO

PS)

MAX

(MHz)

221

6 × 6 2 59827 574 90 — 15759 PendingPendingPendin

170

8 × 8 2 5,538 63 49 — 53,736 2,501 3,987 15.26 332

16 ×

4 8,865 95 80 — 138,05111,057 855 30.93 329

32 ×

8 15,655 159 193 — 699,16452,625 165 55.12 290

64 ×

16 29,940 287 386 22 4,770,369281,50525 83.16 218

ALTERA_FP_MATRIX_INV Functional Description

A matrix inversion function is composed of the following components:

• Cholesky decomposition function. The Cholesky decomposition function generates a lower triangular matrix.

• Triangular matrix inversion function. The triangular matrix inversion process then generates the inverse of the lower triangular using

backward substitution.

• Matrix multiplication function. The matrix multiplier multiplies the transpose of the inverse triangular matrix with the inverse

triangular matrix.

In linear algebra, the Cholesky decomposition states that every positive definite matrix A is decomposed as A = L×LT

where, L is a lower triangular matrix, and LT denotes the transpose of L. The property of invertible matrices states that (X×Y)-1 = X-1×Y-1 and the property of transpose states

that (XT )-1 = (X-1)T. Combining these two properties, the following equation represents a derivation of a matrix inversion using the Cholesky decomposition method:

A-1 = (L×LT)-1

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A L

-1

A(L )

Matrix A

Storage 1 Storage 2

Cholesky

Decomposition

Triangular Matrix

Inversion

Matrix

Multiplication

-f

T -1

-1

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= (LT)-1 × L-1 = (L-1)T × L-1 where a Cholesky decomposition function is needed to obtain L, a triangular matrix inversion is needed to

obtain L-1, and a matrix multiplication is needed for (L-1)T × L-1.

Figure 2-1: Matrix Inversion Flow Diagram

Cholesky Decomposition Function

The functions consists of two memory and two processing blocks. One of the memory blocks is the input matrix memory block and is loaded with the input matrix in a row order, one element at a time. However, during processing, this block is read in a column order, one element at a time when required.

Cholesky Decomposition Function

2-3

The other memory block is the processing matrix block which consists of multiple column memories to enable an entire row to be read at once. During the loading of the input memory, the FPC datapath preprocesses the input elements to generate the first column of the resulting triangular matrix. The top element of the first column, l00, is the square root of the input matrix value a00. The rest of the first column, li0 is the input value ai0 divided by l00. This preprocessing step introduces latency into the load, during which the INIT_BUSY signal is asserted. The CALCULATE signal initiates and starts processing after the INIT_BUSY signal is deasserted.

This figure shows the top-level architecture of the Cholesky decomposition function, where the monolithic input memory and the column-wise processing memory, also known as the vector matrix, are shown. The gray block is the FPC datapath section.

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Cholesky Decomposition Function

Figure 2-2: Cholesky Decomposition Function Top-level Diagram

Although the Cholesky decomposition algorithm only operates on the lower triangular matrix, the core requires the entire matrix to be loaded, during which the processing or vector memory is initialized.

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The FPC datapath is split into two sections. The first section, also known as the vector section, takes the inner product of two vectors and subtracts it from the input matrix element, aij. The second section, also known as the root section, calculates square roots and performs division by the square root. The first element is loaded into both inputs of the root section and the outcome is its own square root. The first element continues to stay latched in the left input field of the root section while all the other elements of the first column are loaded into the right input field. The resulting output is the value of the respective column element divided by the value of the first element of the Cholesky decomposition matrix.

During processing, two rows from the processing matrix are loaded. For the first element in each new column, both rows have the same index; hence contain the same values. The first row is latched into the input register of the vector section. For the rest of the column, the row index is increased, and a new a

element and triangular matrix vector, Lj is loaded. The first result out of the vector section is latched onto the left register of the root section. All results from the column, including the first result, are loaded into the right register of the root section. The root section generates the square root of the first vector result, while for the other results coming from the vector section, the number is divided by the square root of the first result.

All calculated values are written to another memory block for further processing. The first column values are output singly during preprocessing, while the values of other columns are burst out during processing.

There are only minor differences between the architectures for real and complex matrices. For the complex matrix, both the input and processing memory blocks contain complex values. Similarly, all values going into the vector section are complex numbers. The complex conjugate of the latched register is obtained by simply inverting the sign bit. As for the root section, the structure is simplified by the nature of the positive definite matrix. The diagonal value, which is the first value at the top of each column in the decomposition, is always a real number so that the result from the inverse square root calculation is always a real number. The complex multiplier in the root section is therefore a real scalar, so only two real multipliers are required.

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Triangular Matrix Inversion

The triangular matrix, L, obtained from the Cholesky decomposition function is computed using the triangular matrix inversion algorithm to get its inversion. The following MatLab pseudo code shows how the inversion is carried out:

for j = n:-1:1,

X(j,j) = 1/L(j, j);

for k = j+1:n

for i = j+1:n

X(k, j) = X(k, j) + X(k, i)*L(i, j);

end;

for k = j+1:n

X(k, j) = -X(j, j)*X(k, j);

end;

Triangular Matrix Inversion

2-5

The pseudo code is converted into an RTL file. The result, L-1 is stored in the input matrix storage in the Cholesky decomposition function.

Matrix Multiplication

The final stage of the matrix inversion process involves multiplying the transpose of the inverse triangular matrix with the inverse triangular matrix using the Altera Floating-Point Matrix Multiplier. The original version of the matrix multiplier is modified for this purpose. As there are memory blocks already available for the storage of the input matrices in the Cholesky decomposition function, the memory blocks in the matrix multiplier are redundant and can be removed. Data is instead fed directly from the results stored at the end stage of the triangular matrix inversion algorithm.

Matrix Inversion Operation

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sysclk

enable

reset

load

datain

dataout

outvalid

busy

done

Loading Stage Processing Stage Output Stage

2-6

ALTERA_FP_MATRIX_INV Design Example: Matrix Inverse of Single-Precision Format Numbers

Figure 2-3: Matrix Inversion Timing Diagram

The following sequence describes the matrix inversion operation:

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1. The operation begins when the enable signal is asserted and the reset signal is deasserted.

2. The load signal is asserted to load data from the loaddata[] port for the input matrix. As long as the

load signal is high, data is loaded continuously for the input matrix.

3. The busy signal is asserted and the done signal is deasserted for a few clock cycles after the datain[] signal is asserted.

4. The outvalid signal is asserted multiple times to signify the availability of valid data on the dataout[] port. The number of times this signal is asserted equals the number of rows found in the output matrix.

5. The busy and done signals are asserted when the last row of the output matrix has been burst out. This assertion signifies the end of the matrix inversion operation on the first set of data.

ALTERA_FP_MATRIX_INV Design Example: Matrix Inverse of SinglePrecision Format Numbers

This design example uses the ALTERA_FP_MATRIX_INV IP core to show the matrix inversion operation. The input matrix applied is an 8 × 8 matrix with a block size of 2. This example uses the parameter editor GUI to define the core.

Related Information

• Floating-Point IP Cores Design Example Files on page 1-16

• Floating-Point IP Cores Design Examples Provides the design example files for the Floating-Point IP cores

• ModelSim-Altera Software Support Provides information about installation, usage, and troubleshooting

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+ 127 hidden pages

Altera Floating-Point User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Floating-Point IP Cores User Guide

Contents

About Floating-Point IP Cores

List of Floating-Point IP Cores

Installing and Licensing IP Cores

Design Flow

IP Catalog and Parameter Editor

Using the Parameter Editor

Specifying IP Core Parameters and Options

Files Generated for Altera IP Cores

Specifying IP Core Parameters and Options (Legacy Parameter Editors)

Upgrading IP Cores

Migrating IP Cores to a Different Device

Floating-Point IP Cores General Features

IEEE-754 Standard for Floating-Point Arithmetic

Floating-Point Formats

Single-Precision Format

Double-Precision Format

Single-Extended Precision Format

Special Case Numbers

Rounding

Non-IEEE-754 Standard Format

Floating-Points IP Cores Output Latency

Floating-Point IP Cores Design Example Files

VHDL Component Declaration

VHDL LIBRARY-USE Declaration

ALTERA_FP_MATRIX_INV IP Core

ALTERA_FP_MATRIX_INV Features

ALTERA_FP_MATRIX_INV Output Latency

ALTERA_FP_MATRIX_INV Resource Utilization and Performance

ALTERA_FP_MATRIX_INV Functional Description

Cholesky Decomposition Function

Triangular Matrix Inversion

Matrix Multiplication

Matrix Inversion Operation

ALTERA_FP_MATRIX_INV Design Example: Matrix Inverse of Single-Precision Format Numbers