Altera FLEX 8000 Service Manual

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FLEX 8000

®

Programmable Logic

Device Family

September 1998, ver. 9.11 Data Sheet

Low-cost, high-density, register-rich CMOS programmable logic

Features...

■

device (PLD) family (see Table 1)
– 2,500 to 16,000 usable gates
– 282 to 1,500 registers
System-level features

■

– In-circuit reconfigurability (ICR) via external Configuration

EPROM or intelligent controller

– Fully compliant with the peripheral component interconnect

(PCI) standard

– Built-in Joint-Test Action Group (JTAG) boundary-scan test (BST)

circuitry compliant with IEEE Std. 1149.1-1990 on selected devices

– MultiVolt

while I/O pins are compatible with 5.0-V and 3.3-V logic levels

– Low power consumption (typical specification less than 0.5 mA

in standby mode)

Flexible interconnect

■

– FastTrack

predictable interconnect delays

– Dedicated carry chain that implements arithmetic functions such

as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)

– Dedicated cascade chain that implements high-speed, high-fan-in

logic functions (automatically used by software tools and

megafunctions)
– Tri-state emulation that implements internal tri-state nets
Powerful I/O pins

■

– Programmable output slew-rate control reduces switching noise
Peripheral register for fast setup and clock-to-output delay

■

™

I/O interface enabling device core to run at 5.0 V,

™

Interconnect continuous routing structure for fast,

3

FLEX 8000

Table 1. FLEX 8000 Device Features

Feature EPF8282A

EPF8282AV

Usable gates 2,500 4,000 6,000 8,000 12,000 16,000
Flipflops 282 452 636 820 1,188 1,500
Logic array blocks (LABs) 26 42 63 84 126 162
Logic elements (LEs) 208 336 504 672 1,008 1,296
Maximum user I/O pins 78 120 136 152 184 208
JTAG BST circuitry Yes No Yes Yes No Yes

Altera Corporation 1

A-DS-F8000-09.11

EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A

FLEX 8000 Programmable Logic Device Family Data Sheet

■

...and More
Features

Fabricated on an advanced SRAM process

■

Available in a variety of packages with 84 to 304 pins (see Table 2)

■

Software design support and automatic place-and-route provided by
the Altera

®

MAX+PLUS
Pentium-based PCs, and Sun SPARCstation, HP 9000 Series 700/800,
and IBM RISC System/6000 workstations

■

Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and Veribest

Table 2. FLEX 8000 Package Options & I/O Pin Count Note (1)

®

II development system for 486- and

Device 84-Pin

PLCC

EPF8282A 68 78
EPF8282AV 78
EPF8452A 68 68 120 120
EPF8636A 68 118 136 136
EPF8820A 112 120 152 152 152
EPF81188A 148 184 184
EPF81500A 181 208 208

Note:

(1) FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad

flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages.

General
Description

100-

TQFP

Pin

144-

Pin

TQFP

160-

Pin

PQFP

160-

Pin

PGA

192-

Pin

PGA

208-

Pin

PQFP

Altera’s Flexible Logic Element MatriX (FLEX

225-

Pin

BGA

232-

PGA

®

240-

280-

Pin

Pin

PQFP

Pin

PGA

) family combines the
benefits of both erasable programmable logic devices (EPLDs) and field­programmable gate arrays (FPGAs). The FLEX 8000 device family is ideal

304-

Pin

RQFP

for a variety of applications because it combines the fine-grained
architecture and high register count characteristics of FPGAs with the
high speed and predictable interconnect delays of EPLDs. Logic is
implemented in LEs that include compact 4-input look-up tables (LUTs)
and programmable registers. High performance is provided by a fast,
continuous network of routing resources.

2 Altera Corporation

FLEX 8000 devices provide a large number of storage elements for
applications such as digital signal processing (DSP), wide-data-path
manipulation, and data transformation. These devices are an excellent
choice for bus interfaces, TTL integration, coprocessor functions, and
high-speed controllers. The high-pin-count packages can integrate
multiple 32-bit buses into a single device. Table 3 shows FLEX 8000
performance and LE requirements for typical applications.

Table 3. FLEX 8000 Performance

FLEX 8000 Programmable Logic Device Family Data Sheet

Application LEs Used A-2 Speed Grade A-3 Speed Grade A-4 Speed

16-bit loadable counter
16-bit up/down counter
24-bit accumulator
16-bit address decode
16-to-1 multiplexer

16
16
24

10

125 95 83 MHz
125 95 83 MHz

87 67 58 MHz

4

4.2 4.9 6.3 ns

6.6 7.9 9.5 ns

All FLEX 8000 device packages provide four dedicated inputs for
synchronous control signals with large fan-outs. Each I/O pin has an
associated register on the periphery of the device. As outputs, these
registers provide fast clock-to-output times; as inputs, they offer quick
setup times.

The logic and interconnections in the FLEX 8000 architecture are
configured with CMOS SRAM elements. FLEX 8000 devices are
configured at system power-up with data stored in an industry-standard
parallel EPROM or an Altera serial Configuration EPROM device, or with
data provided by a system controller. Altera offers the EPC1, EPC1213,
EPC1064, and EPC1441 Configuration EPROMs, which configure
FLEX 8000 devices via a serial data stream. Configuration data can also be
stored in an industry-standard 32 K × 8 bit or larger EPROM, or
downloaded from system RAM. After a FLEX 8000 device has been
configured, it can be reconfigured in-circuit by resetting the device and
loading new data. Because reconfiguration requires less than 100 ms, real­time changes can be made during system operation.

Units

Grade

3

FLEX 8000

f

Altera Corporation 3

For information on how to configure FLEX 8000 devices, go to the
following documents:

Configuration EPROMs for FLEX Devices Data Sheet

■

BitBlaster Serial Download Cable Data Sheet

■

ByteBlaster Parallel Port Download Cable Data Sheet

■

Application Note 33 (Configuring FLEX 8000 Devices)

■

Application Note 38 (Configuring Multiple FLEX 8000 Devices)

■

FLEX 8000 Programmable Logic Device Family Data Sheet

FLEX 8000 devices contain an optimized microprocessor interface that
permits the microprocessor to configure FLEX 8000 devices serially, in
parallel, synchronously, or asynchronously. The interface also enables the
microprocessor to treat a FLEX 8000 device as memory and configure the
device by writing to a virtual memory location, making it very easy for the
designer to create configuration software.

The FLEX 8000 family is supported by Altera’s MAX+PLUS II
development system, a single, integrated package that offers schematic,
text—including the Altera Hardware Description Language (AHDL),
VHDL, and Verilog HDL—and waveform design entry; compilation and
logic synthesis; simulation and timing analysis; and device programming.
The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, library of
parameterized modules (LPM), VHDL, Verilog HDL, and other interfaces
for additional design entry and simulation support from other industry­standard PC- and UNIX workstation-based EDA tools. The
MAX+PLUS II software runs on 486- and Pentium-based PCs, and Sun
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations.

f

Functional
Description

The MAX+PLUS II software interfaces easily with common gate array
EDA tools for synthesis and simulation. For example, the MAX+PLUS II
software can generate Verilog HDL files for simulation with tools such as
Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains
EDA libraries that use device-specific features such as carry chains, which
are used for fast counter and arithmetic functions. For instance, the
Synopsys Design Compiler library supplied with the MAX+PLUS II
development system includes DesignWare functions that are optimized
for the FLEX 8000 architecture.

For more information on the MAX+PLUS II software, go to the

MAX+PLUS II Programmable Logic Development System & Software Data
Sheet in this data book.

The FLEX 8000 architecture incorporates a large matrix of compact
building blocks called logic elements (LEs). Each LE contains a 4-input
LUT that provides combinatorial logic capability and a programmable
register that offers sequential logic capability. The fine-grained structure
of the LE provides highly efficient logic implementation.

Eight LEs are grouped together to form a logic array block (LAB). Each
FLEX 8000 LAB is an independent structure with common inputs,
interconnections, and control signals. The LAB architecture provides a
coarse-grained structure for high device performance and easy routing.

4 Altera Corporation

Figure 1 shows a block diagram of the FLEX 8000 architecture. Each

group of eight LEs is combined into an LAB; LABs are arranged into rows
and columns. The I/O pins are supported by I/O elements (IOEs) located
at the ends of rows and columns. Each IOE contains a bidirectional I/O
buffer and a flipflop that can be used as either an input or output register.

Figure 1. FLEX 8000 Device Block Diagram

FLEX 8000 Programmable Logic Device Family Data Sheet

I/O Element
(IOE)

IOE

IOE

Logic Array
Block (LAB)

IOE

IOE

Logic
Element (LE)

IOEIOE IOEIOE

IOEIOE IOEIOE

FastTrack
Interconnect

IOE

IOE

IOE

IOE

3

FLEX 8000

Signal interconnections within FLEX 8000 devices and between device
pins are provided by the FastTrack Interconnect, a series of fast,
continuous channels that run the entire length and width of the device.
IOEs are located at the end of each row (horizontal) and column (vertical)
FastTrack Interconnect path.

Altera Corporation 5

FLEX 8000 Programmable Logic Device Family Data Sheet

Logic Array Block

A logic array block (LAB) consists of eight LEs, their associated carry and
cascade chains, LAB control signals, and the LAB local interconnect. The
LAB provides the coarse-grained structure of the FLEX 8000 architecture.
This structure enables FLEX 8000 devices to provide efficient routing,
high device utilization, and high performance. Figure 2 shows a block
diagram of the FLEX 8000 LAB.

Figure 2. FLEX 8000 Logic Array Block

Dedicated

Inputs

Row Interconnect

LAB Local
Interconnect
(32 channels)

LAB Control
Signals

24

4

4

4

Carry-In and
Cascade-In
from LAB
on Left

2

8

See Figure 8
for details.

8

16

Column-to-Row

4

4

4

4

4

4

4

4

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

Interconnect

Column
Interconnect

8

2

Carry-Out and
Cascade-Out
to LAB on Right

6 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

Each LAB provides four control signals that can be used in all eight LEs.
Two of these signals can be used as clocks, and the other two for
clear/preset control. The LAB control signals can be driven directly from
a dedicated input pin, an I/O pin, or any internal signal via the LAB local
interconnect. The dedicated inputs are typically used for global clock,
clear, or preset signals because they provide synchronous control with
very low skew across the device. FLEX 8000 devices support up to four
individual global clock, clear, or preset control signals. If logic is required
on a control signal, it can be generated in one or more LEs in any LAB and
driven into the local interconnect of the target LAB. This process is called
programmable inversion, and is available for all four LAB control signals.

Logic Element

Figure 3. FLEX 8000 LE

DATA1
DATA2
DATA3
DATA4

LABCTRL1
LABCTRL2

LABCTRL3
LABCTRL4

The logic element (LE) is the smallest unit of logic in the FLEX 8000
architecture, with a compact size that provides efficient logic utilization.
Each LE contains a 4-input LUT, a programmable flipflop, a carry chain,
and cascade chain. Figure 3 shows a block diagram of an LE.

Look-Up

T able

(LUT)

Clear/
Preset

Logic

Clock
Select

Carry-In

Carry
Chain

Carry-Out

Cascade-In

Cascade

Chain

Cascade-Out

DFF

PRN

DQ

CLRN

LE-Out

The LUT is a function generator that can quickly compute any function of
four variables. The programmable flipflop in the LE can be configured for
D, T, JK, or SR operation. The clock, clear, and preset control signals on the
flipflop can be driven by dedicated input pins, general-purpose I/O pins,
or any internal logic. For purely combinatorial functions, the flipflop is
bypassed and the output of the LUT goes directly to the output of the LE.

3

FLEX 8000

Altera Corporation 7

FLEX 8000 Programmable Logic Device Family Data Sheet

The FLEX 8000 architecture provides two dedicated high-speed data
paths—carry chains and cascade chains—that connect adjacent LEs
without using local interconnect paths. The carry chain supports high­speed counters and adders; the cascade chain implements wide-input
functions with minimum delay. Carry and cascade chains connect all LEs
in an LAB and all LABs in the same row. Heavy use of carry and cascade
chains can reduce routing flexibility. Therefore, the use of carry and
cascade chains should be limited to speed-critical portions of a design.

Carry Chain

The carry chain provides a very fast (less than 1 ns) carry-forward
function between LEs. The carry-in signal from a lower-order bit moves
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This feature allows the
FLEX 8000 architecture to implement high-speed counters and adders of
arbitrary width. The MAX+PLUS II Compiler can create carry chains
automatically during design processing; designers can also insert carry
chain logic manually during design entry.

Figure 4 shows how an n -bit full adder can be implemented in n + 1 LEs

with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register is typically bypassed for simple adders, but
can be used for an accumulator function. Another portion of the LUT and
the carry chain logic generate the carry-out signal, which is routed directly
to the carry-in signal of the next-higher-order bit. The final carry-out
signal is routed to another LE, where it can be used as a general-purpose
signal. In addition to mathematical functions, carry chain logic supports
very fast counters and comparators.

8 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

Figure 4. FLEX 8000 Carry Chain Operation

Carry-In

a1
b1

a2
b2

a
b

LU

Carry

LUT

Carry Chain

Register

LE

Register

LE

s1

s2

3

n
n

LUT

Carry Chain

Register

LE

s

n

FLEX 8000

LUT

Carry Chain

Register

LE

n

+ 1

Carry-Out

Cascade Chain

With the cascade chain, the FLEX 8000 architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connects the intermediate values. The cascade chain can use a logical AND
or logical OR (via De Morgan’s inversion) to connect the outputs of
adjacent LEs. Each additional LE provides four more inputs to the
effective width of a function, with a delay as low as 0.6 ns per LE.

Altera Corporation 9

FLEX 8000 Programmable Logic Device Family Data Sheet

The MAX+PLUS II Compiler can create cascade chains automatically
during design processing; designers can also insert cascade chain logic
manually during design entry. Cascade chains longer than eight LEs are
automatically implemented by linking LABs together. The last LE of an
LAB cascades to the first LE in the next LAB in the row.

Figure 5 shows how the cascade function can connect adjacent LEs to

form functions with a wide fan-in. These examples show functions of 4 n
variables implemented with n LEs. For a device with an A-2 speed grade,
the LUT delay is approximately 1.6 ns; the cascade chain delay is 0.6 ns.
With the cascade chain, 4.2 ns is needed to decode a 16-bit address.

Figure 5. FLEX 8000 Cascade Chain Operation

AND Cascade Chain OR Cascade Chain

LE1

d[3..0]

d[7..4]

d[(4n-1)..4(n-1)]

LUT

LUT

LUT

LE2

LE

n

d[3..0]

d[7..4]

d[(4n-1)..4(n-1)]

LE Operating Modes

The FLEX 8000 LE can operate in one of four modes, each of which uses
LE resources differently. See Figure 6. In each mode, seven of the ten
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. The three remaining
inputs to the LE provide clock, clear, and preset control for the register.
The MAX+PLUS II software automatically chooses the appropriate mode
for each application. Design performance can also be enhanced by
designing for the operating mode that supports the desired application.

LUT

LUT

LUT

LE1

LE2

LE

n

10 Altera Corporation

Figure 6. FLEX 8000 LE Operating Modes

Normal Mode

FLEX 8000 Programmable Logic Device Family Data Sheet

Arithmetic Mode

Up/Down

DATA1
DATA2

DATA3

DATA4

DATA1
DATA2

DATA1 (ena)
DATA2 (nclr)

DATA3 (data)

DATA4 (nload)

Carry-In

Carry-In

Carry-In

4-Input

LUT

3-Input

LUT

3-Input

LUT

3-Input

LUT

3-Input

LUT

Cascade-In

Cascade-In

Carry-Out

1
0

Cascade-In

Carry-Out

Cascade-Out

Cascade-Out

Cascade-Out

PRN

DQ

CLRN

PRN

DQ

CLRN

PRN

DQ

CLRN

LE-Out

LE-Out

3

FLEX 8000

LE-Out

Clearable Counter Mode

Carry-In

DATA1 (ena)
DATA2 (nclr)

DATA3 (data)

DATA4 (nload)

3-Input

LUT

3-Input

LUT

1

0

Carry-Out

Cascade-Out

PRN

DQ

CLRN

LE-Out

Altera Corporation 11

FLEX 8000 Programmable Logic Device Family Data Sheet

Normal Mode

The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
signal are the inputs to a 4-input LUT. Using a configurable SRAM bit, the
MAX+PLUS II Compiler automatically selects the carry-in or the DATA3
signal as an input. The LUT output can be combined with the cascade-in
signal to form a cascade chain through the cascade-out signal. The LE-Out
signal—the data output of the LE—is either the combinatorial output of
the LUT and cascade chain, or the data output ( Q) of the programmable
register.

Arithmetic Mode

The arithmetic mode offers two 3-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
provides a 3-bit function; the other generates a carry bit. As shown in

Figure 6, the first LUT uses the carry-in signal and two data inputs from

the LAB local interconnect to generate a combinatorial or registered
output. For example, in an adder, this output is the sum of three bits: a , b ,
and the carry-in. The second LUT uses the same three signals to generate
a carry-out signal, thereby creating a carry chain. The arithmetic mode
also supports a cascade chain.

Up/Down Counter Mode

The up/down counter mode offers counter enable, synchronous
up/down control, and data loading options. These control signals are
generated by the data inputs from the LAB local interconnect, the carry-in
signal, and output feedback from the programmable register. Two 3-input
LUTs are used: one generates the counter data, and the other generates the
fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data
can also be loaded asynchronously with the clear and preset register
control signals, without using the LUT resources.

Clearable Counter Mode

The clearable counter mode is similar to the up/down counter mode, but
supports a synchronous clear instead of the up/down control; the clear
function is substituted for the cascade-in signal in the up/down counter
mode. Two 3-input LUTs are used: one generates the counter data, and
the other generates the fast carry bit. Synchronous loading is provided by
a 2-to-1 multiplexer, and the output of this multiplexer is AND ed with a
synchronous clear.

12 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

Internal Tri-State Emulation

Internal tri-state emulation provides internal tri-stating without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable signals select the signal that drives the bus.
However, if multiple output enable signals are active, contending signals
can be driven onto the bus. Conversely, if no output enable signals are
active, the bus will float. Internal tri-state emulation resolves contending
tri-state buffers to a low value and floating buses to a high value, thereby
eliminating these problems. The MAX+PLUS II software automatically
implements tri-state bus functionality with a multiplexer.

Clear & Preset Logic Control

Logic for the programmable register’s clear and preset functions is
controlled by the DATA3 , LABCTRL1 , and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE is used to asynchronously load
signals into a register. The register can be set up so that LABCTRL1
implements an asynchronous load. The data to be loaded is driven to

DATA3 ; when LABCTRL1 is asserted, DATA3 is loaded into the register.

During compilation, the MAX+PLUS II Compiler automatically selects
the best control signal implementation. Because the clear and preset
functions are active-low, the Compiler automatically assigns a logic high
to an unused clear or preset.

The clear and preset logic is implemented in one of the following six
asynchronous modes, which are chosen during design entry. LPM
functions that use registers will automatically use the correct
asynchronous mode. See Figure 7.

Clear only

■

Preset only

■

Clear and preset

■

Load with clear

■

Load with preset

■

Load without clear or preset

■

3

FLEX 8000

Altera Corporation 13

FLEX 8000 Programmable Logic Device Family Data Sheet

Figure 7. FLEX 8000 LE Asynchronous Clear & Preset Modes

Asynchronous Clear

VCC

PRN

Q

D

CLRN

LABCTRL1 or

LABCTRL2

Asynchronous Load with Clear

LABCTRL1

(Asynchronous

Load)

DATA3

(Data)

LABCTRL2

(Clear)

NOT

NOT

Asynchronous Load with Preset

LABCTRL1

(Asynchronous

Load)

NOT

Asynchronous Preset

LABCTRL1 or

LABCTRL2

D

D

PRN

CLRN

PRN

CLRN

Q

Asynchronous Clear & Preset

LABCTRL1

PRN

Q

Q

LABCTRL2

D

CLRN

LABCTRL2

(Preset)

DATA3

(Data)

NOT

D

PRN

CLRN

Q

Asynchronous Load without Clear or Preset

LABCTRL1

(Asynchronous

Load)

DATA3

(Data)

NOT

NOT

PRN

D

CLRN

Q

14 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

Asynchronous Clear

A register is cleared by one of the two LABCTRL signals. When the CLRn
port receives a low signal, the register is set to zero.

Asynchronous Preset

An asynchronous preset is implemented as either an asynchronous load
or an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRLl
asynchronously loads a 1 into the register. Alternatively, the
MAX+PLUS II software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two LABCTRL signals, the DATA3 input is not
needed and can be used for one of the LE operating modes.

Asynchronous Clear & Preset

When implementing asynchronous clear and preset, LABCTRL1 controls
the preset and LABCTRL2 controls the clear. The DATA3 input is tied to VCC;
therefore, asserting LABCTRL1 asynchronously loads a 1 into the register,
effectively presetting the register. Asserting LABCTRL2 clears the register.

Asynchronous Load with Clear

3

FLEX 8000

When implementing an asynchronous load with the clear, LABCTRL1
implements the asynchronous load of DATA3 by controlling the register
preset and clear. LABCTRL2 implements the clear by controlling the
register clear.

Asynchronous Load with Preset

When implementing an asynchronous load in conjunction with a preset,
the MAX+PLUS II software provides preset control by using the clear and
inverting the input and output of the register. Asserting LABCTRL2 clears
the register, while asserting LABCTRL1 loads the register. The
MAX+PLUS II software inverts the signal that drives the DATA3 signal to
account for the inversion of the register’s output.

Asynchronous Load without Clear or Preset

When implementing an asynchronous load without the clear or preset,
LABCTRL1 implements the asynchronous load of DATA3 by controlling the
register preset and clear.

Altera Corporation 15

FLEX 8000 Programmable Logic Device Family Data Sheet

FastTrack Interconnect

In the FLEX 8000 architecture, connections between LEs and device I/O
pins are provided by the FastTrack Interconnect, a series of continuous
horizontal (row) and vertical (column) routing channels that traverse the
entire FLEX 8000 device. This device-wide routing structure provides
predictable performance even in complex designs. In contrast, the
segmented routing structure in FPGAs requires switch matrices to
connect a variable number of routing paths, which increases the delays
between logic resources and reduces performance.

The LABs within FLEX 8000 devices are arranged into a matrix of
columns and rows. Each row of LABs has a dedicated row interconnect
that routes signals both into and out of the LABs in the row. The row
interconnect can then drive I/O pins or feed other LABs in the device.

Figure 8 shows how an LE drives the row and column interconnect.

Figure 8. FLEX 8000 LAB Connections to Row & Column Interconnect

16 Column

Channels

Row Channels

Note (1)

Each LE drives one
row channel.

LE1

LE2

to Local
Feedback

Note:

(1) See Table 4 for the number of row channels.

16 Altera Corporation

to Local
Feedback

Each LE drives up to
two column channels.

FLEX 8000 Programmable Logic Device Family Data Sheet

Each LE in an LAB can drive up to two separate column interconnect
channels. Therefore, all 16 available column channels can be driven by the
LAB. The column channels run vertically across the entire device, and
share access to LABs in the same column but in different rows. The
MAX+PLUS II Compiler chooses which LEs must be connected to a
column channel. A row interconnect channel can be fed by the output of
the LE or by two column channels. These three signals feed a multiplexer
that connects to a specific row channel. Each LE is connected to one 3-to-1
multiplexer. In an LAB, the multiplexers provide all 16 column channels
with access to 8 row channels.

Each column of LABs has a dedicated column interconnect that routes
signals out of the LABs into the column. The column interconnect can then
drive I/O pins or feed into the row interconnect to route the signals to
other LABs in the device. A signal from the column interconnect, which
can be either the output of an LE or an input from an I/O pin, must
transfer to the row interconnect before it can enter an LAB. Table 4
summarizes the FastTrack Interconnect resources available in each
FLEX 8000 device.

Table 4. FLEX 8000 FastTrack Interconnect Resources

Device Rows Channels per Row Columns Channels per Column

EPF8282A
EPF8282AV

EPF8452A 2 168 21 16
EPF8636A 3 168 21 16
EPF8820A 4 168 21 16
EPF81188A 6 168 21 16
EPF81500A 6 216 27 16

2 168 13 16

3

FLEX 8000

Figure 9 shows the interconnection of four adjacent LABs, with row,

column, and local interconnects, as well as the associated cascade and
carry chains.

Altera Corporation 17

FLEX 8000 Programmable Logic Device Family Data Sheet

Figure 9. FLEX 8000 Device Interconnect Resources

Each LAB is named according to its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device.

See Figure 11
for details.

IOE

1

IOE

8

IOE

1

IOE

8

LAB Local
Interconnect

Column
Interconnect

LAB

A1

LAB

B1

IOEIOE

Row
Interconnect

LAB

A2

LAB

B2

Cascade &
Carry Chain

IOEIOE IOEIOE

IOEIOE

See Figure 10
for details.

IOE

1

IOE

8

IOE

1

IOE

8

I/O Element

An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time,
or as an output register for data that requires fast clock-to-output
performance. IOEs can be used as input, output, or bidirectional pins. The
MAX+PLUS II Compiler uses the programmable inversion option to
automatically invert signals from the row and column interconnect where
appropriate. Figure 10 shows the IOE block diagram.

18 Altera Corporation

Figure 10. FLEX 8000 IOE

Numbers in parentheses are for EPF81500A devices only.

I/O Controls

FLEX 8000 Programmable Logic Device Family Data Sheet

to Row or Column
Interconnect

from Row or Column
Interconnect

6

Programmable

(6)

Inversion

VCC

DQ

Slew-Rate

Control

CLR0

CLR1/OE0

CLK0

CLK1/OE1

OE2

CLRN

VCC

OE3

(OE [4..9])

Row-to-IOE Connections

Figure 11 illustrates the connection between row interconnect channels

and IOEs. An input signal from an IOE can drive two separate row
channels. When an IOE is used as an output, the signal is driven by an
n-to-1 multiplexer that selects the row channels. The size of the
multiplexer varies with the number of columns in a device. EPF81500A
devices use a 27-to-1 multiplexer; EPF81188A, EPF8820A, EPF8636A, and
EPF8452A devices use a 21-to-1 multiplexer; and EPF8282A and
EPF8282AV devices use a 13-to-1 multiplexer. Eight IOEs are connected to
each side of the row channels.

3

FLEX 8000

Altera Corporation 19