Altera FIR Compiler II MegaCore Function User Manual
FIR II IP Core
User Guide
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FIR II IP Core User Guide
Contents
About the FIR II IP Core.....................................................................................1-1
FIR II IP Core Getting Started............................................................................2-1
Altera DSP IP Core Features...................................................................................................................... 1-1
FIR II IP Core Features............................................................................................................................... 1-2
DSP IP Core Device Family Support.........................................................................................................1-2
DSP IP Core Verification............................................................................................................................1-3
FIR II IP Core Release Information...........................................................................................................1-3
FIR II IP Core Performance and Resource Utilization...........................................................................1-3
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................ 2-1
FIR II IP Core OpenCore Plus Timeout Behavior...................................................................... 2-2
IP Catalog and Parameter Editor...............................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-3
Files Generated for Altera IP Cores...............................................................................................2-5
Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-8
DSP Builder Design Flow............................................................................................................................2-9
FIR II IP Core Parameters.................................................................................. 3-1
Filter Specification Parameters.................................................................................................................. 3-1
Coefficient Parameters................................................................................................................................3-3
Loading Coefficients from a File................................................................................................................3-3
Input and Output Options..........................................................................................................................3-4
Signed Fractional Binary.................................................................................................................3-5
MSB and LSB Truncation, Saturation, and Rounding............................................................................3-6
Memory and Multiplier Trade-Offs..........................................................................................................3-6
Using CDelay RAM Block Threshold...........................................................................................3-7
Using CDual Mem Dist RAM Threshold.....................................................................................3-7
Using M-RAM Threshold...............................................................................................................3-8
Using Hard Multiplier Threshold..................................................................................................3-8
FIR II IP Core Functional Description...............................................................4-1
FIR II IP Core Interfaces and Signals........................................................................................................4-1
Avalon-ST Interfaces in DSP IP Cores..........................................................................................4-2
FIR II IP Core Avalon-ST Interfaces.............................................................................................4-2
FIR II IP Core Signals......................................................................................................................4-8
FIR II IP Core Time-Division Multiplexing.......................................................................................... 4-11
FIR II IP Core Multichannel Operation................................................................................................. 4-12
Vectorized Inputs...........................................................................................................................4-12
Channelization............................................................................................................................... 4-13
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FIR II IP Core User Guide
TOC-3
Channel Input and Output Format.............................................................................................4-15
FIR II IP Core Multiple Coefficient Banks.............................................................................................4-20
FIR II IP Core Coefficient Reloading......................................................................................................4-21
Document Revision History................................................................................5-1
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2014.12.15
xin
yout
Z
-1
Z
-1
Z
-1
Z
-1
Tapped
Delay Line
Coefficient
Multipliers
Adder Tree
C
0
1
C
0
2
C
1
1
C
1
2
C
2
1
C
2
2
C
3
1
C
3
2
Coefficient
Banks
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About the FIR II IP Core
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The Altera® FIR II IP core provides a fully-integrated finite impulse response (FIR) filter function
optimized for use with Altera FPGA devices. The II IP core has an interactive parameter editor that allows
you to easily create custom FIR filters. The parameter editor outputs IP functional simulation model files
for use with Verilog HDL and VHDL simulators.
You can use the parameter editor to implement a variety of filter types, including single rate, decimation,
interpolation, and fractional rate filters.
Many digital systems use signal filtering to remove unwanted noise, to provide spectral shaping, or to
perform signal detection or analysis. FIR filters and infinite impulse response (IIR) filters provide these
functions. Typical filter applications include signal preconditioning, band selection, and low-pass
filtering.
Figure 1-1: Basic FIR Filter with Weighted Tapped Delay Line
To design a filter, identify coefficients that match the frequency response you specify for the system. These
coefficients determine the response of the filter. You can change which signal frequencies pass through
the filter by changing the coefficient values in the parameter editor.
Altera DSP IP Core Features
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
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FIR II IP Core Features
• Avalon® Streaming (Avalon-ST) interfaces
• DSP Builder ready
• Testbenches to verify the IP core
• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
FIR II IP Core Features
• Exploiting maximal designs efficiency through hardware optimizations such as:
• Interpolation
• Decimation
• Symmetry
• Decimation half-band
• Time sharing
• Easy system integration using Avalon Streaming (Avalon-ST) interfaces.
• Memory and multiplier trade-offs to balance the implementation between logic elements (LEs) and
memory blocks (M512, M4K, M9K, M10K, M20K, or M144K).
• Support for run-time coefficient reloading capability and multiple coefficient banks.
• User-selectable output precision via truncation, saturation, and rounding.
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DSP IP Core Device Family Support
Altera offers the following device support levels for Altera IP cores:
• Preliminary support—Altera verifies the IP core with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. You can use it in production designs with caution.
• Final support—Altera verifies the IP core with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family. You can use it in production
designs.
Table 1-1: DSP IP Core Device Family Support
Device Family Support
Arria® II GX Final
Arria II GZ Final
Arria V Final
Arria 10 Final
Cyclone® IV Final
Cyclone V Final
MAX® 10 FPGA Final
Stratix® IV GT Final
Stratix IV GX/E Final
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Device Family Support
Stratix V Final
Other device families No support
DSP IP Core Verification
Before releasing a version of an IP core, Altera runs comprehensive regression tests to verify its quality
and correctness. Altera generates custom variations of the IP core to exercise the various parameter
options and thoroughly simulates the resulting simulation models with the results verified against master
simulation models.
FIR II IP Core Release Information
Use the release information when licensing the IP core.
Table 1-2: Release Information
Item Description
DSP IP Core Verification
1-3
Version 14.1
Release Date December 2014
Ordering Code IP-FIRII
Product ID 00D8
Vendor ID 6AF7
Altera verifies that the current version of the Quartus II software compiles the previous version of each IP
core. Altera does not verify that the Quartus II software compiles IP core versions older than the previous
version. The Altera IP Release Notes lists any exceptions.
Related Information
• Altera IP Release Notes
• Errata for FIR II IP core in the Knowledge Base
FIR II IP Core Performance and Resource Utilization
Table 1-3: FIR II IP Core Performance—Arria V Devices
Typical expected performance using the Quartus II software with Arria V (5AGXFB3H4F40C4).
Parameters
ALM
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
DSP
Blocks
Memory Registers
f
MAX
(MHz)
8 2 Decimation — 1,607 24 0 — 1,232 64 30
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Parameters
ALM
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
DSP
Blocks
Memory Registers
8 2 Decimation Write 2,120 24 0 — 1,298 141 30
8 2 Fractional
— 1,395 16 0 — 2,074 99 28
Rate
8 2 Fractional
Write 1,745 16 0 — 2,171 91 28
Rate
8 2 Fractional
— 1,493 16 0 — 2,167 117 28
Rate
8 2 Fractional
Write 1,852 16 0 — 2,287 116 27
Rate
8 2 Interpolation — 1,841 32 0 — 2,429 52 28
8 2 Interpolation Write 1,994 32 0 — 2,826 41 27
8 2 Interpolation Multiple
2,001 32 0 — 2,737 74 27
banks
f
MAX
(MHz)
8
1
2
0
0
2
8
9
8 2 Interpolation Multiple
banks;
2,700 32 0 — 2,972 130 28
2
Write
8 2 Single rate — 932 20 0 — 318 20 27
8
8 2 Single rate Write 1,057 20 0 — 713 3 27
9
8 1 Decimation — 329 3 1 — 321 33 30
1
8 1 Decimation Write 430 3 1 — 366 34 30
7
8 1 Decimation Multiple
banks
8 1 Decimation Multiple
banks;
395 3 3 — 483 44 31
0
510 3 3 — 472 40 29
1
Write
8 1 Fractional
Rate
8 1 Fractional
Rate
— 661 5 4 — 877 75 31
0
Write 788 5 4 — 936 98 30
9
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FIR II IP Core Performance and Resource Utilization
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Parameters
ALM
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
DSP
Blocks
Memory Registers
8 1 Interpolation — 381 5 0 — 442 32 27
8 1 Interpolation Write 514 5 0 — 540 27 27
8 1 Single Rate — 493 10 0 — 191 20 27
8 1 Single Rate Write 633 10 0 — 588 1 27
1 — Decimation — 220 3 0 — 158 27 31
1 super
— Decimation — 404 20 0 — 400 41 30
sample
1 super
— Decimation Write 505 20 0 — 785 35 30
sample
1 — Decimation Write 318 3 0 — 208 26 30
f
MAX
(MHz)
8
8
8
8
0
5
8
9
1 Half
Band
1 Half
Band
1 — Fractional
1 — Fractional
1 Half
Band
1 Half
Band
— Decimation — 234 3 0 — 192 34 30
8
— Decimation Write 320 3 0 — 232 27 30
9
— 297 3 0 — 504 57 31
Rate
0
Write 391 3 0 — 563 56 31
Rate
— Fractional
Rate
— Fractional
Rate
— 196 2 0 — 251 5 27
Write 266 2 0 — 301 15 28
0
7
0
1 — Interpolation — 266 5 0 — 290 30 27
8
1 super
sample
1 super
sample
— Interpolation — 717 32 0 — 903 45 30
8
— Interpolation Write 842 32 0 — 1,281 48 30
8
1 — Interpolation Write 405 5 0 — 380 15 27
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FIR II IP Core Performance and Resource Utilization
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Parameters
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
1 Half
— Interpolation — 254 3 0 — 293 8 31
ALM
DSP
Blocks
Memory Registers
Band
1 Half
— Interpolation Write 333 4 0 — 314 10 30
Band
1 — Single rate — 93 10 0 — 129 27 29
1 super
— Single rate — 262 20 0 — 307 41 30
sample
1 super
— Single rate Write 373 20 0 — 687 40 30
sample
1 — Single rate Write 228 10 0 — 519 16 30
1 Half
— Single rate — 189 5 0 — 254 63 30
Band
1 Half
— Single rate Write 272 5 0 — 496 29 31
Band
f
MAX
(MHz)
0
9
9
9
2
0
9
0
1 — Single rate Multiple
109 10 0 — 199 29 28
banks
1 — Single rate Multiple
395 10 0 — 361 19 28
banks;
Write
Table 1-4: FIR II IP Core Performance—Cyclone V Devices
Typical expected performance using the Quartus II software with Cyclone V (5CGXFC7D6F31C6) devices.
Parameters
ALM
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
DSP
Blocks
Memory Registers
8 2 Decimation — 1,607 24 0 — 1,231 46 27
8 2 Decimation Write 2,092 24 0 — 1,352 63 27
8 2 Fractional
— 1,852 16 0 — 3,551 309 25
Rate
8 2 Fractional
Write 2,203 16 0 — 3,675 269 25
Rate
3
2
f
MAX
(MHz)
3
3
4
5
8 2 Fractional
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Rate
— 1,951 16 0 — 3,543 421 22
7
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FIR II IP Core Performance and Resource Utilization
1-7
Parameters
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
8 2 Fractional
Write 2,301 16 0 — 3,601 476 25
ALM
DSP
Blocks
Memory Registers
Rate
8 2 Interpolation — 1,840 32 0 — 2,431 48 25
8 2 Interpolation Write 1,988 32 0 — 2,813 57 25
8 2 Interpolation Multiple
2,006 32 0 — 2,711 98 25
banks
8 2 Interpolation Multiple
2,704 32 0 — 2,990 100 25
banks;
Write
8 2 Single rate — 934 20 0 — 317 19 25
8 2 Single rate Write 1,053 20 0 — 704 12 25
8 1 Decimation — 474 3 1 — 541 50 27
f
MAX
(MHz)
0
5
2
3
0
2
1
5
8 1 Decimation Write 559 3 1 — 574 58 27
3
8 1 Decimation Multiple
banks
8 1 Decimation Multiple
banks;
544 3 3 — 691 83 27
5
636 3 3 — 677 82 27
5
Write
8 1 Fractional
Rate
8 1 Fractional
Rate
— 1,165 5 4 — 1,715 205 27
5
Write 1,287 5 4 — 1,770 198 27
5
8 1 Interpolation — 381 5 0 — 433 42 24
8
8 1 Interpolation Write 513 5 0 — 540 26 25
0
8 1 Single Rate — 493 10 0 — 191 18 24
9
8 1 Single Rate Write 624 10 0 — 563 26 25
1
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FIR II IP Core Performance and Resource Utilization
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Parameters
ALM
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
DSP
Blocks
Memory Registers
1 — Decimation — 219 3 0 — 159 23 28
1 super
— Decimation — 404 20 0 — 398 43 28
sample
1 super
— Decimation Write 503 20 0 — 774 46 25
sample
1 — Decimation Write 312 3 0 — 208 26 28
1 Half
— Decimation — 234 3 0 — 192 29 28
Band
1 Half
— Decimation Write 323 3 0 — 228 32 28
Band
1 — Fractional
— 422 3 0 — 723 94 31
Rate
1 — Fractional
Write 516 3 0 — 787 86 29
Rate
f
MAX
(MHz)
9
8
6
9
9
8
0
2
1 Half
Band
1 Half
Band
— Fractional
Rate
— Fractional
Rate
— 195 2 0 — 251 12 26
1
Write 267 2 0 — 299 15 25
2
1 — Interpolation — 262 5 0 — 296 25 25
2
1 super
sample
1 super
sample
— Interpolation — 708 32 0 — 914 34 27
2
— Interpolation Write 841 32 0 — 1,297 32 25
9
1 — Interpolation Write 400 5 0 — 382 12 25
8
1 Half
Band
1 Half
Band
— Interpolation — 288 3 0 — 456 13 29
0
— Interpolation Write 331 4 0 — 315 9 29
0
1 — Single rate — 87 10 0 — 142 14 25
3
1 super
sample
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— Single rate — 258 20 0 — 315 33 26
0
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FIR II IP Core Performance and Resource Utilization
1-9
Parameters
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
1 super
— Single rate Write 369 20 0 — 704 23 27
ALM
DSP
Blocks
Memory Registers
sample
1 — Single rate Write 227 10 0 — 535 0 25
1 Half
— Single rate — 187 5 0 — 273 44 28
Band
1 Half
— Single rate Write 274 5 0 — 506 19 27
Band
1 — Single rate Multiple
110 10 0 — 187 41 25
banks
1 — Single rate Multiple
375 10 0 — 349 32 25
banks;
Write
Table 1-5: FIR II IP Core Performance—Stratix V Devices
Typical expected performance using the Quartus II software with Stratix V (5SGSMD4H2F35C2) devices.
Parameters
ALM
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
DSP
Blocks
Memory Registers
f
MAX
(MHz)
4
1
8
5
5
5
f
MAX
(MHz)
8 2 Decimation — 1,609 24 — 0 1,231 60 45
0
8 2 Decimation Write 2,319 24 — 0 2,077 66 45
0
8 2 Fractional
Rate
8 2 Fractional
Rate
8 2 Fractional
Rate
8 2 Fractional
Rate
— 1,350 16 — 0 2,099 88 44
8
Write 1,771 16 — 0 2,291 78 45
0
— 1,457 16 — 0 2,213 88 44
4
Write 1,873 16 — 0 2,418 89 45
0
8 2 Interpolation — 1,777 32 — 0 2,303 15 44
4
8 2 Interpolation Write 2,081 32 — 0 3,009 26 45
0
8 2 Interpolation Multiple
banks
1,825 32 — 0 2,473 39 43
0
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FIR II IP Core Performance and Resource Utilization
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Parameters
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
8 2 Interpolation Multiple
ALM
2,652 32 — 0 2,842 236 42
DSP
Blocks
Memory Registers
banks;
Write
8 2 Single rate — 920 20 — 0 332 2 44
8 2 Single rate Write 1,359 20 — 0 1,323 1 45
8 1 Decimation — 340 3 — 0 324 25 45
8 1 Decimation Write 463 3 — 0 457 29 45
8 1 Decimation Multiple
466 3 — 0 569 42 45
banks
8 1 Decimation Multiple
577 3 — 0 567 41 45
banks;
Write
f
MAX
(MHz)
4
4
0
0
0
0
0
8 1 Fractional
Rate
8 1 Fractional
Rate
— 709 5 — 0 870 45 45
0
Write 852 5 — 0 991 65 45
0
8 1 Interpolation — 216 5 — 0 197 13 45
0
8 1 Interpolation Write 361 5 — 0 290 22 45
0
8 1 Single Rate — 483 10 — 0 212 4 44
7
8 1 Single Rate Write 783 10 — 0 894 4 45
0
1 — Decimation — 215 3 — 0 175 10 45
0
1 super
sample
1 super
sample
— Decimation — 547 20 — 0 1,167 88 45
0
— Decimation Write 989 20 — 0 2,214 105 45
0
1 — Decimation Write 331 3 — 0 310 7 45
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FIR II IP Core Performance and Resource Utilization
1-11
Parameters
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
1 Half
— Decimation — 226 3 — 0 206 16 45
ALM
DSP
Blocks
Memory Registers
Band
1 Half
— Decimation Write 343 3 — 0 327 18 45
Band
1 — Fractional
— 252 3 — 0 318 21 44
Rate
1 — Fractional
Write 353 3 — 0 380 13 45
Rate
1 Half
Band
1 Half
Band
— Fractional
Rate
— Fractional
Rate
— 140 2 — 0 185 13 45
Write 214 2 — 0 235 21 45
1 — Interpolation — 168 5 — 0 127 19 45
1 super
— Interpolation — 573 32 — 0 1,084 51 44
sample
f
MAX
(MHz)
0
0
5
0
0
0
0
6
1 super
sample
— Interpolation Write 870 32 — 0 1,774 136 45
0
1 — Interpolation Write 313 5 — 0 196 5 45
0
1 Half
Band
1 Half
Band
— Interpolation — 253 3 — 0 292 9 45
0
— Interpolation Write 370 4 — 0 418 9 45
0
1 — Single rate — 226 10 — 0 706 31 44
7
1 _
ssample
1 _
ssample
— Single rate — 468 20 — 0 1,354 53 45
0
— Single rate Write 927 20 — 0 2,267 203 45
0
1 — Single rate Write 524 10 — 0 1,391 31 50
0
1 Half
Band
— Single rate — 195 5 — 0 270 50 45
0
1 Half
Band
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— Single rate Write 351 5 — 0 645 28 45
0
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Parameters
ALM
Channel Wires Filter Type Coefficients M10K M20K Primary Secondary
1 — Single rate Multiple
250 10 — 0 716 93 44
DSP
Blocks
Memory Registers
banks
1 — Single rate Multiple
671 10 — 0 1,228 50 45
banks;
Write
f
MAX
(MHz)
9
0
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acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
<IP core name> - Contains the IP core source files
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FIR II IP Core Getting Started
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1.
Installing and Licensing IP Cores
The Altera IP Library provides many useful IP core functions for your production use without purchasing
an additional license. Some Altera MegaCore® IP functions require that you purchase a separate license
for production use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulation
and compilation in the Quartus® II software. After you are satisfied with functionality and perfformance,
visit the Self Service Licensing Center to obtain a license number for any Altera product.
Figure 2-1: IP Core Installation Path
Note:
The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is
<home directory>/altera/ <version number>.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
OpenCore Plus IP Evaluation
Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and
hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take
your design to production. OpenCore Plus supports the following evaluations:
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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FIR II IP Core OpenCore Plus Timeout Behavior
• Simulate the behavior of a licensed IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming files for designs that include IP cores.
• Program a device with your IP core and verify your design in hardware.
OpenCore Plus evaluation supports the following two operation modes:
• Untethered—run the design containing the licensed IP for a limited time.
• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a
connection between your board and the host computer.
Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times
out.
FIR II IP Core OpenCore Plus Timeout Behavior
All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If
there is more than one IP core in a design, the time-out behavior of the other IP cores may mask the timeout behavior of a specific IP core .
All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If
there is more than one IP core in a design, a specific IP core's time-out behavior may be masked by the
time-out behavior of the other IP cores. For IP cores, the untethered time-out is 1 hour; the tethered timeout value is indefinite. Your design stops working after the hardware evaluation time expires. The Quartus
II software uses OpenCore Plus Files (.ocp) in your project directory to identify your use of the OpenCore
Plus evaluation program. After you activate the feature, do not delete these files..
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When the evaluation time expires, the ast_source_data signal goes low.
Related Information
• AN 320: OpenCore Plus Evaluation of Megafunctions
IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and
integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,
and generate files representing your custom IP variation.
Note:
The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.
The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch the
parameter editor and generate files representing your IP variation. The parameter editor prompts you to
specify an IP variation name, optional ports, and output file generation options. The parameter editor
generates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your
project. You can also parameterize an IP variation without an open project.
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Search for installed IP cores
Double-click to customize, right-click for
detailed information
Show IP only for target device
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Specifying IP Core Parameters and Options
Use the following features to help you quickly locate and select an IP core:
• Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no
project open, select the Device Family in IP Catalog.
• Type in the Search field to locate any full or partial IP core name in IP Catalog.
• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's
installation folder, and view links to documentation.
• Click Search for Partner IP, to access partner IP information on the Altera website.
Figure 2-2: Quartus II IP Catalog
2-3
Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes
exclusive system interconnect, video and image processing, and other system-level IP that are not
available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer
to Creating a System with Qsys in the Quartus II Handbook.
Specifying IP Core Parameters and Options
You can quickly configure a custom IP variation in the parameter editor. Use the following steps to
specify IP core options and parameters in the parameter editor. Refer to Specifying IP Core Parameters
and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.
FIR II IP Core Getting Started
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