Altera FIR Compiler User Manual

FIR Compiler

User Guide

c The FIR Compiler is scheduled for product obsolescence and discontinued support as

described in PDN1306. Therefore, Altera does not recommend use of this IP in new
designs. For more information about Altera’s current IP offering, refer to Altera’s

Intellectual Property website.

101 Innovation Drive
San Jose, CA 95134
www.altera.com

Software Version: 11.0
Document Date: May 2011

Copyright © 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap­plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services

.

UG-FIRCOMPILER 11.0

Contents

Chapter 1. About the FIR Compiler

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6

Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6

Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8

OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8

OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9

Chapter 2. Getting Started

Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

DSP Builder Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

MegaWizard Plug-In Manager Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Parameterize the MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Generate the MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

Simulating in ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

Simulating in MATLAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Simulating in Third-Party Simulation Tools Using NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Compile the Design and Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Chapter 3. Parameter Settings

Specifying the Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Using the FIR Compiler Coefficient Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Loading Coefficients from a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Analyzing the Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Specify the Input and Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Specify the Architecture Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11

Resource Estimates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

Filter Design Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

Chapter 4. Functional Description

FIR Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Number Systems and Fixed-Point Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Generating or Importing Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Coefficient Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Symmetrical Architecture Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Symmetrical Serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Coefficient Reloading and Reordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

Structure Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

Multicycle Variable Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

Parallel Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

Serial Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

Multibit Serial Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

Multichannel Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

© May 2011 Altera Corporation FIR Compiler User Guide

iv Contents

Interpolation and Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

Implementation Details for Interpolation and Decimation Structures . . . . . . . . . . . . . . . . . . . . . 4–10

Availability of Interpolation and Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

Half-Band Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

Symmetric-Interpolation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

Simulation Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13

Avalon Streaming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13

Avalon-ST Data Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

Packet Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15

Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

Reset and Global Clock Enable Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18

Single Rate Filter Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18

Interpolation Filter Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20

Decimation Filter Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21

Coefficient Reloading Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22

Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

Appendix A. FIR Compiler Supported Device Structures

Supported Device Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Support for HardCopy Series Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Compiling HardCopy Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Additional Information

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

FIR Compiler User Guide © May 2011 Altera Corporation

1. About the FIR Compiler

FEC

Reed Solomon

Encoder

Convolutional

Encoder

(Viterbi)

Constellation

Mapper

Outer Encoding Layer

Output
Data

Input
Data

NCO

Compiler

DAC

FIR Compiler

N

LPF

FIR Compiler

N

LPF

Convolutional

Interleaver

Inner Coding Layer

I

Q

This document describes the Altera® FIR Compiler. The Altera FIR Compiler provides
a fully integrated finite impulse response (FIR) filter development environment
optimized for use with Altera FPGA devices.

You can use the Altera IP Toolbench interface with the Altera FIR Compiler to
implement a variety of filter architectures, including fully parallel, serial, or multibit
serial distributed arithmetic, and multicycle fixed/variable filters. The FIR Compiler
includes a coefficient generator.

Traditionally, designers have been forced to make a trade-off between the flexibility of
digital signal processors and the performance of ASICs and application-specific
standard product (ASSPs) digital signal processing (DSP) solutions. The Altera DSP
solution reduces the need for this trade-off by providing exceptional performance
combined with the flexibility of FPGAs.

Figure 1–1 shows a typical DSP system that uses Altera IP cores, including the FIR

Compiler and other DSP IP cores.

Figure 1–1. Typical Modulator System

Many digital systems use signal filtering to remove unwanted noise, to provide
spectral shaping, or to perform signal detection or analysis. Two types of filters that
provide these functions are finite impulse response (FIR) filters and infinite impulse
response (IIR) filters. Typical filter applications include signal preconditioning, band
selection, and low-pass filtering.

In contrast to IIR filters, FIR filters have a linear phase and inherent stability. This
benefit makes FIR filters attractive enough to be designed into a large number of
systems. However, for a given frequency response, FIR filters are a higher order than
IIR filters, making FIR filters more computationally expensive.

© May 2011 Altera Corporation FIR Compiler User Guide

1–2 Chapter 1: About the FIR Compiler

xin

yout

Z

-1

Z

-1

Z

-1

Z

-1

C

0

C

1

C

2

C

3

Tapped
Delay Line

Coefficient
Multipliers

Adder Tree

The structure of a FIR filter is a weighted, tapped delay line as shown in Figure 1–2.

Figure 1–2. Basic FIR Filter

The filter design process involves identifying coefficients that match the frequency
response specified for the system. These coefficients determine the response of the
filter. You can change the signal frequencies that pass through the filter by changing
the coefficient values or adding more coefficients.

DSP processors have a limited number of multiply accumulators (MACs), and require
many clock cycles to compute each output value (the number of cycles is directly
related to the order of the filter).

A dedicated hardware solution can achieve one output per clock cycle. A fully
parallel, pipelined FIR filter implemented in an FPGA can operate at very high data
rates, making FPGAs ideal for high-speed filtering applications.

Tab le 1– 1 compares resource usage and performance for different implementations of

a 120-tap FIR filter with a 12-bit data input bus.

Table 1–1. FIR Filter Implementation Comparison (Note 1)

Clock Cycles to

Device Implementation

Compute Result

DSP processor 1 MAC 120

FPGA 1 serial filter 12

1 parallel filter 1

Note to Tab le 1– 1:

(1) If you use the FIR Compiler to create a filter, you can also implement a variable filter in a FPGA that uses from 1

to 120 MACs, and 120 to 1 clock cycles.

The Altera FIR Compiler speeds the design cycle by:

■ Generating the coefficients needed to design custom FIR filters.

FIR Compiler User Guide © May 2011 Altera Corporation

■ Generating bit-accurate and clock-cycle-accurate FIR filter models (also known as

bit-true models) in the Verilog HDL and VHDL languages and in the MATLAB
environment.

Chapter 1: About the FIR Compiler 1–3

Features

■ Automatically generating the code required for the Quartus II software to

synthesize high-speed, area-efficient FIR filters of various architectures.

■ Generating a VHDL testbench for all architectures.

Figure 1–3 compares the design cycle using a FIR Compiler with a traditional

implementation.

Figure 1–3. Design Cycle Comparison

Traditional Flow

FIR Filter
Design
6 Weeks

Design Structural or Synthesizable

Define & Design Architectural

Blocks

Determine Behavioral

Characteristics of FIR Filter

Calculate Filter Coefficients

(MATLAB)

Determine Hardware Filter

Architecture

FIR Filter

Simulate

Synthesize & Place & Route

Area/Speed T radeoff

FIR Compiler Flow

Define & Design Architectural

Blocks

FIR Filter Design
1 Day

Specify Filter Characteristics

to FIR Compiler Megafunction

(FIR Compiler Assists in Area/

Speed T radeoff)

Simulate

Synthesize & Place & Route

Features

The Altera® FIR Compiler implements a finite impulse response (FIR) filter MegaCore
function and supports the following features:

■ The following hardware architectures are supported to enable optimal trade- offs

between logic, memory, DSP blocks, and performance:

■ Fully parallel distributed arithmetic

■ Fully serial distributed arithmetic

■ Multibit serial distributed arithmetic

■ Multicycle variable structures

■ Exploit maximal efficiency designs as a result of FIR Compiler hardware

optimizations such as interpolation, decimation, symmetry, decimation half-band,
and time sharing.

■ Easy system integration using Avalon

© May 2011 Altera Corporation FIR Compiler User Guide

®

Streaming (Avalon-ST) interfaces.

1–4 Chapter 1: About the FIR Compiler

■ Precision control of chip resource utilization:

■ Logic cells, M512, M4K, M-RAM, MLAB, M9K, or M144K for data storage.

■ M512, M4K, M9K, M20K, MLAB or logic cells for coefficient storage.

■ Includes a resource estimator.

■ Support for run-time coefficient reloading capability and multiple coefficient sets.

■ Includes a built-in coefficient generator to enable efficient design space

Release Information

exploration.

■ User-selectable output precision via rounding and saturation.

■ DSP Builder ready.

Release Information

Tab le 1– 2 provides information about this release of the Altera® FIR Compiler.

Table 1–2. FIR Compiler Release Information

Item Description

Version 11.0

Release Date May 2011

Ordering Code IP-FIR

Product ID 0012

Vendor ID 6AF7

f For more information about this release, refer to the MegaCore IP Library Release Notes

and Errata.

®

Altera verifies that the current version of the Quartus
previous version of each MegaCore

®

function. The MegaCore IP Library Release Notes

II software compiles the

and Errata report any exceptions to this verification. Altera does not verify

compilation with MegaCore function versions older than one release.

FIR Compiler User Guide © May 2011 Altera Corporation

Chapter 1: About the FIR Compiler 1–5

Device Family Support

Device Family Support

Tab le 1– 3 defines the device support levels for Altera IP cores.

Table 1–3. Altera IP Core Device Support Levels

FPGA Device Families HardCopy Device Families

Preliminary support—The IP core is verified with
preliminary timing models for this device family. The IPcore
meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be
used in production designs with caution.

Final support—The IP core is verified with final timing
models for this device family. The IP core meets all
functional and timing requirements for the device family and
can be used in production designs.

Tab le 1– 4 shows the level of support offered by the FIR Compiler to each Altera

device family.

HardCopy Companion—The IP core is verified with
preliminary timing models for the HardCopy companion
device. The IP core meets all functional requirements, but
might still be undergoing timing analysis for the HardCopy
device family. It can be used in production designs with
caution.

HardCopy Compilation—The IP core is verified with final
timing models for the HardCopy device family. The IP core
meets all functional and timing requirements for the device
family and can be used in production designs.

Table 1–4. Device Family Support

Device Family Support

™

Arria

GX Final

Arria II GX Final

Arria II GZ Final

®

Cyclone

Final

Cyclone II Final

Cyclone III Final

Cyclone III LS Final

Cyclone IV GX Final

HardCopy

®

II HardCopy Compilation

HardCopy III HardCopy Compilation

HardCopy IV E HardCopy Compilation

HardCopy IV GX HardCopy Compilation

®

Final

Stratix

Stratix II Final

Stratix II GX Final

Stratix

III Final

IV GT Final

Stratix

Stratix IV GX/E Final

Stratix V Preliminary

Stratix GX Final

Other device families No support

© May 2011 Altera Corporation FIR Compiler User Guide

1–6 Chapter 1: About the FIR Compiler

MegaCore Verification

MegaCore Verification

Before releasing an updated version of the FIR Compiler, Altera runs a comprehensive
regression test to verify its quality and correctness.

All features and architectures are tested by sweeping all parameter options and
verifying that the simulation matches a master functional model.

Performance and Resource Utilization

This section shows typical expected performance for a FIR Compiler MegaCore
function with Cyclone III and Stratix IV devices. All figures are given for a FIR filter
with 97 taps, 8-bit input data, 14-bit coefficients, a target f

1 Cyclone III devices use combinational look-up tables (LUTs) and logic registers;

Stratix IV devices use combinational adaptive look-up tables (ALUTs) and logic
registers.

The resource and performance data was generated with the source ready signal
(ast_source_ready) always driven high, as described in “Avalon Streaming

Interface” on page 4–13.

set to 1 GHz.

MAX

Tab le 1– 5 shows performance figures for Cyclone III devices:

Table 1–5. FIR Compiler Performance—Cyclone III Devices (Part 1 of 2)

Memory (6)

Combinational

LUTs

Multibit Serial, pipeline level 1 (2), (3)

899 1,331 55,148 31 — 310 62 6

Multicycle variable (1 cycle) decimation by 4, pipeline level 1 (2), (3)

857 1,336 1,158 12 26 281 281 27

Multicycle variable (1 cycle) interpolation by 4, pipeline level 2 (4)

1,528 2,657 66 1 50 290 290 28

Multicycle variable (1 cycle), pipeline level 2 (2), (4)

2,543 4,837 92 1 98 280 280 27

Multicycle variable (4 cycle), pipeline level 2 (2), (3)

1,182 1,715 578 9 26 283 71 7

Logic

Registers

Multipliers

(9x9)

f

max

(MHz)

Throughput

(MSPS)

Processing

Equivalent

(GMACs) (1)Bits M9K

FIR Compiler User Guide © May 2011 Altera Corporation

Chapter 1: About the FIR Compiler 1–7

Performance and Resource Utilization

Table 1–5. FIR Compiler Performance—Cyclone III Devices (Part 2 of 2)

Memory (6)

Combinational

LUTs

Logic

Registers

Multipliers

(9x9)

f

max

(MHz)

Throughput

(MSPS)

Parallel (LE), pipeline level 1(2), (3)

3,416 3,715 208 3 — 288 288 28

Parallel (M9K), pipeline level 1 (2), (5)

1,948 2,155 120,030 48 — 283 283 27

Serial (M9K), pipeline level 1 (2), (3)

327 462 14,167 8 — 323 36 3

Notes to Table 1–5:

(1) GMAC = giga multiply accumulates per second (1 giga = 1,000 million).
(2) This FIR filter takes advantage of symmetric coefficients.
(3) Using EP3C10F256C6 devices.
(4) Using EP3C16F484C6 devices.
(5) Using EP3C40F780C6 devices.
(6) It may be possible to significantly reduce memory utilization by setting a lower target f

MAX

.

Tab le 1– 6 shows performance figures for Stratix IV devices:

Table 1–6. FIR Compiler Performance—Stratix IV Devices

Memory

Combinational

ALUTs

Logic

Registers

Multipliers

(18x18)

f

max

(MHz)

Throughput

(MSPS)

Multibit Serial, pipeline level 1 (2), (3), (4)

766 1,166 55,276 42 16 — 503 101 10

Multicycle variable (1 cycle) decimation by 4, pipeline level 1 (2), (3)

336 844 1,400 16 28 14 443 443 43

Multicycle variable (1 cycle) interpolation by 4, pipeline level 2 (3)

200 1,274 64 — 8 24 372 372 36

Multicycle variable (1 cycle), pipeline level 2 (2), (3)

741 1,936 148 1 8 48 443 443 43

Multicycle variable (4 cycle), pipeline level 2 (2), (3)

717 1,398 796 6 36 14 323 81 8

Parallel (LE), pipeline level 1 (2), (3)

2,153 2,672 157 1 8 — 421 421 41

Parallel (M9K), pipeline level 1 (3)

821 1,730 119,872 45 8 — 457 457 44

Serial (M9K), pipeline level 1 (2), (3)

245 415 14,231 11 8 — 523 58 6

Notes to Table 1–6:

(1) GMAC = giga multiply accumulates per second (1 giga = 1,000 million).
(2) This FIR filter takes advantage of symmetric coefficients.
(3) Using EP4SGX70DF29C2X devices.
(4) The data width is 16-bits and there are 4 serial units.

Processing

Equivalent

(GMACs) (1)Bits M9K

Processing

Equivalent

(GMACS) (1)Bits (M9K) ALUTs

© May 2011 Altera Corporation FIR Compiler User Guide

1–8 Chapter 1: About the FIR Compiler

Installation and Licensing

Installation and Licensing

The FIR Compiler MegaCore function is part of the MegaCore® IP Library, which is
distributed with the Quartus

www.altera.com.

f For system requirements and installation instructions, refer to the Altera Software

Installation and Licensing manual.

Figure 1–4 shows the directory structure after you install the FIR Compiler, where

<path> is the installation directory for the Quartus II software. The default installation
directory on Windows is c:\altera\<version> and on Linux is /opt/altera<version>.

Figure 1–4. Directory Structure

<path>

Installation directory.

ip

Contains the Altera MegaCore IP Library and third-party IP cores.

altera

Contains the Altera MegaCore IP Library.

®

II software and downloadable from the Altera® website,

OpenCore Plus Evaluation

With Altera’s free OpenCore Plus evaluation feature, you can perform the following
actions:

■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP

megafunction) within your system.

■ Verify the functionality of your design, as well as evaluate its size and speed

quickly and easily.

■ Generate time-limited device programming files for designs that include

megafunctions.

■ Program a device and verify your design in hardware.

You only need to purchase a license for the FIR Compiler when you are completely
satisfied with its functionality and performance, and want to take your design to
production.

common

Contains shared components.

fir_compiler

Contains the FIR Compiler MegaCore function files.

lib

Contains encrypted lower-level design files.

misc

Contains the coef_seq program which calculates and re-orders coefficients for reloading.

SM

After you purchase a license, you can request a license file from the Altera website at
www.altera.com/licensing and install it on your computer. When you request a
license file, Altera emails you a license.dat file. If you do not have Internet access,
contact your local Altera representative.

FIR Compiler User Guide © May 2011 Altera Corporation

Chapter 1: About the FIR Compiler 1–9

Installation and Licensing

f For more information about OpenCore Plus hardware evaluation, refer to

AN320: OpenCore Plus Evaluation of Megafunctions.

OpenCore Plus Time-Out Behavior

OpenCore Plus hardware evaluation supports the following operation modes:

■ Untethered—the design runs for a limited time.

■ Tethered—requires a connection between your board and the host computer. If

tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely.

All megafunctions in a device time-out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction’s time-out behavior might be masked by the time-out behavior
of the other megafunctions.

The untethered timeout for the FIR Compiler MegaCore function is one hour; the
tethered timeout value is indefinite.

The data output signal is forced to zero when the hardware evaluation time expires.

© May 2011 Altera Corporation FIR Compiler User Guide

1–10 Chapter 1: About the FIR Compiler

Installation and Licensing

FIR Compiler User Guide © May 2011 Altera Corporation

Design Flows

2. Getting Started

The FIR Compiler MegaCore® function supports the following design flows:

■ DSP Builder: Use this flow if you want to create a DSP Builder model that

includes a FIR Compiler MegaCore function variation.

■ MegaWizard™ Plug-In Manager: Use this flow if you would like to create a FIR

Compiler MegaCore function variation that you can instantiate manually in your
design.

This chapter describes how you can use a FIR Compiler MegaCore function in either
of these flows. The parameterization is the same in each flow and is described in

Chapter 3, Parameter Settings.

After parameterizing and simulating a design in either of these flows, you can
compile the completed design in the Quartus II software.

DSP Builder Flow

Altera’s DSP Builder product shortens digital signal processing (DSP) design cycles
by helping you create the hardware representation of a DSP design in an algorithm­friendly development environment.

DSP Builder integrates the algorithm development, simulation, and verification
capabilities of The MathWorks MATLAB
with Altera Quartus
can combine existing Simulink blocks with Altera DSP Builder blocks and MegaCore
function variation blocks to verify system level specifications and perform simulation.

In DSP Builder, a Simulink symbol for the FIR Compiler appears in the MegaCore
Functions library of the Altera DSP Builder Blockset in the Simulink library browser.

You can use the FIR Compiler in the MATLAB/Simulink environment by performing
the following steps:

1. Create a new Simulink model.

2. Select the FIR Compiler block from the MegaCore Functions library in the

3. Double-click the FIR Compiler block in your model to display IP Toolbench and

®

and Simulink® system-level design tools

®

II software and third-party synthesis and simulation tools. You

Simulink Library Browser, add it to your model, and give the block a unique
name.

click Step 1: Parameterize to parameterize a FIR Compiler MegaCore function
variation. For an example of how to set parameters for the FIR Compiler block,
refer to Chapter 3, Parameter Settings.

4. Click Step 2: Generate in IP Toolbench to generate your FIR Compiler MegaCore
function variation. For information about the generated files, refer to Tab le 2– 1 on

page 2–6.

5. Connect your FIR Compiler MegaCore function variation block to the other
blocks in your model.

© May 2011 Altera Corporation FIR Compiler User Guide

2–2 Chapter 2: Getting Started

MegaWizard Plug-In Manager Flow

6. Simulate the FIR Compiler MegaCore function variation in your DSP Builder
model.

f For more information about the DSP Builder flow, refer to the Using MegaCore

Functions chapter in the DSP Builder User Guide.

1 When you are using the DSP Builder flow, device selection, simulation, Quartus II

compilation and device programming are all controlled within the DSP Builder
environment.

DSP Builder supports integration with SOPC Builder using Avalon
(Avalon-MM) master or slave, and Avalon Streaming (Avalon-ST) source or sink
interfaces.

f For more information about these interface types, refer to the Avalon Interface

Specifications.

MegaWizard Plug-In Manager Flow

The MegaWizard Plug-in Manager flow allows you to customize a FIR Compiler
MegaCore function, and manually integrate the MegaCore function variation into a
Quartus II design.

To launch the MegaWizard Plug-in Manager, perform the following steps:

1. Create a new project using the New Project Wizard available from the File menu
in the Quartus II software.

2. Launch MegaWizard Plug-in Manager from the Tools menu, and select the option
to create a new custom megafunction variation (Figure 2–1).

Figure 2–1. MegaWizard Plug-In Manager

®

Memory-Mapped

3. Click Next and select FIR Compiler <version> from the DSP>Filters section in the
Installed Plug-Ins tab. (Figure 2–2).

FIR Compiler User Guide © May 2011 Altera Corporation

Chapter 2: Getting Started 2–3

MegaWizard Plug-In Manager Flow

Figure 2–2. Selecting the MegaCore Function

4. Verify that the device family is the same as you specified in the New Project
Wizard.

5. Select the top-level output file type for your design; the wizard supports VHDL
and Verilog HDL.

6. Specify the top level output file name for your MegaCore function variation and
click Next to launch IP Toolbench (Figure 2–3 on page 2–4).

Parameterize the MegaCore Function

To parameterize your MegaCore function variation, perform the following steps:

1. Click Step 1: Parameterize in IP Toolbench to display the Parameterize - FIR
Compiler window. Use this interface to specify the required parameters for the
MegaCore function variation. For an example of how to set parameters for the FIR
Compiler MegaCore function, refer to Chapter 3, Parameter Settings.

© May 2011 Altera Corporation FIR Compiler User Guide

2–4 Chapter 2: Getting Started

MegaWizard Plug-In Manager Flow

Figure 2–3. IP Toolbench—Parameterize

2. Click Step 2: Setup Simulation in IP Toolbench to display the Set Up Simulation -
FIR Compiler page (Figure 2–4).

Figure 2–4. Set Up Simulation

3. Turn on Generate Simulation Model to create an IP functional model.

1 An IP functional simulation model is a cycle-accurate VHDL or Verilog

HDL model produced by the Quartus II software.

FIR Compiler User Guide © May 2011 Altera Corporation

Chapter 2: Getting Started 2–5

MegaWizard Plug-In Manager Flow

c Use the simulation models only for simulation and not for synthesis or any

other purposes. Using these models for synthesis creates a non-functional
design.

4. Select the required language from the Language list.

5. Click the MATLAB M-File tab on the Set Up Simulation page (Figure 2–5).

6. Turn on the Generate MathWorks MATLAB M-File option.

This option generates a MATLAB m-file script that contains functions you can use
to analyze a FIR Compiler design in the MATLAB environment. A testbench is also
generated.

Figure 2–5. Create a MATLAB M-File

7. Click Finish.

1 The Quartus II Testbench tab contains an option that is not used in this version of the

FIR Compiler and should be ignored.

© May 2011 Altera Corporation FIR Compiler User Guide

2–6 Chapter 2: Getting Started

MegaWizard Plug-In Manager Flow

Generate the MegaCore Function

To generate your MegaCore function variation, perform the following steps:

1. Click Step 3: Generate in IP Toolbench to generate your MegaCore function
variation and supporting files. The generation phase may take several minutes to
complete. The generation progress and status is displayed in a report window.

Figure 2–6 shows the generation report.

Figure 2–6. Generation Report - FIR Compiler MegaCore Function

Tab le 2– 1 describes the IP Toolbench-generated files and other files that may be in

your project directory. The names and types of files specified in the report vary
based on whether you created your design with VHDL or Verilog HDL.

Table 2–1. Generated Files (Part 1 of 2) (Note 1) ,(2)

Filename Description

<entity name>.vhd A VHDL wrapper file for the Avalon-ST interface.

<variation name>.bsf A Quartus II block symbol file for the MegaCore function variation. You can use this

file in the Quartus II block diagram editor.

<variation name>.cmp A VHDL component declaration file for the MegaCore function variation. Add the

contents of this file to any VHDL architecture that instantiates the MegaCore function.

<variation name>.html A MegaCore function report file in hypertext markup language format.

<variation name>.qip A single Quartus II IP file is generated that contains all of the assignments and other

information required to process your MegaCore function variation in the Quartus II
compiler. You are prompted to add this file to the current Quartus II project when you
exit from IP Toolbench.

FIR Compiler User Guide © May 2011 Altera Corporation

Chapter 2: Getting Started 2–7

MegaWizard Plug-In Manager Flow

Table 2–1. Generated Files (Part 2 of 2) (Note 1) ,(2)

Filename Description

<variation name>.vec Quartus II vector file. This file provides simulation test vectors to be used for

simulating the customized FIR MegaCore function variation with the Quartus II
software.

<variation name>.vhd or .v A VHDL or Verilog HDL file that defines a VHDL or Verilog HDL top-level description

of the custom MegaCore function variation. Instantiate the entity defined by this file
inside of your design. Include this file when compiling your design in the Quartus II
software.

<variation name>.vho or .vo A VHDL or Verilog HDL output file that defines the IP functional simulation model.

<variation name>_bb.v A Verilog HDL black-box file for the MegaCore function variation. Use this file when

using a third-party EDA tool to synthesize your design.

<variation name>_coef_in_mlab.txt

Text files that provides coefficient inputs for the MATLAB testbench model.

<variation name>_coef_int.txt

<variation name>_coef_n_inv.hex

<variation name>_coef_n.hex

<variation name>_zero.hex

Memory initialization files in INTEL Hex format. These files are required both for
simulation with IP functional simulation models and synthesis using the Quartus II
software.

<variation name>_constraints.tcl Constraints setting Tcl file for Quartus II synthesis. This file contains the necessary

constraints to achieve FIR Filter size and speed.

<variation name>_input.txt This text file provides simulation data for the MATLAB model and the simulation

testbench.

<variation name>_mlab.m This MATLAB M-File provides the kernel of the MATLAB simulation model for the

customized FIR MegaCore function variation.

<variation name>_model.m This MATLAB M-File provides a MATLAB simulation model for the customized FIR

MegaCore function variation.

<variation name>_msim.tcl This Tcl script can be used to simulate the VHDL testbench together with the

simulation model of the customized FIR MegaCore function variation.

<variation name>_nativelink.tcl A Tcl script that can be used to assign NativeLink simulation testbench settings to the

Quartus II project.

<variation name>_param.txt This text file records all output parameters for customized FIR MegaCore function

variation.

<variation name>_silent_param.txt This text file records all input parameters for customized FIR MegaCore function

variation.

<variation name>_core.vhd

<variation name>_st.v

Generated FIR Filter netlists. These files are required for Quartus II synthesis and are
added to your current Quartus II project.

<variation name>_st_s.v

<variation name>_st_u.v

<variation name>_st_wr.v

tb_<variation name>.vhd This VHDL file provides

a testbench for the customized FIR MegaCore function

variation.

Notes to Table 2–1

(1) <variation name> is a prefix variation name supplied automatically by IP Toolbench.
(2) The <entity name> prefix is added automatically. The VHDL code for each MegaCore instance is generated dynamically when you click Finish

so that the <entity name> is different for every instance. It is generated from the <variation name> by appending _ast.

© May 2011 Altera Corporation FIR Compiler User Guide

2–8 Chapter 2: Getting Started

MegaWizard Plug-In Manager Flow

The generation report also lists the ports defined in the MegaCore function
variation file (Figure 2–7). For a full description of the signals supported on
external ports for your MegaCore function variation, refer to Table 4–3 on

page 4–16.

Figure 2–7. Port Lists in the Generation Report

2. After you review the generation report, click Exit to close IP Toolbench. Then click

Simulate the Design

To simulate your design in Verilog HDL or VHDL, use the IP functional simulation
models generated by IP Toolbench.

The IP functional simulation model is the .vo or .vho file (located in your design
directory) generated as specified in Step 1 on page 2–3.

f For more information about IP functional simulation models, refer to the Simulating

Altera Designs chapter in volume 3 of the Quartus II Handbook.

Simulating in ModelSim

A Tcl script (<variation name>_msim.tcl) is also generated which can be used to load
the VHDL testbench into the ModelSim simulator.

This script uses the file <variation name>_input.txt to provide input data to the FIR
filter. The output from the simulation is stored in a file <variation name>_output.txt.

Yes on the Quartus II IP Files prompt to add the .qip file describing your custom
MegaCore function variation to the current Quartus II project.

FIR Compiler User Guide © May 2011 Altera Corporation

Chapter 2: Getting Started 2–9

MegaWizard Plug-In Manager Flow

Simulating in MATLAB

To simulate in a MATLAB environment, run the <variation_name>_model.m testbench
m-script, which also is located in your design directory. This script also uses the file
<variation name>_input.txt to provide input data. The output from the MATLAB
simulation is stored in the file <variation name>_model_output.txt.

For MCV decimation filters, the <variation name>_model_output_full.txt file is
generated to display all the phases of the filter. You can compare this file with the
<variation name>_output.txt file to understand which phase the output belongs. For
all other architectures, decimation filters provide the Nth phase where N is the
decimation factor.

Simulating in Third-Party Simulation Tools Using NativeLink

You can perform a simulation in a third-party simulation tool from within the
Quartus II software, using NativeLink.

The Tcl script file <variation name>_nativelink.tcl can be used to assign default
NativeLink testbench settings to the Quartus II project.

To perform a simulation in the Quartus II software using NativeLink, perform the
following steps:

1. Create a custom MegaCore function variation as described earlier in this chapter
but ensure you specify your variation name to match the Quartus II project name.

2. Verify that the absolute path to your third-party EDA tool is set in the Options
page under the Tools menu in the Quartus II software.

3. On the Processing menu, point to Start and click Start Analysis & Elaboration.

4. On the Tools menu, click Tcl scripts. In the Tcl Scripts dialog box, select
<variation name>_nativelink.tcl and click Run. Check for a message confirming
that the Tcl script was successfully loaded.

5. On the Assignments menu, click Settings, expand EDA Tool Settings, and select
Simulation. Select a simulator under Too l n am e then in NativeLink Settings,
select Compile test bench and click Test Benches.

6. On the Tools menu, point to EDA Simulation Tool and click Run EDA RTL
Simulation.

The Quartus II software selects the simulator, and compiles the Altera libraries,
design files, and testbenches. The testbench runs and the waveform window
shows the design signals for analysis.

f For more information, refer to the Simulating Altera Designs chapter in volume 3 of the

Quartus II Handbook.

Compile the Design and Program a Device

You can use the Quartus II software to compile your design.

After you have compiled your design, program your targeted Altera device and
verify your design in hardware.

f For instructions on compiling and programming your design, and more information

about the MegaWizard Plug-In Manager flow, refer to the Quartus II Help.

© May 2011 Altera Corporation FIR Compiler User Guide