Altera FFT MegaCore Function User Manual
FFT IP Core
User Guide
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TOC-2
Contents
About This IP Core..............................................................................................1-1
FFT IP Core Getting Started...............................................................................2-1
Altera DSP IP Core Features...................................................................................................................... 1-1
FFT IP Core Features...................................................................................................................................1-1
General Description.....................................................................................................................................1-2
Fixed Transform Size FFT.............................................................................................................. 1-2
Variable Streaming FFT..................................................................................................................1-2
DSP IP Core Device Family Support.........................................................................................................1-2
DSP IP Core Verification............................................................................................................................1-3
FFT IP Core Release Information..............................................................................................................1-3
Performance and Resource Utilization.....................................................................................................1-4
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................ 2-1
FFT II IP Core OpenCore Plus Timeout Behavior..................................................................... 2-2
IP Catalog and Parameter Editor...............................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-3
Files Generated for Altera IP Cores...............................................................................................2-4
Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-7
DSP Builder Design Flow............................................................................................................................2-8
FFT IP Core Functional Description..................................................................3-1
Fixed Transform FFTs.................................................................................................................................3-1
Variable Streaming FFTs............................................................................................................................ 3-1
Fixed-Point Variable Streaming FFTs...........................................................................................3-2
Floating-Point Variable Streaming FFTs......................................................................................3-2
Input and Output Orders................................................................................................................3-2
FFT Processor Engines................................................................................................................................3-3
Quad-Output FFT Engine.............................................................................................................. 3-3
Single-Output FFT Engine..............................................................................................................3-4
I/O Data Flow...............................................................................................................................................3-5
Streaming FFT..................................................................................................................................3-5
Variable Streaming.......................................................................................................................... 3-7
Buffered Burst.................................................................................................................................3-11
Burst.................................................................................................................................................3-13
FFT IP Core Parameters........................................................................................................................... 3-14
FFT IP Core Interfaces and Signals.........................................................................................................3-16
Avalon-ST Interfaces in DSP IP Cores....................................................................................... 3-16
FFT IP Core Avalon-ST Signals...................................................................................................3-17
FFT IP Core Signals in Qsys Systems..........................................................................................3-19
Altera Corporation
TOC-3
Block Floating Point Scaling...............................................................................4-1
Possible Exponent Values...........................................................................................................................4-2
Implementing Scaling..................................................................................................................................4-3
Example of Scaling...........................................................................................................................4-3
Unity Gain in an IFFT+FFT Pair...............................................................................................................4-5
Document Revision History................................................................................5-1
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About This IP Core
1
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Altera DSP IP Core Features
• Avalon® Streaming (Avalon-ST) interfaces
• DSP Builder ready
• Testbenches to verify the IP core
• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
FFT IP Core Features
• Bit-accurate MATLAB models
• Variable streaming FFT:
• Single-precision floating-point or fixed-point representation
• Radix-4, mixed radix-4/2 implementations (for floating-point FFT), and radix-22 single delay
feedback implementation (for fixed-point FFT)
• Input and output orders: natural order, bit-reversed or digit-reversed, and DC-centered (-N/2 to
N/2)
• Reduced memory requirements
• Support for 8 to 32-bit data and twiddle width (foxed-point FFTs)
• Fixed transform size FFT that implements block floating-point FFTs and maintains the maximum
dynamic range of data during processing (not for variable streaming FFTs)
• Multiple I/O data flow options: streaming, buffered burst, and burst
• Uses embedded memory
• Maximum system clock frequency more than 300 MHz
• Optimized to use Stratix series DSP blocks and TriMatrix memory
• High throughput quad-output radix 4 FFT engine
• Support for multiple single-output and quad-output engines in parallel
• User control over optimization in DSP blocks or in speed in Stratix V devices, for streaming, buffered
burst, burst, and variable streaming fixed-point FFTs
• Avalon Streaming (Avalon-ST) compliant input and output interfaces
• Parameterization-specific VHDL and Verilog HDL testbench generation
• Transform direction (FFT/IFFT) specifiable on a per-block basis
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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1-2
General Description
General Description
The FFT IP core is a high performance, highly-parameterizable Fast Fourier transform (FFT) processor.
The FFT IP core implements a complex FFT or inverse FFT (IFFT) for high-performance applications.
The FFT MegaCore function implements:
• Fixed transform size FFT
• Variable streaming FFT
Fixed Transform Size FFT
The fixed transform FFT implements a radix-2/4 decimation-in-frequency (DIF) FFT fixed-transform
size algorithm for transform lengths of 2m where 6 ≤ m ≤16. This FFT uses block-floating point
representations to achieve the best trade-off between maximum signal-to-noise ratio (SNR) and
minimum size requirements.
The fixed transform FFT accepts a two's complement format complex data vector of length N inputs,
where N is the desired transform length in natural order. The function outputs the transform-domain
complex vector in natural order. The FFT produces an accumulated block exponent to indicate any data
scaling that has occurred during the transform to maintain precision and maximize the internal signal-tonoise ratio. You can specify the transform direction on a per-block basis using an input port.
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Variable Streaming FFT
The variable streaming FFT implements two different types of FFT. The variable streaming FFTs
implement either a radix-22 single delay feedback FFT, using a fixed-point representation, or a mixed
radix-4/2 FFT, using a single precision floating point representation. After you select your FFT type, you
can configure your FFT variation during runtime to perform the FFT algorithm for transform lengths of
2m where 3 ≤ m ≤18.
The fixed-point representation grows the data widths naturally from input through to output thereby
maintaining a high SNR at the output. The single precision floating-point representation allows a large
dynamic range of values to be represented while maintaining a high SNR at the output.
The order of the input data vector of size N can be natural, bit- or digit-reversed, or -N/2 to N/2 (DCcentered). The fixed-point representation supports a natural, bit-reversed, or DC-centered order and the
floating point representation supports a natural, digit-reversed order. The FFT outputs the transformdomain complex vector in natural, bit-reversed, or digit-reversed order. You can specify the transform
direction on a per-block basis using an input port.
DSP IP Core Device Family Support
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Altera® offers the following device support levels for Altera IP cores:
• Preliminary support—Altera verifies the IP core with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. You can use it in production designs with caution.
• Final support—Altera verifies the IP core with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family. You can use it in production
designs.
Table 1-1: DSP IP Core Device Family Support
Device Family Support
Arria® II GX Final
Arria II GZ Final
Arria V Final
Arria 10 Final
Cyclone® IV Final
Cyclone V Final
MAX® 10 FPGA Final
DSP IP Core Verification
1-3
Stratix® IV GT Final
Stratix IV GX/E Final
Stratix V Final
Other device families No support
DSP IP Core Verification
Before releasing a version of an IP core, Altera runs comprehensive regression tests to verify its quality
and correctness. Altera generates custom variations of the IP core to exercise the various parameter
options and thoroughly simulates the resulting simulation models with the results verified against master
simulation models.
FFT IP Core Release Information
Table 1-2: FFT IP Core Release Information
Item Description
Version 14.1
Release Date December 2014
Ordering Code IP-FFT
Product ID 0034
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Performance and Resource Utilization
Item Description
Vendor ID 6AF7
Performance and Resource Utilization
Table 1-3: Performance and Resource Utilization
Typical performance using the Quartus II software with the Arria V (5AGXFB3H4F40C4), Cyclone V
(5CGXFC7D6F31C6), and Stratix V (5SGSMD4H2F35C2) devices
Device
Parameters
Type Length Engines M10K M20K PrimarySecondar
ALM
DSP
Blocks
Memory Registers
y
f
MAX
(MHz)
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ArriaVBuffered
Burst
ArriaVBuffered
Burst
ArriaVBuffered
Burst
ArriaVBuffered
Burst
ArriaVBuffered
Burst
ArriaVBuffered
Burst
ArriaVBuffered
Burst
ArriaVBuffered
Burst
ArriaVBuffered
Burst
ArriaVBurst
Quad
Output
1,024 1 1,572 6 16 -- 3,903 143 27
5
1,024 2 2,512 12 30 -- 6,027 272 27
4
1,024 4 4,485 24 59 -- 10,765 426 26
2
256 1 1,532 6 16 -- 3,713 136 27
5
256 2 2,459 12 30 -- 5,829 246 24
5
256 4 4,405 24 59 -- 10,539 389 26
0
4,096 1 1,627 6 59 -- 4,085 130 27
5
4,096 2 2,555 12 59 -- 6,244 252 27
5
4,096 4 4,526 24 59 -- 10,986 438 26
5
1,024 1 1,565 6 8 -- 3,807 147 27
3
ArriaVBurst
ArriaVBurst
ArriaVBurst
Altera Corporation
Quad
Output
Quad
Output
Quad
Output
1,024 2 2,497 12 14 -- 5,952 225 27
5
1,024 4 4,461 24 27 -- 10,677 347 25
7
256 1 1,527 6 8 -- 3,610 153 27
2
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Performance and Resource Utilization
1-5
Device
ArriaVBurst
ArriaVBurst
ArriaVBurst
ArriaVBurst
ArriaVBurst
ArriaVBurst
Parameters
Type Length Engines M10K M20K PrimarySecondar
ALM
DSP
Blocks
Memory Registers
256 2 2,474 12 14 -- 5,768 233 27
Quad
Output
256 4 4,403 24 27 -- 10,443 437 25
Quad
Output
4,096 1 1,597 6 27 -- 3,949 151 27
Quad
Output
4,096 2 2,551 12 27 -- 6,119 223 27
Quad
Output
4,096 4 4,494 24 27 -- 10,844 392 25
Quad
Output
1,024 1 672 2 6 -- 1,488 101 27
Single
Output
f
MAX
y
(MHz)
5
7
5
5
6
5
ArriaVBurst
Single
1,024 2 994 4 10 -- 2,433 182 27
5
Output
ArriaVBurst
Single
256 1 636 2 3 -- 1,442 95 27
5
Output
ArriaVBurst
Single
256 2 969 4 8 -- 2,375 152 27
5
Output
ArriaVBurst
Single
4,096 1 702 2 19 -- 1,522 126 27
0
Output
ArriaVBurst
Single
4,096 2 1,001 4 25 -- 2,521 156 27
5
Output
ArriaVStreaming 1,024 — 1,880 6 20 -- 4,565 167 27
5
ArriaVStreaming 256 — 1,647 6 20 -- 3,838 137 27
5
ArriaVStreaming 4,096 — 1,819 6 71 -- 4,655 137 27
5
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Performance and Resource Utilization
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Device
ArriaVVariable
Streaming
Floating
Point
ArriaVVariable
Streaming
Floating
Point
ArriaVVariable
Streaming
Floating
Point
ArriaVVariable
Streaming
ArriaVVariable
Streaming
ArriaVVariable
Streaming
Parameters
Type Length Engines M10K M20K PrimarySecondar
ALM
DSP
Blocks
Memory Registers
y
1,024 — 11,195 48 89 -- 18,843 748 16
256 — 8,639 36 62 -- 15,127 609 16
4,096 — 13,947 60 138 -- 22,598 854 16
1,024 — 2,535 11 14 -- 6,269 179 22
256 — 1,913 8 8 -- 4,798 148 22
4,096 — 3,232 15 31 -- 7,762 285 21
f
MAX
(MHz)
3
1
2
3
9
0
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Buffered
Burst
Buffered
Burst
Buffered
Burst
Buffered
Burst
Buffered
Burst
Buffered
Burst
Buffered
Burst
1,024 1 1,599 6 16 -- 3,912 114 22
6
1,024 2 2,506 12 30 -- 6,078 199 21
9
1,024 4 4,505 24 59 -- 10,700 421 20
7
256 1 1,528 6 16 -- 3,713 115 22
7
256 2 2,452 12 30 -- 5,833 211 23
2
256 4 4,487 24 59 -- 10,483 424 22
1
4,096 1 1,649 6 59 -- 4,060 138 22
3
Cycl
one
V
Altera Corporation
Buffered
Burst
4,096 2 2,555 12 59 -- 6,254 199 22
7
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Performance and Resource Utilization
1-7
Device
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Parameters
Type Length Engines M10K M20K PrimarySecondar
Buffered
4,096 4 4,576 24 59 -- 10,980 377 21
ALM
DSP
Blocks
Memory Registers
Burst
Burst
1,024 1 1,562 6 8 -- 3,810 122 22
Quad
Output
Burst
1,024 2 2,501 12 14 -- 5,972 196 23
Quad
Output
Burst
1,024 4 4,480 24 27 -- 10,643 372 21
Quad
Output
Burst
256 1 1,534 6 8 -- 3,617 120 22
Quad
Output
Burst
256 2 2,444 12 14 -- 5,793 153 22
Quad
Output
f
MAX
y
(MHz)
4
5
1
6
6
4
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Burst
Quad
Output
Burst
Quad
Output
Burst
Quad
Output
Burst
Quad
Output
Burst
Single
Output
Burst
Single
Output
Burst
Single
Output
256 4 4,443 24 27 -- 10,402 379 22
3
4,096 1 1,590 6 27 -- 3,968 120 23
7
4,096 2 2,547 12 27 -- 6,135 209 22
7
4,096 4 4,512 24 27 -- 10,798 388 21
0
1,024 1 673 2 6 -- 1,508 83 22
2
1,024 2 984 4 10 -- 2,475 126 23
1
256 1 639 2 3 -- 1,382 159 22
9
Cycl
one
V
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Burst
Single
Output
256 2 967 4 8 -- 2,353 169 24
0
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Performance and Resource Utilization
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Device
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Parameters
Type Length Engines M10K M20K PrimarySecondar
Burst
4,096 1 695 2 19 -- 1,540 105 23
ALM
DSP
Blocks
Single
Memory Registers
(MHz)
y
7
Output
Burst
Single
4,096 2 1,009 4 25 -- 2,536 116 24
0
Output
Streaming 1,024 — 1,869 6 20 -- 4,573 132 21
1
Streaming 256 — 1,651 6 20 -- 3,878 85 22
6
Streaming 4,096 — 1,822 6 71 -- 4,673 124 19
9
Variable
Streaming
1,024 — 11,184 48 89 -- 18,830 628 13
3
Floating
Point
f
MAX
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Cycl
one
V
Strati
x V
Strati
x V
Variable
Streaming
Floating
Point
Variable
Streaming
Floating
Point
Variable
Streaming
Variable
Streaming
Variable
Streaming
Buffered
Burst
Buffered
Burst
256 — 8,611 36 62 -- 15,156 467 13
3
4,096 — 13,945 60 138 -- 22,615 701 13
2
1,024 — 2,533 11 14 -- 6,254 240 17
9
256 — 1,911 8 8 -- 4,786 176 18
0
4,096 — 3,226 15 31 -- 7,761 320 17
6
1,024 1 1,610 6 -- 16 4,141 107 42
4
1,024 2 2,545 12 -- 30 6,517 170 42
7
Strati
x V
Altera Corporation
Buffered
Burst
1,024 4 4,554 24 -- 59 11,687 250 36
6
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Performance and Resource Utilization
1-9
Device
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Parameters
Type Length Engines M10K M20K PrimarySecondar
Buffered
256 1 1,546 6 -- 16 3,959 110 49
ALM
DSP
Blocks
Memory Registers
Burst
Buffered
256 2 2,475 12 -- 30 6,314 134 44
Burst
Buffered
256 4 4,480 24 -- 59 11,477 281 38
Burst
Buffered
4,096 1 1,668 6 -- 30 4,312 122 43
Burst
Buffered
4,096 2 2,602 12 -- 30 6,718 176 41
Burst
Buffered
4,096 4 4,623 24 -- 59 11,876 249 39
Burst
Burst
1,024 1 1,550 6 -- 8 4,037 115 45
Quad
Output
Burst
1,024 2 2,444 12 -- 14 6,417 164 43
Quad
Output
f
MAX
y
(MHz)
3
0
3
2
6
2
5
3
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Burst
Quad
Output
Burst
Quad
Output
Burst
Quad
Output
Burst
Quad
Output
Burst
Quad
Output
Burst
Quad
Output
Burst
Quad
Output
1,024 4 4,397 24 -- 27 11,548 330 41
6
256 1 1,487 6 -- 8 3,868 83 47
7
256 2 2,387 12 -- 14 6,211 164 45
8
256 4 4,338 24 -- 27 11,360 307 40
9
4,096 1 1,593 6 -- 14 4,222 93 44
8
4,096 2 2,512 12 -- 14 6,588 154 47
0
4,096 4 4,468 24 -- 27 11,773 267 40
3
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Performance and Resource Utilization
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Device
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Parameters
Type Length Engines M10K M20K PrimarySecondar
Burst
1,024 1 652 2 -- 4 1,553 111 50
ALM
DSP
Blocks
Memory Registers
Single
Output
Burst
1,024 2 1,011 4 -- 8 2,687 149 47
Single
Output
Burst
256 1 621 2 -- 3 1,502 132 50
Single
Output
Burst
256 2 978 4 -- 8 2,555 173 50
Single
Output
Burst
4,096 1 681 2 -- 9 1,589 149 50
Single
Output
Burst
4,096 2 1,039 4 -- 14 2,755 161 47
Single
Output
f
MAX
y
(MHz)
0
6
0
0
0
6
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Strati
x V
Streaming 1,024 — 1,896 6 -- 20 4,814 144 49
0
Streaming 256 — 1,604 6 -- 20 4,062 99 44
9
Streaming 4,096 — 1,866 6 -- 38 4,889 118 46
1
Variable
Streaming
1,024 — 11,607 32 -- 87 19,031 974 35
5
Floating
Point
Variable
Streaming
256 — 8,850 24 -- 59 15,297 820 37
4
Floating
Point
Variable
Streaming
4,096 — 14,335 40 -- 115 22,839 1,047 32
5
Floating
Point
Variable
Streaming
Variable
Streaming
1,024 — 2,334 14 -- 13 5,623 201 38
2
256 — 1,801 10 -- 8 4,443 174 36
5
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1-11
Device
Strati
x V
Parameters
Type Length Engines M10K M20K PrimarySecondar
Variable
4,096 — 2,924 18 -- 23 6,818 238 35
ALM
DSP
Blocks
Memory Registers
Streaming
f
MAX
(MHz)
y
5
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acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
<IP core name> - Contains the IP core source files
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FFT IP Core Getting Started
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Installing and Licensing IP Cores
The Altera IP Library provides many useful IP core functions for your production use without purchasing
an additional license. Some Altera MegaCore® IP functions require that you purchase a separate license
for production use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulation
and compilation in the Quartus® II software. After you are satisfied with functionality and perfformance,
visit the Self Service Licensing Center to obtain a license number for any Altera product.
Figure 2-1: IP Core Installation Path
Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is
<home directory>/altera/ <version number>.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
OpenCore Plus IP Evaluation
Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and
hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take
your design to production. OpenCore Plus supports the following evaluations:
• Simulate the behavior of a licensed IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming files for designs that include IP cores.
• Program a device with your IP core and verify your design in hardware.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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