Altera EP2SGX90 User Manual

Stratix II GX EP2SGX90 Transceiver
Signal Integrity Development Board

101 Innovation Drive
San Jose, CA 95134
[phone]
www.altera.com

Reference Manual

Development Board Version: 1.0.0
Document Version: 1.0.0
Document Date: May 2006

Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des­ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al­tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap­plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in­formation and before placing orders for products or services.

Part Number MNL-S2GXSIDB-1.0

ii Development Board Version 1.0.0 Altera Corporation
Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board Reference Manual May 2006

Contents

About this Manual

Revision History ......................................................................................................................................... v

How to Contact Altera ............................................................................................................................... v

Typographic Conventions....................................................................................................................... vi

Chapter 1. Introduction

General Description................................................................................................................................ 1-1

Board Component Blocks................................................................................................................. 1-2

Block Diagram ................................................................................................................................... 1-3

Target Applications........................................................................................................................... 1-3

Data Rate & Clock Frequency Support Per Protocol ................................................................... 1-4

Handling the Board ................................................................................................................................ 1-4

Chapter 2. Board Components & Interfaces

Board Overview ...................................................................................................................................... 2-1

Featured Device ...................................................................................................................................... 2-6

Clocking Circuitry ................................................................................................................................. 2-7

Clock Buffer Functional Descriptions ............................................................................................ 2-9

ICS557-03 (U5): Spread Spectrum Clock Generator for PCI-Express ................................. 2-10

ICS8543 (U8): General Purpose 1:4 Differential Fanout Buffer ........................................... 2-11

ICS83023 (U7): Differential I/O to Single Converter for Trigger Clock ............................ 2-11

Interfaces ................................................................................................................................................ 2-12

SMA Connectors for High-Speed I/O ............................................................................................... 2-12

USB Interface ......................................................................................................................................... 2-14

General User Interfaces ........................................................................................................................ 2-16

Debug Header (J1) ........................................................................................................................... 2-16

LEDs (D1 Through D8) ................................................................................................................... 2-18

7-Segment Displays (D9, D10) ....................................................................................................... 2-19

Push-Button Switches (S1 Through S6) ........................................................................................ 2-21

DIP Switches (S7 and S8) ................................................................................................................ 2-22

Clock Selection Switches (S9 and S10) ......................................................................................... 2-24

Power Supply ....................................................................................................................................... 2-25

Thermal Management Block ............................................................................................................... 2-27

FPGA Configuration Block ................................................................................................................. 2-28

JTAG Configuration ........................................................................................................................ 2-28

Active Serial Configuration Using EPCS64 Device (U22) ......................................................... 2-28

Flash Memory ....................................................................................................................................... 2-30

Altera Corporation iii
May 2006 Preliminary

Contents Stratix II GX EP2GX90 Signal Integrity Development Board Reference Manual

iv Altera Corporation

Preliminary May 2006

About this Manual

Revision History

Chapter Date Version Changes Made

All May 2006 1.0.0 First publication

How to Contact Altera

Information Type USA & Canada All Other Locations

Technical support www.altera.com/mysupport/ www.altera.com/mysupport/

Product literature www.altera.com www.altera.com
Altera literature services [e-mail] [e-mail]
Non-technical customer

service

FTP site ftp.altera.com ftp.altera.com

The table below displays the revision history for the chapters in this
reference manual.

This reference manual provides comprehensive information about the

®

Altera

Stratix®II GX family of devices and the Stratix II GX EP2SGX90

transceiver signal integrity development board.

For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com. For technical support on
this product, go to www.altera.com/mysupport. For additional
information about Altera products, consult the sources shown below.

(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m. Pacific Time)

[phone] + 1 408-544-7000

[phone]
7:00 a.m. to 5:00 p.m. (GMT -8:00)
Pacific Time

7:00 a.m. to 5:00 p.m. (GMT -8:00)
Pacific Time

Altera Corporation v
May 2006 Preliminary

Typographic Conventions Stratix II GX EP2GX90 Signal Integrity Development Board Reference Manual

Typographic

This document uses the typographic conventions shown below.

Conventions

Visual Cue Meaning

Bold Type with Initial
Capital Letters

bold type External timing parameters, directory names, project names, disk drive names,

Italic Type with Initial Capital
Letters

Italic type Internal timing parameters and variables are shown in italic type.

Initial Capital Letters Keyboard ke ys and menu names are shown with initial capital letters. Examples:

“Subheading Title” References to sections within a document and titles of on-line help topics are

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,

1., 2., 3., and
a., b., c., etc.

● • Bullets are used in a list of items when the sequence of the items is not important.

■

v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.

c

w

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

Command names, dialog box titles, chec kbox options, and dialog bo x options are
shown in bold, initial capital letters. Example: Save As dialog box.

filenames, filename extensions, and software utility names are shown in bold
type. Examples: f

Document titles are shown in italic type with initial capital letters. Example: AN 75:

High-Speed Board Design.

Examples: t

Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.

Delete key, the Options menu.

shown in quotation marks. Example: “Typographic Conventions.”

PIA

, \qdesigns directory, d: drive, chiptrip.gdf file.

MAX

, n + 1.

tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For
example:
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword
Courier.

Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.

The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.

The warning indicates information that should be read prior to starting or
continuing the procedure or processes

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an

SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

vi Altera Corporation

Preliminary May 2006

1. Introduction

General Description

The Stratix®II GX EP2SGX90 transceiver signal integrity development
board provides a hardware platform for developing and prototyping
high-speed designs using power-efficient Stratix II GX devices. The
transceiver technology embedded in Stratix II GX devices ensures that
signal integrity extends to high frequencies while also providing a
power-efficient, single-chip solution that supports the following
high-speed serial protocols:

■ PCI-Express

■ CEI-6G

■ Gigabit Ethernet

■ XAUI

■ Serial RapidIO

■ SONET Backplane

■ SDI

■ SerialLite II

As board designs move into the Gbps space, it is increasingly more
difficult to maintain signal integrity. In fact, increasing data rates for both
I/O interfaces and memory interfaces can present significant data
transmission problems and performance issues.

The Stratix II GX device’s embedded transceivers provide enhanced
transmit pre-emphasis technology that conditions the signal prior to
transmission as well as programmable receiver equalization circuitry.
Also, because the Stratix II GX device’s embedded transceivers have
built-in clock data recovery, you do not have to route the clock and data
on the board, which greatly simplifies high-speed board designs.

™

®

To further simplify the process, Altera
use as either a design starting point or an experimental platform. The
reference design is designed and tested by Altera engineers and
distributed with the Transceiver SI Development Kit, Stratix II GX
Edition (ordering code: DK-SI-2SGX90N).

Altera Corporation Reference Manual 1–1
May 2006 Preliminary

provides a reference design for

General Description

Board Component Blocks

The board provides the following major component blocks:

■ Flexible clock management system

● Four high-speed clock oscillators to support a variety of

protocols:

• 156.25 MHz

• 25, 100, 125, and 200-MHz from the clock generator

• 50 MHz

● SMA connectors for clock input and output

■ High-speed I/O & SMA connectors

● SMA connectors for high-speed interfaces

● Six channels of transmit differential output and six channels of

receive differential input at up to 6.375 Gbps

■ Power-supply management

● 5-V, 3.3-V, and 1.2-V switching regulators

● 3.3-V and 1.5-V/1.2-V linear regulators

■ USB interface

● Operates like a COM port on a host PC

● Eliminates the need for:

• Full USB software and hardware implementation

• USB software driver

■ General user-interface

● Debugging header

● LEDs

● 7-Segment LEDs

● Push-buttons

● DIP switches

■ Thermal management

■ Flash memory

● 56-pin TSOP package

● Compliant with common Flash interface (CFI)

● Reduces development time when used with the Altera SOPC

Builder CFI controller module

■ FPGA configuration

● JTAG interface header

● Active serial configuration scheme using EPCS64 device

• Configures Stratix II GX device on power-up

1–2 Reference Manual Altera Corporation
Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006

Introduction

e

Block Diagram

Figure 1–1 shows a functional block diagram of the Stratix II GX

EP2SGX90 transceiver signal integrity development board.

Figure 1–1. Stratix II GX EP2SGX90 Transceiver Signal Integrity Development
Board Block Diagram

Power Supply

Management Block

with Switching &

Linear Regulators

Clock

Management

Unit

USB

Interface

SMA

Connectors

for High-Speed

Interfaces

Thermal

Management

Block

Active Serial

Configuration Using

EPCS64 Device

Stratix II GX

Device

JTAG

Configuration

Debugging
Header

LEDs

7-Segment Displays

Push Buttons
DIP Switches

Flash Memory

FPGA
Configuation
Block

General
User
Interfac
Block

Target Applications

The board is used for the following applications:

■ Demonstrating key StratixIIGX device features

■ Device qualification, e.g., jitter, pre-emphasis, equalization, and

signal integrity testing, as well as receiver sensitivity.

■ De-coupling Quartus

Altera MegaWizard
devices and interfaces included)

■ Demonstrating Stratix II GX device transceiver features

■ Characterization testing of high-speed serial interfaces

■ Interoperability testing between various devices via on-board SMA

connectors

■ Power supply evaluation (on-board regulation and banana jack

options)

®

II software, transceiver architecture, and

®

Plug-In Manager demonstrations (supporting

Altera Corporation Reference Manual 1–3
May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board

Handling the Board

■ Clocking evaluation to qualify the Stratix II GX device with user

clock sources

■ Demonstrate signal integrity features on a standalone basis

Data Rate & Clock Frequency Support Per Protocol

Table 1–1 shows the board’s data rate and clock frequency support per

protocol.

Table 1–1. Board Protocol Support

Handling the
Board

Protocol

6G - CEI 6.25 156.25 On board oscillator
5G scrambled 5 156.25 On board oscillator
4G FC, (1) 4.25 – SMA clock input
XAUI 3.125 156.25 On board oscillator
PCI-Express/PIPE 2.5 100 On board oscillator
SONET backplane 2.488 – SMA clock input
2G FC, (1) 2.125 – SMA clock input
HD - SDI 1.485 – SMA clock input
GIGE 1.25 125 On board oscillator
1G FC, (1) 1.063 – SMA clock input

Note to Ta b l e 1 – 1:

(1) There is no support planned for Fibre channel protocol. This table only shows

supported data rate.

Data Rate

(Gbps)

Clock

Frequency

(MHz)

Clock Source

When handling the board, it is important to observe the following
precaution:

w Static Discharge Precaution—Without proper anti-static

handling, the board can be damaged. Therefore, use anti-static
handling precautions when touching the board.

1–4 Reference Manual Altera Corporation
Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006

2. Board Components & Interfaces

Board Overview

f For information on powering-up the Stratix II GX transceiver signal

This chapter provides operational and connectivity detail for the board’s
major components and interfaces and is divided into the following major
blocks:

■ Featured device

■ Clocking circuitry

■ Interfaces

● SMA connectors for high-speed I/O

● USB interface

● General user interfaces

■ Power supply

■ Thermal management

■ FPGA configuration

■ Flash memory

1 Board schematics, the physical layout database, and

®

manufacturing files for the Stratix

II GX EP2SGX90 transceiver
signal integrity development board are included in the
Transceiver SI Development Kit, Stratix II GX Edition in the
following directory:

<install path>\SIIGX_SI_Kit-v1.0.0\Docs\BoardDesignFiles

integrity development board and installing the demo software, refer to
the Transceiver SI Development Kit, Stratix II GX Edition Getting Started
User Guide.

Altera Corporation Reference Manual 2–1
May 2006 Preliminary

Board Overview

Figure 2–1 shows the top view of the Stratix II GX EP2SGX90 transceiver

signal integrity development board.

Figure 2–1. Top View of the Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board

Temperature Sensor

with Alarm (U17)

Stratix II GX Device (U20)

SMA Transmit &

Receive Connectors

(J26 through J49)

SMA Output Clock Connectors

Reference Clock for Quad 1

Transceivers (J7, J8)

SMA Output Clock Connectors

Reference Clock for Quad 3

Transceivers (J9, J10)

Configuration
Done LED (D14)

156.25-MHz
Oscillator (U9)

50-MHz Oscillator

Used for System Clock (U10)

Optional Power Input

Connection Jacks (J15, J17-21)

25-MHz
Crystal (U6)

Differential

Fan-out

Buffer (U8)

Differential to
Single-Ended
Buffer (U7)

Clock
Generator (U5)

Switch (S9)

Clock
Setting
DIP Switch
Bank (S8)

Debug
Header (J1)

EPCS64 Device (U22)

Slide

Connectors for FPGA (J12, J14)

Jumper Header for

VCCH Voltage (J50)

User Push-Button
Switches (S1 through S6)

User LEDs
(D1 through D8)

SMA Input Clock

Power LED (D13)

10-pin Configuration Header
for EPCS64 Device (J23)

10-pin JTAG Configuration
Header for FPGA (J24)

Power Switch (S10)

Power Supply Input

Dual 7-Segment

Displays (D9, D10)

USB Interface (U2)

USB Connector (J2)

16 Mbytes Flash
Memory (U19)

User DIP Switch
Bank (S7)

2–2 Reference Manual Altera Corporation
Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006