The pin connection guidelines in the device pin-out are considered preliminary. These pin connection guidelines should only be used as a recommendation, not as a specification.
The use of the pin connection guidelines for any particular design should be verified for device operation, with the datasheet and Altera.
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(1) The optional functions (e.g. LVDS, DDR) are not available for some pins in certain packages.
For example, for the EP2C8 device, the LVDS70 pair is available for the Q208 and F256 packages, but not for the T144 package.
(2) The DQS0T, DQS1T, DQS0B, and DQS1B pin functions are only available in the F672 and F896 packages.
(3) If the dedicated CLK pins are not used to feed the global clock networks, they can be used as general-purpose input pins to feed the core logic.
The dedicated CLK pins do not support the I/O register.
Pin Type (1st, 2nd, and
3rd Function)Pin DescriptionConnection Guidelines
Power
Ground
I/O
Power
Power
Ground
Ground
Input (PS)
Output (AS)
Input
Input
Input
Bidirectional
(open-drain)
Pin Information for the Cyclone® II EP2C5 Device
These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers
used for the LVPECL, LVDS (regular I/O and CLK pins), differential HSTL, and differential SSTL I/O
standards.
These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage
level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to
the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, 3.3-V PCI, and 3.3-V PCI-X,
differential SSTL, differential HSTL, and LVDS (regular I/O) I/O standards.
Device ground pins. Connect all GND pins to the board GND plane.
Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then
these pins are used as the voltage-referenced pins for the bank.
Analog power for PLLs[1..4].
Digital power for PLLs[1..4].
Analog ground for PLLs[1..4].
Ground for PLLs[1..4]. Connect these pins to the GND plane on the board.
No ConnectDo not drive signals into these pins.
Dedicated configuration clock pin. In PS configuration, DCLK is used to clock configuration data from
an external source into the Cyclone II device. In AS mode, DCLK is an output from the Cyclone II
device that provides timing for the configuration interface. The input buffer on this pin supports
hysteresis using the Schmitt trigger circuitry.
Dedicated configuration data input pin. In serial configuration modes, bit-wide configuration data is
received through this pin. In AS mode, DATA0 has an internal pull-up resistor that is always active.
The input buffer on this pin supports hysteresis using the Schmitt trigger circuitry.
Configuration input pins that set the Cyclone II device configuration scheme.
Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the
device is disabled. The input buffer on this pin supports hysteresis using the Schmitt trigger circuitry.
Dedicated configuration control input. Pulling this pin low during user mode causes the FPGA to lose
its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high
level initiates reconfiguration. The input buffer on this pin supports hysteresis using the Schmitt trigger
circuitry.
This is a dedicated configuration status pin. As a status output, the CONF_DONE pin drives low
before and during configuration. Once all configuration data is received without error and the
initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after
all data is received. Then the device initializes and enters user mode. It is not available as a user I/O
pin. The input buffer on this pin supports hysteresis using the Schmitt trigger circuitry.
Supply and Reference Pins
Dedicated Configuration/JTAG Pins
Connect all VCCINT pins to 1.2 V. Decoupling depends on the design decoupling requirements
of the specific board. (Note 2)
Verify that the VCCIO voltage level connected is consistent with the .pin report from the
®
Quartus
II software. Decoupling depends on the design decoupling requirements of the specific
board. (Note 2)
If voltage-referenced I/O standards are not used in the bank, the VREF pins are available as
user I/O pins. Decoupling depends on the design decoupling requirements of the specific board.
(Note 2)
Connect these pins to 1.2 V, even if the PLL is not used. Use an isolated linear supply for better
jitter performance. You can connect all VCCA_PLL pins to a single linear supply to minimize
cost. Power on the PLLs should be decoupled. Decoupling depends on the design decoupling
requirements of the specific board (Note 2). For more information on this pin, refer to the PLLs in Cyclone II Devices chapter in the Cyclone II Device Handbook.
Connect these pins to the quietest digital supply on board (1.2 V), which is also supplied to the
VCCINT, even if the PLL is not used. Power on the PLLs should be decoupled. Decoupling
depends on the design decoupling requirements of the specific board (Note 2) . For more
information on this pin, refer to the PLLs in Cyclone II Devices chapter in the Cyclone II Device
Handbook.
Connect these pins directly to the same ground plane as the digital ground of the device, even if
the PLL is not used. For more information on this pin, refer to the PLLs in Cyclone II Devices
chapter in the Cyclone II Device Handbook.
DCLK should not be left floating. You should drive it high or low, whichever is more convenient
on the board.
DATA0 should not be left floating. You should drive it high or low, whichever is more convenient
on the board.
These pins must be hardwired to VCCIO of the bank they reside in or GND. Do not leave these
pins floating. When these pins are unused, connect them to GND. For MSEL pin settings for
different configuration schemes, refer to the Configuring Cyclone II Devices chapter in the
Cyclone II Device Handbook.
In a multi-device configuration, nCE of the first device is tied low while its nCEO pin drives the
nCE of the next device in the chain. In a single-device configuration, nCE is tied low.
nCONFIG should be pulled high by an external 10-k pull-up resistor to a 3.3-V supply. If the
configuration scheme uses an enhanced configuration device or EPC2, nCONFIG can be tied
directly to the nINIT_CONF pin of the configuration device. If this pin is not used, this pin can be
connected through a resistor to VCCIO.
CONF_DONE should be pulled high by an external 10-k pull-up resistor to a 3.3-V supply. If
internal pull-up resistors on the enhanced configuration device are used, external 10-k pull-up
resistors should not be used on this pin.
Pin Type (1st, 2nd, and
3rd Function)Pin DescriptionConnection Guidelines
Bidirectional
(open-drain)
Input
Input
Input
Output
Clock, Input
Clock, Input
I/O, Output
I/O, Output
I/O (when option off),
Input (when option on)
I/O (when option off),
Input (when option on)
I/O, Output
(open-drain)
Pin Information for the Cyclone® II EP2C5 Device
ersion 2.0
This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after powerup and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs
during configuration. As a status input, the device enters an error state when nSTATUS is driven low
by an external source during configuration or initialization. It is not available as a user I/O pin. The
input buffer on this pin supports hysteresis using the Schmitt trigger circuitry.nSTATUS should be pulled high by an external 10-k pull-up resistor to a 3.3-V supply.
Dedicated JTAG clock input pin. This pin has weak internal pull-down resistors. The input buffer on
this pin supports hysteresis using the Schmitt trigger circuitry.
Dedicated JTAG input pin that provides the control signal to determine the transitions of the TAP
controller state machine. This pin has weak internal pull-up resistors. The input buffer on this pin
supports hysteresis using the Schmitt trigger circuitry.
weak internal pull-up resistors. The input buffer on this pin supports hysteresis using the Schmitt
trigger circuitry.
Dedicated JTAG data output pin for instructions, and test and programming data.
Dedicated global clock input pins that can also be used for the positive terminal inputs for differential
global clock input or user input pins.Connect unused pins to GND.
Dedicated global clock input pins that can also be used for the negative terminal inputs for differential
global clock input or user input pins.Connect unused pins to GND.
Optional positive terminal for external clock outputs from PLLs[1..4]. These pins can only use the
differential I/O standard if it is being fed by a PLL output.
Optional negative terminal for external clock outputs from PLLs[1..4]. These pins can only use the
differential I/O standard if it is being fed by a PLL output.
Output that drives low when device configuration is complete.
Output control signal from the Cyclone II FPGA to the nCS pin of the serial configuration device in AS
mode that enables the configuration device by driving it low. In AS mode, the nCSO has internal weak
pull-up resistor, which is always active.
Output control signal from the Cyclone II FPGA to the serial configuration device in AS mode used to
read out configuration data. In AS mode, the ASDO has internal weak pull-up resistor, which is alway
active.
Active-high signal that indicates the error-detection circuit has detected errors in the configuration
SRAM bits. This pin is optional and is used when the CRC error-detection circuit is enabled.
Optional chip-wide reset pin that allows you to override all clears on all device registers. When this pin
is driven low, all registers are cleared; when this pin is driven high, all registers behave as
programmed. The DEV_CLRn pin does not affect JTAG boundary-scan or programming operations.
This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option in the Quartus II
software.
Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O
pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. This pin is
enabled by turning on the Enable device-wide output enable (DEV_OE) option in the Quartus II
software.
This is a dual-purpose status pin and can be used as an I/O pin when not enabled as INIT_DONE.
When enabled, a transition from low to high at the pin indicates when the device has entered user
mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after
configuration. This pin is enabled by turning on the Enable INIT_DONE output option in the Quartus II
software.
Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is
not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin. This pin is
enabled by turning on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II
software.
Connect this pin to GND via a 1-k resistor. If the JTAG circuitry is not used, connect TCK to
GND.
Connect this pin to a 1-k resistor via the VCCIO of the bank it resides in. If the JTAG circuitry is
not used, connect TMS to VCCIO.
Connect this pin to a 1-k resistor via the VCCIO of the bank it resides in. If the JTAG circuitry is
not used, connect TDI to VCCIO.
When not in JTAG mode, this pin should be left unconnected.
When not used as PLL output pins, these pins can be used as user I/O pins. When these pins
are not used, they may be left floating.
When not used as PLL output pins, these pins can be used as user I/O pins. When these pins
are not used, they may be left floating.
During a multi-device configuration, this pin feeds the nCE pin of a subsequent device and must
be pulled high to VCCIO by an external 10-k pull-up resistor. During a single-device
configuration and for the last device in a multi-device configuration, this pin can be left
unconnected or used as an user I/O after configuration.
When not programming the device in AS mode, the nCSO pin can be used as user I/O. When
this pin is not used as an I/O, Altera recommends that you leave the pin unconnected.
When not programming the device in AS mode, the ASDO pin can be used as user I/O. When
this pin is not used as an I/O, Altera recommends that you leave the pin unconnected.
When the dedicated output for CRC_ERROR is not used and this pin is not used as an I/O,
Altera recommends that you leave the pin unconnected.
When the dedicated output for DEV_CLRn is not used and this pin is not used as an I/O, Altera
recommends that you tie this pin to the VCCIO of the bank that it resides in or ground. (Note 6)
When the dedicated output for DEV_OE is not used and this pin is not used as an I/O, Altera
recommends that you tie this pin to the VCCIO of the bank that it resides in or ground. (Note 6)
When INIT_DONE is enabled, connect this pin to a 10-k resistor via the VCCIO of the bank
that it resides in.
If the CLKUSR pin is not used as a configuration clock input and the pin is not used as an I/O,
Altera recommends that you connect this pin to ground.
Altera provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.
Pin Type (1st, 2nd, and
3rd Function)Pin DescriptionConnection Guidelines
Dual-purpose differential transmitter/receiver channels 0 to 256. These channels can be used for
transmitting or receiving LVDS-compatible signals. Pins with a "p" suffix carry the positive signal for
I/O, TX/RX channel
I/O, DPCLK/DQS
I/O, CDPCLK/DQS
I/O, DQ
I/O, DQ
I/O, DM
I/O, DM
I/O, BWS
I/O, BWS
the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If
not used for differential signaling, these pins are available as user I/O pins.
Dual-purpose DPCLK/DQS pins can connect to the global clock network for high-fanout control
signals such as clocks, asynchronous clears, presets, and clock enables. It can also be used as
optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS
phase-shift circuitry, which allows for the fine-tuning of the phase shift for input clocks or strobes to
properly align clock edges needed to capture data.
Dual-purpose CDPCLK/DQS pins can connect to the global clock network for high-fanout control
signals such as clocks, asynchronous clears, presets, and clock enables. Only one of the two
CDPCLK in each corner can feed the clock control block at a time. The other pin can be used as a
general-purpose I/O pin. The CDPCLK signals incur more delay to the clock block control because
they are multiplexed before being driven into the clock block control. It can also be used as optional
data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phaseshift circuitry, which allows for the fine-tuning of the phase shift for input clocks or strobes to properly
align clock edges needed to capture data.
Optional data signal for use in external memory interfacing in the x16 or x18 modes.
Optional data signal for use in external memory interfacing in the x8 or x9 modes.
Optional data mask pins for x8/x9 modes are required when writing to DDR SDRAM and DDR2
SDRAM devices. A low signal indicates that the write is valid. If the DM signal is high, the memory
masks the DQ signals. Each group of DQ and DQS signals requires a DM pin.
Optional data mask pins for x16/x18 modes are required when writing to DDR SDRAM and DDR2
SDRAM devices. A low signal indicates that the write is valid. If the DM signal is high, the memory
masks the DQ signals. Each group of DQ and DQS signals requires a DM pin.
Byte Write Select is an active-low pin. When asserted active, BWS selects which byte is written into
the device during write operation. Bytes not written remain unchanged. Deselecting BWS causes writ
data to be ignored and not written into device.
Byte Write Select is an active-low pin. When asserted active, BWS selects which byte is written into
the device during write operation. Bytes not written remain unchanged. Deselecting BWS causes writ
data to be ignored and not written into device.
When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or
GND. (Note 6)
When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or
GND. (Note 6)
When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or
GND. (Note 6)
When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or
GND. (Note 6)
When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or
GND. (Note 6)
When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or
GND. (Note 6)
When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or
GND. (Note 6)
When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or
GND. (Note 6)
When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or
GND. (Note 6)
Pin Information for the Cyclone® II EP2C5 Device
ersion 2.0
Note
Notes:
1) These pin connection guidelines are created based on the largest Cyclone II device, EP2C70F896. Refer to the pin list for the availability of pins in each density.
2) Capacitance values for the power supply should be selected after considering the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on
current draw and voltage droop requirements of the device or supply. The power plane should then be decoupled using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the
mounting of the packages. Proper board design techniques such as interplaning capacitance with low inductance should be considered for higher frequency decoupling.
3) The differential transmitter/receiver channel count for each device and package is different; smaller packages may contain less than the maximum number of differential transmitter/receiver channels. For details on the differential transmitter/receiver channel count for
each device, refer to the corresponding pin-out from www.altera.com.
4) The EP2C5, EP2C8, and EP2C8A devices have only PLL1 and PLL2.
5) The DQ, DQS, DM, and BWS# bus mode count for each device and package is different. Smaller packages may contain less than the maximum number of DQ, DQS, DM, and BWS# bus modes. For details on the DQ, DQS, DM, and BWS# bus mode count for each
device, refer to the corresponding pin-out from www.altera.com.
6) Make sure that unused pins are set to input tristated in the Quartus II software. For instructions on how to set this, refer to the Quartus II Handbook.
1.22/24/2005Modified Pin Definitions for DATA0 pin
1.35/3/2005Added CRC_ERROR pin in Pin List and Pin Definition
Changed pin name from GNDD_PLL and GNDG_PLL to GND_PLL
Finalize
1.46/2/2005Modified Pin Type column in Pin Definitions for VREFB[1..8]N[0..1] pins
1.57/28/2005Modified LVDS naming in Pin List:
LVDS12p/n to LVDS22p/n
LVDS22p/n to LVDS21p/n
LVDS21p/n to LVDS20p/n
LVDS20p/n to LVDS19p/n
LVDS19p/n to LVDS18p/n
LVDS18p/n to LVDS17p/n
LVDS11p/n to LVDS16p/n
LVDS17p/n to LVDS15p/n
LVDS10p/n to LVDS14p/n
LVDS16p/n to LVDS13p/n
LVDS15p/n to LVDS12p/n
LVDS14p/n to LVDS11p/n
LVDS13p/n to LVDS10p/n
1.62/10/2006Added footnote for pins that do not support Optional Functions (LVDS, DDR, etc)
Added footnote for DQS0T, DQS1T, DQS0B and DQS1B pins
Modified Pin Description of NC pins
Modified Pin Description of VREFB[1..4]N[0..1] pins
Modified Pin Description of VCCA_PLL[1..4] and VCCD_PLL[1..4] pins
Added Pin Description for BWS pins
1.73/1/2006Added comment for PLL_OUT pins in Pin Definitions
1.8
1.910/11/2006Modified Pin Description for number of PLLs available from 4 to 2.
2.04/25/2008Incorporated pin connection guidelines into pin definitions worksheet.
6/16/2006
Added "I/O" to pin type of pin nCEO, nCSO and ASDO
Modified Pin Description for NCONFIG, NCE, DATA0, TMS, TCK, TDI, NSTATUS,
CONDONE and DCLK pins
Modified Pin Description of VCCIO and VCCINT.
Moved nCEO Discription from section "Dedicated Configuration/JTAG Pins" to section
"Optional/Dual-Purpose Configuration Pins"