ALTERA EP2C5 User Manual
®
Page 1 of 15
Cyclone
II EP2C5 Device Pin-Out
PT-EP2C5-2.0
© 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are
identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
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except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before
placing orders for products or services.
The pin connection guidelines in the device pin-out are considered preliminary. These pin connection guidelines should only be used as a recommendation, not as a specification.
The use of the pin connection guidelines for any particular design should be verified for device operation, with the datasheet and Altera.
PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THE DEVICE PIN-OUT("PIN-OUT") PROVIDED TO YOU. BY USING
THE PIN-OUT, YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND CONDITIONS, WHICH CONSTITUTE THE LICENSE AGREEMENT ("AGREEMENT") BETWEEN
YOU AND ALTERA CORPORATION ("ALTERA"). IF YOU DO NOT AGREE WITH ANY OF THESE TERMS AND CONDITIONS, DO NOT DOWNLOAD, COPY, INSTALL, OR USE OF
THE PIN-OUT.
1. Subject to the terms and conditions of this Agreement, Altera grants to you a license to use the Pin-out to determine the pin connections of the associated Altera programmable logic
device or field programmable gate array. You may not use the Pin-out for other purpose. You are expressly prohibited from using the Pin-out with any programmable logic devices or field
programmable gate arrays designed or manufactured by any company or entity other than Altera.
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SUBJECT MATTER OF THIS AGREEMENT.
Device Pin-Out Agreement © 2008 Altera Corporation. All rights reserved.
PT-EP2C5-2.0.xls
Copyright © 2008 Altera Corp.
Disclaimer
Pin Information for the Cyclone® II EP2C5 Device
V
Page 2 of 15
ersion 2.0
Note (1), (2)
Bank
Number
B1 VREFB1N0 IO ASDO ASDO 1 1 C3
B1 VREFB1N0 IO nCSO nCSO 2 2 F4
B1 VREFB1N0 IO LVDS9p CRC_ERROR 3 3 C1
B1 VREFB1N0 IO LVDS9n CLKUSR 4 4 C2
B1 VREFB1N0 IO LVDS8p 5 D5
B1 VREFB1N0 IO LVDS8n 6 E5 DQ0L0 DQ1L0
B1 VREFB1N0 VCCIO1 5 7
B1 VREFB1N0 IO LVDS7p 8 E3 DQ1L0 DQ0L1 DQ1L1
B1 VREFB1N0 GND 6 9
B1 VREFB1N0 IO LVDS7n 10 E4 DQ1L1 DQ0L2 DQ1L2
B1 VREFB1N0 IO LVDS6p 11 D3 DQ1L2 DQ0L3 DQ1L3
B1 VREFB1N0 IO LVDS6n 12 D4 DQ1L3 DQ0L4 DQ1L4
B1 VREFB1N0 IO VREFB1N0 7 13 F3
B1 VREFB1N0 VCCIO1
B1 VREFB1N0 IO LVDS5p 8 14 E1 DPCLK0/DQS0L DPCLK0/DQS0L DPCLK0/DQS0L DPCLK0/DQS0L DPCLK0/DQS0L
B1 VREFB1N0 IO LVDS5n 9 15 E2 DQ0L5 DQ1L5
B1 VREFB1N0 TDO TDO 10 16 G2
B1 VREFB1N0 TMS TMS 11 17 G1
B1 VREFB1N0 TCK TCK 12 18 F2
B1 VREFB1N0 TDI TDI 13 19 H5
B1 VREFB1N0 DATA0 DATA0 DATA0 14 20 F1
B1 VREFB1N0 DCLK DCLK DCLK 15 21 H4
B1 VREFB1N0 nCE nCE 16 22 G5
B1 VREFB1N0 CLK0
B1 VREFB1N0 CLK1
B1 VREFB1N0 GND 19 25
B1 VREFB1N0 nCONFIG nCONFIG 20 26 J5
B1 VREFB1N1 CLK2
B1 VREFB1N1 CLK3
B1 VREFB1N1 VCCIO1 23 29
B1 VREFB1N1 IO LVDS4p 24 30 K2 DPCLK1/DQS1L DPCLK1/DQS1L DPCLK1/DQS1L DPCLK1/DQS1L DPCLK1/DQS1L
B1 VREFB1N1 IO LVDS4n 25 31 K1 DQ0L6 DQ1L6
B1 VREFB1N1 IO LVDS3p 26 32 K4 DQ0L7 DQ1L7
B1 VREFB1N1 IO LVDS3n 27 33 K5 DQ1L4 DQ1L8
B1 VREFB1N1 IO 34 M1 DQ1L5 DM0L DM1L0/BWS#1L0
B1 VREFB1N1 IO LVDS2p 35 L1 DQ1L6 DQ1L0 DQ1L9
VREFB
Group
Pin Name /
Function
Optional Function(s) Configuration
Function
LVDSCLK0p/input(3)
LVDSCLK0n/input(3)
LVDSCLK1p/input(3)
LVDSCLK1n/input(3)
T144 Q208 F256 DQS for x8/x9 in
T144
17 23 H2
18 24 H1
21 27 J2
22 28 J1
DQS for x8/x9 in
Q208
DQS for x16/x18
in Q208
DQS for x8/x9 in
F256
DQS for x16/x18
in F256
PT-EP2C5-2.0.xls
Copyright © 2008 Altera Corp.
Pin List
Pin Information for the Cyclone® II EP2C5 Device
V
Page 3 of 15
ersion 2.0
Note (1), (2)
Bank
Number
B1 VREFB1N1 IO LVDS2n 36 L2 DQ1L1 DQ1L10
B1 VREFB1N1 IO VREFB1N1 28 37 J4
B1 VREFB1N1 IO M2 DQ1L2 DQ1L11
B1 VREFB1N1 GND 38
B1 VREFB1N1 IO 39 M3 DQ1L7 DQ1L3 DQ1L12
B1 VREFB1N1 IO LVDS1p 40 N1 DQ1L8 DQ1L4 DQ1L13
B1 VREFB1N1 IO LVDS1n 41 N2 DM1L/BWS#1L DQ1L5 DQ1L14
B1 VREFB1N1 VCCIO1 29 42
B1 VREFB1N1 IO 43 L3 DQ1L6 DQ1L15
B1 VREFB1N1 IO LVDS0p 44 P1 DQ1L7 DQ1L16
B1 VREFB1N1 IO LVDS0n 45 P2 DQ1L8 DQ1L17
B1 VREFB1N1 IO 30 46 P3 DM1L/BWS#1L DM1L1/BWS#1L1
B1 VREFB1N1 IO PLL1_OUTp 31 47 L4
B1 VREFB1N1 IO PLL1_OUTn 32 48 M4
B1 VREFB1N1 GND 33 49
B1 VREFB1N1 GND_PLL1 34 50 L5
B1 VREFB1N1 VCCD_PLL1 35 51 L6
B1 VREFB1N1 GND_PLL1 36 52 N5
B4 VREFB4N1 VCCA_PLL1 37 53 M5
B4 VREFB4N1 GNDA_PLL1 38 54 M6
B4 VREFB4N1 GND 39 55
B4 VREFB4N1 IO LVDS58n DEV_OE 40 56 R3
B4 VREFB4N1 IO LVDS58p 41 57 T3 DM1B/BWS#1B DM1B/BWS#1B DM1B1/BWS#1B1 DM1B/BWS#1B DM1B1/BWS#1B1
B4 VREFB4N1 IO LVDS57p 42 58 P5 DQ1B8 DQ1B8 DQ1B17 DQ1B8 DQ1B17
B4 VREFB4N1 IO LVDS57n 43 59 P4 DQ1B7 DQ1B7 DQ1B16 DQ1B7 DQ1B16
B4 VREFB4N1 IO LVDS56p 44 60 T4 DQ1B6 DQ1B6 DQ1B15 DQ1B6 DQ1B15
B4 VREFB4N1 IO LVDS56n 45 61 R4 DQ1B5 DQ1B5 DQ1B14 DQ1B5 DQ1B14
B4 VREFB4N1 VCCIO4 46 62
B4 VREFB4N1 IO LVDS55p 47 63 T5 DPCLK2/DQS1B DPCLK2/DQS1B DPCLK2/DQS1B DPCLK2/DQS1B DPCLK2/DQS1B
B4 VREFB4N1 GND
B4 VREFB4N1 IO LVDS55n 48 64 R5 DQ1B4 DQ1B13
B4 VREFB4N1 VCCIO4
B4 VREFB4N1 GND
B4 VREFB4N1 GND 49 65
B4 VREFB4N1 IO T6 DQ1B3 DQ1B12
B4 VREFB4N1 VCCINT 50 66
VREFB
Group
Pin Name /
Function
Optional Function(s) Configuration
Function
T144 Q208 F256 DQS for x8/x9 in
T144
DQS for x8/x9 in
Q208
DQS for x16/x18
in Q208
DQS for x8/x9 in
F256
DQS for x16/x18
in F256
PT-EP2C5-2.0.xls
Copyright © 2008 Altera Corp.
Pin List
Pin Information for the Cyclone® II EP2C5 Device
V
Page 4 of 15
ersion 2.0
Note (1), (2)
Bank
Number
B4 VREFB4N1 IO VREFB4N1 51 67 N8
B4 VREFB4N1 IO LVDS54p 52 68 T7 DQ1B4 DQ1B4 DQ1B13 DQ1B2 DQ1B11
B4 VREFB4N1 IO LVDS54n 69 R7 DQ1B3 DQ1B12 DQ1B1 DQ1B10
B4 VREFB4N1 IO LVDS60p L7
B4 VREFB4N1 IO LVDS60n L8
B4 VREFB4N1 IO LVDS53p 53 70 T8 DQ1B3 DQ1B2 DQ1B11 DQ1B0 DQ1B9
B4 VREFB4N1 VCCIO4 54 71
B4 VREFB4N1 IO LVDS53n 55 72 R8 DQ1B2 DQ1B1 DQ1B10 DM1B0/BWS#1B0
B4 VREFB4N1 GND 56 73
B4 VREFB4N1 IO LVDS52p 57 74 T9 DQ1B1 DQ1B0 DQ1B9
B4 VREFB4N1 IO LVDS52n 58 75 R9 DQ1B0
B4 VREFB4N0 IO LVDS59p N9
B4 VREFB4N0 IO LVDS59n N10
B4 VREFB4N0 VCCIO4
B4 VREFB4N0 IO LVDS51p 59 76 T11
B4 VREFB4N0 GND
B4 VREFB4N0 IO LVDS51n 60 77 R11 DM0B DQ1B8
B4 VREFB4N0 GND 61 78
B4 VREFB4N0 VCCINT 62 79
B4 VREFB4N0 IO 80 P11
B4 VREFB4N0 IO LVDS50p 81 L9
B4 VREFB4N0 IO LVDS50n 82 L10
B4 VREFB4N0 VCCIO4 83
B4 VREFB4N0 IO LVDS49p 84 R10 DM0B DM1B0/BWS#1B0
B4 VREFB4N0 GND 85
B4 VREFB4N0 IO LVDS49n 86 T10 DQ1B8 DQ0B7 DQ1B7
B4 VREFB4N0 IO LVDS48p 87 K11 DQ0B7 DQ1B7
B4 VREFB4N0 IO LVDS48n 88 K10 DQ0B6 DQ1B6
B4 VREFB4N0 IO VREFB4N0 63 89 N11
B4 VREFB4N0 IO LVDS47p 90 P12 DQ0B5 DQ1B5 DQ0B6 DQ1B6
B4 VREFB4N0 VCCIO4 91
B4 VREFB4N0 IO LVDS47n 92 P13 DQ0B4 DQ1B4 DQ0B5 DQ1B5
B4 VREFB4N0 GND 93
B4 VREFB4N0 IO LVDS46p 64 94 T12 DPCLK4/DQS0B DPCLK4/DQS0B DPCLK4/DQS0B DPCLK4/DQS0B DPCLK4/DQS0B
B4 VREFB4N0 IO LVDS46n 65 95 R12 DQ0B4 DQ1B4
B4 VREFB4N0 IO 96 L12 DQ0B3 DQ1B3
VREFB
Group
Pin Name /
Function
Optional Function(s) Configuration
Function
T144 Q208 F256 DQS for x8/x9 in
T144
DQS for x8/x9 in
Q208
DQS for x16/x18
in Q208
DQS for x8/x9 in
F256
DQS for x16/x18
in F256
PT-EP2C5-2.0.xls
Copyright © 2008 Altera Corp.
Pin List
Pin Information for the Cyclone® II EP2C5 Device
V
Page 5 of 15
ersion 2.0
Note (1), (2)
Bank
Number
B4 VREFB4N0 IO LVDS45p 97 T13 DQ0B2 DQ1B2 DQ0B3 DQ1B3
B4 VREFB4N0 VCCIO4 66 98
B4 VREFB4N0 IO LVDS45n 67 99 R13 DQ0B1 DQ1B1 DQ0B2 DQ1B2
B4 VREFB4N0 GND 68 100
B4 VREFB4N0 IO LVDS44p 69 101 T14 DQ0B0 DQ1B0 DQ0B1 DQ1B1
B4 VREFB4N0 IO LVDS44n 70 102 R14 DQ0B0 DQ1B0
B4 VREFB4N0 IO LVDS43p 71 103 M11
B4 VREFB4N0 IO LVDS43n 72 104 L11
B3 VREFB3N1 IO LVDS42n 73 105 N12 DM1R/BWS#1R
B3 VREFB3N1 IO LVDS42p 74 106 M12 DQ1R8 DM1R/BWS#1R DM1R1/BWS#1R1
B3 VREFB3N1 IO LVDS41n INIT_DONE 75 107 N13
B3 VREFB3N1 IO LVDS41p nCEO 76 108 N14
B3 VREFB3N1 IO P14
B3 VREFB3N1 VCCIO3 77 109
B3 VREFB3N1 IO LVDS40n 110 P15 DQ1R8 DQ1R17 DM1R/BWS#1R DM1R1/BWS#1R1
B3 VREFB3N1 GND 78 111
B3 VREFB3N1 IO LVDS40p 112 P16 DQ1R7 DQ1R16 DQ1R8 DQ1R17
B3 VREFB3N1 IO LVDS39n 113 N15 DQ1R6 DQ1R15 DQ1R7 DQ1R16
B3 VREFB3N1 IO LVDS39p 114 N16 DQ1R5 DQ1R14 DQ1R6 DQ1R15
B3 VREFB3N1 IO LVDS38n 115 M15 DQ1R4 DQ1R13 DQ1R5 DQ1R14
B3 VREFB3N1 IO LVDS38p 116 M16 DQ1R3 DQ1R12 DQ1R4 DQ1R13
B3 VREFB3N1 IO VREFB3N1 79 117 M14
B3 VREFB3N1 IO 118 L14 DQ1R2 DQ1R11
B3 VREFB3N1 IO LVDS37n 80 119 L15 DQ1R3 DQ1R12
B3 VREFB3N1 IO LVDS37p 81 120 L16 DQ1R2 DQ1R11
B3 VREFB3N1 nSTATUS nSTATUS 82 121 M13
B3 VREFB3N1 VCCIO3 122
B3 VREFB3N1 CONF_DONE CONF_DONE 83 123 L13
B3 VREFB3N1 GND 124
B3 VREFB3N1 MSEL1 MSEL1 84 125 K12
B3 VREFB3N1 MSEL0 MSEL0 85 126 J13
B3 VREFB3N1 IO LVDS36n 86 127 K16 DQ1R7 DQ1R1 DQ1R10 DQ1R1 DQ1R10
B3 VREFB3N1 IO LVDS36p 87 128 K15 DPCLK6/DQS1R DPCLK6/DQS1R DPCLK6/DQS1R DPCLK6/DQS1R DPCLK6/DQS1R
B3 VREFB3N1 CLK7
B3 VREFB3N1 CLK6
B3 VREFB3N0 CLK5
VREFB
Group
Pin Name /
Function
Optional Function(s) Configuration
Function
LVDSCLK3n/input(3)
LVDSCLK3p/input(3)
LVDSCLK2n/input(3)
T144 Q208 F256 DQS for x8/x9 in
T144
88 129 J16
89 130 J15
90 131 H15
DQS for x8/x9 in
Q208
DQS for x16/x18
in Q208
DQS for x8/x9 in
F256
DQS for x16/x18
in F256
PT-EP2C5-2.0.xls
Copyright © 2008 Altera Corp.
Pin List
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