Altera Embedded Peripherals IP User Manual

Embedded Peripheral IP User Guide

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UG-01085

2014.24.07

101 Innovation Drive San Jose, CA 95134

www.altera.com

TOC-2

Introduction........................................................................................................ 1-1

SDRAM Controller Core.....................................................................................2-1

Tool Support.................................................................................................................................................1-1

Obsolescence.................................................................................................................................................1-1

Device Support.............................................................................................................................................1-2

Document Revision History.......................................................................................................................1-2

Core Overview..............................................................................................................................................2-1

Functional Description............................................................................................................................... 2-1

Avalon-MM Interface......................................................................................................................2-2

Off-Chip SDRAM Interface............................................................................................................2-2

Board Layout and Pinout Considerations....................................................................................2-3

Performance Considerations..........................................................................................................2-4

Configuration............................................................................................................................................... 2-4

Memory Profile Page.......................................................................................................................2-5

Timing Page......................................................................................................................................2-6

Hardware Simulation Considerations.......................................................................................................2-7

SDRAM Controller Simulation Model.........................................................................................2-7

SDRAM Memory Model.................................................................................................................2-7

Example Configurations............................................................................................................................. 2-8

Software Programming Model...................................................................................................................2-9

Clock, PLL and Timing Considerations................................................................................................... 2-9

Factors Affecting SDRAM Timing................................................................................................2-9

Symptoms of an Untuned PLL.....................................................................................................2-10

Estimating the Valid Signal Window..........................................................................................2-10

Example Calculation......................................................................................................................2-11

Document Revision History.....................................................................................................................2-13

Tri-State SDRAM................................................................................................ 3-1

Altera Corporation

Feature Description..................................................................................................................................... 3-1

Block Diagram..................................................................................................................................3-2

Configuration Parameter............................................................................................................................3-2

Memory Profile Page.......................................................................................................................3-2

Timing Page......................................................................................................................................3-2

Interface.........................................................................................................................................................3-3

Reset and Clock Requirements.................................................................................................................. 3-8

Architecture..................................................................................................................................................3-8

Avalon-MM Slave Interface and CSR........................................................................................... 3-9

Block Level Usage Model................................................................................................................3-9

Document Revision History.....................................................................................................................3-10

TOC-3

Compact Flash Core............................................................................................ 4-1

Core Overview..............................................................................................................................................4-1

Functional Description............................................................................................................................... 4-1

Required Connections.................................................................................................................................4-2

Software Programming Model...................................................................................................................4-3

HAL System Library Support.........................................................................................................4-3

Software Files....................................................................................................................................4-3

Register Maps................................................................................................................................... 4-4

Document Revision History.......................................................................................................................4-5

Common Flash Interface Controller Core..........................................................5-1

........................................................................................................................................................................ 5-1

Core Overview..............................................................................................................................................5-1

Functional Description............................................................................................................................... 5-2

Configuration............................................................................................................................................... 5-2

Attributes Page.................................................................................................................................5-2

Timing page......................................................................................................................................5-3

Software Programming Model...................................................................................................................5-3

HAL System Library Support.........................................................................................................5-4

Software Files....................................................................................................................................5-4

Document Revision History.......................................................................................................................5-4

EPCS Serial Flash Controller Core..................................................................... 6-1

Core Overview..............................................................................................................................................6-1

Functional Description............................................................................................................................... 6-2

Avalon-MM Slave Interface and Registers...................................................................................6-3

Configuration..............................................................................................................................................6-4

Software Programming Model...................................................................................................................6-4

HAL System Library Support.........................................................................................................6-4

Software Files....................................................................................................................................6-5

Document Revision History.......................................................................................................................6-5

JTAG UART Core................................................................................................7-1

Core Overview..............................................................................................................................................7-1

Functional Description............................................................................................................................... 7-1

Avalon Slave Interface and Registers.............................................................................................7-2

Read and Write FIFOs.....................................................................................................................7-2

JTAG Interface................................................................................................................................. 7-2

Host-Target Connection.................................................................................................................7-2

Configuration............................................................................................................................................... 7-3

Configuration Page..........................................................................................................................7-3

Simulation Settings..........................................................................................................................7-4

Hardware Simulation Considerations.......................................................................................................7-5

Software Programming Model...................................................................................................................7-5

Altera Corporation

TOC-4

HAL System Library Support.........................................................................................................7-5

Software Files....................................................................................................................................7-8

Accessing the JTAG UART Core via a Host PC..........................................................................7-9

Register Map.....................................................................................................................................7-9

Interrupt Behavior.........................................................................................................................7-10

Document Revision History.....................................................................................................................7-11

UART Core..........................................................................................................8-1

Core Overview..............................................................................................................................................8-1

Functional Description............................................................................................................................... 8-1

Avalon-MM Slave Interface and Registers...................................................................................8-2

RS-232 Interface...............................................................................................................................8-2

Transmitter Logic.............................................................................................................................8-2

Receiver Logic...................................................................................................................................8-2

Baud Rate Generation..................................................................................................................... 8-3

Instantiating the Core..................................................................................................................................8-3

Configuration Settings.................................................................................................................... 8-3

Simulation Settings..........................................................................................................................8-6

Simulation Considerations.........................................................................................................................8-7

Software Programming Model...................................................................................................................8-7

HAL System Library Support.........................................................................................................8-7

Software Files..................................................................................................................................8-11

Register Map...................................................................................................................................8-11

Interrupt Behavior.........................................................................................................................8-16

Document Revision History.....................................................................................................................8-16

16550 UART........................................................................................................ 9-1

Core Overview..............................................................................................................................................9-1

Feature Description..................................................................................................................................... 9-1

Unsupported Features.....................................................................................................................9-2

Interface.............................................................................................................................................9-2

General Architecture....................................................................................................................... 9-4

Configuration Parameters.............................................................................................................. 9-4

DMA Support...................................................................................................................................9-5

FPGA Resource Usage.....................................................................................................................9-5

Timing and Fmax.............................................................................................................................9-6

Avalon-MM Slave............................................................................................................................ 9-7

Overrun/Underrun Conditions.....................................................................................................9-8

Hardware Auto Flow-Control........................................................................................................9-9

Clock and Baud Rate Selection.................................................................................................... 9-10

Software Programming Model.................................................................................................................9-10

Overview......................................................................................................................................... 9-10

Supported Features........................................................................................................................9-10

Unsupported Features...................................................................................................................9-11

Configuration.................................................................................................................................9-11

16550 UART API...........................................................................................................................9-12

Driver Examples.............................................................................................................................9-16

Altera Corporation

TOC-5

Document Revision History.....................................................................................................................9-20

SPI Core.............................................................................................................10-1

Core Overview............................................................................................................................................10-1

Functional Description............................................................................................................................. 10-1

Example Configurations............................................................................................................... 10-2

Transmitter Logic.......................................................................................................................... 10-2

Receiver Logic.................................................................................................................................10-3

Master and Slave Modes............................................................................................................... 10-3

Avalon-MM Interface....................................................................................................................10-5

Configuration.............................................................................................................................................10-5

Master/Slave Settings.....................................................................................................................10-5

Data Register Settings....................................................................................................................10-6

Timing Settings.............................................................................................................................. 10-6

Software Programming Model.................................................................................................................10-7

Hardware Access Routines...........................................................................................................10-7

Software Files..................................................................................................................................10-8

Register Map...................................................................................................................................10-9

Document Revision History...................................................................................................................10-11

Optrex 16207 LCD Controller Core..................................................................11-1

Core Overview............................................................................................................................................11-1

Functional Description............................................................................................................................. 11-1

Software Programming Model.................................................................................................................11-2

HAL System Library Support.......................................................................................................11-2

Displaying Characters on the LCD..............................................................................................11-2

Software Files..................................................................................................................................11-3

Register Map...................................................................................................................................11-3

Interrupt Behavior.........................................................................................................................11-3

Document Revision History.....................................................................................................................11-4

PIO Core............................................................................................................12-1

Core Overview............................................................................................................................................12-1

Functional Description............................................................................................................................. 12-1

Data Input and Output................................................................................................................. 12-2

Edge Capture.................................................................................................................................. 12-2

IRQ Generation..............................................................................................................................12-2

Example Configurations...........................................................................................................................12-3

Avalon-MM Interface....................................................................................................................12-3

Configuration.............................................................................................................................................12-3

Basic Settings.................................................................................................................................. 12-3

Input Options.................................................................................................................................12-4

Simulation.......................................................................................................................................12-5

Software Programming Model.................................................................................................................12-5

Software Files..................................................................................................................................12-5

Register Map...................................................................................................................................12-5

Altera Corporation

TOC-6

Interrupt Behavior.........................................................................................................................12-7

Software Files..................................................................................................................................12-7

Document Revision History.....................................................................................................................12-8

Avalon-ST Serial Peripheral Interface Core.....................................................13-1

Core Overview............................................................................................................................................13-1

Functional Description............................................................................................................................. 13-1

Interfaces.........................................................................................................................................13-1

Operation........................................................................................................................................13-2

Timing.............................................................................................................................................13-2

Limitations......................................................................................................................................13-3

Configuration.............................................................................................................................................13-3

Document Revision History.....................................................................................................................13-3

PCI Lite Core..................................................................................................... 14-1

Core Overview............................................................................................................................................14-1

Performance and Resource Utilization...................................................................................................14-1

Functional Description............................................................................................................................. 14-2

PCI-Avalon Bridge Blocks............................................................................................................14-2

Avalon-MM Ports..........................................................................................................................14-3

Prefetchable Avalon-MM Master................................................................................................14-3

Non-Prefectchable Avalon-MM Master.....................................................................................14-3

I/O Avalon-MM Master................................................................................................................14-4

PCI Bus Access Slave.....................................................................................................................14-4

Control Register Access (CRA) Avalon-MM Slave...................................................................14-4

Master and Target Performance..................................................................................................14-5

PCI-to-Avalon Address Translation...........................................................................................14-6

Avalon-to-PCI Address Translation...........................................................................................14-6

Avalon-To-PCI Read and Write Operation...............................................................................14-8

Ordering of Requests.....................................................................................................................14-9

PCI Interrupt................................................................................................................................14-10

Configuration...........................................................................................................................................14-10

PCI Timing Constraint Files......................................................................................................14-12

Simulation Considerations.....................................................................................................................14-13

Master Transactor (mstr_tranx)................................................................................................14-14

Simulation Flow...........................................................................................................................14-15

Document Revision History...................................................................................................................14-16

MDIO Core........................................................................................................15-1

Altera Corporation

Functional Description............................................................................................................................. 15-1

MDIO Frame Format (Clause 45)...............................................................................................15-2

MDIO Clock Generation..............................................................................................................15-3

Interfaces.........................................................................................................................................15-3

Operation........................................................................................................................................15-3

Parameter....................................................................................................................................................15-4

Configuration Registers............................................................................................................................ 15-4

TOC-7

Document Revision History.....................................................................................................................15-5

On-Chip FIFO Memory Core............................................................................16-1

Core Overview............................................................................................................................................16-1

Functional Description............................................................................................................................. 16-1

Avalon-MM Write Slave to Avalon-MM Read Slave............................................................... 16-1

Avalon-ST Sink to Avalon-ST Source.........................................................................................16-2

Avalon-MM Write Slave to Avalon-ST Source......................................................................... 16-2

Avalon-ST Sink to Avalon-MM Read Slave...............................................................................16-4

Status Interface...............................................................................................................................16-5

Clocking Modes............................................................................................................................. 16-5

Configuration.............................................................................................................................................16-5

FIFO Settings..................................................................................................................................16-6

Interface Parameters......................................................................................................................16-6

Software Programming Model.................................................................................................................16-7

HAL System Library Support.......................................................................................................16-7

Software Files..................................................................................................................................16-7

Programming with the On-Chip FIFO Memory...................................................................................16-7

Software Control............................................................................................................................16-8

Software Example........................................................................................................................ 16-11

On-Chip FIFO Memory API..................................................................................................................16-12

altera_avalon_fifo_init().............................................................................................................16-12

altera_avalon_fifo_read_status()...............................................................................................16-12

altera_avalon_fifo_read_ienable().............................................................................................16-13

altera_avalon_fifo_read_almostfull()........................................................................................16-13

altera_avalon_fifo_read_almostempty().................................................................................. 16-13

altera_avalon_fifo_read_event()................................................................................................16-14

altera_avalon_fifo_read_level()................................................................................................. 16-14

altera_avalon_fifo_clear_event()...............................................................................................16-14

altera_avalon_fifo_write_ienable()........................................................................................... 16-15

altera_avalon_fifo_write_almostfull()...................................................................................... 16-15

altera_avalon_fifo_write_almostempty().................................................................................16-15

altera_avalon_write_fifo()..........................................................................................................16-16

altera_avalon_write_other_info()............................................................................................. 16-16

altera_avalon_fifo_read_fifo()...................................................................................................16-17

Document Revision History...................................................................................................................16-18

Avalon-ST Multi-Channel Shared Memory FIFO Core...................................17-1

Core Overview............................................................................................................................................17-1

Performance and Resource Utilization...................................................................................................17-1

Functional Description............................................................................................................................. 17-3

Interfaces.........................................................................................................................................17-3

Operation........................................................................................................................................17-4

Parameters.................................................................................................................................................. 17-4

Software Programming Model.................................................................................................................17-6

HAL System Library Support.......................................................................................................17-6

Register Map...................................................................................................................................17-6

Altera Corporation

TOC-8

Document Revision History.....................................................................................................................17-8

SPI Slave/JTAG to Avalon Master Bridge Cores.............................................. 18-1

Core Overview............................................................................................................................................18-1

Functional Description............................................................................................................................. 18-1

Parameters.................................................................................................................................................. 18-3

Document Revision History.....................................................................................................................18-3

Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores................ 19-1

Functional Description............................................................................................................................. 19-1

Interfaces.........................................................................................................................................19-2

Operation—Avalon-ST Bytes to Packets Converter Core....................................................... 19-2

Operation—Avalon-ST Packets to Bytes Converter Core....................................................... 19-3

Document Revision History.....................................................................................................................19-3

Avalon Packets to Transactions Converter Core..............................................20-1

Core Overview............................................................................................................................................20-1

Functional Description............................................................................................................................. 20-1

Interfaces.........................................................................................................................................20-1

Operation........................................................................................................................................20-2

Document Revision History.....................................................................................................................20-4

Scatter-Gather DMA Controller Core.............................................................. 21-1

Core Overview............................................................................................................................................21-1

Example Systems............................................................................................................................21-1

Comparison of SG-DMA Controller Core and DMA Controller Core.................................21-2

Resource Usage and Performance...........................................................................................................21-2

Functional Description............................................................................................................................. 21-3

Functional Blocks and Configurations....................................................................................... 21-3

DMA Descriptors...........................................................................................................................21-6

Error Conditions............................................................................................................................21-7

Parameters.................................................................................................................................................. 21-9

Simulation Considerations.....................................................................................................................21-10

Software Programming Model...............................................................................................................21-10

HAL System Library Support.....................................................................................................21-10

Software Files................................................................................................................................21-10

Register Maps...............................................................................................................................21-10

DMA Descriptors.........................................................................................................................21-13

Timeouts....................................................................................................................................... 21-15

Programming with SG-DMA Controller.............................................................................................21-16

Data Structure.............................................................................................................................. 21-16

SG-DMA API............................................................................................................................... 21-17

alt_avalon_sgdma_do_async_transfer()...................................................................................21-18

alt_avalon_sgdma_do_sync_transfer().....................................................................................21-18

alt_avalon_sgdma_construct_mem_to_mem_desc()............................................................ 21-19

Altera Corporation

TOC-9

alt_avalon_sgdma_construct_stream_to_mem_desc()..........................................................21-20

alt_avalon_sgdma_construct_mem_to_stream_desc()..........................................................21-21

alt_avalon_sgdma_check_descriptor_status().........................................................................21-22

alt_avalon_sgdma_register_callback()......................................................................................21-23

alt_avalon_sgdma_start()........................................................................................................... 21-23

alt_avalon_sgdma_stop()............................................................................................................21-24

alt_avalon_sgdma_open().......................................................................................................... 21-24

Document Revision History...................................................................................................................21-25

Altera Modular Scatter-Gather DMA...............................................................22-1

Overview..................................................................................................................................................... 22-1

Feature Description...................................................................................................................................22-1

mSGDMA Interfaces and Parameters.........................................................................................22-4

mSGDMA Descriptors..................................................................................................................22-7

Register Map of mSGDMA........................................................................................................ 22-12

Unsupported Feature.................................................................................................................. 22-15

Document Revision History.......................................................................................................22-15

DMA Controller Core....................................................................................... 23-1

Core Overview............................................................................................................................................23-1

Functional Description............................................................................................................................. 23-1

Setting Up DMA Transactions.....................................................................................................23-2

The Master Read and Write Ports...............................................................................................23-2

Addressing and Address Incrementing...................................................................................... 23-3

Parameters.................................................................................................................................................. 23-3

DMA Parameters (Basic)..............................................................................................................23-3

Advanced Options......................................................................................................................... 23-4

Software Programming Model.................................................................................................................23-5

HAL System Library Support.......................................................................................................23-5

Software Files..................................................................................................................................23-6

Register Map...................................................................................................................................23-6

Interrupt Behavior.........................................................................................................................23-9

Document Revision History...................................................................................................................23-10

Video Sync Generator and Pixel Converter Cores........................................... 24-1

Core Overview............................................................................................................................................24-1

Video Sync Generator............................................................................................................................... 24-1

Functional Description................................................................................................................. 24-1

Parameters...................................................................................................................................... 24-2

Signals..............................................................................................................................................24-3

Timing Diagrams...........................................................................................................................24-4

Pixel Converter...........................................................................................................................................24-5

Functional Description................................................................................................................. 24-5

Parameters...................................................................................................................................... 24-5

Signals..............................................................................................................................................24-5

Hardware Simulation Considerations.................................................................................................... 24-6

Altera Corporation

TOC-10

Document Revision History.....................................................................................................................24-6

Interval Timer Core...........................................................................................25-1

Core Overview............................................................................................................................................25-1

Functional Description............................................................................................................................. 25-1

Avalon-MM Slave Interface..........................................................................................................25-2

Configuration.............................................................................................................................................25-2

Timeout Period.............................................................................................................................. 25-2

Counter Size....................................................................................................................................25-3

Hardware Options......................................................................................................................... 25-3

Configuring the Timer as a Watchdog Timer........................................................................... 25-4

Software Programming Model.................................................................................................................25-4

HAL System Library Support.......................................................................................................25-4

Software Files..................................................................................................................................25-5

Register Map...................................................................................................................................25-5

Interrupt Behavior.........................................................................................................................25-8

Document Revision History.....................................................................................................................25-8

Mutex Core........................................................................................................ 26-1

Core Overview............................................................................................................................................26-1

Functional Description............................................................................................................................. 26-1

Configuration.............................................................................................................................................26-2

Software Programming Model.................................................................................................................26-2

Software Files..................................................................................................................................26-2

Hardware Access Routines...........................................................................................................26-2

Mutex API...................................................................................................................................................26-3

altera_avalon_mutex_is_mine()..................................................................................................26-3

altera_avalon_mutex_first_lock()............................................................................................... 26-4

altera_avalon_mutex_lock().........................................................................................................26-4

altera_avalon_mutex_open()....................................................................................................... 26-4

altera_avalon_mutex_trylock()....................................................................................................26-5

altera_avalon_mutex_unlock()....................................................................................................26-5

Document Revision History.....................................................................................................................26-5

Mailbox Core..................................................................................................... 27-1

Altera Corporation

Core Overview............................................................................................................................................27-1

Functional Description............................................................................................................................. 27-1

Configuration.............................................................................................................................................27-2

Software Programming Model.................................................................................................................27-2

Software Files..................................................................................................................................27-3

Programming with the Mailbox Core.........................................................................................27-3

Mailbox API................................................................................................................................................27-4

altera_avalon_mailbox_close().................................................................................................... 27-4

altera_avalon_mailbox_get()........................................................................................................27-5

altera_avalon_mailbox_open()....................................................................................................27-5

altera_avalon_mailbox_pend()....................................................................................................27-5

TOC-11

altera_avalon_mailbox_post()..................................................................................................... 27-6

Document Revision History.....................................................................................................................27-6

Vectored Interrupt Controller Core.................................................................28-1

Core Overview............................................................................................................................................28-1

Functional Description............................................................................................................................. 28-3

External Interfaces.........................................................................................................................28-3

Functional Blocks...........................................................................................................................28-4

Register Maps............................................................................................................................................. 28-6

Parameters................................................................................................................................................ 28-11

Altera HAL Software Programming Model.........................................................................................28-11

Software Files................................................................................................................................28-11

Macros...........................................................................................................................................28-12

Data Structure.............................................................................................................................. 28-13

VIC API.........................................................................................................................................28-13

Run-time Initialization................................................................................................................28-16

Board Support Package...............................................................................................................28-16

Document Revision History...................................................................................................................28-23

Avalon-ST JTAG Interface Core.......................................................................29-1

Functional Description............................................................................................................................. 29-1

Interfaces.........................................................................................................................................29-1

Core Behavior.................................................................................................................................29-2

Parameters...................................................................................................................................... 29-3

Document Revision History.....................................................................................................................29-3

System ID Core..................................................................................................30-1

Core Overview............................................................................................................................................30-1

Functional Description............................................................................................................................. 30-1

Configuration.............................................................................................................................................30-2

Software Programming Model.................................................................................................................30-2

alt_avalon_sysid_test()..................................................................................................................30-2

Document Revision History.....................................................................................................................30-3

Performance Counter Core...............................................................................31-1

Core Overview............................................................................................................................................31-1

Functional Description............................................................................................................................. 31-1

Section Counters............................................................................................................................31-1

Global Counter...............................................................................................................................31-2

Register Map...................................................................................................................................31-2

System Reset................................................................................................................................... 31-3

Configuration.............................................................................................................................................31-3

Define Counters.............................................................................................................................31-3

Multiple Clock Domain Considerations.....................................................................................31-3

Hardware Simulation Considerations.................................................................................................... 31-3

Altera Corporation

TOC-12

Software Programming Model.................................................................................................................31-3

Software Files..................................................................................................................................31-4

Using the Performance Counter..................................................................................................31-4

Interrupt Behavior.........................................................................................................................31-6

Performance Counter API........................................................................................................................31-6

PERF_RESET()...............................................................................................................................31-6

PERF_START_MEASURING().................................................................................................. 31-7

PERF_STOP_MEASURING().....................................................................................................31-7

PERF_BEGIN()..............................................................................................................................31-7

PERF_END()..................................................................................................................................31-8

perf_print_formatted_report().................................................................................................... 31-8

perf_get_total_time().................................................................................................................... 31-9

perf_get_section_time()................................................................................................................31-9

perf_get_num_starts()................................................................................................................ 31-10

alt_get_cpu_freq()....................................................................................................................... 31-10

Document Revision History...................................................................................................................31-11

PLL Cores...........................................................................................................32-1

Core Overview............................................................................................................................................32-1

Functional Description............................................................................................................................. 32-2

ALTPLL Megafunction................................................................................................................. 32-2

Clock Outputs................................................................................................................................ 32-2

PLL Status and Control Signals....................................................................................................32-2

System Reset Considerations........................................................................................................32-3

Instantiating the Avalon ALTPLL Core..................................................................................................32-3

Instantiating the PLL Core....................................................................................................................... 32-3

Hardware Simulation Considerations.................................................................................................... 32-5

Register Definitions and Bit List..............................................................................................................32-5

Status Register................................................................................................................................ 32-5

Control Register.............................................................................................................................32-6

Phase Reconfig Control Register................................................................................................. 32-7

Document Revision History.....................................................................................................................32-8

Altera MSI to GIC Generator............................................................................33-1

Altera Interrupt Latency Counter.....................................................................34-1

Altera Corporation

Overview..................................................................................................................................................... 33-1

Background.................................................................................................................................................33-1

Feature Description...................................................................................................................................33-1

Interrupt Servicing Process.......................................................................................................... 33-2

Registers of Component................................................................................................................33-3

Unsupported Feature.................................................................................................................... 33-4

Altera SMBus Core Interface....................................................................................................................33-5

Component Interface.................................................................................................................... 33-7

Component Parameterization......................................................................................................33-7

Document Revision History.....................................................................................................................33-9

TOC-13

Overview..................................................................................................................................................... 34-1

Feature Description...................................................................................................................................34-2

Avalon-MM Compliant CSR Registers.......................................................................................34-2

32-bit Counter................................................................................................................................34-4

Interrupt Detector..........................................................................................................................34-5

Component Interface................................................................................................................................ 34-5

Component Parameterization..................................................................................................................34-5

Software Access..........................................................................................................................................34-6

Routine for Level Sensitive Interrupts........................................................................................ 34-6

Routine for Edge/Pulse Sensitive Interrupts..............................................................................34-6

Implementation Details............................................................................................................................ 34-7

Interrupt Latency Counter Architecture.................................................................................... 34-7

IP Caveats....................................................................................................................................................34-8

Document Revision History.....................................................................................................................34-8

Altera Corporation

2014.24.07

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Introduction

UG-01085

This user guide describes the IP cores provided by Altera that are included in the Quartus® II design software.

The IP cores are optimized for Altera® devices and can be easily implemented to reduce design and test time. You can use the IP parameter editor from Qsys to add the IP cores to your system, configure the cores, and specify their connectivity.

Altera's Qsys system integration tool is available in the Quartus II software subcription edition version

14.0. Before using Qsys, review the (Quartus II software Version 14.0 Release Notes) for known issues and

limitations. To submit general feedback or technical support, click Feedback on the Quartus II software Help menu and also on all Altera technical documentation.

Quartus II Handbook 14.0 Quartus II Software and Device Support Release Notes Version 14.0

Tool Support

Qsys is a system-level integration tool which is included as part of the Quartus II software. Qsys leverages the easy-to-use interface of SOPC Builder and provides backward compatibility for easy migration of existing embedded systems.You can implement a design using the IP cores from the Qsys component library.

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All the IP cores described in this user guide are supported by Qsys except for the following cores which are only supported by SOPC Builder.

• Common Flash Interface Controller Core

• SDRAM Controller Core (pin-sharing mode)

• System ID Core

Obsolescence

The following IP cores are scheduled for product obsolescence and discontinued support:

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO 9001:2008 Registered

1-2

Device Support

• PCI Lite Core

• Mailbox Core Altera recommends that you do not use these cores in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property

website.

Device Support

The IP cores described in this user guide support all Altera® device families except the cores listed in the table below.

Table 1-1: Device Support

IP Cores Device Support

Off-Chip Interfaces

EPCS Serial Flash Controller Core All device families except HardCopy

series.

UG-01085

2014.24.07

Cyclone III Remote Update

Only Cyclone III device.

Controller Core

On-Chip Interfaces

On-Chip FIFO Memory Core All device families except HardCopy

series.

Different device families support different I/O standards, which may affect the ability of the core to interface to certain components. For details about supported I/O types, refer to the device handbook for the target device family.

Document Revision History

Table 1-2: Document Revision History

Date and

Document

Version

July 2014 v14.0.0

December 2013 v13.1.0

-Removed mention of SOPC Builder, updated to Qsys Maintenance

Removed listing of the DMA Controller core in the Qsys unsupported list. The DMA controller core is now supported in Qsys.

Changes Made Summary of Changes

Release

—

Altera Corporation

Removed listing of the MDIO core in Device Support Table. The MDIO core support all device families that the 10-Gbps Ethernet MAC MegaCore Function supports.

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Document Revision History

1-3

Date and

Document

Version

December 2010

v10.1.0

Changes Made Summary of Changes

Initial release. —

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SDRAM Controller Core

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Core Overview

The SDRAM controller core with Avalon® interface provides an Avalon Memory-Mapped (Avalon-MM) interface to off-chip SDRAM. The SDRAM controller allows designers to create custom systems in an Altera® device that connect easily to SDRAM chips. The SDRAM controller supports standard SDRAM as described in the PC100 specification.

SDRAM is commonly used in cost-sensitive applications requiring large amounts of volatile memory. While SDRAM is relatively inexpensive, control logic is required to perform refresh operations, open-row management, and other delays and command sequences. The SDRAM controller connects to one or more SDRAM chips, and handles all SDRAM protocol requirements. Internal to the device, the core presents an Avalon-MM slave port that appears as linear memory (flat address space) to Avalon-MM master peripherals.

The core can access SDRAM subsystems with various data widths (8, 16, 32, or 64 bits), various memory sizes, and multiple chip selects. The Avalon-MM interface is latency-aware, allowing read transfers to be pipelined. The core can optionally share its address and data buses with other off-chip Avalon-MM tristate devices. This feature is valuable in systems that have limited I/O pins, yet must connect to multiple memory chips in addition to SDRAM.

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Functional Description

The diagram below shows a block diagram of the SDRAM controller core connected to an external SDRAM chip.

ISO 9001:2008 Registered

Avalon-MM slave

interface

to on-chip

logic

SDRAM Controller Core

data, control

Avalon-MM Slave Port

clock

waitrequest

readdatavalid

dqm

PLL

Phase Shift

Interface to SDRAM pins

Altera FPGA

clk

addr

ras

cas

cke

Control

Logic

address

SDRAM Clock

Controller Clock

Clock

Source

SDRAM Chip

(PC100)

2-2

Avalon-MM Interface

Figure 2-1: SDRAM Controller with Avalon Interface Block Diagram

The following sections describe the components of the SDRAM controller core in detail. All options are specified at system generation time, and cannot be changed at runtime.

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Avalon-MM Interface

The Avalon-MM slave port is the user-visible part of the SDRAM controller core. The slave port presents a flat, contiguous memory space as large as the SDRAM chip(s). When accessing the slave port, the details of the PC100 SDRAM protocol are entirely transparent. The Avalon-MM interface behaves as a simple memory interface. There are no memory-mapped configuration registers.

The Avalon-MM slave port supports peripheral-controlled wait states for read and write transfers. The slave port stalls the transfer until it can present valid data. The slave port also supports read transfers with variable latency, enabling high-bandwidth, pipelined read transfers. When a master peripheral reads sequential addresses from the slave port, the first data returns after an initial period of latency. Subsequent reads can produce new data every clock cycle. However, data is not guaranteed to return every clock cycle, because the SDRAM controller must pause periodically to refresh the SDRAM.

For details about Avalon-MM transfer types, refer to the Avalon Interface Specifications.

Off-Chip SDRAM Interface

The interface to the external SDRAM chip presents the signals defined by the PC100 standard. These signals must be connected externally to the SDRAM chip(s) through I/O pins on the Altera device.

Signal Timing and Electrical Characteristics

The timing and sequencing of signals depends on the configuration of the core. The hardware designer configures the core to match the SDRAM chip chosen for the system. See the Configuration section for details. The electrical characteristics of the device pins depend on both the target device family and the assignments made in the Quartus® II software. Some device families support a wider range of electrical

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standards, and therefore are capable of interfacing with a greater variety of SDRAM chips. For details, refer to the device handbook for the target device family.

Synchronizing Clock and Data Signals

The clock for the SDRAM chip (SDRAM clock) must be driven at the same frequency as the clock for the Avalon-MM interface on the SDRAM controller (controller clock). As in all synchronous designs, you must ensure that address, data, and control signals at the SDRAM pins are stable when a clock edge arrives. As shown in the above SDRAM Controller with Avalon Interface block diagram, you can use an on-chip phase-locked loop (PLL) to alleviate clock skew between the SDRAM controller core and the SDRAM chip. At lower clock speeds, the PLL might not be necessary. At higher clock rates, a PLL is necessary to ensure that the SDRAM clock toggles only when signals are stable on the pins. The PLL block is not part of the SDRAM controller core. If a PLL is necessary, you must instantiate it manually. You can instantiate the PLL core interface or instantiate an ALTPLL megafunction outside the Qsys system module.

If you use a PLL, you must tune the PLL to introduce a clock phase shift so that SDRAM clock edges arrive after synchronous signals have stabilized. See Clock, PLL and Timing Considerations sections for details.

For more information about instantiating a PLL, refer to PLL Cores chapter. The Nios® II development tools provide example hardware designs that use the SDRAM controller core in conjunction with a PLL, which you can use as a reference for your custom designs.

Synchronizing Clock and Data Signals

2-3

The Nios II development tools are available free for download from www.Altera.com.

Clock Enable (CKE) not Supported

The SDRAM controller does not support clock-disable modes. The SDRAM controller permanently asserts the CKE signal on the SDRAM.

Sharing Pins with other Avalon-MM Tri-State Devices

If an Avalon-MM tri-state bridge is present, the SDRAM controller core can share pins with the existing tri-state bridge. In this case, the core’s addr, dq (data) and dqm (byte-enable) pins are shared with other devices connected to the Avalon-MM tri-state bridge. This feature conserves I/O pins, which is valuable in systems that have multiple external memory chips (for example, flash, SRAM, and SDRAM), but too few pins to dedicate to the SDRAM chip. See Performance Considerations section for details about how pin sharing affects performance.

The SDRAM addresses must connect all address bits regardless of the size of the word so that the loworder address bits on the tri-state bridge align with the low-order address bits on the memory device. The Avalon-MM tristate address signal always presents a byte address. It is not possible to drop A0 of the tristate bridge for memories when the smallest access size is 16 bits or A0-A1 of the tri-state bridge when the smallest access size is 32 bits.

Board Layout and Pinout Considerations

When making decisions about the board layout and device pinout, try to minimize the skew between the SDRAM signals. For example, when assigning the device pinout, group the SDRAM signals, including the SDRAM clock output, physically close together. Also, you can use the Fast Input Register and Fast Output Register logic options in the Quartus II software. These logic options place registers for the SDRAM signals in the I/O cells. Signals driven from registers in I/O cells have similar timing characteris‐ tics, such as tCO, tSU, and tH.

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Performance Considerations

Under optimal conditions, the SDRAM controller core’s bandwidth approaches one word per clock cycle. However, because of the overhead associated with refreshing the SDRAM, it is impossible to reach one word per clock cycle. Other factors affect the core’s performance, as described in the following sections.

Open Row Management

SDRAM chips are arranged as multiple banks of memory, in which each bank is capable of independent open-row address management. The SDRAM controller core takes advantage of open-row management for a single bank. Continuous reads or writes within the same row and bank operate at rates approaching one word per clock. Applications that frequently access different destination banks require extra management cycles to open and close rows.

Sharing Data and Address Pins

When the controller shares pins with other tri-state devices, average access time usually increases and bandwidth decreases. When access to the tri-state bridge is granted to other devices, the SDRAM incurs overhead to open and close rows. Furthermore, the SDRAM controller has to wait several clock cycles before it is granted access again.

To maximize bandwidth, the SDRAM controller automatically maintains control of the tri-state bridge as long as back-to-back read or write transactions continue within the same row and bank.

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This behavior may degrade the average access time for other devices sharing the Avalon-MM tri-state bridge.

The SDRAM controller closes an open row whenever there is a break in back-to-back transactions, or whenever a refresh transaction is required. As a result:

• The controller cannot permanently block access to other devices sharing the tri-state bridge.

• The controller is guaranteed not to violate the SDRAM’s row open time limit.

Hardware Design and Target Device

The target device affects the maximum achievable clock frequency of a hardware design. Certain device families achieve higher f

performance than other families. Furthermore, within a device family, faster

MAX

speed grades achieve higher performance. The SDRAM controller core can achieve 100 MHz in Altera’s high-performance device families, such as Stratix® series. However, the core might not achieve 100 MHz performance in all Altera device families.

The f

performance also depends on the system design. The SDRAM controller clock can also drive

MAX

other logic in the system module, which might affect the maximum achievable frequency. For the SDRAM controller core to achieve f

performance of 100 MHz, all components driven by the same clock must

MAX

be designed for a 100 MHz clock rate, and timing analysis in the Quartus II software must verify that the overall hardware design is capable of 100 MHz operation.

Configuration

The SDRAM controller MegaWizard has two pages: Memory Profile and Timing. This section describes the options available on each page.

The Presets list offers several pre-defined SDRAM configurations as a convenience. If the SDRAM subsystem on the target board matches one of the preset configurations, you can configure the SDRAM

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controller core easily by selecting the appropriate preset value. The following preset configurations are defined:

• Micron MT8LSDT1664HG module

• Four SDR100 8 MByte × 16 chips

• Single Micron MT48LC2M32B2-7 chip

• Single Micron MT48LC4M32B2-7 chip

• Single NEC D4564163-A80 chip (64 MByte × 16)

• Single Alliance AS4LC1M16S1-10 chip

• Single Alliance AS4LC2M8S0-10 chip

Selecting a preset configuration automatically changes values on the Memory Profile and Timing tabs to match the specific configuration. Altering a configuration setting on any page changes the Preset value to custom.

Memory Profile Page

The Memory Profile page allows you to specify the structure of the SDRAM subsystem such as address and data bus widths, the number of chip select signals, and the number of banks.

Table 2-1: Memory Profile Page Settings

Memory Profile Page

2-5

Settings Allowed

Values

Default

Values

Description

Data Width 8, 16, 32,6432 SDRAM data bus width. This value determines the

width of the dq bus (data) and the dqm bus (byteenable).

Chip Selects 1, 2, 4, 8 1 Number of independent chip selects in the SDRAM

subsystem. By using multiple chip selects, the

Archite cture Setting s

Banks 2, 4 4 Number of SDRAM banks. This value determines the

SDRAM controller can combine multiple SDRAM chips into one memory subsystem.

width of the ba bus (bank address) that connects to the SDRAM. The correct value is provided in the data sheet for the target SDRAM.

Row 11, 12, 13,1412 Number of row address bits. This value determines

the width of the addr bus. The Row and Column

Addres s Width

values depend on the geometry of the chosen SDRAM. For example, an SDRAM organized as 4096 (212) rows by 512 columns has a Row value of 12.

Setting s

Column >= 8, and

less than Row value

8 Number of column address bits. For example, the

SDRAM organized as 4096 rows by 512 (29) columns has a Column value of 9.

Share pins via tristate bridge dq/dqm/ addr I/O pins

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On, Off Off When set to No, all pins are dedicated to the SDRAM

chip. When set to Yes, the addr, dq, and dqm pins can be shared with a tristate bridge in the system. In this case, select the appropriate tristate bridge from the pull-down menu.

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Timing Page

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Settings Allowed

Include a functional memory model in the system testbench

Values

On, Off On When on, Qsys functional simulation model for the

Default

Values

Description

SDRAM chip. This default memory model acceler‐ ates the process of creating and verifying systems that use the SDRAM controller. See Hardware Simulation Considerations section.

Based on the settings entered on the Memory Profile page, the wizard displays the expected memory capacity of the SDRAM subsystem in units of megabytes, megabits, and number of addressable words. Compare these expected values to the actual size of the chosen SDRAM to verify that the settings are correct.

Timing Page

The Timing page allows designers to enter the timing specifications of the SDRAM chip(s) used. The correct values are available in the manufacturer’s data sheet for the target SDRAM.

Table 2-2: Timing Page Settings

Settings Allowe

Values

CAS latency 1, 2, 3 3 Latency (in clock cycles) from a read command to data

Default

Value

Description

out.

Initialization refresh cycles

1–8 2 This value specifies how many refresh cycles the

SDRAM controller performs as part of the initialization sequence after reset.

Issue one refresh command every

— 15.625 µs This value specifies how often the SDRAM controller

refreshes the SDRAM. A typical SDRAM requires 4,096 refresh commands every 64 ms, which can be achieved by issuing one refresh command every 64 ms / 4,096 =

15.625 μs.

Delay after power up, before initiali‐

— 100 µs The delay from stable clock and power to SDRAM

initialization.

zation Duration of refresh

— 70 ns Auto Refresh period.

command (t_rfc) Duration of

— 20 ns Precharge command period. precharge command (t_rp)

ACTIVE to READ

— 20 ns ACTIVE to READ or WRITE delay. or WRITE delay (t_rcd)

Access time (t_ac) — 17 ns Access time from clock edge. This value may depend on

CAS latency.

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Hardware Simulation Considerations

2-7

Settings Allowe

Write recovery time (t_wr, No auto precharge)

Values

— 14 ns Write recovery if explicit precharge commands are

Default

Value

issued. This SDRAM controller always issues explicit precharge commands.

Regardless of the exact timing values you specify, the actual timing achieved for each parameter is an integer multiple of the Avalon clock period. For the Issue one refresh command every parameter, the actual timing is the greatest number of clock cycles that does not exceed the target value. For all other parameters, the actual timing is the smallest number of clock ticks that provides a value greater than or equal to the target value.

Hardware Simulation Considerations

This section discusses considerations for simulating systems with SDRAM. Three major components are required for simulation:

• A simulation model for the SDRAM controller.

• A simulation model for the SDRAM chip(s), also called the memory model.

• A simulation testbench that wires the memory model to the SDRAM controller pins. Some or all of these components are generated by Qsys at system generation time.

Description

SDRAM Controller Simulation Model

The SDRAM controller design files generated by Qsys are suitable for both synthesis and simulation. Some simulation features are implemented in the HDL using “translate on/off” synthesis directives that make certain sections of HDL code invisible to the synthesis tool.

The simulation features are implemented primarily for easy simulation of Nios and Nios II processor systems using the ModelSim® simulator. The SDRAM controller simulation model is not ModelSim specific. However, minor changes may be required to make the model work with other simulators.

If you change the simulation directives to create a custom simulation flow, be aware that Qsys overwrites existing files during system generation. Take precautions to ensure your changes are not overwritten.

Refer to AN 351: Simulating Nios II Processor Designs for a demonstration of simulation of the SDRAM controller in the context of Nios II embedded processor systems.

SDRAM Memory Model

This section describes the two options for simulating a memory model of the SDRAM chip(s).

Using the Generic Memory Model

If the Include a functional memory model the system testbench option is enabled at system generation, Qsys generates an HDL simulation model for the SDRAM memory. In the auto-generated system testbench, Qsys automatically wires this memory model to the SDRAM controller pins.

Using the automatic memory model and testbench accelerates the process of creating and verifying systems that use the SDRAM controller. However, the memory model is a generic functional model that does not reflect the true timing or functionality of real SDRAM chips. The generic model is always

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data

128 Mbits 16 Mbytes

32 data width device

SDRAM

Controller

Altera FPGA

Avalon-MM

interface

on-chip

logic

addr

cs_n

ctl

addr

ctl cs_n

SDRAM

Controller

Altera FPGA

Avalon-MM

interface

on-chip

logic

64 Mbits

8 Mbytes

16 data width device

64 Mbits

8 Mbytes

16 data width device

data

2-8

Using the SDRAM Manufacturer's Memory Model

structured as a single, monolithic block of memory. For example, even for a system that combines two SDRAM chips, the generic memory model is implemented as a single entity.

Using the SDRAM Manufacturer's Memory Model

If the Include a functional memory model the system testbench option is not enabled, you are responsible for obtaining a memory model from the SDRAM manufacturer, and manually wiring the model to the SDRAM controller pins in the system testbench.

Example Configurations

The following examples show how to connect the SDRAM controller outputs to an SDRAM chip or chips. The bus labeled ctl is an aggregate of the remaining signals, such as cas_n, ras_n, cke and we_n.

The address, data, and control signals are wired directly from the controller to the chip. The result is a 128-Mbit (16-Mbyte) memory space.

Figure 2-2: Single 128-Mbit SDRAM Chip with 32-Bit Data

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The address and control signals connect in parallel to both chips. The chips share the chipselect (cs_n) signal. Each chip provides half of the 32-bit data bus. The result is a logical 128-Mbit (16-Mbyte) 32-bit data memory.

Figure 2-3: Two 64-MBit SDRAM Chips Each with 16-Bit Data

SDRAM Controller Core

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addr ctl

cs_n [0]

cs_n [1]

SDRAM

Controller

Altera FPGA

Avalon-MM

interface

on-chip

logic

data

128 Mbits

16 Mbytes

32 data width device

128 Mbits

16 Mbytes

32 data width device

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The address, data, and control signals connect in parallel to the two chips. The chipselect bus (cs_n[1:0]) determines which chip is selected. The result is a logical 256-Mbit 32-bit wide memory.

Figure 2-4: Two 128-Mbit SDRAM Chips Each with 32-Bit Data

Software Programming Model

2-9

The SDRAM controller behaves like simple memory when accessed via the Avalon-MM interface. There are no software-configurable settings and no memory-mapped registers. No software driver routines are required for a processor to access the SDRAM controller.

Clock, PLL and Timing Considerations

This section describes issues related to synchronizing signals from the SDRAM controller core with the clock that drives the SDRAM chip. During SDRAM transactions, the address, data, and control signals are valid at the SDRAM pins for a window of time, during which the SDRAM clock must toggle to capture the correct values. At slower clock frequencies, the clock naturally falls within the valid window. At higher frequencies, you must compensate the SDRAM clock to align with the valid window.

Determine when the valid window occurs either by calculation or by analyzing the SDRAM pins with an oscilloscope. Then use a PLL to adjust the phase of the SDRAM clock so that edges occur in the middle of the valid window. Tuning the PLL might require trial-and-error effort to align the phase shift to the properties of your target board.

For details about the PLL circuitry in your target device, refer to the appropriate device family handbook. For details about configuring the PLLs in Altera devices, refer to the ALTPLL Megafunction User Guide.

Factors Affecting SDRAM Timing

The location and duration of the window depends on several factors:

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Symptoms of an Untuned PLL

• Timing parameters of the device and SDRAM I/O pins — I/O timing parameters vary based on device family and speed grade.

• Pin location on the device — I/O pins connected to row routing have different timing than pins connected to column routing.

• Logic options used during the Quartus II compilation — Logic options such as the Fast Input Register and Fast Output Register logic affect the design fit. The location of logic and registers inside the device affects the propagation delays of signals to the I/O pins.

• SDRAM CAS latency As a result, the valid window timing is different for different combinations of FPGA and SDRAM

devices. The window depends on the Quartus II software fitting results and pin assignments.

Symptoms of an Untuned PLL

Detecting when the PLL is not tuned correctly might be difficult. Data transfers to or from the SDRAM might not fail universally. For example, individual transfers to the SDRAM controller might succeed, whereas burst transfers fail. For processor-based systems, if software can perform read or write data to SDRAM, but cannot run when the code is located in SDRAM, the PLL is probably tuned incorrectly.

Estimating the Valid Signal Window

This section describes how to estimate the location and duration of the valid signal window using timing parameters provided in the SDRAM datasheet and the Quartus II software compilation report. After finding the window, tune the PLL so that SDRAM clock edges occur exactly in the middle of the window.

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Calculating the window is a two-step process. First, determine by how much time the SDRAM clock can lag the controller clock, and then by how much time it can lead. After finding the maximum lag and lead values, calculate the midpoint between them.

These calculations provide an estimation only. The following delays can also affect proper PLL tuning, but are not accounted for by these calculations.

• Signal skew due to delays on the printed circuit board — These calculations assume zero skew.

• Delay from the PLL clock output nodes to destinations — These calculations assume that the delay from the PLL SDRAM-clock output-node to the pin is the same as the delay from the PLL controllerclock output-node to the clock inputs in the SDRAM controller. If these clock delays are significantly different, you must account for this phase shift in your window calculations.

Lag is a negative time shift, relative to the controller clock, and lead is a positive time shift. The SDRAM clock can lag the controller clock by the lesser of the maximum lag for a read cycle or that for a write cycle. In other words, Maximum Lag = minimum(Read Lag, Write Lag). Similarly, the SDRAM clock can lead by the lesser of the maximum lead for a read cycle or for a write cycle. In other words, Maximum Lead = minimum(Read Lead, Write Lead).

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Figure 2-5: Calculating the Maximum SDRAM Clock Lag

Figure 2-6: Calculating the Maximum SDRAM Clock Lead

Example Calculation

2-11

Example Calculation

This section demonstrates a calculation of the signal window for a Micron MT48LC4M32B2-7 SDRAM chip and design targeting the Stratix II EP2S60F672C5 device. This example uses a CAS latency (CL) of 3 cycles, and a clock frequency of 50 MHz. All SDRAM signals on the device are registered in I/O cells, enabled with the Fast Input Register and Fast Output Register logic options in the Quartus II software.

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Example Calculation

Table 2-3: Timing Parameters for Micron MT48LC4M32B2 SDRAM Device

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Parameter Symbol

Access time from CLK (pos. edge)

CL = 3 t CL = 2 t

CL = 1 t Address hold time t Address setup time t CLK high-level width t CLK low-level width t

CL = 3 t Clock cycle time

CL = 2 t

CL = 1 t CKE hold time t CKE setup time t CS#, RAS#, CAS#, WE#, DQM

hold time

AC(3)

AC(2)

AC(1)

CK(3)

CK(2)

CK(1)

CKH

CKS

CMH

Value (ns) in -7 Speed Grade

Min. Max.

— 5.5 — 8 — 17 1 — 2 —

2.75 —

2.75 — 7 — 10 — 20 — 1 — 2 — 1 —

CS#, RAS#, CAS#, WE#, DQM

CMS

setup time Data-in hold time t Data-in setup time t Data-out

highimpedance time

CL = 3 t

CL = 2 t

CL = 1 t Data-out low-impedance time t Data-out hold time t

HZ(3)

HZ(2)

HZ(1)

The FPGA I/O Timing Parameters table below shows the relevant timing information, obtained from the Timing Analyzer section of the Quartus II Compilation Report. The values in the table are the maximum or minimum values among all device pins related to the SDRAM. The variance in timing between the SDRAM pins on the device is small (less than 100 ps) because the registers for these signals are placed in the I/O cell.

Table 2-4: FPGA I/O Timing Parameters

Parameter Symbol Value (ns)

Clock period t Minimum clock-to-output time t

CLK

CO_MIN

2 —

1 2

5.5 — 8 — 17 1 —

2.5

2.399

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Parameter Symbol Value (ns)

Document Revision History

2-13

Maximum clock-to-output time t Maximum hold time after clock t Maximum setup time before clock t

CO_MAX

H_MAX

SU_MAX

2.477 –5.607

5.936

You must compile the design in the Quartus II software to obtain the I/O timing information for the design. Although Altera device family datasheets contain generic I/O timing information for each device, the Quartus II Compilation Report provides the most precise timing information for your specific design.

The timing values found in the compilation report can change, depending on fitting, pin location, and other Quartus II logic settings. When you recompile the design in the Quartus II software, verify that the I/O timing has not changed significantly.

The following examples illustrate the calculations from figures Maximum SDRAM Clock Lag and Maximum Lead also using the values from the Timing Parameters and FPGA I/O Timing Parameters table.

The SDRAM clock can lag the controller clock by the lesser of Read Lag or Write Lag: Read Lag = tOH(SDRAM) – t

H_MAX

(FPGA) = 2.5 ns – (–5.607 ns) = 8.107 ns or Write Lag = t

CLK

– t

CO_MAX

(FPGA) – tDS(SDRAM) = 20 ns – 2.477 ns – 2 ns = 15.523 ns The SDRAM clock can lead the controller clock by the lesser of Read Lead or Write Lead: Read Lead = t

CO_MIN

(FPGA) – tDH(SDRAM) = 2.399 ns – 1.0 ns = 1.399 ns or Write Lead = t

CLK

– t

(SDRAM) – t

HZ(3)

= 20 ns – 5.5 ns – 5.936 ns = 8.564 ns Therefore, for this example you can shift the phase of the SDRAM clock from –8.107 ns to 1.399 ns

relative to the controller clock. Choosing a phase shift in the middle of this window results in the value (–

8.107 + 1.399)/2 = –3.35 ns.

Document Revision History

Table 2-5: Document Revision History

Date and

Document

Version

July 2014 V14.0

-Removed mention of SOPC Builder, updated to Qsys Maintenance

SU_MAX

Changes Made Summary of Changes

(FPGA)

Release

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Document Revision History

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Date and

Document

Version

December 2010

v10.1.0

July 2010 v10.0.0

November 2009

v9.1.0

March 2009 v9.0.0

November 2008

v8.1.0

Changes Made Summary of Changes

Removed the “Device Support”, “Instantiating the Core in

—

SOPC Builder”, and “Referenced Documents” sections.

No change from previous release. —

Changed to 8-1/2 x 11 page size. No change to content. —

May 2008

No change from previous release. —

v8.0.0

For previous versions of this chapter, refer to the

Quartus II Handbook Archive.

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+ 306 hidden pages

Altera Embedded Peripherals IP User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Embedded Peripheral IP User Guide

Contents

Introduction

Tool Support

Obsolescence

Device Support

Document Revision History

SDRAM Controller Core

Core Overview

Functional Description

Avalon-MM Interface

Off-Chip SDRAM Interface

Signal Timing and Electrical Characteristics

Synchronizing Clock and Data Signals

Clock Enable (CKE) not Supported

Sharing Pins with other Avalon-MM Tri-State Devices

Board Layout and Pinout Considerations

Performance Considerations

Open Row Management

Sharing Data and Address Pins

Hardware Design and Target Device

Configuration

Memory Profile Page

Timing Page

Hardware Simulation Considerations

SDRAM Controller Simulation Model

SDRAM Memory Model

Using the Generic Memory Model

Using the SDRAM Manufacturer's Memory Model

Example Configurations

Software Programming Model

Clock, PLL and Timing Considerations

Factors Affecting SDRAM Timing

Symptoms of an Untuned PLL

Estimating the Valid Signal Window

Example Calculation

Document Revision History