Altera DQ (ALTDQ) User Manual

DQ (ALTDQ) and DQS (ALTDQS)

Megafunctions

UG-MF9304-3.2 User Guide

Introduction

The Quartus®II software provides parameterizable megafunctions ranging from simple arithmetic units, such as adders and counters, to advanced phase-locked loop (PLL) blocks, multipliers, and memory structures. These megafunctions are performance-optimized for Altera devices and therefore provide more efficient logic synthesis and device implementation, because they automate the coding process and save valuable design time. You should use these functions during design implementation so you can consistently meet your design goals.

General Description

This user guide discusses the following topics:

■ General features of the ALTDQ and ALTDQS megafunctions

■ Parameterization of the ALTDQ and ALTDQS megafunctions through the MegaWizard

Plug-In Manager

™

■ Port and parameter definitions of the ALTDQ and ALTDQS megafunctions

The ALTDQ and ALTDQS megafunctions allow you to control the functionality of the DDR I/O pins for each of the device families. Most of the features of the megafunction map directly into features of the I/O element (IOE) for each device family. For Cyclone

that do not have DDR I/O registers in the IOE, the features are implemented in logic cells.

The ALTDQ and ALTDQS megafunctions are provided in the Quartus II software MegaWizard Plug-In Manager. You can configure the DQ and DQS pins as input, output, or bidirectional DDR pins on all the I/O banks of the device, depending on the specific custom external memory interface requirements. Both DQ and DQS are bidirectional (the same signals are used for both writes and reads). A group of DQ pins is associated with one DQS pin. Use the ALTDQ and ALTDQS megafunctions to configure the DQ and DQS paths, respectively.

Device Family Support

The ALTDQ and ALTDQ_DQS megafunctions support the following Altera® device families:

■ Arria

■ Cyclone II

■ Cyclone III

■ Cyclone IV GX

■ HardCopy

II devices

© 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in

101 Innovation Drive San Jose, CA 95134

www.altera.com

November 2010 Altera Corporation

accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Page 2 Introduction

■ Stratix

■ Stratix GX

■ Stratix II

■ Stratix II GX

ALTDQ Megafunction

The ALTDQ megafunction allows you to easily configure the DDR I/O elements in supported Altera devices for DQ data signal functionality. The ALTDQ megafunction is a variation of the ALTDDIO_BIDIR megafunction modified to be used with the ALTDQS megafunction.

The ALTDQ megafunction implements a DDR interface and offers many additional features, which include:

■ Transmission and reception of data on both edges of the reference clock

■

ddioinclk

devices only)

■ Active high asynchronous clear and clock-enable control inputs

■ Registered or unregistered output-enable input

clock input for the negative-edge input register (available for Stratix II

ALTDQS Megafunction

The ALTDQS megafunction allows you to easily configure the I/O elements of the data strobe (DQS) in supported Altera devices.

You typically use the ALTDQS megafunction used with the ALTDQ megafunction which provides the following features:

■ A group of DQS pins used to strobe the read and write data in external DDR

memory interfaces using a common DLL to phase shift the read strobe

■ Implementing one DLL and a number of user-specified DQS pins (the maximum

number of DQS supported by a DLL is also dependent on the device side)

■ Clocks generated for the DQ negative-edge input registers from the DQSn pins

that is the

■ Delay buffer setting output option

■ Frequency settings of DQS inputs and system reference clock

■ Active-high asynchronous clear and clock-enable control inputs

■ Registered or unregistered output-enable input

■ DQS outputs configurable as open drain mode

■ Speed setting of the DQS and delay buffers as either low or high (available for

Stratix II devices only)

dqddioinclk[]

signal (available for Stratix II devices only)

DQ (ALTDQ) and DQS (ALTDQS) Megafunctions November 2010 Altera Corporation

Getting Started Page 3

Common Applications

The ALTDQ and ALTDQS megafunctions implement proprietary interfaces and variations of the external memories that require features not supported by the Altera SDRAM controller and external memory interfaces.

1 You should use the clear-text data path generated by the DDR SDRAM Controller to

implement all DDR SDRAM, DDR2 SDRAM, RLDRAM II, and QDRII systems. This data path has been validated by Altera and you can generate this data path for many variations of these interfaces. To use the clear text data path, you need not purchase or instantiate the Altera DDR SDRAM controller IP.

f For more information, refer to the DDR & DDR2 SDRAM Controller Compiler User

Guide, RLDRAM II Controller MegaCore Function User Guide, and QDRII SRAM Controller MegaCore Function User Guide.

Resource Utilization and Performance

f For details about the resource utilization and performance of ALTDQ and ALTDQS

megafunctions, refer to the MegaWizard Plug-In Manager and the compilation reports for each device in the Quartus II software.

Getting Started

f The instructions in this section require the Quartus II software version 9.1 or later. For

operating system support information, refer to the Operation System Support page on the Altera website.

MegaWizard Plug-In Manager Page Option and Description for ALTDQS Megafunction

Tab le 1 defines the parameterization options that are available in the MegaWizard

Plug-In Manager for the ALTDQS megafunction.

Table 1. MegaWizard Plug-In Manager Page Option and Description

Page Option Description

You can select from the following options: Create a new custom megafunction variation, Edit an existing custom megafunction variation, or Copy an existing custom megafunction variation.

Select ALTDQS from the I/O category.

Specify the device family you want to use.

You can choose from AHDL (.tdf), VHDL (.vhd), or Verilog HDL (.v) as the output file type.

Specify the file name without the file extension.

Which action do you want to perform?

Select a megafunction from the list below

Which device family will you be using?

Which type of output file do you want to create?

What name do you want for the output file?

November 2010 Altera Corporation DQ (ALTDQ) and DQS (ALTDQS) Megafunctions

Page 4 Getting Started

Page 3 of the ALTDQS parameter editor is the General page. Table 2 on pag e 4 describes options available on page 3 of the ALTDQS megafunction.

Table 2. General Settings (Part 1 of 3)

Supported Devices

Option Description

Cyclone II

Stratix, Stratix GX,

Cyclone III, Cyclone IV GX

Stratix II, Stratix II GX, Arria GX, HardCopy II

Currently selected device family Displays the currently selected device family. Yes Yes Yes Yes

What is the frequency of the DQS input(s) ?

This is the input DQS frequency. (1) Yes Yes No No

Specifies the number of DQS pins that are

How many DQS pins would you like?

implemented or the number of DQS/DQSn pin pairs generated.The maximum number of pins possible depends on the chosen device and the

Yes Yes Yes Yes

'dqsn_padio' port option. (2)

This enables the DQS output path. Turn on this

Create an output enable for the DQS pins

option to create an output enable for the DQS pins. If you select the no output enable port is used option, the

dqs_padio

signal drives out

Yes Yes Yes Yes

permanently.

This enables the DQS OE path. Turn on this

option to register the output enable port with

outclk

the

■ DLL feedback loop counter controls the

signal.

Yes Yes Yes Yes

DQS/nDQS delay chains

What will control the DQS/nDQS delay chains?

This is the default option. DLL inserts a delay equivalent to requested phase-shift at input clock frequency. Input clock frequency and phase-shift are set on page 4. (3)

■ No DLL is used

Yes Yes

Yes.

Always

uses DLL.

Yes. Have an option

to choose either DLL or no DLL.

No DLL and no delay is added between the DQS/nDQS and the

dqinclk

port.

DQ (ALTDQ) and DQS (ALTDQS) Megafunctions November 2010 Altera Corporation

Getting Started Page 5

Table 2. General Settings (Part 2 of 3)

Supported Devices

Option Description

Cyclone II

Stratix, Stratix GX,

Cyclone III, Cyclone IV GX

Stratix II, Stratix II GX, Arria GX, HardCopy II

This can be either a setting in ps or a value from 0-63. This is the user-requested delay on the clock delay control block. Delay is specified either by number of delay buffers used or desired time delay. Time delay is converted to number of buffers during compilation. For the

How should the delay chain be specified?

actual buffer delay, refer to the respective device data sheet.

Yes

(5)

No No

These buffers have a fixed delay, which is not dependent on input clock frequency clock delay control circuit on each DQS pin allows a phase shift that center-aligns the incoming DQS signals within the data window of their corresponding DQ data signals. (4)

Inhibits the

ddioinclk

signal during read

postamble (when the DQS transitions from 0 to

Allow DQS to be disabled during read post-amble.

Z). Stops the

ddioinclk

signal from creating false clocks as the DQS goes to tristate. If selected, adds an stop the

ddioinclk

enable_dqs

signal.

input port to

Yes

(6)

No No

November 2010 Altera Corporation DQ (ALTDQ) and DQS (ALTDQS) Megafunctions

Page 6 Getting Started

Table 2. General Settings (Part 3 of 3)

Supported Devices

Option Description

Cyclone II

Stratix, Stratix GX,

Cyclone III, Cyclone IV GX

Stratix II, Stratix II GX, Arria GX, HardCopy II

Invert dqs_padio port (when driving output)

Notes to Table 2:

(1) For supported DQS frequencies in these devices, refer to the “Cyclone II DDR Memory Support Overview” section of the External Memory

Interfaces in Cyclone II Devices chapter in volume 1 of the Cyclone II Device Handbook or the “Introduction” section of the External Memory Interfaces in Cyclone III Devices chapter in volume 1 of the Cyclone III Device Handbook.

(2) For number of DQS/DQSn pair pins available in supported devices, refer to the External Memory Interfaces in Arria GX Devices chapter in volume

2 of the Arria GX Device Handbook, External Memory Interfaces in Cyclone II Devices chapter in volume 1 of the Cyclone II Device Handbook,

External Memory Interfaces in Cyclone III Devices chapter in volume 1 of the Cyclone III Device Handbook, External Memory Interfaces in Stratix and Stratix GX Devices chapter in volume 2 of the Stratix Device Handbook, or the External Memory Interfaces in Stratix II and Stratix II GX Devices chapter in volume 2 of the Stratix Device Handbook.

(3) The delay-locked loop (DLL) controls the delay chain settings to achieve a compensated delay for PVT. For example, you can use a DQS read

strobe or clock that is edge-aligned to its associated read data to clock the data into I/O registers if the data is delayed before reaching the register. The DLL block computes the necessary delay settings by comparing the period of an input reference clock to the delay through an internal delay chain. For more information about DLL, refer to the “DQS Phase-Shift Circuitry” section of the External Memory Interfaces in

Stratix and Stratix GX Devices chapter in volume 2 of the Stratix Device Handbook, External Memory Interfaces in Stratix II and Stratix II GX Devices chapter in volume 2 of the Stratix Device Handbook, and External Memory Interfaces in Arria GX Devices chapter in volume 2 of the

Arria GX Device Handbook.

(4) For more information about the clock delay control block, refer to the “Clock Delay Control” section of the External Memory Interfaces in Cyclone

II Devices chapter in volume 1 of the Cyclone II Device Handbook.

(5) For Cyclone III, Cyclone III GX, and Cyclone III LS devices, you must use the "Input Delay from Dual-Purpose Clock Pin" assignment in the

Assignment Editor to set DQS clock delay.

(6) For more information about the DQS postamble circuitry, refer to the “DQS Postamble” section of the External Memory Interfaces in Cyclone II

Devices chapter in volume 1 of the Cyclone II Device Handbook.

When you select this option, the

dqs_padio

port is inverted, if driven as an output.

Yes Yes No No

DQ (ALTDQ) and DQS (ALTDQS) Megafunctions November 2010 Altera Corporation

Getting Started Page 7

Page 4 of the ALTDQS parameter editor is the General 2 page. Table 3 on pag e 7 describes options available on page 4 of the ALTDQS megafunction.

Table 3. General 2 Settings (Part 1 of 2)

Supported Devices

Option Description

Cyclone II

Stratix, Stratix GX,

Cyclone III, Cyclone IV GX

Stratix II, Stratix II GX, Arria GX, HardCopy II

What is the frequency of the DQS inputs(s)?

The input clock frequency for the signals. For the supported frequencies, refer to the “External Memory” chapter in the respective device

inclk

outclk

No No Yes Yes

handbook.

Controls internal set up of delay chains. Available options depend upon the DQS frequency you

What is the frequency mode?

entered. (1)

No No Yes Yes

For the respective modes, refer to the respective device datasheet.

What is the delay buffer mode?

What is the DLL delay chain length?

How much phase shifting would you like to use for the DQS clock?

Only available in custom frequency mode. Delay buffers can be set for High or Low delay modes.

Option only available in custom frequency mode. A delay chain length of 10, 12, or 16 buffers may be implemented.

Select phase-shift with pull-down options of 0, 72, or 90°. The values calculated from previously specified delay buffer mode and DLL delay chain setting.

Inhibits the

ddioinclk

signal during read postamble

No No Yes Yes

(when DQS transitions from 0 to Z). This stops the

ddioinclk

signal from creating false clocks as the DQS goes into a tri-state. The device architecture cannot implement this option on the DQSn port.

Allow DQS to be disabled during read post-amble

Therefore, if you select this option, the DQSn port may only be used as an output (or left used). The

ddioinclk

signal is inhibited by a register clocked

No No Yes Yes

by the DLL delayed DQS.

The

dqs_areset

this register. You must set the

due to architectural constraints and control the

ddioinclk

and

dqs_sreset

signal using

signals control

dqs_sreset

dqs_areset

signal to

signal.

November 2010 Altera Corporation DQ (ALTDQ) and DQS (ALTDQS) Megafunctions

Page 8 Getting Started

Table 3. General 2 Settings (Part 2 of 2)

Supported Devices

Option Description

Cyclone II

Stratix, Stratix GX,

Cyclone III, Cyclone IV GX

Stratix II, Stratix II GX, Arria GX, HardCopy II

Only affects simulation and has no affect on actual

How many valid half cycles of the inclk input should pass before the DLL simulates a lock?

device operation. Use to reduce number of clock cycles for which a simulation must be run before the DLL locks. By setting this to 1, the DLL immediately

No No Yes Yes

locks and simulation can begin transferring data.

How many invalid half clock cycles of the inclk input should pass before the DLL simulates a loss of lock? (2)

Notes to Table 3:

(1) Low/high refers to jitter mode. The DLL in Stratix II device DQS phase-shift circuitry can operate between 100 and 300 MHz in either fast lock

mode or low jitter mode. Fast lock mode requires fewer clock cycles to calculate the input clock period, but the low jitter mode is more accurate. The DQS delay settings (the up/down counter output) are updated every eight clock cycles. If the low jitter mode is enabled, the phase comparator also issues a clock-enable signal to the up/down counter notifying the counter when to update the DQS settings. In low jitter mode, the enable signal is only active when the settings do not get updated. This enable signal is always active if the DLL is in fast lock mode.

(2) Stratix II devices do not support this feature, and the option is disabled in the MegaWizard Plug-In Manager for these devices.

Only affects simulation and has no affect on actual device operation. Use to reduce number of clock cycles for which a simulation must be run before the

No No Yes Yes

DLL locks. By setting this to 1, the DLL immediately locks and simulation can begin transferring data.

upndn

signal is incremented or decremented by 4, otherwise the clock-enable is off and the DQS delay

DQ (ALTDQ) and DQS (ALTDQS) Megafunctions November 2010 Altera Corporation

Getting Started Page 9

Page 5 of the ALTDQS parameter editor is the Output Registers page. Tabl e 4 o n

page 9 describes options available on page 5 of the ALTDQS megafunction.

Table 4. Output Register Settings

Supported Devices

Option Description

Cyclone II

Stratix, Stratix GX,

Cyclone III, Cyclone IV GX

Stratix II, Stratix II GX, Arria GX, HardCopy II

What effect should the ‘dqs_areset’ port have on output registers?

Use the

dqs_areset

preset or clear output registers. If you select the None option, the signal is not instantiated and you can specify the power-up state of the output

port to asynchronously

Yes Yes Yes Yes

registers

What effect should the ‘dqs_sreset’ port have on output registers? (1)

Use the

dqs_sreset

preset or clear output registers. If you select the None option, the port is not instantiated. (2)

port to synchronously

Yes Yes Yes Yes

If you selected None for the What effect should

How should the output registers powerup? (1)

the ‘dqs_areset’ port have on output registers? option, use this option to specify

Yes Yes Yes Yes

power-up condition of output registers.

Use clock enable for the output register

(3)

Notes to Table 4:

(1) Cyclone II devices do not support this feature. Option is disabled when Cyclone II device family is selected. (2) This option is not available for Stratix II devices if the Allow DQS to be disabled during read postamble option has been selected on a previous

page of the wizard (refer to Table 3 on page 7).

(3) This option is enabled only when Register the output enable option is turned on in page 3 of the MegaWizard Plug-In Manager.

Create the for the output registers). Use as a clock enable for the output registers.

outclkena

port (if not implemented

Yes Yes Yes Yes

November 2010 Altera Corporation DQ (ALTDQ) and DQS (ALTDQS) Megafunctions

Page 10 Getting Started

Page 6 of the ALTDQS parameter editor is the Output Enable Registers page. Tab le 5

on page 10 describes options available on page 6 of the ALTDQS megafunction.

Table 5. Output Enable Registers Settings

Supported Devices

Option Description

Cyclone II

Stratix, Stratix GX,

Cyclone III, Cyclone IV GX

Stratix II, Stratix II GX, Arria GX, HardCopy II

What effect should the ‘dqs_areset’ port have on output enable registers?

Use the

dqs_areset

Preset or Clear the output-enable registers. If set to None, the port is not instantiated and you have the option to specify the power-up state of output

port to asynchronously

Yes Yes Yes Yes

enable registers.

What effect should the ‘dqs_sreset’ port have on output enable registers? (1)

Use the

dqs_areset

Preset or Clear output enable registers. If set to None, the

dqs_areset

port to synchronously

port is not instantiated.

Yes Yes Yes Yes

(2)

If None is selected for the What effect should the How should the output enable registers power-up? (1)

‘dqs_areset’ port have on output enable

registers?option, use this option to specify

Yes Yes Yes Yes

power-up condition of output-enable registers.

Hold output drive at high impedance for an extra half-clock cycle when output enable goes high

Use clock enable for the output enable register

Notes to Table 5:

page of the MegaWizard Plug-In Manager (refer to Table 3 on page 7).

Delays DQS write mode by half a clock cycle. The

DQS transitions from Z to 0, providing a cleaner

start to sequence than a Z to 1 transition.

Creates the

outclkena

port (if not implemented for output enable register). Use as a clock-enable for output enable register.

Yes Yes Yes Yes

DQ (ALTDQ) and DQS (ALTDQS) Megafunctions November 2010 Altera Corporation

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