Altera Double Data Rate I/O User Manual

2015.01.23

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Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT,

and ALTDDIO_BIDIR) IP Cores User Guide

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®

The Altera

®

DDR I/O megafunction IP cores configure the DDR I/O registers in APEX™ II, Arria

series, Cyclone® series, HardCopy® series, and Stratix® series devices.
You can also use these IP cores to implement DDR registers in the logic elements (LEs). In Arria GX,

Stratix series, HardCopy II, HardCopy Stratix, and APEX II devices, the DDR registers are implemented
in the I/O element (IOE). In Cyclone series devices, the IP cores automatically implement the DDR
registers in the LEs closest to the pin. The ALTDDIO_IN IP core implements the interface for DDR
inputs. The ALTDDIO_OUT IP core implements the interface for DDR outputs. The ALTDDIO_BIDIR
IP core implements the interface for bidirectional DDR inputs and outputs.

ALTDDIO Features

The ALTDDIO IP cores implement a DDR interface and offer the following additional features:

• The ALTDDIO_IN IP core receives data on both edges of the reference clock

• The ALTDDIO_OUT IP core transmits data on both edges of the reference clock

• The ALTDDIO_BIDIR IP core transmits and receives data on both edges of the reference clock

• Asynchronous clear and asynchronous set input options available

• Synchronous clear and synchronous set input options available for Arrix GX and Stratix series devices.

• inclock signal to sample the DDR input

• outclock signal to register the data output

• Clock enable signals

• Bidirectional port for the ALTDDIO_BIDIR IP core

• An output enable input for the ALTDDIO_OUT and ALTDDIO_BIDIR IP cores

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ALTDDIO Common Applications

DDR registers capture and/or send data at twice the rate of the clock or data strobe to interface with a
memory device or other high-speed interface application in which the data is clocked at both edges of the
clock.

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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
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DDR SDRAM, DDR2 SDRAM and RLDRAM II Memory

The DDR registers interface with DDR SDRAM, DDR2 SDRAM, RLDRAM II, QDR SRAM, and QDRII
SRAM memory devices. You can also use the DDR I/O registers as a SERDES bypass mechanism in LVDS
applications. This section provides information about the following DDR I/O applications:

• DDR SDRAM, DDR2 SDRAM, and RLDRAM II memory interfaces

• QDR SRAM and QDRII SRAM memory interfaces

• High-speed interface applications

DDR SDRAM, DDR2 SDRAM and RLDRAM II Memory

DDR SDRAM, DDR2 SDRAM, and RLDRAM II write and read data at twice the clock rate by capturing
data on both the positive and negative edge of a clock.

DDR and DDR2 SDRAM are JEDEC standards. RLDRAM II devices have minimal latency to support
designs that require fast response times. These DDR memory interfaces use a variety of I/O standards,
such as SSTL-II, 1.8-V HSTL, LVTTL, and LVCMOS.

Related Information

DDR and DDR2 SDRAM Controller MegaCore Functions

The DDR and DDRII SDRAM controller is available by downloading the Altera DDR SDRAM Controller
MegaCore function

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QDR SRAM and QDRII SRAM Memory Interfaces

The QDR and QDRII SRAM standard is defined jointly by Cypress Semiconductor Corporation,
Integrated Device Technology, Inc., and Micron Technology, Inc.

QDR and QDRII SRAMs have separate DDR read and write ports that pass data concurrently. The
combination of concurrent transactions and DDR signaling allows data to be passed four times faster than
by conventional SRAMs. The I/O standards used for QDR SRAM devices are 1.5-V HSTL class I and II.
QDRII SRAMs use both 1.5-V and 1.8-V HSTL class I.

High-Speed Interface Applications

High-speed interface applications use various differential standards, such as LVDS, LVPECL, PCML, or
HyperTransport technology to transfer data.

These standards often use DDR data. Stratix series devices implement high-speed standards either by
using the dedicated differential I/O SERDES blocks or by bypassing SERDES and using the DDR I/O
circuitry in SERDES bypass mode. DDR IP cores, PLLs, and shift registers are all used in SERDES
functionality.

Related Information

• External Memory Interfaces in Stratix II and Stratix II GX Devices

• Implementing Double Data Rate I/O Signaling in Cyclone Devices

• AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices

ALTDDIO Resource Utilization and Performance

For details about the resource utilization of the ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR
IP cores in various devices, and the performance of devices that include these IP cores, refer to the
Parameter Editor and the compilation reports for each device.

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ALTDDIO Parameter Settings

These tables list the parameter settings for the ALTDDIO IP cores.

Table 1: ALTDDIO_IN Parameter Settings

This table lists the parameter settings for the ALTDDIO_IN IP core.

Parameter Description

Currently selected device family Specify the Altera® device family you are using.
Width: (bits) Specify the width of the data buses.
Asynchronous clear and asynchronous set ports Select Use ‘aclr’ port for asynchronous clear (aclr).

ALTDDIO Parameter Settings

Select Use ‘aset’ port for asynchronous preset (aset)
.

If you are not using any of the asynchronous clear
options, select Not used and specify whether
registers should power up high or low by turning
on/off Registers power up high.

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Synchronous clear and synchronous set ports Select Use ‘sclr’ port for synchronous clear (sclr).

Select Use ‘sset’ port for synchronous preset (sset).
If you are not using any of the synchronous clear
options, select Not used.

The synchronous reset option is available for
Arria GX, Stratix III, Stratix II, Stratix II GX,
Stratix, Stratix GX, HardCopy II, and HardCopy
Stratix devices only.

Use ‘inclocken’ port Turn on this option to add a clock enable port that

controls when data input is clocked in. This signal
prevents data from being passed through.

Invert input clock When enabled, the first bit of data is captured on

the rising edge of the input clock. If not enabled, the
first bit of data is captured on the falling edge of the
input clock.

Table 2: ALTDDIO_OUT Parameter Settings

This table lists the parameter settings for the ALTDDIO_OUT IP core.

Parameter Description

Currently selected device family Specify the Altera device family you are using.
Width: (bits) Specify the width of the data buses.

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ALTDDIO Parameter Settings

Parameter Description

Asynchronous clear and asynchronous set ports Select Use ‘aclr’ port for asynchronous clear (aclr).

Select Use ‘aset’ port for asynchronous preset (aset)
.

If you are not using any of the asynchronous clear
options, select Not used and specify whether
registers should power up high or low by turning
on/off Registers power up high.

Use ‘outclocken’ port Turn on this option to add a clock enable port to

control when data output is clocked in. This signal
prevents data from being passed through.

Invert ‘dataout’ output Turn on this option to invert the dataout[] output

port. This option is available for Cyclone III and
Cyclone II devices only.

Use output enable port Turn on this option to create an output enable input

port (oe) to control when the data is set out to the

dataout port.

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Use ‘oe_out’ port to connect to tri-state output
buffer(s)

Turn on this option to create an output enable port
for the bidirectional padio port. This port is
available for Stratix III and Cyclone III devices only.

Register ‘oe’ port Turn on this option tp register the output-enable

(oe) input port.

Delay switch-on by half a clock cycle Turn on this option to use an additional oe register.

When the additional oe register is used, the output
pin is held at high impedance for an extra half clock
cycle after the oe port goes high.

Synchronous clear and synchronous set ports Select Use ‘sclr’ port for synchronous clear (sclr).

Select Use ‘sset’ port for synchronous preset (sset).
If you are not using any of the synchronous clear
options, select Not used.

The synchronous reset option is available for
Arria GX, Stratix III, Stratix II, Stratix II GX,
Stratix, Stratix GX, HardCopy II, and HardCopy
Stratix devices only.

Table 3: ALTDDIO_BIDIR Parameter Settings

This table lists the parameter settings for the ALTDDIO_BIDIR IP core. The ALTDDIO_BIDIR IP core combines
the ALTDDIO_IN and ALTDDIO_OUT IP core functionality into a single IP core, which instantiates
bidirectional DDR ports.

Parameter Description

Currently selected device family Specify the Altera device family you are using.

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Width: (bits) Specify the width of the data buses.
Asynchronous clear and asynchronous set ports Select Use ‘aclr’ port for asynchronous clear (aclr).

Synchronous clear and synchronous set ports Select Use ‘sclr’ port for synchronous clear (sclr).

ALTDDIO Parameter Settings

Parameter Description

Select Use ‘aset’ port for asynchronous preset (aset)
.

If you are not using any of the asynchronous clear
options, select Not used and specify whether
registers should power up high or low by turning
on/off Registers power up high.

Select Use ‘sset’ port for synchronous preset (sset).
If you are not using any of the synchronous clear
options, select Not used.

The synchronous reset option is available for
Arria GX, Stratix III, Stratix II, Stratix II GX,
Stratix, Stratix GX, HardCopy II, and HardCopy
Stratix devices only.

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Invert ‘padio’ port The ‘padio’ port is inverted whenever driven as an

output. This option is available for Cyclone III and
Cyclone II devices only.

Use ‘inclocken’ and ‘outclocken’ ports Turn on this option to add a clock enable port to

control when data input and output are clocked in.
This signal prevents data from being passed
through.

Use output enable port Turn on this option to create an output enable input

port (oe) to control when the data is set out to the

dataout port.

Use oe_out port to connect to tri-state output
buffer(s)

Output enable for the bidirectional padio port. This
port is available for Stratix III and Cyclone III
devices only.

Register ‘oe’ port Turn on this option to register the output-enable

(oe) input port.

Delay switch-on by a half clock cycle Turn on this option to use an additional oe register.

When the additional oe register is used, the output
pin is held at high impedance for an extra half clock
cycle after the oe port goes high.

Use ‘combout’ port Use the optional data port combout. The combout

port sends data to the core, bypassing the DDR I/O
input registers. For bidirectional operation, you
must enable the dataout_h and dataout_l ports,
the combout port, or both.

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D Q

DFF

D Q

LATCH

ENA

D Q

DFF

INPUT

datain

inclock

neg_reg_out

dataout_l

dataout_h

Input Register A

Input Register B

Latch C

Latch

Logic
Array

I

I

I

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ALTDDIO Functional Description

Parameter Description

Use ‘dqsundelayedout’ port Creates undelayed output from the DQS pins. If you

use the ALTDDIO_BIDIR IP core for your DQS
signal in an external memory interface, you route
the undelayed DQS signal to the LE, in Stratix II and
Stratix devices. This option is available in Stratix,

Stratix GX, and HardCopy Stratix devices only.
Use ‘dataout_h’ and ‘dataout_l’ ports Enables the dataout_h and dataout_l ports.
Implement input registers in LEs Implements the input path in logic elements. This

option is available only if the dataout_h and

dataout_l ports are enabled.

ALTDDIO Functional Description

DDR Device Configuration

The following sections describe how the DDR registers are configured in the Stratix series and APEX II
devices.

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Input Configuration

When the IOE is configured as an input pin, input registers AI and BI and latch CI implement the input
path for DDR I/O.

Figure 1: Input DDR I/O Path Configuration for a Stratix Series or APEX II Device

This figure shows an IOE configured for DDR inputs for a Stratix series or APEX II device.

Note:

On the falling edge of the clock, the negative-edge triggered register BI acquires the first data bit.
On the corresponding rising edge of the clock, the positive-edge triggered register AI acquires the
second data bit. For a successful data transfer to the logic array, the latch CI synchronizes the data
from register BI to the positive edge of the clock.

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CLRN/PRN

D Q

ENA

Chip-Wide Reset

Input Register

CLRN/PRN

D Q

ENA

Input Register

VCCIO

VCCIO

PCI Clamp

Programmable
Pull-Up
Resistor

Column, Row,

or Local

Interconnect

DQS Local

Bus

To DQS Logic

Block

ioe_clk[7..0]

Bus-Hold

Circuit

CLRN/PRN

D Q

ENA

Latch

Input Pin to

Input RegisterDelay

sclr/spreset

clkin

aclr/apreset

On-Chip

Termination

ce_in

(2)

(3)

(4)

1) All input signals to the IOE can be inverted at the IOE.

2) This signal connection is only allowed on dedicated DQ function pins.

3) This signal is for dedicated DQS function pins only.

4) The optional PCI clamp is only available on column I/O pins.

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Figure 2: Stratix II IOE in DDR Input I/O Configuration

Output Configuration

This figure shows an IOE configured for DDR inputs for a Stratix or Stratix II device.

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Output Configuration

The dedicated output registers for Stratix series and APEX II devices are labeled AO and BO. These
positive-edge triggered registers and a multiplexer are used to implement the output path for DDR I/O.

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