Altera DDR Timing Wizard User Manual
101 Innovation Drive
San Jose, CA 95134
http://www.altera.com
UG-DDRTMNG-3.0
DDR Timing Wizard
User Guide
Document Version: 3.0
Document Date: November 2007
Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company,
the stylized Altera logo, specific device designations, and all other words and logos that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their re-
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Technical Support:
www.altera.com/support/
Literature Services:
spective holders. Altera products are protected under numerous U.S. and foreign patents and pending
applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products
to current specifications in a ccordance with Altera's standard warranty, but reserve s the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability
arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Altera Corporation. Altera customers
are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
literature@altera.com
ii Altera Corporation
Table of Contents
About this User Guide .............................................................................. v
Revision History .................................................................................................................................... 1–v
How to Contact Altera .......................................................................................................................... 1–v
Typographic Conventions .................................................................................................................. 1–vi
Chapter 1. About the DDR Timing Wizard
Release Information ............................................................................................................................... 1–1
Device Family Support ......................................................................................................................... 1–2
Introduction ............................................................................................................................................ 1–2
Background ....................................................................................................................................... 1–2
DDR Timing Wizard ........................................................................................................................ 1–3
Features ................................................................................................................................................... 1–6
Chapter 2. Getting Started
System and Software Requirements ................................................................................................... 2–1
Design Flow ............................................................................................................................................ 2–1
Launching the DDR Timing Wizard ................................................................................................... 2–5
Entering and Editing Inputs to the DTW ........................................................................................... 2–6
Import Flow for the Altera Legacy Memory Controller IP Core or Recommended Data Path
.............................................................................................................................................................. 2–7
Manual Flow for Other External Memory Interfaces or Source Synchronous Systems ...... 2–14
The DTW Pages for DDR/DDR2 SDRAM ............................................................................ 2–14
The DTW Pages for QDRII+/QDRII SRAM & RLDRAM II ............................................... 2–45
DTW Limitations ................................................................................................................................. 2–46
Chapter 3. Using the dtw_timing_analysis.tcl Script
Introduction ............................................................................................................................................ 3–1
Running dtw_timing_analysis.tcl Script ....................................................................................... 3–3
The dtw_timing_analysis.tcl Script Results .................................................................................. 3–6
Timing Closure Process ...................................................................................................................... 3–12
Timing Closure Differences in DDR2/DDR SDRAM, QDRII+/QDRII SRAM, and RLDRAM II
Interfaces .......................................................................................................................................... 3–14
DDR2/DDR SDRAM Interfaces ............................................................................................. 3–14
QDRII+/QDRII SRAM Interfaces ........................................................................................... 3–14
RLDRAM II Interfaces .............................................................................................................. 3–15
Selecting Initial Phase Shifts ......................................................................................................... 3–16
Re-run DTW After First Compile When Using Classic Timing Analyzer ............................. 3–18
Ensure the Changes Made Outside Legacy Controller MegaWizard Are Not Erased When the
Core is Regenerated ....................................................................................................................... 3–19
Decide When to Change Clock Phase Shift ................................................................................ 3–21
Altera Corporation iii
November 2007
Table of Contents DDR Timing Wizard User Guide
Changing Clock Phase Shift .......................................................................................................... 3–23
Adjusting Clock Cycle Selections ................................................................................................. 3–25
Changing Clock Cycles .................................................................................................................. 3–27
Changing the Address/Command Clock Connection and Phase Shift ................................. 3–28
Moving the Data Path Registers Closer to the Pins ................................................................... 3–30
Conclusion ............................................................................................................................................ 3–32
iv Altera Corporation
November 2007
About this User Guide
Revision History
Chapter Date
All November 2007 3.0 ● Replaced all references to “IP Tool Bench” to “legacy controller
All July 2007 2.1
All December 2006 2.0
All May 2006 1.0
How to Contact Altera
The table below displays the revision history for the chapters in this user
guide.
Document
Version
MegaWizard” and “altmemphy” to “ALTMEMPHY”.
● Updated the Entering and Editing Inputs to the DTW section in
Chapter 2. Getting Started for Quartus II 7.2 support.
● Added Chapter 3. Using the dtw_timing_analysis.tcl Script to
replace the Performing Timing Analysis section.
● Changed title of referenced document to: AN 413, Using Legacy
Integrated Static Data Path and Controller Megafunction with
Hardcopy II Structured ASICs.
● Updated document for Quartus II version 6.1 software.
● Added design flow.
● Introduced dtw_timing_analysis.tcl and usage.
● Introduced the clock uncertainties option.
● Initial version of the document.
Changes Made
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com. For technical support on
this product, go to www.altera.com/mysupport. For additional
information about Altera products, consult the sources shown below.
Information Type USA & Canada All Other Locations
Technical support www.altera.com/mysupport/ www.altera.com/mysupport/
Product literature www.altera.com (1) www.altera.com (1)
Altera literature services literature@altera.com literature@altera.com
FTP site ftp.altera.com ftp.altera.com
Note to table:
(1) You can also contact your local Altera sales office or sales representative.
Altera Corporation v
November 2007 Preliminary
Typographic Conventions DDR Timing Wizard User Guide
Typographic
This document uses the typographic conventions shown below.
Conventions
Visual Cue Meaning
Bold Type with Initial
Capital Letters
bold type External timing parameters, directory names, project names, disk drive names,
Italic Type with Initial Capital
Letters
Italic type Internal timing parameters and variables are shown in italic type.
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:
“Subheading Title” References to sections within a document and titles of on-line help topics are
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,
1., 2., 3., and
a., b., c., etc.
● • Bullets are used in a list of items when the sequence of the items is not important.
■
v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.
c
w
r The angled arrow indicates you should press the Enter key.
f The feet direct you to more information on a particular topic.
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
filenames, filename extensions, and software utility names are shown in bold
type. Examples: f
Document titles are shown in italic type with initial capital letters. Example: AN
75: High-Speed Board Design.
Examples: t
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Delete key, the Options menu.
shown in quotation marks. Example: “Typographic Conventions.”
PIA
, \qdesigns directory, d: drive, chiptrip.gdf file.
MAX
, n + 1.
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example:
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword
Courier.
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.
The warning indicates information that should be read prior to starting or
continuing the procedure or processes
c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
vi Altera Corporation
Preliminary November 2007
1. About the DDR Timing Wizard
Release Information
Table 1–1 shows the first Quartus® II software version that supports the
DDR Timing Wizard (DTW) Tcl script for each device family. The
dtw_timing_analysis.tcl script supports Quartus II version 6.0 SP1 and
higher.
Table 1–1. DTW Release Information
Device Family Quartus II Version
Stratix®III (1)
Stratix II 5.1
Stratix II GX 6.0
®
HardCopy
Cyclone
Note to Ta b l e 1– 1 :
(1) Stratix III support is only for migration of legacy PHY designs from Stratix II
II
®
II
devices. Any new Stratix III designs containing a memory interface must use the
ALTMEMPHY-based controllers. DTW and the dtw_timing_analysis.tcl script
do not support ALTMEMPHY.
6.1
5.1
6.0
Use DTW and the dtw_timing_analysis.tcl script to constrain and report
your memory interface timing when using the legacy integrated static
data path and controller.
1 The legacy integrated static data path and controller is referred
to as the legacy controller from this point onwards in this
document.
f Altera
®
also offers memory interfaces with dynamically calibrated
resynchronization using the ALTMEMPHY megafunction. For more
information about ALTMEMPHY-based memory controllers, refer to the
ALTMEMPHY Megafunction User Guide.
Altera Corporation 1–1
November 2007
Device Family Support
Device Family
Support
Introduction
The DTW Tcl script provides full support for the target Altera device
families and memory interfaces listed in Table 1–2. In Quartus II software
version 6.0 SP1, the dtw_timing_analysis.tcl script was created to
supplement DTW. The dtw_timing_analysis.tcl script supports the same
device family and external memory interface combinations as the DTW.
Table 1–2. Device Family and External Memory Support for Quartus II
version 7.2
Device Family External Memory Supported (2)
Stratix III (1) DDR2/DDR SDRAM, QDRII+/QDRII SRAM, RLDRAM II
Stratix II DDR2/DDR SDRAM, QDRII+/QDRII SRAM, RLDRAM II
Stratix II GX DDR2/DDR SDRAM, QDRII+/QDRII SRAM, RLDRAM II
HardCopy II DDR2/DDR SDRAM, QDRII+/QDRII SRAM, RLDRAM II
Cyclone II DDR2/DDR SDRAM
Notes to Ta b l e 1– 2
(1) DTW support for Stratix III devices is only for design migration from Stratix II
devices. Any new Stratix III designs containing a memory interface must use the
ALTMEMPHY solution. DTW and the dtw_timing_analysis.tcl script do not
support ALTMEMPHY.
(2) DTW constrains the data path timing for these memory interfaces. The example
driver and the controller are not constrained by the DTW.
:
External memory interfaces have timing requirements that must be met
for both the FPGA and the memory devices. Some timing requirements,
such as controller f
, can be analyzed by the Quartus II software and
MAX
easily met, but some timing requirements need further analysis or
manual handling. To meet these timing requirements, you should
constrain the placements of the registers or specify timing constraints for
the Quartus II software to optimize during compilation.
Background
Previously, the legacy controller MegaWizard generated a script to
constrain critical registers for the system called
auto_add_ddr_constraints.tcl. This script was used with the
verify_timing.tcl script, which was run to verify the system timing based
on these constraints. The verify_timing.tcl script, however, made some
assumptions that may not have been true for your design. For example,
the verify_timing.tcl script assumed that all clocks used for the memory
interface were using the global clock networks, so if you used a regional
clock network, some of the timing reported by the verify_timing.tcl
script may not have been accurate.
1–2 Altera Corporation
DDR Timing Wizard User Guide November 2007
About the DDR Timing Wizard
1 The new ALTMEMPHY megafunction, introduced in Quartus II
version 6.1 uses timing constraints generated by the
ALTMEMPHY MegaWizard, so that you do not need to use
DTW to constrain the design. DTW does not support
ALTMEMPHY-based memory controllers.
In addition to possible inaccurate assumptions of the design, placement
constraints did not work well for designs migrating to HardCopy II or
other FPGA devices. When migrating designs, especially to a HardCopy
II device, you would need two different sets of placement constraints: one
for the FPGA prototype device and one for the HardCopy production
device. This also applies when migrating designs to a different FPGA
device.
DDR Timing Wizard
The DDR Timing Wizard (DTW) is a Tcl-based GUI that calculates timing
constraints based on the FPGA and memory device chosen. It simplifies
the process of constraining your design by using timing assignments,
which the Quartus II software uses to place and route the design in the
target device. These timing constraints are applicable for FPGAs and their
HardCopy-equivalent devices, eliminating the need to convert
assignments for the different device families (as you would have
previously done with the placement constraints from legacy controller
MegaWizard). Some critical register placements can be constrained by
using LogicLock region assignments, but other than the pin location,
output pin load, and I/O standards assignments, you do not need any
hard placement constraints. Instead, the timing-driven compilation of the
Quartus II software ensures that all DTW timing constraints are met in
both FPGA-prototype and HardCopy-production devices.
DTW also gives you the ability to change the pin names of the memory
interface to use regional clock networks, and to use TimeQuest Timing
Analyzer to analyze the design, which are not supported by the
verify_timing.tcl script. DTW constraints also lead to a more accurate
timing analysis, as all the information used are based on your particular
design, instead of general assumptions made by the MegaWizard.
Furthermore, the timing verification script does not report write timing
margin. DTW, on the other hand, constrains timing for the write path,
allowing Quartus II to analyze the write timing margin. You can then use
the dtw_timing_analysis.tcl script to report read, write,
address/command, resynchronization, and postamble timing margins
that are applicable to your memory interface design. DTW constraints
provide more accurate timing results compared to the verify_timing.tcl
script.
Altera Corporation 1–3
November 2007 DDR Timing Wizard User Guide
Introduction
1 Critical resynchronization register placement constraints
provided by the legacy controller MegaWizard can still be used
even when DTW is used. You can use LogicLock regions in lieu
of hard placement constraints.
1 The results reported by the dtw_timing_analysis.tcl script have
no correlation with the verify_timing.tcl script. You should rely
on the dtw_timing_analysis.tcl report, as it is more accurate
due to the design-specific constraints created by the DTW. The
verify_timing.tcl script may have some assumption that does
not apply to your particular design.
To use the DTW, you must enter the memory device parameters and your
board information correctly in the legacy controller MegaWizard. The
Quartus II Fitter uses timing-driven compilation to route the design to
meet the timing constraints set by the DTW.
Because the DTW is primarily a constraining tool, the
dtw_timing_analysis.tcl script is provided to help you analyze and close
timing with a minimum number of compilations. The
dtw_timing_analysis.tcl script extracts the system timing margin by
re-running timing analysis if needed, adjusting the clock cycles in the
DTW (with the -auto_adjust_cycles switch) if required, and
suggesting the ideal phase shifts for the system. The
dtw_timing_analysis.tcl is backwards-compatible with designs
constrained with an older version of DTW. Both DTW and the
dtw_timing_analysis.tcl scripts are available in the Quartus II
installation directory.
1 If you use the default installation directory, the DTW and
dtw_timing_analysis.tcl scripts are available in the
c:\altera\<version>\quartus\common\tcl\apps\
gui\dtw directory.
1–4 Altera Corporation
DDR Timing Wizard User Guide November 2007
Figure 1–1 shows the typical Quartus II external memory design flow
using DTW and the dtw_timing_analysis.tcl script.
Figure 1–1. Quartus II External Memory Design Flow
Instantiate PHY
and Controller in a
Quartus II Project
About the DDR Timing Wizard
Compile Design
Run add_constraints.tcl
(Pin Locations,
I/O Standards, and Loading)
Run DTW
(Timing Constraints)
Add Assignments for Clock,
Command, and Address Pin
Locations, and Other Pertinent
Assignments for the Interface
Run dtw_timing_analysis.tcl
to Get Margin and
Recommended Settings
Memory
Interface Timing
Adjust Constraints
Using the MegaWizard,
the Assignment Editor,
or the DTW
Ye s
(1)
Is
Met?
No
Done
Note to Figure 1–1:
(1) It may be necessary to modify the controller and PHY settings (such as the clock cycles and clock phase shifts) using
the legacy controller or the altpll MegaWizard, based on dtw_timing_analysis.tcl results.
This user guide explains how to constrain designs using DTW, how to
analyze the memory interface timing using the dtw_timing_analysis.tcl
script, and how to adjust design constraints using the MegaWizard, the
Assignment Editor, or DTW to achieve timing closure.
Altera Corporation 1–5
November 2007 DDR Timing Wizard User Guide
Features
Features
The DDR Timing Wizard has the capability to:
■ Constrain a design with one or multiple memory controllers that
may reside in subdirectories of the main project.
■ Calculate all of the timing constraints based on your chosen FPGA or
HardCopy device, and memory device.
■ Import timing information from the legacy controller MegaWizard.
■ Enable timing driven compilation.
■ Allow the Quartus II software to analyze and report the
post-compile timing analysis for both fast and slow timing models in
one panel.
■ Create both classic timing analyzer and TimeQuest Timing Analyzer
assignments for memory interface timing paths.
The dtw_timing_analysis.tcl script complements the DTW with the
ability to:
■ Extract and report system timing margin for both fast and slow
model timing.
■ Re-run timing analysis using either the Classic Timing Analyzer or
TimeQuest Timing Analyzer.
■ Adjust resynchronization and postamble clock cycles in DTW.
■ Calculate ideal PLL phase shifts.
■ Import legacy controller MegaWizard settings into DTW (with the
option to compile the design after the import).
■ Update design t
information in DTW.
CO
1–6 Altera Corporation
DDR Timing Wizard User Guide November 2007
2. Getting Started
System and Software Requirements
Design Flow
The instructions in this section require Quartus II software version 7.2 or
higher. DTW and the dtw_timing_analysis.tcl script can be found in the
Quartus II installation directory. You can either run the script from that
directory or copy the script to your project directory.
1 If you use the default installation directory, the DTW and
dtw_timing_analysis.tcl script are available in the
c:\altera\<version>\quartus\common\tcl\apps\
gui\dtw directory.
The design flow when creating a system with external memory interfaces
is as follows:
1. Create a memory interface PHY with Altera’s legacy memory
controller MegaWizard.
f For more information about how to create a memory
controller, refer to the DDR & DDR2 SDRAM Controller
Compiler User Guide, QDRII SRAM Controller MegaCore
Function User Guide, and RLDRAM II Controller MegaCore
Function User Guide. Follow the instructions up to
generating the core, but do not compile the design yet.
®
f To create an example design, follow the Instantiate PHY
and Controller in a Quartus II Project step of the
"Example Walkthrough for 267-MHz DDR2 SDRAM
Interface using the Legacy PHY" section in AN328:
Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and
Arria GX Devices.
If you are not using the Altera memory controller, remove the
encrypted controller produced by the legacy controller MegaWizard
and connect the Altera-recommended data path from the legacy
controller MegaWizard with your memory controller.
2. Run the auto_add_ddr_constraints.tcl script produced by the
legacy controller MegaWizard for pin location, I/O standard,
output pin load, and register placement assignments for the
resynchronization and postamble registers in DDR2/DDR SDRAM
interfaces.
Altera Corporation 2–1
November 2007
Design Flow
1 You do not need to remove these location assignments
when using DTW even though DTW makes the correct
timing constraints for the paths to these registers.
To locate the auto_add_ddr_constraints.tcl script, on the Tools
menu, click Tcl Scripts. The script is under the Project folder.
(Figure 2–1).
Figure 2–1. Add Constraints TCL Script
After running the auto_add_ddr_constraints.tcl script, assign the
other pin locations, I/O standards, and loading for the design. The
legacy controller MegaWizard does not make pin location
constraints for the command, address, input, and output clock pins.
You can add those constraints using the Quartus II Pin Planner or the
Quartus II Assignment Editor.
1 Place address, command, and clock pins in the same bank
as the DQS/DQ pins to minimize output skew.
3. Specify timing requirements using DTW.
Because the controller is generated by the legacy controller
MegaWizard, you can import the memory and board specifications
and pin names entered into the legacy controller MegaWizard
instead of manually entering them into the DTW. Also, DTW extracts
2–2 Altera Corporation
DDR Timing Wizard User Guide November 2007
Getting Started
the names of the PLL clocks and registers (as needed) for the timing
requirements. It also extracts the phase shifts of synthesized PLLs.
The step-by-step instructions are listed in “Import Flow for the
Altera Legacy Memory Controller IP Core or Recommended Data
Path” on page 2–7.
1 You may need to re-run DTW and compile the design
multiple times before achieving timing closure. You can
close timing within two compiles if you do not need to
change the intermediate registers option in the legacy
controller MegaWizard.
4. Add other assignments for the design.
Add the following assignments in the Assignment Editor (unless
indicated otherwise) to the project before you compile the design:
● If you are using classic Timing Analyzer:
• In the Settings tab of the Assignment menu, uncheck the
Optimize hold timing option.
• In the Settings tab of the Assignment menu, uncheck the
Optimize fast corner timing option.
This disallows the Quartus II Fitter from optimize placement
each time the project is recompiled. Having these options
enabled may render your phase shift changes invalid because
the Quartus II Fitter has the priority to optimize for hold timing
and fast cornering.
You can re-enable the Optimize hold timing and Optimize fast
corner timing options for the remainder of the design after you
close timing on your memory interface. To ensure the memory
interface part of the design has similar timing, back-annotate
placements and routing for that portion of the design before reenabling the options.
● If you are using TimeQuest Timing Analyzer, add the
DTW-generated .sdc file to the project.
● Set the delay from Output Register to Output Pin to 0 for the
CK/CK# (clk_to_sdram*) clock outputs and fedback clock
output.
● Assign pin constraints for all the CK/CK# and feedback output
pins and ensure that the feedback output pins use the same I/O
Altera Corporation 2–3
November 2007 DDR Timing Wizard User Guide
Design Flow
standard as the CK/CK# pins, and are placed on the same side
as the DQS/DQ pins.
● Assign pin location, I/O standard, and output pin load
constraints for clock_source, feedback input pins, and
address and command pins.
● For RLDRAM II memory interfaces created in Quartus II
version 7.2 and higher, add the
<variation_name>_controller.sdc file to the project
● For QDRII+/QDRII SRAM memory interfaces using TimeQuest
Timing Analyzer, convert the setup_relationship and
hold_relationship MegaWizard-generated constraints to
SDC constraints. The setup_relationship and
hold_relationship assignment can be directly converted to
set_max_delay and set_min_delay assignments, as shown
in the below example:
set_max_delay -0.2 -from * -to <resync_registers*>
set_min_delay -1.6 -from * -to <resync_registers*>
5. Compile the design.
6. Check the timing analysis results.
After completing a DTW design compilation, refer to Chapter 3,
Using the dtw_timing_analysis.tcl Script for information about
analyzing the memory interfaces.
If problem paths are reported, locate and fix them to maximize setup
and hold slack. For example, you can:
● Adjust PLL clock phases with the legacy controller or the
altpll MegaWizard.
1 Note that some clock phases can only be changed in the
legacy controller MegaWizard, especially for shared PLL
outputs. For example, if your postamble clock was set to 90°
initially, but you want to change it to use either a dedicated
clock or a 180° phase shift.
● Insert or remove intermediate resynchronization and/or
postamble registers in the legacy controller MegaWizard.
2–4 Altera Corporation
DDR Timing Wizard User Guide November 2007
Getting Started
1 You need to insert intermediate resynchronization registers
when you have negative margin in the transfer between
resynchronization registers and the registers clocked by the
system clock. The dtw_timing_analysis.tcl script will tell
you when to add or remove the intermediate postamble
registers.
● Change the data path resynchronization and/or postamble
clock cycles in the legacy controller MegaWizard.
● Change location assignments to the problem PLL clocks, I/O
pins, or registers.
f Refer to Chapter 3, Using the dtw_timing_analysis.tcl
Script for information on how to fix your timing violations
using the dtw_timing_analysis.tcl script.
1 If you need to change any PLL phase shifts, re-run the
Quartus II Analysis and Synthesis to refresh the PLL
settings before importing the new phase shift in the DTW.
You can click on the Start Analyze & Synthesis button
manually or use the –after_iptb import option in the
dtw_timing_analysis.tcl script. You can also enter the PLL
phase shifts manually in the DTW to bypass Quartus II
Analysis and Synthesis. However, DTW will not be able to
confirm if the phase shift entered is the correct phase shift
that is implemented in the design.
If there are no failing paths, your design is complete. Otherwise, go
back to step 5 after making the necessary timing requirements
changes until the design achieves timing closure.
Launching the
To launch the DDR Timing Wizard from the Quartus II software, follow
these steps:
DDR Timing
Wizard
Altera Corporation 2–5
November 2007 DDR Timing Wizard User Guide
1. On the Tools menu, click Tcl S c r i pt s.
2. In the Tcl Scripts dialog box, under Libraries, expand the
<installation_directory>/quartus/common/tcl/apps/gui/dtw
folder, select dtw (Figure 2–2).
Entering and Editing Inputs to the DTW
Figure 2–2. Launching the DDR Timing Wizard
3. Click Run.
1 You can also launch the DTW from the command line with
the following command:
<quartus_ii_installation_directory>/bin/quartus_sh --dtw
Entering and
Editing Inputs to
the DTW
2–6 Altera Corporation
DDR Timing Wizard User Guide November 2007
If you use the Altera legacy controller MegaWizard as a starting point for
your memory interfaces, follow the import flow described below to enter
and edit inputs to the DTW. The legacy controller MegaWizard is the
recommended tool, and simplifies entry of the essential design
requirements. If you have an interface that is not supported by the legacy
controller MegaWizard , refer to “Manual Flow for Other External
Memory Interfaces or Source Synchronous Systems” on page 2–14.
1 The screen captures of the DTW pages shown in this section are
from the Legacy_PHY.qar design that is downloadable with
AN328: Interfacing DDR2 SDRAM in Stratix II, Stratix II GX, and
Arria GX Devices.
Getting Started
1 You do not need to perform Quartus II Analysis and Synthesis
the first time you run DTW as this has been done when running
the auto_add_ddr_constraints.tcl script. However, any
subsequent calls to the DTW must be preceded with a Quartus II
Analysis and Synthesis process, otherwise DTW will not be able
to read any changes to the design.
Import Flow for the Altera Legacy Memory Controller IP Core or Recommended Data Path
When you use the Altera-provided data path, you can benefit by
importing the memory data path settings, which saves time because
parameters required by the DTW do not need to be filled in manually. If
you choose to create your own data path, you can find more information
about the DTW pages in “Manual Flow for Other External Memory
Interfaces or Source Synchronous Systems” on page 2–14.
The following procedure illustrates a DDR/DDR2 SDRAM interface
example, but the steps are identical for the QDRII+/QDRII SRAM or the
RLDRAM II interface. Before performing the following steps, be sure to
run the legacy controller MegaWizard auto_add_ddr_constraints.tcl
script and run Quartus II Analysis and Synthesis.
After launching the DTW, follow these steps to import the timing
parameters and pin names from the legacy controller MegaWizard:
1. On the first page of the DTW, you are prompted to create or edit a
.dwz file. Opening the DTW allows you to make changes to the
saved .dwz file or to create a new .dwz file. This file contains all of
the parameters you enter in the DTW script.
Figure 2–3 shows the first page of the DTW software in which you
can specify the location for the .dwz file. The default name and
location for the file is:
<quartus_ii_project_directory>/ddr_settings.dwz
Ensure that the .dwz file points to the project directory that you are
working on. If you have un-archived the project, the .dwz file may
still be pointing to the old project directory. You can change the file
name and click Next.
1 The saved file name always defaults to ddr_setting.dwz.
Ensure that it is the file name you want to use. If you have
multiple memory controllers in a design, you must have a
unique .dwz file name for each controller.
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Entering and Editing Inputs to the DTW
Figure 2–3. First Page of the DDR Timing Wizard—Create or Edit File
2. Page 2 of the DTW (Figure 2–4) asks you to confirm the project
directory and the revision you want to use. (Note that the project
name is case-sensitive.) The DTW automatically fills in the fields,
but you can change those fields if the project has been moved or if
you have a newer revision. Click Next.
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Figure 2–4. Page 2 of the DTW—Confirm the Project Directory and Revision Name
3. Figure 2–5 shows page 3 of the DTW. This page asks whether you
would like to import data from the legacy controller MegaWizard
instance using Classic Timing Analyzer or TimeQuest Timing
Analyzer names.
If you choose TimeQuest Timing Analyzer names, DTW creates
assignments that are stored in an .sdc file. Choosing Classic Timing
Analyzer names generates both .qsf assignments and an .sdc file.
This means that you can still use TimeQuest Timing Analyzer for
compilation and timing analysis even when you choose Classic
Timing Analyzer names.
Getting Started
You need to add the .sdc file to the project when using TimeQuest
Timing Analyzer for compilation and timing analysis.
1 The difference between the .sdc file created using Classic
Timing Analyzer and TimeQuest Timing Analyzer names
is the clock name convention. There should not be any
difference in timing analysis results between these two .sdc
files.
1 You should use TimeQuest Timing Analyzer for a more
accurate timing analysis as the constraints of the .sdc file
apply to both fast and slow timing models.
Click Import.
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Entering and Editing Inputs to the DTW
Figure 2–5. Page 3 of the DTW—Importing Data from the Legacy Controller MegaWizard
4. Choose the location from which to import the data. Select
<core_variation_name>_<ddr|qdr|rldramii>_settings.txt from the
project directory. The example in Figure 2–6 uses a the DDR2
SDRAM controller named legacy_core, so the DTW must import
data from the legacy_core_ddr_settings.txt file generated by the
legacy controller MegaWizard.
Figure 2–6. Choose the <core_variation_name>_<ddr|qdr|rldramii>_settings.txt File to be Imported
5. The DTW then imports data from the
<core_variation_name>_<ddr|qdr|rldramii>_settings.txt file.
This process may take some time if your design is large.
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Getting Started
1 The DTW can extract the names of PLL clocks, PLL phase
shifts, and names of registers, if you have already run the
Quartus II Analysis and Synthesis. The
auto_add_ddr_constraints.tcl script automatically
analyzes and synthesizes the design, so you do not have to
perform Quartus II Analysis and Synthesis the first time
you invoke DTW after running the
auto_add_ddr_constraints.tcl script. However, any time
you make a change in the PLL or the legacy controller
MegaWizard, you need to analyze and synthesize the
design before invoking DTW, so that DTW can extract the
correct clock names and phase shifts when performing an
Import function.
When the import is complete, click Skip to get to the last page of
DTW.
1 Instead of skipping to the end, you can verify the values in
the DTW by clicking Next and checking each page of the
DTW to ensure that everything is imported correctly. These
pages are described in detail in “Manual Flow for Other
External Memory Interfaces or Source Synchronous
Systems” on page 2–14.
At this point, if the DTW has all of the needed information, a page
similar to the one shown in Figure 2–7 appears. Click Finish.
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Entering and Editing Inputs to the DTW
Figure 2–7. Timing Assignments to be Added to the Project
When using Classic Timing Analyzer, the last page of the DTW
names looks a little different than Figure 2–7. This is described in
more detail in “Manual Flow for Other External Memory Interfaces
or Source Synchronous Systems” on page 2–14.
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If DTW failed to extract PLL clock information during the import
step, it asks you to input this information manually. The PLL Phase
Shift Selection page (Figure 2–8) then displays a warning indicating
“Missing required PLL clock info.” Figure 2–8 shows an example in
which the DTW cannot find the resynchronization clock from the
system PLL.
Figure 2–8. PLL Phase Shift Selection Page
Getting Started
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Entering and Editing Inputs to the DTW
After entering the resynchronization clock name (omitted in
Figure 2–8) click Skip to get to the last page of DTW.
Click Finish.
6. Add the additional assignments as listed on Step 4 of the “Design
Flow” section.
7. Compile the design and perform timing analysis.
f For more details, refer to Chapter 3, Using the dtw_timing_analysis.tcl
Script.
Manual Flow for Other External Memory Interfaces or Source Synchronous Systems
Use this flow when you have a custom implementation for an
Altera-supported memory interface, including the following:
■ DDR/DDR2 SDRAM
■ QDRII+/QDRII SRAM
■ RLDRAM II
1 Always implement the Altera data path and use the legacy
controller MegaWizard flow unless the feature set of the Altera
memory controller makes it impossible to do so.
The DTW Pages for DDR/DDR2 SDRAM
This section details each page in the DDR/DDR2 SDRAM interface. The
pages for QDRII+/QDRII SRAM and RLDRAM II interfaces are slightly
different than the pages for DDR/DDR2 SDRAM interfaces. The DTW
pages for QDRII+/QDRII SRAM and RLDRAM II are listed in “The DTW
Pages for QDRII+/QDRII SRAM & RLDRAM II” on page 2–45.
1 The following page-by-page information is based from a
controller created by the legacy controller MegaWizard but the
DTW import option is not used.
1. On the Tools menu, select Tc l S c r i pt s. Select dtw and click Run.
2. Specify a .dwz file name to save the timing constraints for the
design and click Next.
3. Confirm the project directory and revision you want to use.
Click Next.
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Getting Started
4. Page 3 asks if you want to import data from the legacy controller
MegaWizard, and whether you want to use TimeQuest or Classic
Timing Analyzer names. Click on one of the radio buttons (even if
you are not using the Import function) and click Next.
5. Select your memory type: DDR/DDR2 SDRAM, QDRII+/QDRII
SRAM or RLDRAM II. For this example, choose DDR/DDR2
SDRAM. Refer to Figure 2–9.
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Entering and Editing Inputs to the DTW
Figure 2–9. Select Memory Type
6. Select the appropriate memory device from the drop-down menu
(Figure 2–10).
The rest of the fields are filled in automatically when you pick a
device. Click Next.
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