Altera DDR SDRAM Controller User Manual

DDR and DDR2 SDRAM Controller Compiler User

Guide

101 Innovation Drive San Jose, CA 95134 www.altera.com

Software Version: 9.0 Document Date: March 2009

Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services

UG-DDRSDRAM-10.0

Chapter 1. About This Compiler

Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6

Chapter 2. Getting Started

Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

SOPC Builder Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

DDR & DDR2 SDRAM Controller Walkthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Create Your Top-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Simulate the SOPC Builder Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Compile the SOPC Builder Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

MegaWizard Plug-In Manager Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

DDR & DDR2 SDRAM Controller Walkthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Simulate the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Compile the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

Implement Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

Set Up Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

Chapter 3. Functional Description

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Device-Level Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

PLL Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

DLL Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18

Interfaces & Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19

Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19

Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–28

Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–32

Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–33

Controller Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–37

Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–38

Board Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–39

Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–40

Manual Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–41

MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–41

Simulation Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–41

Hardware Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–41

Appendix A. Manual Timing Settings

Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4

Resynchronization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5

Intermediate Resynchronization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–10

DQS Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–10

Postamble Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–11

Intermediate Postamble Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–12

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–13

Appendix B. DDR SDRAM on the Nios Development Board, Cyclone II Edition

Appendix C. HardCopy II Design Walkthrough

Appendix D. Maximizing Performance

Device & Board Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1

Adjust the PLL Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–2

Assign Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–2

Place the Fedback PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–2

Update the PLL Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–3

Additional Information

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–i

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–i

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–i

DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Release Information

Tab le 1– 1 provides information about this release of the DDR and DDR2 SDRAM

Controller Compiler.

Table 1–1. DDR & DDR2 SDRAM Controller Release Information

Version 9.0

Release Date March 2009

Ordering Codes IP-SDRAM/DDR (DDR SDRAM)

Product IDs 0055 (DDR SDRAM)

Vendor ID 6AF7

1. About This Compiler

Item Description

IP-SDRAM/DDR2 (DDR2 SDRAM)

00A7 (DDR2 SDRAM)

00A8 (common library)

Device Family Support

MegaCore® functions provide either full or preliminary support for target Altera® device families, as described below:

■ Full support means the MegaCore function meets all functional and timing

requirements for the device family and may be used in production designs

■ Preliminary support means the MegaCore function meets all functional

requirements, but may still be undergoing timing analysis for the device family; it may be used in production designs with caution

Tab le 1– 2 shows the level of support offered by the DDR and DDR2 SDRAM

Controller Compiler to each of the Altera device families.

Table 1–2. Device Family Support (Part 1 of 2)

Cyclone

Cyclone II Full Full

HardCopy

Stratix

Stratix GX Full No support

Stratix II (1) Full Full

Stratix II GX Full Full

II Preliminary Preliminary

Device Family

Support

DDR SDRAM DDR2 SDRAM

Full No support

March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

1–2 Chapter 1: About This Compiler

Features

Table 1–2. Device Family Support (Part 2 of 2)

Support

Features

Device Family

DDR SDRAM DDR2 SDRAM

Other device families (2), (3) No support No support

Notes to Table 1–2:

(1) For new Stratix II designs, use the DDR and DDR2 SDRAM High-Performance Controller. (2) For more information on support for Stratix III devices with existing designs, contact Altera. (3) For new Stratix III or Cyclone III designs, use the DDR and DDR2 SDRAM High-Performance Controller.

■ Support for industry-standard DDR and DDR2 SDRAM devices and modules

■ 1, 2, 4, or 8 chip-select signals

■ Data mask signals for partial write operations

■ Bank management architecture, which minimizes latency

■ Configurable data width

■ DQS read postamble control logic

■ Free clear-text datapath for use with custom controller

■ Automatic or user-controlled refresh

■ Support for registered DIMMs

■ Optional non-DQS read mode for Stratix and Stratix II side banks

■ IP Toolbench-generated constraint script

■ Quick and easy implementation with example design

■ System timing analysis

■ Support for OpenCore Plus evaluation

■ SOPC Builder ready

■ IP functional simulation models for use in Altera-supported VHDL and Verilog

HDL simulators

General Description

The Altera DDR and DDR2 SDRAM Controller Compiler comprises the DDR SDRAM Controller MegaCore function and the DDR2 SDRAM Controller MegaCore function. The MegaCore functions provide simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM devices.

The DDR and DDR2 SDRAM Controllers handle the complex aspects of using DDR or DDR2 SDRAM—initializing the memory devices, managing SDRAM banks, and keeping the devices refreshed at appropriate intervals. The DDR and DDR2 SDRAM Controllers translate read and write requests from the local interface into all the necessary SDRAM command signals.

DDR and DDR2 SDRAM Controller Compiler User Guide March 2009 Altera Corporation

Chapter 1: About This Compiler 1–3

DDR SDRAMExample Driver

PLL

DLL (1)

DDR SDRAM

Interface

Pass or Fail

Local

Interface

Example Design

Control

Logic

(Encrypted)

DDR SDRAM Controller

Data Path

(Clear Text)

General Description

The DDR SDRAM Controller is optimized for Altera Stratix and Cyclone series; the DDR2 SDRAM Controller is optimized for Altera Stratix II and Cyclone II devices only. The advanced features available in these devices allow you to interface directly to DDR or DDR2 SDRAM devices and to use the DQS signal in the read and write direction.

Figure 1–1 shows a system-level diagram including the example design that the DDR

or DDR2 SDRAM Controller MegaCore functions create for you.

Figure 1–1. DDR & DDR2 SDRAM Controller System-Level Diagram

Note to Figure 1–1:

(1) Optional, for Stratix series and HardCopy II devices only.

Whether you use IP Toolbench in SOPC Builder or in the Quartus II software, it generates example design, instantiates a phase-locked loop (PLL), an example driver, your DDR or DDR2 SDRAM controller custom variation, and an optional DLL (for Stratix series only). The example design is a fully-functional design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals.

You can replace the DDR or DDR2 SDRAM controller encrypted control logic in the example design with your own custom logic, which allows you to use the Altera clear-text datapath with your own control logic.

The DDR and DDR2 SDRAM Controllers are very similar. The following differences exist:

■ Initialization timing (refer to “DDR SDRAM Initialization Timing” on page 3–25

and “DDR2 SDRAM Initialization Timing” on page 3–26)

■ CAS latency options:

■ 2.0, 2.5, or 3.0, for DDR SDRAM

■ 3, 4, or 5, for DDR2 SDRAM

March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

1–4 Chapter 1: About This Compiler

■ Burst lengths:

■ 2, 4, or 8, for DDR SDRAM

■ 4, for DDR2 SDRAM

■ Banks:

■ 4 for DDR SDRAM

■ 4 or 8 for DDR2 SDRAM

■ Support for ODT in DDR2 SDRAM

Performance and Resource Utilization

Tab le 1– 3 shows typical performance results for the DDR SDRAM controller using the

Quartus II software version 9.0.

Table 1–3. Typical Performance

System fMAX (MHz)

Device

DDR SDRAM DDR2 SDRAM

Cyclone (EP1C20F400C6) 133 –

Cyclone II (EP2C35F672C6) 167 167

Stratix (EP1S25F780C5) 200 –

Stratix II (EP2S60F1020C3) 200 267 (1)

Stratix II GX (EP2SGX30CF780C3) 200 (2) 267 (1) (2)

Note to Tab le 1– 3:

(1) For information on a solution that achieves speeds greater than 267 MHz (533 Mbps) up to 333 MHz (667 Mbps),

contact your local Altera sales representative. To achieve speeds greater than 267 MHz, a new dynamic autocalibration circuit is required.

(2) Pending device characterization.

f For more information on device performance, refer to the relevant device handbook.

Tab le 1– 4 shows typical sizes in logic elements (LEs) or adaptive look-up tables

(ALUTs) for the DDR SDRAM controller.

Table 1–4. Typical Size (Part 1 of 2) (Note 1)

Combinational

Device Memory Width (Bits) LEs

ALUTs Logic Registers M4K RAM Blocks (2)

Cyclone 16 860 — — 1

32 1,050 — — 2

Cyclone II 16 940 — — 1

32 1,120 — — 2

64 1,500 — — 4

72 1,600 — — 5

DDR and DDR2 SDRAM Controller Compiler User Guide March 2009 Altera Corporation

Chapter 1: About This Compiler 1–5

Installation and Licensing

Table 1–4. Typical Size (Part 2 of 2) (Note 1)

Combinational

Device Memory Width (Bits) LEs

ALUTs Logic Registers M4K RAM Blocks (2)

Stratix 16 — 750 — 1

32 — 830 — 2

64 — 1,000 — 4

72 — 1,040 — 5

Stratix II 16 — 800 — 1

32 — 960 — 2

64 — 1,250 — 4

72 — 1,320 — 5

Stratix II GX 16 — 800 — 1

32 — 960 — 2

64 — 1,250 — 4

72 — 1,320 — 5

Notes to Table 1–4:

(1) These sizes are a guide only and vary with different choices of parameters. These numbers are created with the default settings for each device

family, varying only the width of the interface. Generally, the controller uses about 700 LEs while the size of the datapath varies with width and the amount of pipelining and clocking scheme required.

(2) The controller uses M4K RAM blocks to buffer write data from the user logic. If you select a burst length of 1 (2 on the DDR SDRAM side), this

buffer is not necessary and no memory blocks are used in your variation, regardless of data width.

The performance of the entire system and in general the DDR or DDR2 SDRAM controller depends upon the number of masters and slaves connected to the Avalon Memory-Mapped (Avalon-MM) interface, which degrades as the number of masters and slaves connected to it increases. If the number of masters connected to the slave increases, the size of the arbiter (which is part of the Avalon-MM interface) increases, which reduces the performance of the system. The DDR or DDR2 SDRAM controller performance is limited by the frequency of Avalon-MM interface.

There is no latency associated within the Avalon-MM interface, when it transfers the read or write request to the controller local interface. If there are multiple masters connected to the DDR or DDR2 SDRAM controller, there may be wait states before the request from the master is accepted by the controller.

f For more information, refer to the System Interconnect Fabric for Memory-Mapped

Interfaces chapter in the Quartus II Handbook.

Installation and Licensing

The DDR and DDR2 SDRAM Controller Compiler is part of the MegaCore IP Library, which is distributed with the Quartus website, www.altera.com.

f For system requirements and installation instructions, refer to Quartus II Installation &

Licensing for Windows and Linux Workstations.

II software and downloadable from the Altera

March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

1–6 Chapter 1: About This Compiler

Installation and Licensing

Figure 1–2 shows the directory structure after you install the DDR and DDR2 SDRAM

Controller Compiler, where <path> is the installation directory. The default installation directory on Windows is c:\altera\<version>; on Linux it is /opt/altera<version>.

Figure 1–2. Directory Structure

<path>

Installation directory.

Contains the Altera MegaCore IP Library and third-party IP cores.

altera

Contains the Altera MegaCore IP Library.

common

Contains shared components.

ddr_ddr2_sdram

Contains the DDR and DDR2 SDRAM Controller Compiler files and documentation.

constraints

Contains scripts that generate an instance-specific Tcl script for each instance of the DDR and DDR2 SDRAM Controller Compiler in various Altera devices.

dat

Contains a data file for each Altera device combination that is used by the Tcl script to generate the instance-specific Tcl script.

doc

Contains the documentation for the DDR and DDR2 SDRAM Controller Compiler.

lib

Contains encrypted lower-level design files and other support files.

system_timing

Contains system timing analysis scripts and associated files.

OpenCore Plus Evaluation

With Altera’s free OpenCore Plus evaluation feature, you can perform the following actions:

■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP

megafunction) within your system

■ Verify the functionality of your design, as well as evaluate its size and speed

quickly and easily

■ Generate time-limited device programming files for designs that include

MegaCore functions

■ Program a device and verify your design in hardware

You only need to purchase a license for the megafunction when you are completely satisfied with its functionality and performance, and want to take your design to production.

f For more information on OpenCore Plus hardware evaluation using the DDR and

DDR2 SDRAM Controller, refer to “OpenCore Plus Time-Out Behavior” on page 3–3 and AN 320: OpenCore Plus Evaluation of Megafunctions.

DDR and DDR2 SDRAM Controller Compiler User Guide March 2009 Altera Corporation

Design Flow

2. Getting Started

The Altera DDR and DDR2 SDRAM Controller Compiler and the Quartus II software provide many options for creating custom, high-performance DDR and DDR2 SDRAM designs.

You can parameterize the DDR and DDR2 SDRAM Controller Compiler using either one of the following flows:

■ SOPC Builder flow

■ MegaWizard

The SOPC Builder flow creates a simpler, automatically-integrated system; the MegaWizard Plug-In flow requires more user-customization.

Tab le 2– 1 summarizes the advantages offered by the different parameterization flows.

Table 2–1. Advantages of the Parameterization Flows

Plug-In Manager flow

SOPC Builder Flow MegaWizard Plug-In Manager Flow

■ Requires minimal DDR or DDR2 SDRAM

design expertise

■ Simple and flexible GUI to create complete

DDR or DDR2 SDRAM system within hours

■ Automatically-generated simulation

environment

■ Create custom components and integrate

them via the component wizard

■ All components are automatically

interconnected via the Avalon-MM interface

SOPC Builder Design Flow

The SOPC Builder design flow involves the following steps:

1. In SOPC Builder, use IP Toolbench to create a custom variation of the DDR or DDR2 SDRAM controller MegaCore function and implement and generate the rest of your SOPC Builder system.

2. Create your design, based on the DDR or DDR2 SDRAM example design.

3. Perform functional simulation with IP functional simulation models.

4. Use the Quartus II software to edit the PLL(s), add constraints, compile, and perform post-compilation timing analysis.

■ More control of the system feature set

■ Design directly from the DDR or DDR2

SDRAM interface to peripheral device(s)

■ Achieves higher-frequency operation

5. If you have a suitable development board, you can generate an OpenCore Plus time-limited programming file, which you can use to verify the operation of the design in hardware.

2–2 Chapter 2: Getting Started

SOPC Builder Design Flow

The DDR and DDR2 SDRAM Controller Compiler with SOPC Builder flow option allows you to build a complete DDR or DDR2 SDRAM system. The DDR and DDR2 SDRAM Controller Compiler with SOPC Builder flow connects the DDR or DDR2 SDRAM Controller to the Avalon-MM interface, which allows you to easily create any system that includes one or more of the Avalon-MM peripherals.

You specify system components and choose system options from a rich set of features, and the SOPC Builder automatically generates the interconnect logic and simulation environment. Thus, you define and generate a complete system in dramatically less time than manual-integration methods.

To perform burst transactions when the DDR or DDR2 SDRAM controller is instantiated in SOPC builder, you need another master such as a DMA controller to initiate the burst transactions.

The performance of the entire system and in general the DDR or DDR2 SDRAM controller depends upon the number of masters and slaves connected to the Avalon-MM interface, which degrades as the number of masters and slaves connected to it increases. If the number of masters connected to the slave increases, the size of the arbiter (which is part of the Avalon-MM interface) increases, which reduces the performance of the system. The DDR or DDR2 SDRAM controller performance is limited by the frequency of Avalon-MM interface.

DDR & DDR2 SDRAM Controller Walkthrough

This walkthrough explains how to create a custom variation of the DDR or DDR2 SDRAM Controller MegaCore function in a SOPC Builder system using the Altera DDR SDRAM controller IP Toolbench and the Quartus II software.

As you go through the wizard, each step is described in detail. The flow used in this SOPC Builder walkthrough ensures that the PLL is properly connected to the DDR or DDR2 SDRAM controller and that the wizard-generated constraints are correctly applied.

f For more information on SOPC Builder, refer to volume 4 of the Quartus II Handbook.

This walkthrough involves the following steps:

■ “Create a New Quartus II Project” on page 2–3

■ “Launch SOPC Builder & IP Toolbench” on page 2–4

■ “Parameterize” on page 2–4

■ “Constraints” on page 2–5

■ “Add/Update Component” on page 2–5

DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–3

SOPC Builder Design Flow

Create a New Quartus II Project

You need to create a new Quartus II project with the New Project Wizard, which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity. To create a new project follow these steps:

1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. Alternatively, you can use the Quartus II Web Edition software.

2. Choose New Project Wizard (File menu).

3. Click Next in the New Project Wizard: Introduction page (the introduction page does not display if you turned it off previously).

4. In the New Project Wizard: Directory, Name, Top-Level Entity page, enter the following information:

a. Specify the working directory for your project. For example, this walkthrough

uses the c:\altera\projects\ddr_project directory.

b. Specify the name of the project. This walkthrough uses project for the project

name.

1 The Quartus II software automatically specifies a top-level design entity

that has the same name as the project. Do not change it.

5. Click Next to close this page and display the New Project Wizard: Add Files page.

1 When you specify a directory that does not already exist, a message asks if

the specified directory should be created. Click Yes to create the directory.

6. If you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software, you must add the user libraries:

a. Click User Libraries.

b. Type <path>\ip into the Library name field, where <path> is the directory in

which you installed the DDR and DDR2 SDRAM Controller.

c. Click Add to add the path to the Quartus II project.

d. Click OK to save the library path in the project.

7. Click Next to close this page and display the New Project Wizard: Family & Device Settings page.

8. On the New Project Wizard: Family & Device Settings page, choose a supported target device family in the Family list. Select Ye s for Do you want to assign a specific device?.

1 Ensure you select Ye s for Do you want to assign a specific device? to

choose a specific device, as IP Toolbench will not work correctly if you select No.

1 The DDR2 SDRAM controller only supports Cyclone II, HardCopy II,

Stratix II GX, and Stratix II devices.

2–4 Chapter 2: Getting Started

SOPC Builder Design Flow

1 If you are targeting a specific Altera development board, ensure you choose

the correct target device and memory type.

9. Choose the target device in the Available devices list.

10. The remaining pages in the New Project Wizard are optional. Click Finish to complete the Quartus II project.

Launch SOPC Builder & IP Toolbench

To launch SOPC Builder, follow these steps:

1. Choose SOPC Builder (Tools menu).

2. Enter a System Name.

1 The system name must not be the same as the Quartus II project name (and

therefore the top-level design entity name).

3. Type a value for the clk_0 (MHz). For example, 80.0.

4. Build your system from the System Contents list. Expand the Memories and Memory Controllers folder, and click either DDR SDRAM MegaCore Function or DDR2 SDRAM MegaCore Function in the SDRAM folder. Click Add. The DDR SDRAM controller IP Toolbench opens.

Parameterize

To parameterize the DDR or DDR2 SDRAM Controller, follow these steps:

1. Click Step 1: Parameterize, to parameterize your custom variation.

2. In the Presets list, click a specific memory device, Altera development board, or click Custom.

1 If you chose to target an Altera board, all the settings on the Basic Settings

tab and all Advanced Mode settings are correct for that board.

1 You cannot alter the clock speed in IP Toolbench. To alter the clock speed of

your system, close IP Toolbench and return to step 3 on page 2–4.

3. If you chose Custom, choose the appropriate Memory Interface values and enter your Board Trace Delays.

1 You must accurately set the board trace delays for your system to work in

hardware.

4. Click Show Timing Estimates, at any time to see the results of the system timing analysis.

5. You may turn on Advanced Mode at any time, to see all the settings you can change on the DDR or DDR2 SDRAM Controller.

f For more information on Advanced Mode settings, refer to “Parameterize” on

page 2–11.

DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–5

SOPC Builder Design Flow

6. Turn on Advanced Mode, and click the Project Settings tab.

7. Ensure Update the example design file that instantiates the controller variation is turned on, so that the IP Toolbench automatically updates the example design and the testbench.

Constraints

To choose the constraints for your device, follow these steps:

1 If you chose to target an Altera board, all the constraint settings are correct for that

board.

1. Click Step 2: Constraints.

2. Select the positions on the device for each of the DDR SDRAM byte groups. To place a byte group, select the byte group in the drop-down menu at your chosen position.

1 The floorplan matches the orientation of the Quartus II floorplanner. The

layout represents the die as viewed from above. A byte group consists of four or eight DQ pins, a DM pin, and a DQS pin.

1 IP Toolbench chooses the correct positions, if you are using an Altera board

preset.

Add/Update Component

To add or update the component and generate the system, follow these steps:

1. Click Step 3: Add/Update Component, to add the custom variation to SOPC Builder.

2. SOPC Builder uses the module name (default ddr_sdram_0) for the variation name of your DDR or DDR2 SDRAM Controller. You can change this name if you want to.

3. In SOPC Builder, create the rest of your SOPC Builder system.

4. Optional. Click the System Generation tab and turn on Simulation. Create project simulator files. to create simulation files for your project.

c Only use these simulation model output files for simulation purposes and expressly

not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.

f For more information on the Nios II simulation flow, refer to volume 4 of the Quartus

II Handbook.

5. On the System Generation tab, click Generate.

1 Before you click Generate, you must add at least one Avalon-MM master to

your system.

2–6 Chapter 2: Getting Started

DDR SDRAM

Other

SOPC Builder

Components

SOPC Builder System

DDR SDRAM

Interface

UART, etc.

Editted Example Top-Level Design

DDR SDRAM

Controller

Avalon Switch

Fabric

PLL

DLL (

)

SOPC Builder Design Flow

SOPC Builder generates the SOPC Builder system files. You must create a top-level design that instantiates the SOPC Builder system, PLL(s) and a DLL, before you compile the SOPC Builder project in the Quartus II software (refer to “Create Your

Top-Level Design” on page 2–6).

In addition to the SOPC Builder system files, SOPC Builder generates an example design, <variation name>_debug_design.v or .vhd. The example design contains the DDR or DDR2 SDRAM Controller, PLL, and the example driver; it has no SOPC Builder components (refer to Figure 1–1 on page 1–3).

You can use the example design to test boards and simulate, to understand the DDR or DDR2 SDRAM interface.

Create Your Top-Level Design

Use the example design, <variation name>_debug_design.v or .vhd, as a guide to connect and instantiate the PLL, the optional fed-back PLL, and DLL, to your SOPC Builder system. You must remove the example driver and the controller, and replace them with the SOPC Builder-generated system (refer to Figure 2–1).

1 To ensure that the wizard-generated constraints are correctly applied, either allow the

constraints script to automatically detect your hierarchy, or ensure that the hierarchy and pin names on the Hierarchy tab match those names in your HDL.

f For more example designs, refer to the Cyclone II reference designs in the Nios

Development Kit.

Figure 2–1. SOPC Builder System with the DDR SDRAM Controller

Simulate the SOPC Builder Design

To simulate the SOPC Builder design, either use the Nios II simulation flow or create your own testbench instantiating the top-level design and a memory model.

f For more information on the Nios II simulation flow, refer to volume 4 of the Quartus

II Handbook.

Compile the SOPC Builder Design

DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

You can now edit the PLL(s) and use the Quartus II software to compile the example design and perform post-compilation timing analysis.

Chapter 2: Getting Started 2–7

SOPC Builder Design Flow

Edit the PLL

The IP Toolbench-generated example design includes a PLL, which has an input to output clock ratio of 1:1 and a clock frequency that you entered in IP Toolbench. In addition, IP Toolbench correctly sets all the phase offsets of all the relevant clock outputs for your design. You can edit the PLL input clock to make it conform to your system requirements. If you re-run IP Toolbench, it does not overwrite this PLL, if you turn off Automatically generate the PLL, so your edits are not lost.

1 If you turn on Use fed-back clock for resynchronization, IP Toolbench generates a

second PLL—the fed-back PLL. You need not edit the fed-back PLL.

f For more information on the PLL, refer to “PLL Configurations” on page 3–13.

To edit the example PLL, follow these steps:

1. Choose MegaWizard Plug-In Manager (Tools menu).

2. Select Edit an existing custom megafunction variation and click Next.

3. In your Quartus II project directory, for VHDL choose ddr_pll_<device name>.vhd; for Verilog HDL choose ddr_pll_<device name>.v.

4. Click Next.

5. Edit the PLL parameters in the ALTPLL MegaWizard Plug-In Manager.

f For more information on the ALTPLL megafunction, refer to the Quartus II Help or

click Documentation in the ALTPLL MegaWizard Plug-In Manager.

Compile & Perform Timing Analysis

Before the Quartus II software compiles the SOPC Builder design, it runs the IP Toolbench-generated Tcl constraints script, auto_add_constraints.tcl.

The auto_add_constraints.tcl script calls the add_constraints_for_<variation

name>.tcl script for each variation in your design. The add_constraints_for_<variation name>.tcl script checks for any previously added constraints specific to that variation,

removes them, and then adds constraints for that variation.

The constraints script analyzes and elaborates your design, to automatically extract the hierarchy to your variation. To prevent the constraints script analyzing and elaborating your design, turn on Enable hierarchy control in the wizard, and enter the correct hierarchy path to your datapath (refer to step 24 on page 2–13).

When the constraints script runs, it creates another script, remove_constraints_for_<variation name>.tcl, which can be used to remove the constraints from your design.

1 Click Start Compilation (Processing menu), to run the add constraints scripts,

compile the design, and perform timing analysis.

When the compilation is complete, the Quartus II processing message tab displays the post-compilation timing analysis results. The results are also written to the <variation name>_post_summary.txt file in your project directory.

2–8 Chapter 2: Getting Started

c Turn ing o ff the Display entity name for node name setting prevents the

timing analysis script from completing successfully. To enable this setting, open the Assignments menu and click Settings. On the Settings page, click Compilation Process Settings, and then click More Settings. In the Name list, select Display entity name for node name and in the Setting list, select On.

The results show how much slack you have for each of the various timing requirements—negative slack means that you are not meeting timing. The Message window shows various timing margins for your design.

If the verify timing script reports that your design meets timing, you have successfully generated and implemented your DDR or DDR2 SDRAM Controller.

If the timing does not reach your requirements, adjust the resynchronization and postamble clock phases on the IP Toolbench Manual Timings tab (refer to “Manual

Timing Settings” on page A–1).

f For more information on how to achieve timing, refer to Appendix B, DDR SDRAM

on the Nios Development Board, Cyclone II Edition.

MegaWizard Plug-In Manager Design Flow

1 If you have “?” characters in the Quartus II Assignment Editor, the Quartus II

f For more information on constraints, refer to “Constraints” on page 3–18.

Program a Device

f For more information on OpenCore Plus hardware evaluation using the DDR or

To view the constraints in the Quartus II Assignment Editor, choose Assignment Editor (Assignments menu).

software cannot find the entity to which it is applying the constraints, probably because of a hierarchy mismatch. Either edit the constraints script, or enter the correct hierarchy path in the Hierarchy tab (refer to step 24 on page 2–13).

After you have compiled the SOPC Builder design, you can perform gate-level simulation (refer to “Simulate the SOPC Builder Design” on page 2–6) or program your targeted Altera device to verify the SOPC Builder design in hardware.

With Altera's free OpenCore Plus evaluation feature, you can evaluate the DDR or DDR2 SDRAM controller MegaCore function before you purchase a license. OpenCore Plus evaluation allows you to produce a time-limited programming file.

DDR2 SDRAM controller MegaCore function, refer to “OpenCore Plus Evaluation”

on page 1–6, “OpenCore Plus Time-Out Behavior” on page 3–3, and the AN 320:

OpenCore Plus Evaluation of Megafunctions.

MegaWizard Plug-In Manager Design Flow

MegaWizard Plug-In Manager design flow involves the following steps:

1. Create a custom variation of the DDR or DDR2 SDRAM controller MegaCore function using IP Toolbench from the MegaWizard Plug-In Manager.

DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–9

MegaWizard Plug-In Manager Design Flow

2. Use the IP Toolbench-generated IP functional simulation model to verify the operation of the example design and the example driver.

3. Use the Quartus II software to edit the PLL(s), add constraints to the example design, compile the example design, and perform post-compilation timing analysis.

4. Perform gate-level timing simulation, or if you have a suitable development board, you can generate an OpenCore Plus time-limited programming file, which you can use to verify the operation of the example design in hardware.

5. Generate a programming file for the Altera device(s) on your board.

6. Program the Altera device(s) with the completed design.

The DDR and DDR2 SDRAM Controller Compiler with MegaWizard Plug-In flow option allows you to fully specify a DDR or DDR2 SDRAM controller. With this flow, you design to a low-level interface.

DDR & DDR2 SDRAM Controller Walkthrough

If you are not using SOPC Builder, this walkthrough explains how to create a custom variation of the DDR or DDR2 SDRAM Controller MegaCore function using the Altera DDR and DDR2 SDRAM Controller IP Toolbench and the Quartus II software. As you go through the wizard, each step is described in detail.

For more information on using HardCopy II devices, refer to Appendix C, HardCopy

II Design Walkthrough.

This walkthrough requires the following steps:

■ “Create a New Quartus II Project” on page 2–9

■ “Launch IP Toolbench from the MegaWizard Plug-In Manager” on page 2–11

■ “Parameterize” on page 2–11

■ “Constraints” on page 2–15

■ “Set Up Simulation” on page 2–15

■ “Generate” on page 2–15

Create a New Quartus II Project

1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. Alternatively, you can use the Quartus II Web Edition software.

2. Choose New Project Wizard (File menu).

3. Click Next in the New Project Wizard: Introduction page (the introduction page does not display if you turned it off previously).

2–10 Chapter 2: Getting Started

MegaWizard Plug-In Manager Design Flow

4. In the New Project Wizard: Directory, Name, Top-Level Entity page, enter the following information:

a. Specify the working directory for your project. For example, this walkthrough

uses the c:\altera\projects\ddr_project directory.

b. Specify the name of the project. This walkthrough uses project for the project

name.

1 The Quartus II software automatically specifies a top-level design entity

that has the same name as the project. Do not change it.

5. Click Next to close this page and display the New Project Wizard: Add Files page.

1 When you specify a directory that does not already exist, a message asks if

the specified directory should be created. Click Yes to create the directory.

6. If you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software, you must add the user libraries:

a. Click User Libraries.

b. Type <path>\ip into the Library name box, where <path> is the directory in

which you installed the DDR and DDR2 SDRAM Controller.

c. Click Add to add the path to the Quartus II project.

d. Click OK to save the library path in the project.

7. Click Next to close this page and display the New Project Wizard: Family & Device Settings page.

8. On the New Project Wizard: Family & Device Settings page, choose the target device family in the Family list. Select Ye s for Do you want to assign a specific device?.

1 Ensure you select Ye s for Do you want to assign a specific device? to

choose a specific device, as IP Toolbench will not work correctly if you select No.

1 The DDR2 SDRAM controller only supports Cyclone II, HardCopy II,

Stratix II GX, and Stratix II devices.

1 If you are targeting a specific Altera development board, ensure you choose

the correct target device and memory type.

9. Select the target device in the Available Devices list.

10. The remaining pages in the New Project Wizard are optional. Click Finish to complete the Quartus II project.

DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–11

MegaWizard Plug-In Manager Design Flow

Launch IP Toolbench from the MegaWizard Plug-In Manager

To launch the wizard in the Quartus II software, follow these steps:

1. Start the MegaWizard Plug-In Manager by choosing the MegaWizard Plug-In Manager command (Tools menu). The MegaWizard Plug-In Manager dialog box displays.

1 Refer to Quartus II Help for more information on how to use the

MegaWizard Plug-In Manager.

2. Specify that you want to create a new custom megafunction variation and click Next.

3. Expand the Interfaces > Memory Controllers directory, then click either DDR SDRAM Controller v9.0 or DDR2 SDRAM Controller v9.0.

4. Select the output file type for your design; the wizard supports VHDL and Verilog HDL.

5. The MegaWizard Plug-In Manager shows the project path that you specified in the New Project Wizard. Append a variation name for the MegaCore function output files <project path>\<variation name>.

1 The <variation name> must be a different name from the project name and

the top-level design entity name.

6. Click Next to launch IP Toolbench.

Parameterize

To parameterize your MegaCore function, follow these steps:

f For more information on the parameters, refer to “Parameters” on page 3–31.

1. Click Step 1: Parameterize in IP Toolbench.

2. In the Presets list, click a specific memory device, Altera development board, or click Custom.

1 You can add your own memory devices to this list by editing the

memory_types.dat file in the \constraints directory.

3. Enter a Clock Speed in MHz. For example 200.0. The constraints script, timing analysis, and the datapath use this clock speed. It must be set to the value that you intend to use. The first time you use the DDR SDRAM controller IP Toolbench or if you turn on Automatically generate the PLL, it uses this value for the IP Toolbench-generated PLL’s input and output clocks (refer to “Edit the PLL” on

page 2–22).

4. Choose the memory parameters.

a. Choose your memory interface parameters.

b. Choose the memory properties.

c. Select either Registered DIMM or Unbuffered memory.

2–12 Chapter 2: Getting Started

MegaWizard Plug-In Manager Design Flow

1 Select Unbuffered memory if you are using unbuffered modules or

devices.

f For more information on memory parameters, refer to “Memory” on

page 3–32.

5. Click the Controller tab.

f For more information on controller parameters, refer to “Controller ” on

page 3–33.

6. Select Native or Avalon Memory-Mapped local interface. The Avalon-MM interface allows you to easily connect to other Avalon-MM peripherals.

f For more information on the Avalon-MM interface, refer to the Avalon

Interface Specifications.

7. Turn on the relevant clocking options.

8. Select your memory initialization options.

9. Select your memory controller options.

10. Turn on the relevant DLL reference clock options.

11. Click the Controller Timings tab.

f For more information on controller timings, refer to “Controller Timings”

on page 3–37.

12. Enter your memory timing parameters in the Required column, so that the controller timings meet the requirements specified on your memory’s datasheet. The wizard picks the appropriate number of clock cycles between commands that are needed and calculates the resulting delay in the Actual column.

1 To manually enter the number of clock cycles, turn on Manually choose

clock cycles and enter values in the Cycles column.

13. Click Memory Timings tab.

f For more information on memory timings, refer to “Memory Timings” on page 3–38.

14. If you chose Custom memory device, enter the device settings from your chosen memory’s datasheet, otherwise your chosen memory type device settings are entered automatically.

15. Click the Board Timings tab.

f For more information on board timings, refer to “Board Timings” on page 3–39.

16. Turn on Manual pin load control, if you want to enter the pin loading for the FPGA pins.

Chapter 2: Getting Started 2–13

MegaWizard Plug-In Manager Design Flow

1 You must enter suitable values for the pin loading, because the values affect

timing. Unsuitable values may lead to inaccurate timing analysis.

17. Enter the board trace delays. These delays are used by the timing analysis and to configure the datapath.

1 You must accurately set the board trace delays for your system to work in

hardware.

18. Click Show Timing Estimates, at any time in the parameterize screen ), to see the results of the system timing analysis.

19. Click the Project Settings tab.

f For more information on project settings, refer to “Project Settings” on

page 3–40.

20. Enter the pin name of the clock driving the memory (+); enter the pin name of the clock driving the memory (–). IP Toolbench suggests the name for the fed-back clock input, but you can edit this name if you wish.

1 The pin names must end in [0], even if you have more than one clock pair. 1 Only change the suggested clock pin names, if you have edited the clock

pin names in the top-level design file. Changing the clock pin names changes the names of the clock outputs and fed-back clock in the example top-level design.

21. Ensure Update the example design file that instantiates the controller variation is turned on, for IP Toolbench to automatically update the example design and the testbench.

22. Altera recommends that you turn on Automatically apply datapath-specific

contraints to the Quartus II project and Automatically verify datapath-specific timing in the Quartus II project, so that the Quartus II software automatically

runs these scripts when you compile the example design.

23. Turn off Update the example design PLLs, if you have edited the PLL and you do not want the wizard to regenerate the PLL when you regenerate the variation.

24. The constraints script analyzes and elaborates your design to automatically extract the hierarchy to your variation. To prevent the constraints script analyzing and elaborating your design, turn on Enable hierarchy control, and enter the correct hierarchy path to your variation. The hierarchy path is the path to the datapath in your DDR SDRAM controller, without the top-level name. Figure 2–1 on

page 2–14 shows a system example.

1 The constraints apply to the datapath (rather than the controller) so that if

you replace the controller logic with your own controller, the add constraints script is still valid. So, if you maintain the entity and instance names, the Quartus II software will correctly add the constraints to your design.

2–14 Chapter 2: Getting Started

DDR SDRAM

Other Logic

PLL

DDR SDRAM

Interface

example_top

Example Top-Level Design

my_ddr_sdram

DDR SDRAM Controller

Data Path

auk_ddr_sdram

my_system

System

MegaWizard Plug-In Manager Design Flow

Figure 2–1. System Naming

25. IP Toolbench uses a prefix (for example, ddr_, or ddr2_) for the names of all memory interface pins. Enter a prefix for all memory interface pins associated with this custom variation.

26. If you want to access the manual timing settings, click the Manual Timing tab. Otherwise, click Finish and proceed to “Constraints” on page 2–15.

f For more information on the manual timing settings, refer to Appendix A,

Manual Timing Settings.

27. Choose Automatic, Always, or Never in the Reclock resynchronized data to the positive edge list.

28. Turn on Manual resynchronization control, only if you want to override the wizard-calculated values.

1 Under most circumstances, IP Toolbench calculates the correct

resynchronization settings for your custom variation.

f For more information on resynchronization, refer to “Resynchronization”

on page A–4.

29. Turn on Manual postamble control, only if you want to override the wizard-calculated values.

1 Under most circumstances, IP Toolbench calculates the correct postamble

settings for your custom variation.

f For more information on postamble, refer to “DQS Postamble” on

page A–10.

30. Turn on your timing analysis options.

31. Click Finish.

Chapter 2: Getting Started 2–15

MegaWizard Plug-In Manager Design Flow

Constraints

To choose the constraints for your device, follow these steps:

1. Click Step 2: Constraints in IP Toolbench.

2. Choose the positions on the device for each of the DDR SDRAM byte groups. To place a byte group, select the byte group in the drop-down box at your chosen position.

1 The floorplan matches the orientation of the Quartus II floorplanner. The

layout represents the die as viewed from above. A byte group consists of four or eight DQ pins, a DM pin, and a DQS pin.

1 IP Toolbench chooses the correct positions, if you are using an Altera board

preset.

Set Up Simulation

An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model produced by the Quartus II software. The model allows for fast functional simulation of IP using industry-standard VHDL and Verilog HDL simulators.

c You may only use these simulation model output files for simulation

purposes and expressly not for synthesis or any other purposes. Using these models for synthesis will create a nonfunctional design.

To generate an IP functional simulation model for your MegaCore function, follow these steps:

1. Click Step 3: Set Up Simulation in IP Toolbench.

2. Turn on Generate Simulation Model.

3. Choose the language in the Language list.

1 To use the IP Toolbench-generated testbench, choose the same language

that you chose for your variation.

4. Some third-party synthesis tools can use a netlist that contains only the structure of the MegaCore function, but not detailed logic, to optimize performance of the design that contains the MegaCore function. If your synthesis tool supports this feature, turn on Generate netlist.

5. Click OK.

Generate

To generate your MegaCore function, follow these steps:

1. Click Step 4: Generate in IP Toolbench.

Tab le 2– 1 describes the generated files and other files that may be in your project

directory. The names and types of files specified in the IP Toolbench report vary based on whether you created your design with VHDL or Verilog HDL.

2–16 Chapter 2: Getting Started

MegaWizard Plug-In Manager Design Flow

Table 2–1. Generated Files (Part 1 of 2) (Note 1) (2)

Filename Description

<variation name>.bsf Quartus II symbol file for the MegaCore function variation. You

can use this file in the Quartus II block diagram editor.

<variation name>.html MegaCore function report file.

<variation name>.vo or .vho VHDL or Verilog HDL IP functional simulation model.

<variation name> .v or .vhd A MegaCore function variation file, which defines a VHDL or

Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.

<variation name>_bb.v Verilog HDL black-box file for the MegaCore function variation.

Use this file when using a third-party EDA tool to synthesize your design.

<variation name>_auk_ddr_clk_gen.v or .vhd Design file that contains the clock output generators.

<variation name>_auk_ddr_datapath.v or .vhd Design file that instantiates the byte groups and the clock output

generators.

<variation name>_auk_ddr_datapath_pack.v or .vhd A VHDL package, which contains a component that the IP

functional simulation model uses.

<variation name>_auk_ddr_dll.v or .vhd Optional design file that instantiates the Stratix or Stratix II DLL

(Stratix series only).

<variation name>_auk_ddr_dqs_group.v or .vhd Design file that contains the datapath byte groups.

<variation name>_auk_ddr_sdram.v or .vhd Design file that instantiates the controller logic and the datapath

<variation name>_ddr_sdram_vsim.tcl The ModelSim simulation script.

<variation name>_example_driver.v or .vhd The example driver.

<variation name>_example_settings.txt The settings file for your variation, which the add constraints

and the verify timing scripts use.

<variation name>.qip Contains Quartus II project information for your MegaCore

function variations.

<variation name>.v or .vhd (1) Example design file.

add_constraints_for_<variation name>.tcl The add constraints script for the variation.

altera_vhdl_support.vhd A VHDL package that contains functions for the generated

entities. This file may be shared between MegaCore functions.

auto_add_ddr_constraints.tcl The add constraints script, which calls the variation-specific add

constraints scripts.

auto_verify_ddr_timing_constraints.tcl The auto verify timing script, which calls the variation-specific

verify timing scripts.

constraints_out.txt

Log file that IP Toolbench creates while generating the add constraints script.

ddr_lib_path.tcl The Tcl library path file.

ddr_pll_fb_stratixii.v or .vhd Design file for the Stratix II fedback PLL.

ddr_pll_<device name>.v or .vhd Design file for the system PLL.

generic_ddr_dimm_model.vhd VHDL simulation file.

generic_ddr_sdram.vhd VHDL simulation file.

generic_ddr2_sdram.vhd VHDL simulation file.

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MegaWizard Plug-In Manager Design Flow

Table 2–1. Generated Files (Part 2 of 2) (Note 1) (2)

Filename Description

remove_constraints_for_<variation name>.tcl The remove constraints script for the variation.

top_ddr_settings.txt Critical settings file that stores the custom variation’s

parameters. IP Toolbench uses this file to generate the add constraints script. The verify timing script and the DDR Timing Wizard also read this file.

top_pre_compile_ddr_timing_summary.txt Log file that stores the results of the precompilation system

timing analysis.

verify_timing_for_<variation name>.tcl The verify timing script.

Notes to Table 2–1:

(1) <project name> is the name of the Quartus II project top-level entity. (2) <variation name> is the name you give to the controller you create with the Megawizard.

2. After you review the generation report, click Exit to close IP Toolbench.

1 The Quartus II IP File (.qip) is a file generated by the MegaWizard interface or SOPC

Builder that contains information about a generated IP core. You are prompted to add this .qip file to the current Quartus II project at the time of file generation. In most cases, the .qip file contains all of the necessary assignments and information required to process the core or system in the Quartus II compiler. Generally, a single .qip file is generated for each MegaCore function and for each SOPC Builder system. However, some more complex SOPC Builder components generate a separate .qip file, so the system .qip file references the component .qip file.

You have finished the walkthrough. Now, simulate the example design (see

“Simulate the Example Design” on page 2–17), edit the PLL(s), and compile (refer to “Compile the Example Design” on page 2–22).

Simulate the Example Design

You can simulate the example design with the IP Toolbench-generated IP functional simulation models. IP Toolbench generates a VHDL or Verilog HDL testbench for your example design, which is in the testbench directory in your project directory.

f For more information on the testbench, refer to “Example Design” on page 3–16.

You can use the IP functional simulation model with any Altera-supported VHDL or Verilog HDL simulator. The instructions for the ModelSim simulator are different to other simulators.

Simulating With the ModelSim Simulator

To simulate the example design with the ModelSim® simulator, follow these steps:

1. Obtain a memory model that matches your chosen parameters and save it to the <directory name>\testbench directory. For example, you can download a Micron memory model from the Micron web site at www.micron.com.

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2. For VHDL, edit generic_ddr_sdram.vhd to instantiate your memory model (the file already contains three example Micron memory model instantiations).

For Verilog HDL, edit the memory instantiations in the testbench to match your memory model.

3. Start the ModelSim-Altera simulator.

4. Change your working directory to your IP Toolbench-generated file directory <directory name>\testbench\modelsim.

5. Type the following command:

set memory_model <model_name>r

where <model_name> is the filename of the downloaded memory model.

6. To simulate with an IP functional simulation model simulation, type the following command:

source <variation name>_ddr_sdram_vsim.tclr

7. For a gate-level timing simulation (VHDL or Verilog HDL ModelSim output from the Quartus II software), type the following commands:

set use_gate_model 1r source <variation name>_ddr_sdram_vsim.tclr

Simulating With Other Simulators

The IP Toollbench-generated Tcl script is for the ModelSim simulator only. If you prefer to use a different simulation tool, follow these instructions. You can also use the generated script as a guide. You also need to download and compile an appropriate memory model.

1 The following variables apply in this section:

■ <QUARTUS ROOTDIR> is the Quartus II installation directory

■ <simulator name> is the name of your simulation tool

■ <device name> is the Altera device family name

■ <project name> is the name of your Quartus II top-level entity or module.

■ <testbench name> is the name of your testbench entity or module

■ <MegaCore install directory> is the DDR and DDR2 SDRAM Controller

installation directory

Chapter 2: Getting Started 2–19

MegaWizard Plug-In Manager Design Flow

VHDL IP Functional Simulations

For VHDL simulations with IP functional simulation models, follow these steps:

1. Create a directory in the <project directory>\testbench directory.

2. Launch your simulation tool inside this directory and create the following libraries:

■ altera_mf

■ lpm

■ sgate

■ <device name>

■ altera

■ auk_ddr_user_lib

3. Compile the files in Table 2–2 into the appropriate library. The files are in VHDL93 format.

Table 2–2. Files to Compile—VHDL IP Functional Simulation Models

Library Filename

altera_mf <QUARTUS ROOTDIR>/eda/sim_lib/altera_mf_components.vhd

<QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.vhd

lpm <QUARTUS ROOTDIR>/eda/sim_lib/220pack.vhd

<QUARTUS ROOTDIR>/eda/sim_lib/220model.vhd

sgate <QUARTUS ROOTDIR>/eda/sim_lib/sgate_pack.vhd

<QUARTUS ROOTDIR>/eda/sim_lib/sgate.vhd

<device name><QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.vhd

<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_components.vhd

altera <QUARTUS ROOTDIR>/libraries/vhdl/altera/altera_europa_support_lib.vhd

auk_ddr_user_lib <MegaCore install directory>/lib/auk_ddr_tb_functions.vhd

<project directory>/<variation name>_auk_ddr_dqs_group.vhd

<project directory>/<variation name>_auk_ddr_clk_gen.vhd

<project directory>/<variation name>_auk_ddr_datapath.vhd

<project directory>/<variation name>_auk_ddr_datapath_pack.vhd

<project directory>/<v>.vho

<MegaCore install directory>/lib/example_lfsr8.vhd

/<variation name>_example_driver.vhd

<project directory>/ddr_pll_<device name>.vhd

<project directory>/ddr_pll_fb_<device name>.vhd (1)

<project directory>/<variation name>_auk_ddr_dll.vhd (2)

<project directory>/<project name>.vhd

<project directory>/testbench/<testbench name>.vhd

Notes to Table 2–2:

(1) Fed-back clock mode only. (2) Stratix series only.

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4. Set the Tcl variable gRTL_DELAYS to 1, which tells the testbench to model the extra delays in the system necessary for RTL simulation

5. Load the testbench in your simulator with the timestep set to picoseconds.

VHDL Gate-Level Simulations

For VHDL simulations with gate-level models, follow these steps:

1. Create a directory in the <project directory>\testbench directory.

2. Launch your simulation tool inside this directory and create the following libraries.

■ <device name>

■ altera

■ auk_ddr_user_lib

3. Compile the files in Table 2–3 into the appropriate library. The files are in VHDL93 format.

Table 2–3. Files to Compile—VHDL Gate-Level Simulations

Library Filename

<device name><QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.vhd

<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_components.vhd

altera <QUARTUS ROOTDIR>/libraries/vhdl/altera/altera_europa_support_lib.vhd

auk_ddr_user_lib <MegaCore install directory>/lib/auk_ddr_tb_functions.vhd

<project directory>/simulation/<simulator name>/<project name>.vho (1)

<project directory>/testbench/<testbench name>.vhd

Notes to Table 2–3:

(1) If you are simulating the slow or fast model, the .vho file has a suffix _min or _max added to it. Compile whichever file is appropriate. The

Quartus II software creates models for the simulator you have defined in a directory simulation/<simulator name> in your <project name> directory..

4. Set the Tcl variable gRTL_DELAYS to 0, which tells the testbench not to use the insert extra delays in the system, because these are applied inside the gate-level model.

5. Load the testbench in your simulator with the timestep set to picoseconds.

+ 76 hidden pages

Altera DDR SDRAM Controller User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Release Information

1. About This Compiler

Device Family Support

Features

General Description

Performance and Resource Utilization

Installation and Licensing

OpenCore Plus Evaluation

Design Flow

2. Getting Started

SOPC Builder Design Flow

DDR & DDR2 SDRAM Controller Walkthrough

Create Your Top-Level Design

Simulate the SOPC Builder Design

Compile the SOPC Builder Design

MegaWizard Plug-In Manager Design Flow

Program a Device

DDR & DDR2 SDRAM Controller Walkthrough

Simulate the Example Design