Altera Cyclone III Development Board User Manual

Cyclone III 3C120 Development Board

Reference Manual

101 Innovation Drive San Jose, CA 95134

www.alter a.com

Document Version: 1.4 Document Date: March 2009

Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services

MNL-01029-1.4

Chapter 1. Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

Chapter 2. Board Components

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Featured FPGA (U20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

I/O and Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

MAX II CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

FPGA Programming Over USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Flash Programming over USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Board Specific LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Power Display (U28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

JTAG Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

MAX II Device Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

System Reset and Configuration Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

POWER SELECT Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

PGM CONFIG SELECT Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Speaker Header (J5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Clocking Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Cyclone III FPGA Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Cyclone III FPGA Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

General User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

User-Defined Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

DDR2 User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

7-Segment Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

User 7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

Power 7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

LCD Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

Character LCD (J4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

Graphics LCD (J13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Communication Ports and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

USB 2.0 MAC/PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–40

High-Speed Mezzanine Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

On-Board Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–54

Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–58

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–62

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–64

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–64

Additional Information

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–2

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–2

Cyclone III 3C120 Development Board Reference Manual © March 2009 Altera Corporation

Introduction

This document describes the hardware features of the Cyclone® III development board, including detailed pin-out information to enable you to create custom FPGA designs that interface with all components of the board.

f For information about setting up and powering up the Cyclone III development

board and using the kit’s demo software, refer to the Cyclone III Development Kit User

Guide.

General Description

The Cyclone® III development board provides a hardware platform for developing and prototyping low-power, high-volume, and feature-rich designs as well as to demonstrate the Cyclone III device’s on-chip memory, embedded multipliers, and the Nios® II embedded processor.

1. Overview

With up to 4 Mbits of embedded memory and 288 embedded 18-bit × 18-bit multipliers, the Cyclone III device supplies internal memory while also providing external support for high-speed, low-latency memory access via dual-channel DDR SDRAM and low-power SRAM.

Built on TSMC’s 65-nm low-power process technology, Cyclone III devices are designed to provide low static and dynamic power consumption. Additionally, with the support of the Quartus® II software’s PowerPlay technology, designs are automatically optimized for power consumption. Therefore, the Cy clone III development board provides a power-optimized, integrated solution for memory-intensive, high-volume applications.

Accordingly, the Cyclone III development board is especially suitable for wireless, video and image processing, and other high-bandwidth, parallel processing applications. Through the use of Altera®-provided video and image intellectual property (or other MegaCore® functions) and board expansion connectors, you can enable the inter-operability of the Cyclone III device, allowing application-specific customization of the development board.

f For more information about the Altera Video and Image Processing Suite MegaCore

functions, refer to the Video and Image Processing Suite User Guide.

To get you started, Altera provides application-specific design examples. The pre-built and tested design examples allow you to:

■ Create a Cyclone III FPGA design in an hour

■ View Cyclone III FPGA power measurement examples

■ Design a 32-bit soft processor system inside the Cyclone III FPGA in an hour

1–2 Chapter 1: Overview

General Description

The Cyclone III development board has the following main features:

■ High logic density to implement more functions and features

■ Embedded memory for high-bandwidth applications

■ Expandable through two Altera High-Speed Mezzanine Connectors (HSMCs)

■ 256-MB of dual channel DDR2 SDRAM with a 72-bit data width

■ Supports high-speed external memory interfaces including dual-channel DDR

SDRAM and low-power SRAM

■ Four user push-button switches

■ Eight user LEDs

■ Power consumption display

The Cyclone III development board provides the following advantages:

■ Unique combination of low-cost, low-power Cyclone III FPGA that supports

high-volume, memory-intensive designs

■ Highest multiplier-to-logic ratio FPGA in the industry

■ Lowest cost, density- and power-optimized FPGA

■ Quartus II development software’s power optimization tools

Board Component Blocks

The board features the following major component blocks:

■ 780-pin Altera Cyclone III EP3C120 FPGA in a BGA package

■ 119K logic elements (LEs)

■ 3,888 Kbits of memory

■ 288 18 × 18 multiplier blocks

■ Four phase locked loops (PLLs)

■ 20 global clock networks

■ 531 user I/Os

■ 1.2-V core power

■ 256-pin Altera MAX

package

■ 1.8-V core power

■ On-board memory

■ 256-MB dual-channel DDR2 SDRAM

II EPM2210G CPLD in a FineLine Ball Grid Array (FBGA)

■ 8-MB SRAM

■ 64-MB flash memory

Cyclone III 3C120 Development Board Reference Manual © March 2009 Altera Corporation

Chapter 1: Overview 1–3

General Description

■ FPGA configuration circuitry

■ MAX II CPLD and flash passive serial configuration

■ On-board USB-Blaster™ circuitry using the Quartus II Programmer

■ On-board clocking circuitry

■ Two clock oscillators to support Cyclone III device user logic

■ 50 MHz

■ 125 MHz

■ 80 I/O, 6 clocks, SMBus, and JTAG

■ SMA connector for external clock input and output

■ General user and configuration interfaces

■ LEDs/displays:

■ Eight user LEDs

■ One transmit/receive LED (TX/RX) per HSMC interface

■ One configuration done LED

■ Ethernet LEDs

■ User 7-segment d isplay

■ Power consumption display

■ Memory activity LEDs:

■ SRAM

■ FLASH

■ DDR2 Top

■ DDR2 Bottom

■ Push-buttons:

■ One user reset push-button (CPU reset)

■ Four general user push-buttons

■ One system reset push-button (user configuration)

■ One factory push-button switch (factory configuration)

■ DIP switches:

■ One MAX control DIP switch

■ One JTAG control switch

■ Eight user DIP switches

■ Speaker header

■ Displays

■ 128 × 64 graphics LCD

■ 16 × 2 line character LCD

1–4 Chapter 1: Overview

CMOS + LVDS

Cyclone III

EP3C120F780

125 MHz

XTAL

SMA Input

MAX II

Device (x32)

2.5V CMOS

1.8V CMOS

Power

Measure/

Display

HSMC Port A

CMOS + LVDS

HSMC Port B

8MB SRAM

(x32)

64MB Flash

(x16)

256MB DDR2 Dual Channel

(x72)

USB

2.0

1.8V CMOS

50 MHz

Buttons/

Switches

1.8V CMOS

Quad 7-Seg/

User LEDs

1.8V SSTL

SMA Output

10/100/1000

Ethernet

2.5V CMOS

RJ-45

Jack

Graphics LCD

Character LCD

LP Filter and

Audio Amp

2.5V CMOS

Speaker

Header

General Description

■ Power supply

■ 14 V – 20 V DC input

■ On-board power measurement circuitry

■ Up to 19.8 W per HSMC interface

■ Mechanical

■ 6” × 8” board

■ Bench-top design

1 The Cyclone III FPGA Development Kit ships with additional HSMC daughter card

loopback and break-out headers for convenient testing of some of the HSMC signals. For more details regarding these test daughter cards, refer to their respective schematics at these locations in the installed kit directory:

■ <path>\board_design_files\schematic\breakout_hsmc

debug_header_breakout.pdf

■ <path>\board_design_files\schematic\loopback_hsmc

loopback_test_lowcost.pdf

Block Diagram

Figure 1–1 shows the functional block diagram of the Cyclone III development board.

Figure 1–1. Cyclone III Development Board Block Diagram

Cyclone III 3C120 Development Board Reference Manual © March 2009 Altera Corporation

Chapter 1: Overview 1–5

Handling the Board

When handling the board, it is important to observe the following precaution:

c Static Discharge Precaution: Without proper anti-static handling, the board can be

damaged. Therefore, use anti-static handling precautions when touching the board.

1–6 Chapter 1: Overview

Handling the Board

Cyclone III 3C120 Development Board Reference Manual © March 2009 Altera Corporation

Introduction

2. Board Components

This chapter introduces all the important components on the Cyclone III development board. Figure 2–1 illustrates all component locations and Ta bl e 2–1 describes component features.

The chapter is divided into the following sections:

■ “Featured FPGA (U20)” on page 2–4

■ “MAX II CPLD” on page 2–6

■ “Configuration, Status, and Setup Elements” on page 2–14

■ “Clocking Circuitry” on page 2–23

■ “General User Interfaces” on page 2–26

■ “Communication Ports and Interfaces” on page 2–37

■ “On-Board Memory” on page 2–48

■ “Power Supply” on page 2–62

■ “Statement of China-RoHS Compliance” on page 2–64

1 A complete set of board schematics, a physical layout database, and GERBER files for

the Cyclone III development board are installed in the Cyclone III Development Kit documents directory.

f For information about powering up the development board and installing the demo

software, refer to the Cyclone III Development Kit User Guide.

Board Overview

This section provides an overview of the Cyclone III development board, including an annotated board image and component descriptions.

Figure 2–1 shows the top view of the Cyclone III development board.

2–2 Chapter 2: Board Components

Speaker Header (J5)

DC Power Jack (J2)

Ethernet PHY

LEDs (D1, D3, D4)

Ethernet PHY

Duplex LED (D6)

Powe r

Switch (SW2)

Powe r

LED (D5)

Ethernet PHY TX/RX

Activity LEDS (D7, D8)

MAX II CPLD (U7)

DDR2 SDRAM Device Interface

Four x16 and one x8

(U11, U12, U25, U26, U13)

(Three on Top and Two on Bottom)

DDR2TOP_ACTIVE

LED (D11)

Cyclone III FPGA (U20)

MAX II Device

Control DIP

Switch (SW1)

24-MHz Crystal (Y1)

6-MHz Crystal (Y2)

Clock Out SMA (J11)

HSMC Port B Present LED (D19)

PGM Config Select Rotary Switch (SW5)

User Push Buttons

(S1 through S4)

User DIP

Switch (SW6)

CPU Reset Push

Button Switch (S5)

Power Select

Rotary Switch (SW4)

User Defined 7-Segment Display (U30)

Board-Specific LEDs (D20 through D24)

SRAM Active LED (D17)

HSMC Port A

Present LED (D18)

Clock In SMA (J10)

Power Display (U28)

Flash Active

LED (D23)

Configuration

Done LED (D25)

User LEDs

(D26 through D33)

Reset and

Factory Configuration Push Buttons

(S6 and S7)

DDR2BOT_ACTIVE

LED (D16)

50-MHz

Clock (Y5)

125-MHz

Clock (Y4)

24-MHz USB-

Blaster Clock (Y3)

JTAG Control

DIP Switch (SW3)

Graphics

LCD (J13)

HSMC Port B (J9) (Debug Header Shown)

HSMC Port A (J8)

(Loopback Board Shown)

Device Select Jumper (J6)

Board Overview

Figure 2–1. Top View of the Cyclone III Development Board

Ta b l e 2–1 describes the components and lists their corresponding board references.

Table 2–1. Cyclone III Development Boar d (Part 1 of 3)

Board Ref erence Type Description

Featured Devices

U20 FPGA EP3C120, 780-pin FineLine BGA pac kage.

U7 CPLD EPM2210G, 256-pin device in a FineLine BGA package.

Configuration Status and Setup Element s

J6 Device select

(DEV_SEL) jumper

J3 Input Type B USB connector that allows for connecting a Type A-B USB cable

D20 through D24 User LEDs Board-specific configuration green LEDs.

D25 Configuration done LED Green LED that illuminates when the FPGA is successfully configured.

Sets target device for JTAG signals when using an external USB-Blaster or equivalent.

between a PC and the board.

D12 through D15 Channel activity LEDs Green LEDs that indicate the RX and TX activity on the HSMC Ports A or B.

Cyclone III 3C120 Development Board Reference Manual © March 2009 Altera Corporation

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Cyclone III Development Boar d (Part 2 of 3)

Board Ref erence Type Description

J5 Header Speaker header.

D1, D3, D4 Ethernet PHY LEDs Green Ethernet PHY LEDs. Illuminate when Ethernet PHY is using the

10/100/1000 Mbps (D1, D3, D4) connection speeds.

D6 Duplex Ethernet PHY

LED

Green Ethernet PHY LED. Illuminates when Ethernet PHY is both sending and receiving data.

D5 Power LED Blue LED indicates when power is applied to the board.

D7, D8 Ethernet PHY

transmit/receive activity

Green LED. Illuminates when transmit/receive data is active from the Ethernet PHY.

LEDs

SW1 MAX II device control

Controls various features specific to the Cyclone III development board.

DIP switch

SW3 JTAG control switch JTAG control DIP switch used to remove or include devices in the active JTAG

chain.

D17 SRAM active SRAM active LED. Illuminates when the SRAM device is accessed.

D23 Flash active Flash active LED. Illuminates when the flash device is accessed.

U28 Power display Displays power measured by the MAX II CPLD.

D16 DDR2 LED Indicates that the DDR2 top devices are active.

D11 DDR2 LED Indicates that the DDR2 bottom devices are active.

Cloc k Circuitry

Y4 125 MHz 125-MHz clock oscillator used for the system clock.

Y5 50 MHz 50-MHz clock oscillat or used for data processing.

Y1 24-MHz crystal Cypress USB PHY.

Y2 6-MHz crystal USB PHY FTDI reference clock.

Y3 24 MHz MAX II device clock.

J10 SMA clock input SMA connector that allows the provisi on of an ext ernal clock input.

J11 SMA clock output SMA connector that allows the provision of an external clock output.

General User Input and Output

S1 through S4 User push buttons Four 1.8-V push-button switches for user-defined, logic inputs.

S5 CPU reset push button One 1.8-V push-button switch for FPGA logic and CPU reset.

S6 and S7 Reset and factory

confi guration push

Two 1.8-V push-button switches that control FPGA configuration from flash memory.

buttons

D26 through D33 User LEDs Eight user-defined LEDs.

SW5 PGM CONFIG SELECT Rotary switch to select which FPGA configuration file to use in flash memory.

SW4 Power select rotary

Power rail select for on-board power monitor.

switch

U30 User display User-defined, green 7-segment display.

J4 Character LCD 14-pin LCD display.

J13 Graphics LCD 30-posit ion dot matrix graphics LCD display.

Memory

U31 Flash 64 MB of flash memory with a 16-bit data bus.

2–4 Chapter 2: Board Components

Featured FPGA (U20)

Table 2–1. Cyclone III Development Boar d (Part 3 of 3)

Board Ref erence Type Description

U23 and U24 SRAM The SRAM devices connect to the MAX II device as well as the flash memory

device.

U11, U12, U13, U25, U26

Components and Inter faces

U6 USB device USB device that provides JTAG programming of on-board devices, including

U3 Ethernet cable jack The RF-45 jack is for Ethernet cabl e connection. The connector is fed by a

J8, J9 HSMC Port A and Port B High-speed mezzanine header allows for the connection of HSMC daughter

Power Supply

J2 DC power jack 14–20 V DC power source.

SW2 Input Switches the board’s power on and off.

DDR2 SDRAM Four ×16 devices and a single ×8 device.

the Cyclone III device and flash memory device.

10/100/1000 base T PHY device with an RGMII interface to the Cyclone III device.

cards.

Featured FPGA (U20)

The Cyclone III Development Kit features the EP3C120F780 device (U20) in a 780-pin BGA package.

f For more information about Cyclone III devices, refer to the Cyclone III Device

Handbook.

Ta b l e 2–2 lists the main Cyclone III device features.

Table 2–2. Cyclone III Device Features

Feature Quantity

Logic elements 119,088

Memory (Kbits) 3,888

Multipliers 288

PLLs 4

Global clock ne tworks 20

Ta b l e 2–3 lists the Cyclone III component reference and manufacturing information.

Table 2–3. Cyclone III Component Reference and Manufacturing Information

Manufact uring

Board Reference Description Manufact urer

U20 Memory rich FPGA device Altera Corporation EP3C120F780 www.altera.com

Cyclone III 3C120 Development Board Reference Manual © March 2009 Altera Corporation

Part Number

Manufacturer

Website

Chapter 2: Board Components 2–5

Featured FPGA (U20)

Ta b l e 2–4 lists the Cyclone III EP3C120F780C7 device pin count.

Table 2–4. Cyclone III Device Pin Count

Function I/O Type I/O Count Special Pins

Oscil lators and SMAs 1.8-V CMOS 4 Three clock inputs, one

output

DDR2 1.8-V SSTL 148 Nine data strobe signal

(DQS), 10 V

REF

Flash/SRAM/MAX 1.8-V CMOS 78 —

Horizontal bank OCT calibration 1.8-V CMOS 4 2 Rup, 2 Rdn

Vertical bank OCT calibration 2.5-V CMOS 4 2 Rup, 2 Rdn

Passive serial configuration 2.5-V CMOS 2 DATAO, DCLK

Ether net 2.5-V CMOS 16 1 clock input

Buttons, Switches, LEDs 1.8-V CMOS 34 DEV_CLR

Character LCD, Graphics LCD 2.5-V CMOS 14 —

Speaker header 2.5-V CMOS 1 —

USB 2.5-V CMOS 14 1 clock input

HSMC Port A 2.5-V CMOS

2.5-V LVDS

86 5 clock inputs

(1 single-ended,

2 dif ferential)

HSMC Port B 2.5-V CMOS

2.5-V LVDS

86 5 clock inputs

(1 single-ended,

2 dif ferential)

Device I/O total: 491

f For additional information about Altera devices, go to

www.altera.com/products/devices.

I/O and Clocking Resources

This section lists specific I/O and clocking resources available with the EP3C120F780C7 device, which is the largest of the Cyclone III devices.

Figure 2–2 illustrates the available I/O bank resources on the EP3C120F780C7 device.

2–6 Chapter 2: Board Components

MAX II CPLD

Figure 2–2. Cyclone III Device I/O Bank Resources

72 I/O 72 I/O

B8 B7

MAX II CPLD

58 I/O

63 I/O

73 I/O 71 I/O

58 I/O

65 I/O

The board utilizes an Altera MAX II CPLD for the following purposes:

■ Power-up configuration of the FPGA from flash memory

■ Embedded USB-Blaster core for USB-based configuration of the FPGA

■ Power consumption monitoring and display

There are two USB MAC/PHY devices— FTDI and Cypress USB PHY devices— on the board. They are muxed through the MAX II CPLD. Only one can operate at any time. The FTDI device is the default device and it supports the embedded blaster functionality. The Cypress USB PHY is held in reset and is reserved for future use. Each device has a shared path between the USB device and the MAX II CPLD. The individual paths then drive to the FPGA separately. Figure 2–3 illustrates the MAX II device’s block diagram.

Cyclone III 3C120 Development Board Reference Manual © March 2009 Altera Corporation

Chapter 2: Board Components 2–7

MAX II CPLD

Figure 2–3. MAX II Device’s Block Diagram

Power Display

JTAG

Header

64-MB

Flash (x16)

8-MB

SRAM (x32)

Cyclone III

Device

EP3C120F780

To FPGA

1.8-V CMOS FSM Bus

24 MHz

PS Config

JTAG Config

USB Data Bus

PWR_SEL

PGM_CONFIG_SEL

Power

Measure

2.5 V CMOS

MAX II CPLD

EPM2210GF256

CPU_RESET

2.5 V CMOS

RESET_CONFIG

2.5-V CMOS

1.8-V CMOS

FACTORY_CONFIG

Cypress 480 Mbps

USB (x16)

FTDI

12 Mbps USB (x8)

MAX II Device

Control DIP Switch

JTAG Control

DIP Switch

Config Status

LEDs

Ta b l e 2–5 lists the I/O signals present on the MAX II CPLD. The signal name and

function are relative to the MAX II device.

Table 2–5. MAX II Device Pi n-Out (Note 1) (Part 1 of 8)

Schematic

MAX II Pin Number I/O Stand ard Signal Direction

Signal Name

P3 — Input TCK

L6 — Input TDI

M5 — Output TDO

N4 — Input TMS

C14 1.8 V Output CLKIN_125_EN

J12 1.8 V Input CLKIN_24

E13 1.8 V Output CLKI N_50_EN

M9 1.8 V Input CPU_RESETn

F11 1.8 V Input DEV_SEL

A10 2.5 V Input FACTORY_CONFIGn

G13 1.8 V Output FLASH_ACTIVE

L15 1.8 V Output FLAS H_BYTEn

K14 1.8 V Output FLASH_CEn

2–8 Chapter 2: Board Components

MAX II CPLD

Table 2–5. MAX II Device Pi n-Out (Note 1) (Part 2 of 8)

Schematic

MAX II Pin Number I/O Stand ard Signal Direction

Signal Name

M16 1.8 V Output FLASH_OEn

L11 1.8 V Input FLASH _RDYBSYn

M15 1.8 V Output FLASH_RESETn

L12 1.8 V Output FLASH_WEn

J16 1.8 V Input FPGA_BYPASS

E3 2.5 V Input FPGA_CONF_DONE

D3 2.5 V Output FPGA_DATA

C2 2.5 V Output FPGA_DCLK

N3 2.5 V Input FPGA_JTAG_TCK

N1 2.5 V Output FPGA_JTAG_ TDI

N2 2.5 V Input FPGA_JTAG_TDO

P2 2.5 V Input FPGA_JTAG_TMS

E4 2.5 V Output FPGA_nCONFIG

C3 2.5 V Input FPGA_nSTATUS

N9 1.8 V Output FSA[0]

T8 1.8 V Output FSA[1]

N10 1.8 V Output FSA[10]

R11 1.8 V Output FSA[11]

P10 1.8 V Output FSA[12]

T12 1.8 V Output FSA[13]

M11 1.8 V Output FSA[14]

R12 1.8 V Output FSA[15]

N11 1.8 V Output FSA[16]

T13 1.8 V Output FSA[17]

P11 1.8 V Output FSA[18]

R13 1.8 V Output FSA[19]

T9 1.8 V Output FSA[2]

M12 1.8 V Output FSA[20]

R14 1.8 V Output FSA[21]

N12 1.8 V Output FSA[22]

T15 1.8 V Output FSA[23]

P12 1.8 V Output FSA[24]

R9 1.8 V Output FSA[3]

P9 1.8 V Output FSA[4]

T10 1.8 V Output FSA[5]

K16 1.8 V Output FSA[6]

R10 1.8 V Output FSA[7]

M10 1.8 V Output FSA[8]

T11 1.8 V Output FSA[9]

Cyclone III 3C120 Development Board Reference Manual © March 2009 Altera Corporation

Chapter 2: Board Components 2–9

MAX II CPLD

Table 2–5. MAX II Device Pi n-Out (Note 1) (Part 3 of 8)

Schematic

MAX II Pin Number I/O Stand ard Signal Direction

Signal Name

P4 1.8 V Bidi rectional FSD[0]

R1 1.8 V Bidirectional FSD[1]

M6 1.8 V Bidirectional FS D[10]

R5 1.8 V Bidirectional FSD[11]

P7 1.8 V Bidi rectional FSD[12]

T5 1.8 V Bidirectional FSD[13]

N7 1.8 V Bidirectional FSD[14]

R6 1.8 V Bidirectional FSD[15]

M7 1.8 V Bidirectional FS D[16]

T6 1.8 V Bidirectional FSD[17]

J15 1.8 V Bidirectional FSD[18]

R7 1.8 V Bidirectional FSD[19]

P5 1.8 V Bidi rectional FSD[2]

P8 1.8 V Bidi rectional FSD[20]

T7 1.8 V Bidirectional FSD[21]

N8 1.8 V Bidirectional FSD[22]

R8 1.8 V Bidirectional FSD[23]

F12 1.8 V Bidirectional FSD[24]

D16 1.8 V Bidirectional FSD[25]

F13 1.8 V Bidirectional FSD[26]

D15 1.8 V Bidirectional FSD[27]

F14 1.8 V Bidirectional FSD[28]

D14 1.8 V Bidirectional FSD[29]

T2 1.8 V Bidirectional FSD[3]

E12 1.8 V Bidirectional FSD[30]

C15 1.8 V Bidirectional FSD[31]

N5 1.8 V Bidirectional FSD[4]

R3 1.8 V Bidirectional FSD[5]

P6 1.8 V Bidi rectional FSD[6]

R4 1.8 V Bidirectional FSD[7]

N6 1.8 V Bidirectional FSD[8]

T4 1.8 V Bidirectional FSD[9]

F7 GNDINT Gnd —

G6 GNDINT Gnd —

H7 GNDINT Gnd —

H9 GNDINT Gnd —

J8 GNDINT Gnd —

J10 GNDINT Gnd —

K11 GNDINT Gnd —

2–10 Chapter 2: Board Components

MAX II CPLD

Table 2–5. MAX II Device Pi n-Out (Note 1) (Part 4 of 8)

Schematic

MAX II Pin Number I/O Stand ard Signal Direction

Signal Name

L10 GNDINT Gnd —

A1 GNDIO Gnd —

A16 GNDIO Gnd —

B2 GNDIO Gnd —

B15 GNDIO Gnd —

G7 GNDIO Gnd —

G8 GNDIO Gnd —

G9 GNDIO Gnd —

G10 GNDIO Gnd —

K7 GNDIO Gnd —

K8 GNDIO Gnd —

K9 GNDIO Gnd —

K10 GNDIO Gnd —

R2 GNDIO Gnd —

R15 GNDIO Gnd —

T1 GNDIO Gnd —

T16 GNDIO Gnd —

J13 1.8 V Input HSMA_BYPASS

M4 2.5 V Output HSMA_JTAG_TDI

K4 2.5 V Input HSMA_JTAG_TDO

H16 1.8 V Input HSMB_BYPASS

H1 2.5 V Output HSMAB_JTAG_TDI

B9 2.5 V Input HSMB_JTAG_TDO

E16 1.8 V Input JTAG_SEL

D9 2.5 V Output LCD_BS1

N16 1.8 V Output LCD_SERn

L16 1.8 V Input MAX_CSn

N14 1.8 V Input MAX_DIP[0]

M13 1.8 V Input MAX_DIP[1]

N15 1.8 V Input MAX_DIP[2]

L14 1.8 V Input MAX_DIP[3]

J5 2.5 V Output MAX_EMB

M8 1.8 V Input MAX_EN

J4 2.5 V Output MAX_ERROR

J3 2.5 V Output MAX_FACTORY

K1 2.5 V Output MAX_LOAD

K13 1.8 V Input MAX_OEn

M14 1.8 V Input MAX_RESERVE[0]

P14 1.8 V Input MAX_RESERVE[1]

Chapter 2: Board Components 2–11

MAX II CPLD

Table 2–5. MAX II Device Pi n-Out (Note 1) (Part 5 of 8)

Schematic

MAX II Pin Number I/O Stand ard Signal Direction

Signal Name

K2 2.5 V Output MAX_USER

K15 1.8 V Input MAX_WEn

H12 1.8 V Input MAX2_CLK

M1 2.5 V Input MAXGP_JTAG_TCK

L4 2.5 V Output MAXGP_JTAG_TDI

L5 2.5 V Input MAXGP_JTAG_TDO

M2 2.5 V Input MAXGP_JTAG_TMS

N13 1.8 V Input MWATTS_MAMPS

H13 1.8 V Input PGM[0]

H15 1.8 V Input PGM[1]

H14 1.8 V Input PGM[2]

G16 1.8 V Input PGM[3]

J1 2.5 V Output PMON_CLK

J2 2.5 V Output PMON_CSN

H3 2.5 V Bidir PMON_DATA

H4 2.5 V Output PMON_SDI

H5 2.5 V Output PMON_SYNC

F6 2.5 V Output PWR_DIG_SE L[1]

F1 2.5 V Output PWR_DIG_SE L[2]

G3 2.5 V Output PWR_DIG_SEL[3]

G2 2.5 V Output PWR_DIG_SEL[4]

D2 2.5 V Output PWR_SEG_A

E5 2.5 V Output PWR_SEG_B

D1 2.5 V Output PWR_SEG_C

F3 2.5 V Output PWR_SEG_D

F5 2.5 V Output PWR_SEG_DP

E2 2.5 V Output PWR_SEG_E

F4 2.5 V Output PWR_SEG_F

E1 2.5 V Output PWR_SEG_G

F2 2.5 V Output PWR_S EG_MINUS

G4 2.5 V Input PWR_SEL[0]

G1 2.5 V Input PWR_SEL[1]

G5 2.5 V Input PWR_SEL[2]

H2 2.5 V Input PWR_SEL[3]

D13 — — RESERVED_INP UT

E14 — — RESERVED_INPUT

E15 — — RESERVED_INPUT

G12 — — RESERVED_INP UT

G14 — — RESERVED_INP UT

2–12 Chapter 2: Board Components

MAX II CPLD

Table 2–5. MAX II Device Pi n-Out (Note 1) (Part 6 of 8)

Schematic

MAX II Pin Number I/O Stand ard Signal Direction

Signal Name

G15 — — RESERVED_INP UT

K12 — — RESERVED_INPUT

L13 — — RESERVED_INPUT

P13 — — RESERVED_INPUT

R16 — Input RESET_CONFIGn

F16 — Output SRAM_ACTIVE

F15 — Input SRAM_CSn

B3 2.5 V Input USB_CLKOUT

E10 2.5 V Input USB_CMD_DATA

B10 2.5 V Output USB_EMPTY

E9 2.5 V Bidirectional USB_FD[0]

A9 2.5 V Bidi rectional USB_FD[1]

A8 2.5 V Bidi rectional USB_FD[2]

B8 2.5 V Bidi rectional USB_FD[3]

E8 2.5 V Bidirectional USB_FD[4]

A7 2.5 V Bidi rectional USB_FD[5]

D8 2.5 V Bidirectional USB_FD[6]

B7 2.5 V Bidi rectional USB_FD[7]

C9 2.5 V Output USB_FULL

J14 1.8 V Input USB_IFCLK

A2 2.5 V Bidi rectional USB_PA0_INT0n

D5 2.5 V Bidirectional USB_PA1_IN T1n

B1 2.5 V Bidi rectional USB_PA2_SLOE

D4 2.5 V Bidirectional USB_PA3_WU2

L3 2.5 V Bidirectional USB_PA4_IF0ADR0

L1 2.5 V Bidirectional USB_PA5_IF0ADR1

K5 2.5 V Bidi rectional USB_PA6 _PKTEND

L2 2.5 V Bidirectional USB_PA7_SLCSn

A4 2.5 V Input USB_PHY_CMD_DATA

D6 2.5 V Output USB_PHY_EM PTY

C13 2.5 V Bidirectional USB_PHY_FD [0]

B16 2.5 V Bidirectional USB_PHY_FD [1]

E11 2.5 V Bidirectional USB_PHY_FD [10]

B12 2.5 V Bidirectional USB_PHY_FD [11]

C10 2.5 V Bidirectional USB_PHY_FD [12]

A12 2.5 V Bidirectional USB_PHY_FD [13]

D10 2.5 V Bidirectional USB_ PHY_FD[14]

B11 2.5 V Bidirectional USB_PHY_FD [15]

C12 2.5 V Bidirectional USB_PHY_FD [2]

Chapter 2: Board Components 2–13

MAX II CPLD

Table 2–5. MAX II Device Pi n-Out (Note 1) (Part 7 of 8)

Schematic

MAX II Pin Number I/O Stand ard Signal Direction

Signal Name

A15 2.5 V Bidirectional USB_PHY_FD [3]

D12 2.5 V Bidirectional USB_P HY_FD[4]

B14 2.5 V Bidirectional USB_PHY_FD [5]

C11 2.5 V Bidirectional USB_PHY_FD [6]

B13 2.5 V Bidirectional USB_PHY_FD [7]

D11 2.5 V Bidirectional USB_P HY_FD[8]

A13 2.5 V Bidirectional USB_PHY_FD [9]

C4 2.5 V Output USB_PHY_FULL

C7 2.5 V Input USB_PHY_IFCLK

E6 2.5 V Input USB_PHY_REn

B4 2.5 V Input USB_PHY_WEn

E7 2.5 V Input USB_PWR_ENn

C8 2.5 V Output USB_RDn

A11 2.5 V Input USB_REn

C6 2.5 V Output USB_RESETn

A5 2.5 V Output USB_RSTn

D7 2.5 V Input US B_RSTOUTn

B6 2.5 V Input USB_RXFn

B5 2.5 V Output USB_SI_WU

K3 2.5 V Input USB_TXEn

C5 2.5 V Output USB_WAKEUP

M3 2.5 V Input USB_WEn

A6 2.5 V Output USB_WR

F10 — Power VCCINT

G11 — Power VCCINT

H8 — Power VCCINT

H10 — Power VCCINT

J7 — Power VCCINT

J9 — Power VCCINT

K6 — Power VCC INT

L7 — Power VCCINT

C1 — Power VCC IO1

H6 — Power VCCIO1

J6 — Power VCCIO1

P1 — Power VCC IO1

A3 — Power VCC IO2

A14 — Power VCCIO2

F8 — Power VCCIO2

F9 — Power VCCIO2

2–14 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Table 2–5. MAX II Device Pi n-Out (Note 1) (Part 8 of 8)

Schematic

MAX II Pin Number I/O Stand ard Signal Direction

Signal Name

C16 — Power VCCIO3

H11 — Power VCCIO3

J11 — Power VCCIO3

P16 — Power VCCIO3

L8 — Power VCCIO4

L9 — Power VCCIO4

T3 — Power VCCIO4

T14 — Power VCCIO4

P15 1.8 V Input VOLTS_WATTS

Note to Table 2–5:

(1) For more information about the MAX II pin-out, refer to the Altera website at www.altera.com/literature/lit-dp.jsp.

Ta b l e 2–6 lists the MAX II component reference and manufacturing information.

Table 2–6. MAX II Component Reference and Manufacturing Information

Board

Reference Descr iption Manufacturer

U7 256-pin device in a FineLine Ball Grid

Altera Corporation EPM2210GF256C3N www.altera.com

Array (FBGA) package

Configuration, Status, and Setup Elements

This section describes the board’s configuration, status, and setup elements, and is divided into the following groups:

■ “Configuration” on page 2–15

■ FPGA programming over USB

■ FPGA programming from flash memory

■ Flash programming over USB

■ “Status Elements” on page 2–17

■ Board-specific LEDs

■ Power display

■ “Setup Elements” on page 2–18

■ JTAG control DIP switch

Manufacturing

Part Number

Manufact urer

Website

■ MAX II device control DIP switch

■ System reset and configuration push buttons

■ POWER SELECT rotary switch

■ PGM CONFIG SELECT rotary switch

■ Speaker header

+ 56 hidden pages

Altera Cyclone III Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Introduction

General Description

1. Overview

Board Component Blocks

Block Diagram

Handling the Board

Introduction

2. Board Components

Board Overview

Featured FPGA (U20)

I/O and Clocking Resources

MAX II CPLD

Configuration, Status, and Setup Elements