Altera Cyclone II FPGA Starter Development Board User Manual

Cyclone II FPGA Starter Development Board

Reference Manual

101 Innovation Drive
San Jose, CA 95134
[phone]
http://www.altera.com

Document Version 1.0
Document Date October 2006

Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des­ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al­tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap­plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in­formation and before placing orders for products or services.

Part Number MNL-CDK01004-1.0

ii Altera Corporation

Contents

About This Manual .................................................................................. v

Chapter 1. Introduction

Overview ................................................................................................................................................. 1–1

Hardware Features ........................................................................................................................... 1–2

Software Features ............................................................................................................................. 1–2

Block Diagram ........................................................................................................................................ 1–2

Configuring the Cyclone II FPGA ....................................................................................................... 1–3

JTAG Programming ......................................................................................................................... 1–3

AS Programming .............................................................................................................................. 1–4

Configuration Procedure ................................................................................................................. 1–4

Configuring the FPGA in JTAG Mode ..................................................................................... 1–4

Configuring the EPCS4 Device in AS Mode ........................................................................... 1–5

Component Summary ........................................................................................................................... 1–6

Component Features ............................................................................................................................. 1–7

Cyclone II EP2C20 FPGA ................................................................................................................ 1–7

Serial Configuration Device and USB Blaster Circuit ................................................................. 1–8

SRAM ................................................................................................................................................. 1–8

SDRAM .............................................................................................................................................. 1–8

Flash Memory ................................................................................................................................... 1–8

SD Card Socket ................................................................................................................................. 1–8

Push Button Switches ...................................................................................................................... 1–8

Toggle Switches ................................................................................................................................ 1–8

Clock Inputs ...................................................................................................................................... 1–9

Audio CODEC .................................................................................................................................. 1–9

VGA Output ...................................................................................................................................... 1–9

Serial Ports ......................................................................................................................................... 1–9

Dual 40-Pin Expansion Headers .................................................................................................... 1–9

Chapter 2. Development Board Components

Component List ...................................................................................................................................... 2–1

Cyclone II EP2C20 FPGA ...................................................................................................................... 2–1

USB-Blaster Controller .......................................................................................................................... 2–2

EPCS4 ...................................................................................................................................................... 2–2

VGA DAC ............................................................................................................................................... 2–2

VGA Timing ...................................................................................................................................... 2–3

VGA Circuit Pin List ........................................................................................................................ 2–4

VGA Circuit Schematic .................................................................................................................... 2–4

Audio CODEC ....................................................................................................................................... 2–5

Audio Circuit Schematic ................................................................................................................. 2–6

Audio Circuit Pin List ...................................................................................................................... 2–7

Altera Corporation iii

Preliminary

Contents Stratix Device Handbook, Volume 1

Memory ................................................................................................................................................... 2–7

SDRAM Schematic and Pin List ..................................................................................................... 2–7

SRAM Schematic and Pin List ........................................................................................................ 2–9

Flash Schematic and Pin List ........................................................................................................ 2–11

Clock Circuit ......................................................................................................................................... 2–13

Clock Circuit Schematic ................................................................................................................ 2–13

Clock Input Pin List ....................................................................................................................... 2–14

Switches ................................................................................................................................................. 2–14

Power ON/OFF Switch ................................................................................................................. 2–15

RUN/PROG Switch ....................................................................................................................... 2–15

Push Button Switches .................................................................................................................... 2–16

Push Button Switch Schematic ................................................................................................ 2–17

Push Button Switch Pin List .................................................................................................... 2–17

Toggle Switches .............................................................................................................................. 2–17

Toggle Switch Schematic .........................................................................................................2–18

Toggle Switch Pin List .............................................................................................................. 2–19

Displays ................................................................................................................................................. 2–19

LEDs ................................................................................................................................................. 2–19

LED Schematic ........................................................................................................................... 2–19

LED Pin List ............................................................................................................................... 2–21

Seven-Segment Displays .............................................................................................................. 2–21

Seven-Segment Display Schematic ......................................................................................... 2–22

Seven-Segment Display Pin List ............................................................................................. 2–23

Connectors ............................................................................................................................................ 2–24

USB-Blaster Port ............................................................................................................................. 2–25

Expansion Headers ........................................................................................................................ 2–25

Expansion Header Schematics ................................................................................................ 2–26

Expansion Header Pin List ...................................................................................................... 2–28

SD Card Connector ........................................................................................................................ 2–31

RS-232 Serial Port ........................................................................................................................... 2–32

RS-232 Circuit Schematic ......................................................................................................... 2–33

RS-232 Serial Circuit Pin List .................................................................................................

.. 2–34

PS/2 Port ......................................................................................................................................... 2–34

PS/2 Circuit Schematic ............................................................................................................ 2–34

PS/2 Serial Circuit Pin List ...................................................................................................... 2–34

VGA Video Port .............................................................................................................................. 2–35

Audio Ports ..................................................................................................................................... 2–35

SMA External Clock Connector ................................................................................................... 2–36

Power Supply Connector .............................................................................................................. 2–36

iv Altera Corporation

Preliminary

About This Manual

This reference manual describes the Altera® Cyclone® FPGA Starter
Development Kit. For a description of how to use the development kit,
refer to the Cyclone FPGA Starter Development Kit User Guide.

f The document revision history in Table 2–1 shows the current version of

this document. To ensure that you have the most up-to-date information
on this product, refer to the readme file on the provided CD_ROM for
late-breaking information that is not available in this document.

Table 2–1. Document Revision History

Date Description

October 2006 Initial publication of the Cyclone II FPGA Starter

Development Board Reference Manual, version 1.0.

How to Find

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jump to related information.

How to Contact
Altera

Altera Corporation v
October 2006 Cyclone II FPGA Starter Development Board

To get help regarding this product, use the following contact information:

■ Altera Corporation

101 Innovation Drive
San Jose, California, 95134 USA
www.altera.com

®

Acrobat® or Reader®

About This Manual

For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com. For technical support on
this product, go to www.altera.com/mysupport. For additional
information about Altera products, consult the sources shown below.

Information Type USA & Canada All Other Locations

Technical support www.altera.com/mysupport/ www.altera.com/mysupport/

(800) 800-EPLD (3753)
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Product literature www.altera.com www.altera.com

Altera literature services [e-mail] [e-mail]

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[phone]
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Typographic

This document uses the typographic conventions shown below.

Conventions

Visual Cue Meaning

Bold Type with Initial
Capital Letters

bold type External timing parameters, directory names, project names, disk drive names,

Italic Type with Initial Capital
Letters

Italic type Internal timing parameters and variables are shown in italic type.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:

“Subheading Title” References to sections within a document and titles of on-line help topics are

Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.

filenames, filename extensions, and software utility names are shown in bold
type. Examples: f

Document titles are shown in italic type with initial capital letters. Example: AN

75: High-Speed Board Design.

Examples: t

Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.

Delete key, the Options menu.

shown in quotation marks. Example: “Typographic Conventions.”

PIA

, \qdesigns directory, d: drive, chiptrip.gdf file.

MAX

, n + 1.

vi Reference Manual Altera Corporation
Cyclone II FPGA Starter Development Board October 2006

About This Manual

Visual Cue Meaning

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,

tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For
example:
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword
Courier.

1., 2., 3., and
a., b., c., etc.

● • Bullets are used in a list of items when the sequence of the items is not important.

■

v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.

c

w

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.

The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.

The warning indicates information that should be read prior to starting or
continuing the procedure or processes

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an

SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

Altera Corporation Reference Manual vii
October 2006 Cyclone II FPGA Starter Development Board

About This Manual

viii Reference Manual Altera Corporation
Cyclone II FPGA Starter Development Board October 2006

1. Introduction

Overview

Figure 1–1. Starter Development Board

The Cyclone II FPGA Starter Development Board (Figure 1–1) provides
integrated features that enable users to develop and test designs that
range from simple circuits to various multimedia projects, all without the
need to implement complex application programming interfaces (APIs),
host control software, or SRAM/SDRAM/flash memory controllers.

The following sections of the manual introduce the board features,
describe the configuration methods available, and highlight the
characteristics of the board components.

Altera Corporation 1–1
October 2006

Introduction

Hardware Features

The development board has the following hardware features:

■ Altera Cyclone

■ Altera EPCS4 Serial Configuration device

■ USB-Blaster controller chip set for programming and user API

®

II EP2C20 FPGA device

control, supporting both JTAG and Active Serial (AS) programming
modes

■ 512-KByte SRAM

■ 8-MByte SDRAM

■ 4-MByte Flash memory

■ SD Flash Card socket

■ 4 Push button switches

■ 10 Toggle switches

■ 10 Red user LEDs

■ 8 Green user LEDs

■ 50 MHz, 27 MHz, and 24 MHz oscillators for clock sources

■ 24-bit CD-quality audio CODEC with line-in, line-out, and

microphone-in jacks

■ VGA DAC (4-bit resistor network) with VGA-out connector

■ RS-232 transceiver and 9-pin connector

■ PS/2 mouse/keyboard connector

■ Two 40-pin expansion headers with resistor protection

■ 7.5V DC adapter or a USB cable (provided in the kit) for power

Software Features

Flexible control of the development board and Altera hardware and
software tools provide an effective FPGA-based design environment. In
addition to the hardware features, the development board provides
software support for standard I/O interfaces and a control panel facility
for accessing various components. The kit also provides software for a
number of demonstrations that illustrate the advanced capabilities of the
development board.

Use of the development board requires familiarity with the Altera
Quartus II software. Tutorials for the Quartus II software and for the
Cyclone II FPGA Starter Board are available on the Altera web site or on
the included development kit CD-ROM in the Examples directory.

Block Diagram

The block diagram of the development board (Figure 1–2) shows that for
maximum user flexibility, all the blocks connect through the Cyclone II
FPGA device. Thus, the user can implement any system design by
configuring the FPGA.

1–2 Reference Manual Altera Corporation
Cyclone II FPGA Starter Development Board October 2006

Figure 1–2. Development Board Block Diagram

Introduction

Configuring the Cyclone II FPGA

The Cyclone II FPGA Starter Development Board has integrated the
programming circuitry normally found in a USB-Blaster programming
cable, as well as a serial EEPROM chip (EPCS4) that stores configuration
data for the Cyclone II FPGA. This configuration data loads automatically
from the EEPROM chip into the FPGA each time power is applied to the
board.

Using the Quartus II software, it is possible to reprogram the FPGA at any
time, and it is also possible to change the non-volatile data stored in the
serial EEPROM chip. The following sections describe the two ways to
program the FPGA, JTAG programming and Active Serial (AS)
programming.

JTAG Programming

In this method of programming, named after the IEEE standards Joint Test
Action Group, the configuration bit stream downloads directly into the

Cyclone II FPGA through the USB-Blaster circuitry. The FPGA retains
this configuration as long as power is applied to the board; the FPGA
loses the configuration when the power is turned off.

Altera Corporation Reference Manual 1–3
October 2006 Cyclone II FPGA Starter Development Board

Introduction

f For detailed information about the USB-Blaster circuitry, refer to the Cyclone II

FPGA Starter Board schematic found in the BoardDesignFiles / Schematic
directory in the kit installation directory.

AS Programming

In the Active Serial programming method, the configuration bit stream
downloads into the Altera EPCS4 serial EEPROM chip. The EEPROM
provides non-volatile storage of the bit stream, retaining the information
even when power to the Cyclone II FPGA Starter board is turned off.
When the board powers up, the configuration data in the EPCS4 device
automatically loads into the Cyclone II FPGA.

Configuration Procedure

For both the JTAG and AS programming methods, the Cyclone II FPGA
Starter board connects to a host computer via a USB cable. Because of this
connection type, the host computer identifies the board as an Altera
USB-Blaster device. The following sections describe the JTAG and AS
programming steps.

Configuring the FPGA in JTAG Mode

Figure 1–3 illustrates the JTAG configuration setup. To download a

configuration bit stream into the Cyclone II FPGA, perform the following
steps:

1. Ensure that power is applied to the Cyclone II FPGA Starter board.

2. Connect the supplied USB cable to the USB-Blaster port on the
board.

3. Configure the JTAG programming circuit on the board by setting
the RUN/PROG switch (on the left side of the board) to the RUN
position.

4. To program the FPGA, use the Quartus II Programmer module to
select a configuration bit-stream file with the .sof filename extension.

1–4 Reference Manual Altera Corporation
Cyclone II FPGA Starter Development Board October 2006

Introduction

Figure 1–3. JTAG Configuration Setup

USB Blaster Circuit

USB

MAX
3128

”

JTAG Config Port

FPGA

EPCS Serial

Configuration

Device

Configuring the EPCS4 Device in AS Mode

Figure 1–4 illustrates the AS configuration setup. To download a

configuration bit stream into the EPCS4 serial EEPROM device, perform
the following steps:

1. Ensure that power is applied to the Cyclone II FPGA Starter board.

2. Connect the supplied USB cable to the USB-Blaster port on the
board.

3. Configure the JTAG programming circuit by setting the
RUN/PROG switch (on the left side of the board) to the PROG
position.

4. To program the EPCS4 device, use the Quartus II Programmer
module to select a configuration bit-stream file with the .pof
filename extension.

5. After the programming operation completes, set the RUN/PROG
switch back to the RUN position.

6. Reset the board by turning the power switch off and then on again.
This action causes the new configuration data in the EPCS4 device
to load into the FPGA chip.

f Refer to the Serial Configuration Devices chapter in the Altera Configuration

Device Handbook for more information about the EPCS4 device.

Altera Corporation Reference Manual 1–5
October 2006 Cyclone II FPGA Starter Development Board

Introduction

Figure 1–4. AS Configuration Setup

USB Blaster Circuit

USB

MAX
3128

”

EPCS Serial

Configuration

Device

JTAG Config Port

FPGA

Component

Table 1–1 lists the components, their locations, and brief descriptions.

Summary

Table 1–1. Cyclone II FPGA Development Board Components & Interfaces (Part 1 of 2)

Board Designation Name Description

U2 Cyclone II FPGA EP2C20 device

User Interface

KEY0 – KEY3 Push-button switches Four momentary contact switches for user input to the

FPGA

SW0 – SW9 Toggle switches Ten toggle switches for configuration of the FPGA

LEDG0 – LEDG7 Individual LEDs Eight green LEDs driven by the FPGA

LEDR0 – LEDR9 Individual LEDs Ten red LEDs driven by the FPGA

HEX0 – HEX3 Seven-segment LEDs Four seven-segment LEDs that display numeric

output from the FPGA

Memory

U7 SRAM memory 512 KBytes of SRAM

U9 Flash memory 4 MBytes of nonvolatile memory for use by both the

U6 DDR SDRAM memory 8 MBytes of DDR SDRAM.

Connections & Interfaces

PS2KB PS/2 connector PS/2 keyboard connector

FPGA and the configuration controller. LED7 lights
whenever the flash chip-enable asserts.

1–6 Reference Manual Altera Corporation
Cyclone II FPGA Starter Development Board October 2006

Introduction

Table 1–1. Cyclone II FPGA Development Board Components & Interfaces (Part 2 of 2)

Board Designation Name Description

RS232 Serial connector RS-232 9-pin serial connector with 5 V-tolerant

buffers. Supports all RS-232 signals.

JP1 Expansion header connector Expansion header 1 connecting to 40 I/O pins on the

FPGA with resistor voltage protection

JP2 Expansion header connector Expansion header 2 connecting to 40 I/O pins on the

FPGA with resistor voltage protection

MIC Microphone input Audio CODEC connectors

LINEIN Audio Line input

LINEOUT Audio line output

VGA VGA connector VGA video port

SD CARD SD card socket Secure Data card socket

BLASTER JTAG connector

USB Blaster Port JTAG connection to the MAX
configuration controller

®

Configuration & Reset

U16 Serial configuration device Altera EPCS4 low-cost serial configuration device to

SW11 Power ON/OFF switch Push-button switch to power up the board

configure the FPGA

Clock Circuitry

Y1 Oscillator 50 MHz clock signal driven to FPGA

Y2 Oscillator 27 MHz clock signal driven to FPGA

Y3 Oscillator 24 MHz clock signal driven to FPGA

EXT_CLOCK External clock input Connector to FPGA clock pin

Power Supply

DC7.5V DC power jack 7.5 V DC unregulated power source

Component Features

This section summarizes characteristics of each board component. For
detailed descriptions, refer to Chapter 2, Development Board

Components.

Cyclone II EP2C20 FPGA

■ 18,752 LEs

■ 52 M4K RAM blocks

■ 240K total RAM bits

■ 26 embedded multipliers

■ 4 PLLs

■ 315 user I/O pins

Altera Corporation Reference Manual 1–7
October 2006 Cyclone II FPGA Starter Development Board

Introduction

■ FineLine BGA 484-pin package

Serial Configuration Device and USB Blaster Circuit

■ Altera EPCS4 serial configuration device

■ On-board USB-Blaster chip set for programming

and user API control

■ Selectable JTAG and AS programming modes

SRAM

■ 512-KByte static RAM memory chip

■ Organized as 256K x 16 bits

■ Accessible as memory for the Nios II processor

and by the Control Panel GUI

SDRAM

■ 8-MByte single data rate synchronous dynamic RAM memory chip

■ Organized as 1M x 16 bits x 4 banks

■ Accessible as memory for the Nios II processor

and by the Control Panel GUI

Flash Memory

■ 4-MByte NOR flash memory

■ 8-bit data bus

■ Accessible as memory for the Nios II processor

and by the Control Panel GUI

SD Card Socket

■ Provides SPI mode for SD card access

■ Accessible as memory for the Nios II processor

with the DE1 SD Card Driver

Push Button Switches

■ 4 push button switches

■ Debounced by a Schmitt trigger circuit

■ Normally HIGH; generates one active-LOW pulse

when the switch is pressed

Toggle Switches

■ 10 toggle switches for user inputs

1–8 Reference Manual Altera Corporation
Cyclone II FPGA Starter Development Board October 2006

Introduction

■ A switch produces logic 0 when in the DOWN

(closest to the edge of the board) position
and logic 1 when in the UP position

Clock Inputs

■ 50-MHz oscillator

■ 27-MHz oscillator

■ 24-MHz oscillator

■ SMA external clock input

Audio CODEC

■ Wolfson WM8731 24-bit sigma-delta audio CODEC

■ Line-level input, line-level output, and microphone input jacks

■ Sampling frequency: 8 to 96 KHz

■ Applications for MP3 players and recorders, PDAs,

smart phones, voice recorders

VGA Output

■ Uses a 4-bit resistor-network DAC

■ 15-pin high-density D-sub connector

■ Supports up to 640x480 at 60-Hz refresh rate

■ Can be used with the Cyclone II FPGA to implement

a high-performance TV encoder

Serial Ports

■ One RS-232 port

■ One PS/2 port

■ DB-9 serial connector for the RS-232 port

■ PS/2 connector for connecting a PS2 mouse

or keyboard to the board

Dual 40-Pin Expansion Headers

■ 72 Cyclone II I/O pins and 8 power and ground lines

connect to two, 40-pin expansion connectors

■ 40-Pin header designed to accept a standard 40-pin

ribbon cable used for IDE hard drives

■ Resistor protection provided

Altera Corporation Reference Manual 1–9
October 2006 Cyclone II FPGA Starter Development Board