ALTERA CPRI User Guide
CPRI MegaCore Function User Guide
CPRI MegaCore Function
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-01062-5.0
Document last updated for Altera Complete Design Suite version:
Document publication date:
12.0
June 2012
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ISO
9001:2008
Registered
June 2012 Altera Corporation CPRI MegaCore Function
User Guide
Contents
Chapter 1. About This MegaCore Function
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
CPRI IP Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
Chapter 2. Getting Started
MegaWizard Plug-In Manager Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Specifying Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Simulation Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Specifying Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Compiling and Programming the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Instantiating Multiple CPRI IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Chapter 3. Parameter Settings
Physical Layer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Operation Mode Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Line Rate Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Enable Autorate Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Transceiver Starting Channel Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Rx Elastic Buffer Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Transceiver Reference Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Data Link Layer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Include MAC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Include HDLC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Application Layer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Mapping Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Number of Antenna-Carrier Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Enable Internally-Clocked Synchronization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Chapter 4. Functional Description
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Clocking Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
CPRI IP Core Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Clock Diagrams for the CPRI IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Clock Diagrams for Most CPRI IP Core Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Clock Diagram for CPRI IP Core Arria V GT Variations at 9830.4 Mbps . . . . . . . . . . . . . . . . . . . . 4–6
CPRI Communication Link Line Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
Reset Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
MAP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
MAP Interface Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
Basic AxC Mapping Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
June 2012 Altera Corporation CPRI MegaCore Function
User Guide
iv ContentsContents
Advanced AxC Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
MAP Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
MAP Receiver Interface Signals in Different Synchronization Modes . . . . . . . . . . . . . . . . . . . . . 4–16
MAP Receiver in FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
MAP Receiver in Synchronous Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18
MAP Receiver in the Internally-Clocked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
MAP Transmitter Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21
MAP Transmitter Interface Signals in Different Synchronization Modes . . . . . . . . . . . . . . . . . . 4–22
MAP Transmitter in FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
MAP Transmitter in Synchronous Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24
MAP Transmitter in the Internally-clocked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
Auxiliary Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
AUX Receiver Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
AUX Transmitter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31
Media Independent Interface to an External Ethernet Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
MII Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–35
MII Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–36
CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–38
Accessing the Hyperframe Control Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–39
Recording and Retrieving the Incoming Control Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40
Writing the Outgoing Control Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40
Control Word Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40
Control Word Transmission Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–41
Control Word Retrieval Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–41
Accessing the Ethernet Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–42
Transmitting Ethernet Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–42
Receiving Ethernet Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–43
Accessing the HDLC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–45
CPRI Protocol Interface Layer (Physical Layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–46
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–46
Physical Layer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–47
Ensuring the Physical Layer Routes Your Data as Expected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–47
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–48
High-Speed Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–48
Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–49
Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–49
Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–49
Alarm Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–50
Reset Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–51
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–52
Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53
Tx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53
High-Speed Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53
Chapter 5. Testing Features
Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Internal Reverse Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Physical Layer Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Reverse Loopback Through CPRI Rx and Tx Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
PRBS Generation and Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
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Chapter 6. Signals
MAP Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
MAP Receiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
MAP Transmitter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Auxiliary Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
AUX Receiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
AUX Transmitter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Extended Rx Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
CPRI MII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
CPRI MII Receiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
CPRI MII Transmitter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
CPU Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Physical Layer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
CPRI Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
Layer 1 Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
Layer 1 Error Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Autorate Negotiation Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Transceiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Clock and Reset Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
Chapter 7. Software Interface
CPRI Protocol Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2
MAP Interface and AUX Interface Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14
Ethernet Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21
HDLC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–26
Chapter 8. Testbenches
Test Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5
Reset, Frame Synchronization, and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
Running the Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7
Appendix A. Initialization Sequence
Appendix B. Implementing CPRI Link Autorate Negotiation
Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
Configuring the CPRI IP Core for Autorate Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3
Running Autorate Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3
Appendix C. Advanced AxC Mapping Modes
Backward Compability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1
Advanced Mapping Mode Similarities and Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–2
Fifteen-Bit Width Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–3
Sixteen-Bit Width Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–4
Appendix D. Delay Measurement and Calibration
Altera Delay Measurement and Calibration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1
Delay Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1
Rx Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–3
Rx Path Delay Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–3
Rx Transceiver Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–4
Rx Transceiver Latency in Most CPRI IP Core Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–5
Rx Transceiver Latency in Arria V GT Variations at CPRI Line Rate 9.8 Gbps . . . . . . . . . . . . . . D–5
Extended Rx Delay Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–5
June 2012 Altera Corporation CPRI MegaCore Function
User Guide
vi ContentsContents
M/N Ratio Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–6
Arria V GT Variations with CPRI Line Rate 9.8 Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–6
CPRI Receive Buffer Delay Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–6
Round-Trip Calibration Delay in Rx Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–7
Fixed Rx Core Delay Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–8
Rx Path Delay to AUX Output: Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–8
Tx Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–9
Fixed Tx Core Delay Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–11
Extended Tx Delay Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–11
Tx Bitslip Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–12
Tx Transceiver Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–12
Tx Transceiver Latency in Most CPRI IP Core Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–12
Tx Transceiver Latency in Arria V GT Variations at CPRI Line Rate 9.8 Gbps . . . . . . . . . . . . . D–13
T14, Toffset, Round-Trip Delay, and Round-Trip Cable Delay Calculations . . . . . . . . . . . . . . . . . . . . D–13
Round-Trip and Cable Delay Calculations for a Single-Hop Configuration . . . . . . . . . . . . . . . . . D–14
Tx Bitslip Delay in the Round-Trip Delay Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–15
Single-Hop Round-Trip and Cable Delay Calculation Examples . . . . . . . . . . . . . . . . . . . . . . . . D–15
Dynamic Pipelining for Automatic Round-Trip Delay Calibration . . . . . . . . . . . . . . . . . . . . . . . . . D–21
Round-Trip Calculations for a Multihop Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–22
Multihop Round-Trip Delay Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–22
Multihop Round-Trip Cable Delay Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–23
Two-Hop Round-Trip and Cable Delay Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . D–23
Appendix E. Integrating the CPRI IP Core Timing Constraints in the Full Design
Appendix F. Porting a CPRI IP Core from the Previous Version of the Software
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–3
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–3
CPRI MegaCore Function June 2012 Altera Corporation
User Guide
The Altera® CPRI MegaCore® function implements the Common Public Radio
CPRI
MegaCore Function
(RE Slave)
FPGA FPGA
CPRI
MegaCore Function
(RE Slave)
CPRI
MegaCore Function
(RE Master)
FPGA
CPRI
MegaCore Function
(REC)
Clock
Module
RF
Base Band Module
Optical Link
Optical Link
CPRICPRICPRI
CPRI
RF
Routing Layer
MAP MAPAUX AUX
Interface (CPRI) specification. CPRI is a high-speed serial interface designed for
network radio equipment controllers (REC) to receive data from and provide data to
remote radio equipment (RE).
The CPRI IP core targets high-performance, remote, radio network applications. You
can configure the CPRI IP core as an RE or an REC. Figure 1–1 shows an example
system implementation with a two-hop daisy chain. Optical links between devices
support high performance.
Figure 1–1. Typical CPRI Application on Altera Devices
1. About This MegaCore Function
General Description
June 2012 Altera Corporation CPRI MegaCore Function
The Altera CPRI IP core implements Layer 1 and Layer 2 of the CPRI V4.2
specification. It provides access to the Layer 2 access points through various
interfaces:
■ IQ data access:
■ MAP antenna-carrier interfaces for easy IQ user data plane access based on
pre-configured antenna-carrier channels.
■ Auxiliary interface for full access to the user data plane.
User Guide
1–2 Chapter 1: About This MegaCore Function
General Description
■ Ethernet channel access:
■ Auxiliary interface for full access to the Ethernet space in the CPRI frame.
■ Register support for loading and unloading the Ethernet frame.
■ MI interface port for Ethernet Frame access.
■ HDLC channel access:
■ Auxiliary interface for full access to the high level data link control (HDLC)
space in the CPRI frame.
■ Register support for loading and unloading the HDLC frame.
■ Vendor-specific data (VSS):
■ Auxiliary interface for full access to control bytes.
■ Register support for loading and unloading VSS space.
■ Synchronization and Timing access:
■ Auxiliary interface for full access to synchronization and timing.
You configure the CPRI IP core to support either Ethernet communication with an
Ethernet media access control (MAC) block included in the IP core, or communication
with an external Ethernet module. The CPRI link line rate is configurable. For
information about these interfaces and functionality, refer to Chapter 4, Functional
Description. For information about configuration options, refer to Chapter 3,
Parameter Settings.
CPRI MegaCore Function June 2012 Altera Corporation
User Guide
Chapter 1: About This MegaCore Function 1–3
tx_dataout
Transmitter
Transceiver
Transmitter
rx_datain
CPRI LinkCPRI Link
Receiver
Transceiver
Receiver
Multiplexing
Time Division Multiplexing
IQ
Data
Full access
to
CPRI frame
Vendor
Specific
L1
Inband
Protocol
HDLC (2) Ethernet (3)
MAP
Interface (1)
AUX
Interface
CPU
Interface
MI
Interface
CPRI IP Core Features
Figure 1–2 shows the CPRI IP core interfaces. The IP core assembles the outbound
CPRI frame control words and data from all of these interfaces, and unloads and
routes control words and data from the inbound CPRI frame to the appropriate
interfaces, based on configuration and register settings.
Figure 1–2. CPRI IP Core Interfaces
Notes to Figure 1–2:
(1) You can configure your CPRI IP core with zero, one, or multiple antenna-carrier interfaces. If you configure zero antenna-carrier interfaces, the
MAP interface is not configured in your CPRI IP core. In that case you can communicate IQ data through the AUX interface to your user-defined
routing layer.
(2) You can configure your CPRI IP core with or without a high-level data link control (HDLC) block.
(3) You can configure your CPRI IP core with an Ethernet MAC block or a media-independent (MI) interface (MII) block. The two options are mutually
exclusive.
CPRI IP Core Features
The CPRI IP core has the following features:
■ Complies with the Common Public Radio Interface (CPRI) Specification V4.2
(2010-09-29) Interface Specification for wireless base station submodule
interconnections, without the full range of data sample widths.
■ Supports radio equipment controller (REC) and radio equipment (RE) module
configurations, including RE master, RE slave, and REC master ports.
■ Supports Universal Mobile Telecommunication System (UMTS) Terrestrial Radio
Access (UTRA) – frequency division duplexing (UTRA-FDD) (UMTS/Wideband
Code Division Multiple Access (W-CDMA)), Evolved UTRA (E-UTRA) (3rd
Generation Partnership Project (3GPP) Long Term Evolution (LTE) specification),
and Worldwide interoperability for Microwave Access (WiMAX) (IEEE 802.16
standard).
June 2012 Altera Corporation CPRI MegaCore Function
■ Full access to CPRI frame.
User Guide
1–4 Chapter 1: About This MegaCore Function
CPRI IP Core Features
■ Supports the following additional CPRI link features:
■ Programmable CPRI communication line rate (to 614.4, 1228.8, 2457.6, 3072.0,
4915.2, 6144.0, or 9830.4 Mbps) using Altera on-chip high-speed transceivers.
■ Auto-rate negotiation support.
■ Scrambling and descrambling at 4915.2 Mbps, 6144.0 Mbps, and 9830.4 Mbps.
■ Rx delay measurement.
■ Tx delay calibration.
■ Programmable hardware processing of the reset request bit in the CPRI frame.
■ Vendor-specific subchannel (VSS) communication on the CPRI link.
■ Diagnostic parallel reverse loopback paths.
■ Includes the following additional interfaces:
■ Interface to external or on-chip processor, using the Altera Avalon
®
Memory-Mapped (Avalon-MM) interconnect specification.
■ Ethernet communication interfaces that support simultaneous Ethernet and
HDLC communication to and from the CPRI link.
■ Optional configuration of Ethernet MAC.
■ Optional Media-Independent Interface for Ethernet frame access.
■ Optional configuration of HDLC block.
■ Auxiliary interface provides full access to CPRI frame.
■ Supports data transfer to and from custom mapping functions.
■ Supports data transfer from slave to master ports to implement daisy-chain
topologies.
■ Supports custom IQ sample widths.
■ An IQ data interface with the following features:
■ Implements mapping methods in Sections 4.2.7.2.5 and 4.2.7.2.7 of the CPRI
V4.2 Specification, and mapping Options 1 and 2 in Sections 4.2.7.2.3 and
4.2.7.2.4 of the CPRI V4.2 Specification.
■ Implements WiMAX mapping methods described in Sections 4.2.7.2.2,
4.2.7.2.5, and 4.2.7.2.7 of the CPRI V4.2 Specification.
■ Implements UMTS/LTE mapping methods described in Section 4.2.7.2 of
the CPRI V4.2 Specification.
■ Implements WiMAX timing control methodology described in Section
4.2.8.2 of the CPRI V4.2 Specification.
■ Supports as many as 24 antenna-carrier interfaces.
■ Supports clocking antenna-carrier interfaces with external data channel
clocks or internal IP core clock.
■ Supports synchronous buffer or simple FIFO synchronization modes for
externally clocked antenna-carrier interfaces.
■ Supports independent sample rates for each antenna-carrier interface.
CPRI MegaCore Function June 2012 Altera Corporation
User Guide
Chapter 1: About This MegaCore Function 1–5
Device Family Support
■ Supports 15- and 16-bit data sample widths on uplink and downlink using
the Altera Avalon Streaming (Avalon-ST) interconnect specification.
Device Family Support
Tab le 1– 1 defines the device support levels for Altera IP cores.
Table 1–1. Altera IP Core Device Support Levels
FPGA Device Families HardCopy Device Families
Preliminary support—The IP core is verified with
preliminary timing models for this device family. The IP core
meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be
used in production designs with caution.
Final support—The IP core is verified with final timing
models for this device family. The IP core meets all
functional and timing requirements for the device family and
can be used in production designs.
HardCopy Companion—The IP core is verified with
preliminary timing models for the HardCopy companion
device. The IP core meets all functional requirements, but
might still be undergoing timing analysis for the HardCopy
device family. It can be used in production designs with
caution.
HardCopy Compilation—The IP core is verified with final
timing models for the HardCopy device family. The IP core
meets all functional and timing requirements for the device
family and can be used in production designs.
Tab le 1– 2 lists the level of support offered by the CPRI IP core for each Altera device
family.
Table 1–2. Device Family Support
®
Arria
II (GX and GZ variants) Final
Arria V (GX and GT variants)
®
Cyclone
HardCopy
Stratix
IV GX Final
®
IV GX HardCopy Compilation
®
IV GX Final
Stratix V
Other device families No support
MegaCore Verification
Before releasing a version of the CPRI IP core, Altera runs comprehensive regression
tests in the current version of the Quartus
MegaWizard
simulation and hardware to confirm functionality.
Device Family Support
Refer to the What’s New in Altera IP page of
the Altera website.
Refer to the What’s New in Altera IP page of
the Altera website.
®
™
Plug-In Manager to create the instance files. Altera tests these files in
II software. These tests use the
Altera tests and verifies the CPRI IP core in hardware, especially the deterministic
latency feature, for different platforms and environments.
June 2012 Altera Corporation CPRI MegaCore Function
User Guide
1–6 Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Performance and Resource Utilization
This section contains tables showing IP core variation size and performance examples.
For resource utilization information for additional CPRI IP core variations, refer to the
reports the Quartus II software generates during compilation.
Tab le 1– 3 lists the resources and expected performance for CPRI IP core variations
configured with the following features:
■ Operate in REC master mode
■ Include autorate negotiation support if it is available at the relevant line rate in the
device family (turned off in Arria V GT variations with CPRI line rate
9830.4 Mbps)
■ Provide Ethernet access through the MI interface
■ Do not provide an HDLC block
■ Use Basic mapping mode
■ Clock the AxC channels with independent clocks (the Enable MAP interface
synchronization with core clock parameter is turned off)
The numbers of combinational ALUTs and logic registers are rounded up to the
nearest 100.
Tab le 1– 3 lists results obtained with the Quartus II software v12.0 for the following
devices:
■ Arria V GT (5AGTBD7E3F35I5)
■ Arria V GX (5AGXFB3H4F35C4 for 6144, 4915.2, and 3072 Mbps variations and
5AGXFB3H6F35C6 for other variations)
■ Stratix V GX (5SGXMA5N2F40I2 for 9830.4 Mbps variations and
5SGXMA5N2F40I4 for other variations)
Table 1–3. CPRI IP Core FPGA Resource Utilization (Part 1 of 2)
Parameters Memory
Device
Line Rate
(Mbps)
Number of
Antenna-Carrier
Interfaces
Combinational ALUTs
0 4300 4000 11 —
1 4800 4800 21 —
Arria V GT 9830.4
4 5400 5500 27 —
8 6000 6400 35 —
Logic
Registers
M10K or
M20K
Blocks
Memory
(1)
ALUTs
CPRI MegaCore Function June 2012 Altera Corporation
User Guide
Chapter 1: About This MegaCore Function 1–7
Performance and Resource Utilization
Table 1–3. CPRI IP Core FPGA Resource Utilization (Part 2 of 2)
Parameters Memory
Device
Line Rate
(Mbps)
Number of
Antenna-Carrier
Interfaces
Combinational ALUTs
0 3000 3100 5 —
1 3800 4000 15 —
614.4
2 3900 4200 17 —
3 4100 4500 19 —
Arria V GX
1228.8,
2457.6,
3072,
4915.2,
6144
4 4300 4800 21 —
0 3000 3100 5 —
1 3800 4200 15 —
4 4300 4800 21 —
8 5000 5800 29 —
0 3000 3100 4 9
1 3800 4000 11 9
614.4
2 4000 4300 13 9
3 4100 4500 15 9
Stratix V GX
1228.8,
2457.6,
3072,
4915.2,
6144,
9830.4
Note to Table 1–3:
(1) M10K blocks in Arria V devices and M20K blocks in Stratix V devices.
4 4300 4800 17 9
0 3100 3200 5 —
1 3800 4300 11 —
4 4400 5100 17 —
8 5000 6200 25 —
Logic
Registers
M10K or
M20K
Blocks
Memory
(1)
ALUTs
Tab le 1– 4 shows the slowest device family speed grade that supports each CPRI line
rate in each device family. Lower speed grade numbers correspond to faster devices.
Table 1–4. Slowest Recommended Device Family Speed Grades
Device Family
or Variant
614.4 1228.8 2457.6 3072.0 4915.2 6144 9830.4
ArriaIIGX –6–6–6–6I3
ArriaIIGZ –4–4–4–4–3–3
Arria V GX C6 C6 C6 I5 I5 I5
(1)
(Part 1 of 2)
CPRI Line Rate (Mbps)
(2)
(2) (3)
I3
(3)
(3)
Arria V GT C6 C6 C6 I5 I5 I5 I5
Cyclone IV GX C8, I7 C8, I7 C8, I7 –7
StratixIVGX–4–4–4–4–4–3
June 2012 Altera Corporation CPRI MegaCore Function
(3) (3) (3)
(3)
User Guide
1–8 Chapter 1: About This MegaCore Function
Release Information
Table 1–4. Slowest Recommended Device Family Speed Grades
Device Family
or Variant
Stratix V GX –4 –4 –4 –4 –4 –4 -2
Notes to Table 1–4:
(1) The entry –x indicates that both the industrial speed grade Ix and the commercial speed grade Cx are supported for this device family and CPRI
line rate.
(2) Only the I3 speed grade is available for a CPRI IP core that runs at this line rate and targets the Arria II GX device family.
(3) This CPRI line rate is not supported for this device family.
614.4 1228.8 2457.6 3072.0 4915.2 6144 9830.4
(1)
(Part 2 of 2)
CPRI Line Rate (Mbps)
Release Information
Tab le 1– 5 provides information about this release of the CPRI IP core.
Table 1–5. CPRI Release Information
Item Description
Version 12.0
Release Date June 2012
Ordering Code IP-CPRI
Product ID 00CB
Vendor ID 6AF7
Altera verifies that the current version of the Quartus II software compiles the
previous version of each Altera IP core. Any exceptions to this verification are
reported in the MegaCore IP Library Release Notes and Errata. Altera does not verify
compilation with IP core versions older than the previous release.
Installation and Licensing
The CPRI IP core is part of the MegaCore IP Library, which is distributed with the
Quartus II software. The combined software is downloadable from the Altera website,
www.altera.com.
CPRI MegaCore Function June 2012 Altera Corporation
User Guide
Chapter 1: About This MegaCore Function 1–9
Installation and Licensing
Figure 1–3 shows the directory structure after you install the CPRI IP core, where
<
path> is the installation directory. The default installation directory on Windows is
C:\altera\<version number>; on Linux it is /opt/altera<version number>.
Figure 1–3. Directory Structure
<path>
Installation directory
ip
Contains the Altera MegaCore IP Library and third-party IP cores
altera
Contains the Altera MegaCore IP Library
common
Contains shared components
cpri
Contains the CPRI IP core files
src
Contains the CPRI IP core encrypted lower-level design files
constraints
Contains the Synopsys Design Constraints and Tcl constraints scripts for the CPRI IP core
cus_demo_tb
Contains the demonstration testbenches for the CPRI IP core
You can use Altera’s free OpenCore Plus evaluation feature to evaluate the CPRI IP
core in simulation and in hardware before you purchase a license. You must purchase
a license for the CPRI IP core only when you are satisfied with its functionality and
performance, and you want to take your design to production.
After you purchase a license for the CPRI IP core, you can request a license file from
the Altera website at www.altera.com/licensing and install it on your computer.
When you request a license file, Altera emails you a license.dat file. If you do not have
internet access, contact your local Altera representative.
OpenCore Plus Evaluation
With the Altera free OpenCore Plus evaluation feature, you can perform the following
actions:
■ Simulate the behavior of a megafunction (Altera IP core or AMPP
megafunction) in your system using the Quartus II software and Altera-supported
VHDL and Verilog HDL simulators
■ Verify the functionality of your design and evaluate its size and speed quickly and
easily
■ Generate time-limited device programming files for designs that include Altera IP
cores
■ Program a device and verify your design in hardware
SM
June 2012 Altera Corporation CPRI MegaCore Function
User Guide
1–10 Chapter 1: About This MegaCore Function
Installation and Licensing
OpenCore Plus Time-Out Behavior
OpenCore Plus hardware evaluation supports the following two operation modes:
■ Untethered—the design runs for a limited time.
■ Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely.
All megafunctions in a device time out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction's time-out behavior might be masked by the time-out behavior
of the other megafunctions.
1 For Altera IP cores, the untethered time-out is 1 hour; the tethered time-out value is
indefinite.
Your design stops working after the hardware evaluation time expires.
The CPRI IP core then behaves as if the
reset
and
cpu_reset
signals are asserted: the
CPRI link and the CPU interface reset. The transceivers do not reset, because the
transceiver quad might be shared with other designs, IP cores, and megafunctions.
The CPRI IP core cannot achieve frame synchronization, and cannot participate in
further CPRI communication.
f For information about installation and licensing, refer to Altera Software Installation and
Licensing. For information about the OpenCore Plus evaluation feature, refer to
AN 320: OpenCore Plus Evaluation of Megafunctions.
CPRI MegaCore Function June 2012 Altera Corporation
User Guide
You can customize the CPRI IP core to support a wide variety of applications. You use
MegaWizard Plug-In
Manager Flow
Instantiate MegaCore
In Design
Specify Constraints
Specify Parameters
Generate
MegaCore Function
Compile Design
Program Device
Simulate with
T estbench
Generate
MegaCore Function
the MegaWizard Plug-In Manager in the Quartus II software to parameterize a
custom IP core variation in a CPRI parameter editor. The CPRI parameter editor lets
you interactively set parameter values and select optional ports.
MegaWizard Plug-In Manager Design Flow
Figure 2–1 shows the stages for creating a system with the CPRI IP core and the
Quartus II software. Each stage is described in detail in subsequent sections.
Figure 2–1. CPRI Design Flow
2. Getting Started
The MegaWizard Plug-In Manager flow allows you to customize the CPRI IP core,
and manually integrate the function in your design.
Specifying Parameters
To specify CPRI IP core parameters using the MegaWizard Plug-In Manager, perform
the following steps:
1. Create a Quartus II project using the New Project Wizard available from the File
menu.
June 2012 Altera Corporation CPRI MegaCore Function
User Guide
2–2 Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
2. Launch the MegaWizard Plug-In Manager from the Tools menu, and follow the
prompts in the MegaWizard Plug-In Manager interface to create a custom CPRI IP
core variation.
To select the CPRI IP core, click
Installed Plug-Ins > Interfaces > CPRI > CPRI v12.0.
3. Specify the parameters. For details about these parameters, refer to Chapter 3,
Parameter Settings.
As you specify parameters, the CPRI parameter editor displays messages about
the variation that your current settings define. If your settings define a variation
for which a testbench is automatically generated when the CPRI IP core is
generated, an information message tells you the name of the relevant testbench.
For more information about the testbenches and the variations that provide them,
refer to Chapter 8, Testbenches.
4. Click Finish to generate the CPRI IP core and supporting files.
You might have to wait several minutes for file generation to complete.
5. When you are prompted to generate an example design, turn on Generate
Example Design. You must turn on this option to generate the testbenches
described in Chapter 8, Testbenches.
6. Click Generate. Despite the moving progress bar, generation does not progress
until you click this button.
7. If you generate the CPRI IP core instance in a Quartus II project, you are prompted
to add the Quartus II IP File (.qip) to the current Quartus II project. You can also
turn on Automatically add Quartus II IP Files to all projects.
The .qip file is generated by the parameter editor, and contains information about
the generated IP core. In most cases, the .qip file contains all of the necessary
assignments and information required to process the IP core or system in the
Quartus II compiler. The parameter editor generates a single .qip file for each IP
core.
Generating your custom CPRI IP core variation creates a set of HDL files and
simulation models. You can now integrate your custom CPRI IP core variation in your
design, simulate, and compile.
CPRI MegaCore Function June 2012 Altera Corporation
User Guide
Chapter 2: Getting Started 2–3
MegaWizard Plug-In Manager Design Flow
When you integrate your CPRI IP core variation in your design, observe the following
connection and I/O assignment requirements:
■ In Arria II, Cyclone IV GX, and Stratix IV GX designs:
■ Ensure that you connect the calibration clock (
signal with the appropriate frequency range of 10–125 MHz. The
gxb_cal_blk_clk
) to a clock
cal_blk_clk
ports on other components that use transceivers must be connected to the same
clock signal.
■ Add a dynamic reconfiguration block (
altgx_reconfig
) and connect it as
specified in the Arria II Device Handbook, Cyclone IV Device Handbook, or
Stratix IV Device Handbook. This block supports offset cancellation to
compensate for analog voltages offset from required ranges due to process
variations. The design compiles without the
altgx_reconfig
block, but it
cannot function correctly in hardware.
■ To support the correct signal connections from the CPRI IP core to the dynamic
reconfiguration block, in the ALTGX MegaWizard Plug-In Manager, on the
Reconfiguration Settings tab, turn on Analog controls.
■ In Arria V and Stratix V designs, add an Altera Transceiver Reconfiguration
Controller and connect it as specified in the Altera Transceiver PHY IP Core User
Guide. This block supports offset cancellation to compensate for analog voltages
offset from required ranges due to process variations. The design does not compile
without the Altera Transceiver Reconfiguration Controller, but it cannot function
correctly in hardware.
Before you compile your system to generate a Programmable Object File (.pof) with
which to configure your device, Altera recommends that you create assignments for
the high-speed transceiver VCCH settings.
To create assignments for the high-speed transceiver VCCH settings, perform the
following steps:
1. In the Quartus II window, on the Assignments menu, click Assignment Editor.
2. In the <<new>> cell in the To column, type the top-level signal name for your
CPRI IP core instance
3. Double-click in the Assignment Name column and click I/O Standard.
4. Double-click in the Val u e column and click your standard (for example, 1.5-V
PCML).
5. In the new <<new>> row, repeat steps 2 to 4 for your CPRI IP core instance
gxb_rxdatain
Simulation Files
Generating a CPRI IP core creates an <instance_name>_sim directory with a
subdirectory for each of several different simulators. Each of the vendor-specific
directories contains files and scripts to simulate your CPRI IP core with that vendor ’s
simulation tools.
The <instance_name>_sim/altera_cpri directory contains the top-level simulation file
for your CPRI IP core.
signal.
gxb_txdataout
signal.
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User Guide
2–4 Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
Generating a CPRI IP core creates a more complex directory structure for Arria V and
Stratix V variations than for variations that target other device families, because the
Arria V and Stratix V variations instantiate an Altera Deterministic Latency PHY IP
core or an Altera Native PHY IP core. In an Arria V or Stratix V variation, your
<instance_name>_sim directory contains multiple subdirectories, one for each of the
various components in the Arria V or Stratix V CPRI IP core, and individual
directories for vendors for three different simulators. Each of the vendor-specific
directories contains files and scripts to simulate your CPRI IP core with that vendor ’s
simulation tools.
Figure 2–2 shows the directory structure of your CPRI IP core that contains a
Deterministic Latency PHY IP core and generates a VHDL testbench. For information
about the CPRI IP core variations that provide a VHDL testbench, refer to “Simulating
the Design”.
Figure 2–2. Generated CPRI IP Core Directory Structure for Most Arria V and Stratix V Variations
<working directory>
Quartus II project working directory
<instance name>
CPRI IP core instance HDL files
The altera_xcvr_det_latency directory contains the files to simulate the Altera
Deterministic Latency PHY IP core that is generated as part of your CPRI IP core. It
also contains a mentor subdirectory with IEEE encrypted files to simulate the PHY IP
core efficiently.
Simulating the Design
During the design process, to check your design quickly, you can simulate your CPRI
IP core with any of several Altera-supported EDA simulation tools.
<instance name>_sim
CPRI IP core instance simulation files and scripts
altera_cpri
Contains the CPRI IP core instance top-level simulation file
altera_cpri_instance, altera_merlin_master_translator,
altera_merlin_slave_translator, altera_xcvr-det_latency
Contain the CPRI IP core instance lower-level simulation files
Vendor-specific directories contain simulation scripts
<instance name>_testbench
Contains the VHDL testbench simulation files
altera_cpri
Contains the lower-level testbench simulation files
f For more information about these tools and how to simulate designs created using the
Quartus II software, refer to the “Simulation” section in volume 3 of the Quartus II
Handbook.
CPRI MegaCore Function June 2012 Altera Corporation
User Guide
Chapter 2: Getting Started 2–5
Specifying Constraints
You can simulate your CPRI IP core variation using its IP functional simulation model
and VHDL demonstration testbench. The IP functional simulation model, and
testbench files for the CPRI IP core variations that support demonstration testbenches,
are generated in your project directory when you generate your CPRI IP core. The
testbench files include scripts to compile and run the demonstration testbench. The
testbench demonstrates how to instantiate a model in a design and includes simple
stimuli to control the user interfaces of the CPRI IP core.
1 A Verilog HDL testbench is not generated. If you specify Verilog HDL in the
MegaWizard Plug-In Manager, it generates a Verilog HDL IP functional simulation
model for the CPRI IP core. If your CPRI IP core variation is listed in Table 2–1, the
corresponding VHDL demonstration testbench is also generated. You can use this
model with the VHDL demonstration testbench for simulation using a
mixed-language simulator.
For a complete list of models or libraries required to simulate the CPRI IP core, refer to
the compile[_<variation>]_<HDL>.do scripts provided with the demonstration
testbenches described in Chapter 8, Testbenches.
Not all variations provide demonstration testbenches. To view example scripts and to
run a demonstration testbench, you must generate a variation that provides a
testbench. Tab le 2– 1 lists the CPRI variations that provide a testbench. Refer to
Chapter 8, Testbenches for information about the specific testbench generated for each
variation in Table 2–1. In addition to the variations specified in Table 8–4 on page 8–7,
you generate VHDL testbenches with the corresponding Verilog HDL IP core
variations, as shown in Tabl e 2 –1 .
Table 2–1. CPRI IP Core Variations that Provide a Demonstration Testbench
Properties
Common to all
Variations with
Testbench
REC master
clocking,
0.6144 Gbps line
rate, Include
HDLC Block is
Off, Enable MAP
interface
synchronization is
Off
f For information about IP functional simulation models, refer to the Simulating Altera
Designs chapter in volume 3 of the Quartus II Handbook.
Specifying Constraints
Altera provides a Synopsys Design Constraints (.sdc) file that you must apply to
ensure that the CPRI IP core meets design timing requirements. In most cases the
script requires modification for your design. For modification guidelines, refer to
Appendix E, Integrating the CPRI IP Core Timing Constraints in the Full Design.
Device Family
Arria II
Arria V, Stratix V
Cyclone IV GX,
Stratix IV GX
Enable
Autorate
Negotiation
Off — On or Off 3
Off — Off 0
Off
Off Off 0
On On 0
Off — On or Off 3
Off — Off 0
On — On 0
Reference
Clock
Frequency
61.44 MHz
Include
MAC Block
On or Off 3
Number of
Antenna-Carrier
Interfaces
June 2012 Altera Corporation CPRI MegaCore Function
User Guide
2–6 Chapter 2: Getting Started
f For information about timing analyzers, refer to the Quartus II Help and the “Timing
Analysis” section in volume 3 of the Quartus II Handbook.
Compiling and Programming the Device
Compiling and Programming the Device
You can use the Start Compilation command on the Processing menu in the
Quartus II software to compile your design. After successfully compiling your design,
program the targeted Altera device with the Programmer and verify the design in
hardware.
1 Before compiling your CPRI IP core or other incomplete CPRI design in the Quartus II
software, you must assign unconnected CPRI IP core signals to virtual pins.
f For information about compiling your design in the Quartus II software, refer to the
Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter in
volume 1 of the Quartus II Handbook. For information about programming an Altera
device, refer to the “Device Programming” section in volume 3 of the Quartus II
Handbook.
Instantiating Multiple CPRI IP Cores
If you want to instantiate multiple CPRI IP cores in an Arria II, Cyclone IV GX, or
Stratix IV GX device, you must observe a few additional requirements.
When your design contains multiple IP cores, you must ensure that the
gxb_cal_blk_clk
requirements for your target device family, and that the instances each have different
starting channel numbers.
You must ensure that a single calibration clock source drives the
input to each CPRI IP core (or any other megafunction or user logic that uses the
ALTGX megafunction).
When you merge multiple CPRI IP cores in a single transceiver block, the same signal
must drive
megafunctions, Altera IP cores, and user logic that use the ALTGX megafunction.
Multiple CPRI IP cores in a single device must use distinct transceiver channels. You
enforce this restriction by specifying different starting channel numbers for the
distinct CPRI IP cores. The starting channel number is a parameter whose value you
specify for each CPRI IP core in the CPRI parameter editor. Refer to Chapter 3,
Parameter Settings.
To configure multiple CPRI IP cores in a single transceiver block, you must specify in
your Quartus Settings File (.qsf) that these CPRI link data lines are configured in the
same
GXB_TX_PLL_RECONFIG_GROUP
link
cN_gxb_txdataout
input and
gxb_powerdown
:
gxb_powerdown
to each of the CPRI IP core variations and other
signals are connected according to the
gxb_cal_blk_clk
, using the following syntax for each outgoing CPRI
set_instance_assignment -name GXB_TX_PLL_RECONFIG_GROUP 1 -to cN_gxb_txdataout
CPRI MegaCore Function June 2012 Altera Corporation
User Guide
3. Parameter Settings
You customize the CPRI IP core by specifying parameters in the CPRI parameter
editor, which you access from the MegaWizard Plug-In Manager in the Quartus II
software.
This chapter describes the parameters and how they affect the behavior of the CPRI IP
core. You can modify parameter values to specify the following CPRI IP core
properties:
■ Clocking mode—whether this CPRI IP core instance is configured with slave
clocking mode (RE slave) or with master clocking mode (REC or RE master).
■ Line rate.
■ Autorate negotiation—whether this CPRI IP core instance supports the connection
of external logic to implement autorate negotiation.
■ Starting channel number.
■ Depth of the low-level receiver elastic buffer.
■ Transceiver reference clock frequency. This option is available only in Arria V and
Stratix V devices.
■ Ethernet MAC—whether to include an internal Ethernet MAC block or provide an
MII to connect to an external Ethernet module. These two options are mutually
exclusive.
■ HDLC block—whether to include an internal HDLC block or not.
■ Number of antenna-carrier interfaces.
■ Whether the antenna-carrier interfaces are clocked by the CPRI IP core clock
cpri_clkout
or by external clocks.
Physical Layer Parameters
This section lists the parameters that affect the configuration of the physical layer of
the CPRI IP core.
Operation Mode Parameter
The Operation mode parameter specifies whether the CPRI IP core is configured with
slave clocking mode or with master clocking mode. An REC is configured with master
clocking mode.
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User Guide
3–2 Chapter 3: Parameter Settings
Physical Layer Parameters
Line Rate Parameter
The Line rate parameter specifies the line rate on the CPRI link in gigabits per second
(Gbps). Ta bl e 3 –1 lists the CPRI line rates that each device family supports. A
checkmark indicates a supported variation.
Table 3–1. Device Family Support for CPRI Line Rates
Device Family
or Variant
Arria II GX vvvvv
Arria II GZ vvvvvv—
Arria V GX vvvvvv—
Arria V GT vvvvvvv
Cyclone IV GX vvvv———
Stratix IV GX vvvvvv—
Stratix V GX vvvvvvv
Stratix V GT vvvvvvv
Note to Tab le 3– 1:
(1) If you specify a CPRI line rate of 4.9152 or 6.144 Gbps for a variation that targets an Arria II GX device, your
Quartus II project must target an I3 speed grade device. The parameter editor does not enforce this restriction.
However, if you violate this restriction, compilation fails because the design cannot meet timing in hardware.
614.4 1228.8 2457.6 3072.0 4915.2 6144 9830.4
Enable Autorate Negotiation
Autorate negotiation is the process of stepping down from a higher target CPRI line
rate to a lower target CPRI line rate if you are unable to establish a link at the higher
line rate. If your CPRI IP core has autorate negotiation enabled, and you program it to
step down from its highest target CPRI line rate to its lower target CPRI line rates
when it does not achieve frame synchronization, your CPRI IP core achieves frame
synchronization at the highest possible CPRI line rate in its range of potential line
rates, depending on the capability of its CPRI partner.
CPRI Line Rate (Mbps)
(1)
v
(1)
—
For information about the autorate negotiation feature, refer to Appendix B,
Implementing CPRI Link Autorate Negotiation.
In the current release, CPRI IP core variations configured at the CPRI line rate of
9830.4 Mbps that target an Arria V device do not support autorate negotiation.
Turn o n t he Enable auto-rate negotiation parameter to specify that your CPRI IP core
supports autorate negotiation. By default, this parameter is turned off.
Transceiver Starting Channel Number
You can specify the starting number for the CPRI IP core transceiver. For a CPRI IP
core master, the Master transceiver starting channel number specifies the starting
channel number for the transceiver.
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User Guide
Chapter 3: Parameter Settings 3–3
Physical Layer Parameters
For a CPRI IP core configured with slave clocking mode, the Slave transmitter
starting channel number and Slave receiver starting channel number are two
separate parameters. Both must have values that are starting channel numbers
available in your design. The two numbers must be different but the Quartus II
software creates an FPGA configuration with a single slave transceiver.
If you instantiate multiple CPRI IP cores on the same device, you must ensure each
uses distinct transceiver channels.
These parameters are not available in Arria V and Stratix V devices.
Rx Elastic Buffer Depth
You can specify the depth of the Rx elastic buffer in the CPRI Receiver block. The
Receiver buffer depth value is the log
are 4 to 8, inclusive.
The default depth of the Rx elastic buffer is 64, specified by the Receiver buffer depth
parameter default value of 6. For most systems, the default Rx elastic buffer depth is
adequate to handle dispersion, jitter, and wander that can occur on the link while the
system is running. However, the parameter is available for cases in which additional
depth is required.
of the Rx elastic buffer depth. Allowed values
2
1 Altera recommends that you set Receiver buffer depth to 4 in CPRI RE slave
variations.
CPRI IP core variations configured at a CPRI line rate of 9830.4 Mbps that target an
Arria V GT device do not include an Rx elastic buffer. However, this parameter affects
the depth of the RX buffer between the soft PCS and the Altera Transceiver Native
PHY IP core, instead. Refer to Figure 4–4 on page 4–7.
f For information about the Altera Transceiver Native PHY IP core, refer to the Altera
Transceiver PHY IP Core User Guide.
The value you specify for Receiver buffer depth is referred to as WIDTH_RX_BUF in
this user guide.
For more information about the Rx elastic buffer, refer to “Rx Elastic Buffer” on
page 4–49.
Transceiver Reference Clock Frequency
If your CPRI variation targets an Arria V or a Stratix V device, the Transceiver
reference clock frequency parameter is available. Use this parameter to modify the
expected frequency of the CPRI transceiver input reference clock to the frequency of
an available clock for your design.
The frequency you specify is an input parameter to the Altera Deterministic Latency
PHY IP core that is included in your Arria V or Stratix V CPRI variation. Values
available at each CPRI line rate are the reference clock frequencies for which the
Deterministic Latency PHY IP core supports the target CPRI line rate. The default
value is 122.88 MHz.
June 2012 Altera Corporation CPRI MegaCore Function
User Guide
3–4 Chapter 3: Parameter Settings
f For more information about the Altera Deterministic Latency PHY IP core, refer to the
Altera Transceiver PHY IP Core User Guide.
Data Link Layer Parameters
Data Link Layer Parameters
This section lists the parameter that affects the configuration of the data link layer of
the CPRI IP core.
Include MAC Block
Turn o n t he Include MAC block parameter to specify that your CPRI IP core includes
an internal Ethernet MAC block. By default, this parameter is not turned on. If this
parameter is not turned on, the CPRI IP core implements the media-independent (MI)
interface (MII) to your own external Ethernet MAC, instead.
If this parameter is not turned on in your CPRI IP core, your application cannot access
the Ethernet registers. Attempts to access these registers read zeroes and do not write
successfully, as for a reserved register address.
For information about the internal Ethernet MAC block, refer to “Accessing the
Ethernet Channel” on page 4–42.
For information about the MII, refer to “Media Independent Interface to an External
Ethernet Block” on page 4–34.
Include HDLC Block
Turn o n t he Include HDLC block parameter to specify that your CPRI IP core
includes an internal HDLC block. By default, this parameter is not turned on.
If this parameter is not turned on in your CPRI IP core, your application cannot access
the HDLC registers. Attempts to access these registers read zeroes and do not write
successfully, as for a reserved register address.
Application Layer Parameters
This section lists the parameters that affect the configuration of the application layer
of the CPRI IP core.
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User Guide
Chapter 3: Parameter Settings 3–5
Application Layer Parameters
Mapping Mode
The Mapping mode(s) parameter specifies whether your CPRI IP core MAP interface
supports a programmable AxC mapping mode or is configured with a specific
mapping mode. Tab le 3– 2 lists the supported values.
Table 3–2. MAP Interface AxC Mapping Mode Support
Value Description
If you select this value, you configure a CPRI IP core which you can program
dynamically to be in any mapping mode. In this case, you determine the current
All
Basic
Advanced 1
Advanced 2
Advanced 3
mapping mode for your CPRI IP core by programming the
CPRI_MAP_CONFIG
register (0x100).
For backward compatibility with previous releases of the CPRI IP core, the value of
All is the default value for this parameter.
For information about the
map_mode
register field, refer to Table 7–31 on
page 7–14.
Your CPRI IP core MAP interface is configured to function in basic mapping mode
only. This mapping mode has the following features:
■ Conforms to the description in Sections 4.2.7.2.2 and 4.2.7.2.3 of the CPRI
Specification V4.2 Interface Specification.
■ Supports communication that complies with the LTE/E-UTRA or UMTS/WCDMA
standard.
For information about the basic mapping mode in the CPRI IP core, refer to “MAP
Interface Mapping Modes” on page 4–11.
Your CPRI IP core MAP interface is configured in a single AxC mapping mode only,
a mode that has the following features:
■ Conforms to Method 1: IQ Sample Based described in Section 4.2.7.2.5 of the
CPRI Specification V4.2 Interface Specification.
■ Supports communication that complies with the WiMAX standard.
For information about this AxC mapping mode, refer to Appendix C, Advanced AxC
Mapping Modes.
Your CPRI IP core MAP interface is configured in a single AxC mapping mode only,
a mode that has the following features:
■ Conforms to Method 3: Backward Compatible described in Section 4.2.7.2.4 of
the CPRI Specification V4.2 Interface Specification.
■ Supports communication that complies with the WiMAX or LTE/E-UTRA
standard.
For information about this AxC mapping mode, refer to Appendix C, Advanced AxC
Mapping Modes.
Your CPRI IP core MAP interface is configured in a single AxC mapping mode only,
a legacy mode that has the following features:
■ Conforms to Method 1: IQ Sample Based described in Section 4.2.7.2.5 of the
CPRI Specification V4.2 Interface Specification.
■ Supports communication that complies with the LTE/E-UTRA standard.
This mode does not support 16-bit wide IQ data samples. Refer to Table 7–31 on
page 7–14.
For information about this AxC mapping mode, refer to Appendix C, Advanced AxC
Mapping Modes.
map_mode
field of the
June 2012 Altera Corporation CPRI MegaCore Function
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3–6 Chapter 3: Parameter Settings
Application Layer Parameters
Number of Antenna-Carrier Interfaces
The Number of antenna/carrier interfaces parameter specifies the number of
antenna-carrier interfaces, or data channels, in your CPRI IP core. The supported
values are 0 to 24. Set this parameter to the maximum number of data channels you
expect your CPRI IP core to use at the same time.
If you set this parameter to zero, your CPRI IP core does not implement the CPRI
MAP interface. For example, you might use this option if your CPRI IP core passes IQ
data samples through the AUX interface to an external custom mapping function that
you provide.
You can specify in software that some of the antenna-carrier interfaces that you
configure in your CPRI IP core are not active. This feature allows you to change the
number of active and enabled data channels dynamically.
The combination of CPRI IP core line rate, sampling width, and sampling rate restricts
the number of active antenna-carrier interfaces your CPRI IP core can support. For
example, if your CPRI IP core operates at line rate 3.072 Gbps, it can support as many
as 20 active antenna-carrier interfaces, but if your CPRI IP core operates at line rate
1.2288 Gbps, it can support a maximum of eight active antenna-carrier interfaces. For
details, refer to Tab le 4– 4 and Table 4–5 on page 4–14.
1 The software configuration feature allows you to modify the number of active
antenna-carrier interfaces; if you modify this number, you must keep in mind the
restrictions for your current CPRI line rate. Otherwise, data is dropped in the
mapping to and from the individual antenna-carrier interfaces.
If you set the
lower than the value you specify for Number of antenna/carrier interfaces, then the
first N data channels are active and the others are not. In addition, for each
antenna-carrier interface you can use the relevant
CPRI_IQ_RX_BUF_CONTROL
CPRI_IQ_TX_BUF_CONTROL
direction. A data channel must be configured, active, and enabled to function. If it is
configured and active but not enabled, data to and from it is ignored.
The value you specify for Number of antenna/carrier interfaces is referred to as
N_MAP in this user guide.
For more information about the antenna-carrier interfaces in a CPRI IP core, refer to
“MAP Interface” on page 4–10.
map_ac
field of the
register and the relevant
register to enable or disable the specific data channel and
CPRI_MAP_CNT_CONFIG
map_rx_enable bit
map_tx_enable
register to a number N that is
bit of the
Enable Internally-Clocked Synchronization Mode
If you configure one or more antenna-carrier interfaces, the option to Enable MAP
interface synchronization with core clock is available. If you turn on this option, both
the MAP receiver interface and the MAP transmitter interface are clocked with the
CPRI IP core internal clock,
are clocked with individual Rx and Tx clocks for each antenna-carrier interface.
cpri_clkout
. If you turn off this option, these interfaces
of the
If you turn on this option, the CPRI IP core coordinates communication on these
interfaces in the internally-clocked synchronization mode. Turning on this option
simplifies synchronization of data transfers to and from the antenna-carrier interfaces.
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User Guide
Chapter 3: Parameter Settings 3–7
Application Layer Parameters
The Boolean value you specify for Enable MAP interface synchronization with core
clock is referred to as SYNC_MAP in this user guide. Tab le 3 –3 shows the
correspondence between the parameter, the MAP interface synchronization mode,
and the clocks that clock the antenna-carrier interfaces.
Table 3–3. Meaning of Enable Map Interface synchronization with core clock Parameter
Enable MAP interface
synchronization with core clock
On 1 Internally-clocked mode
Off 0
For more information about these clocks, refer to “Clocking Structure” on page 4–3.
For more information about the synchronization modes for the Rx and Tx MAP
interfaces, and how they vary depending on your selection of this option, refer to
“MAP Interface” on page 4–10.
SYNC_MAP
MAP Interface
Synchronization Mode
Synchronous buffer or
FIFO mode
Clocks for Antenna-Carrier Interfaces
cpri_clkout
mapN_rx_clk, mapN_tx_clk
antenna-carrier interfaces
, for
N
= 1 ... (N_MAP – 1)
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3–8 Chapter 3: Parameter Settings
Application Layer Parameters
CPRI MegaCore Function June 2012 Altera Corporation
User Guide
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