ALTERA CPRI User Guide

Download

CPRI MegaCore Function User Guide

CPRI MegaCore Function

User Guide

101 Innovation Drive San Jose, CA 95134

www.altera.com

UG-01062-5.0

Document last updated for Altera Complete Design Suite version:

Document publication date:

12.0

June 2012

Feedback Subscribe

© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

Chapter 1. About This MegaCore Function

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

CPRI IP Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6

Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8

Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8

OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9

OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10

Chapter 2. Getting Started

MegaWizard Plug-In Manager Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Specifying Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Simulation Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Specifying Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Compiling and Programming the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Instantiating Multiple CPRI IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Chapter 3. Parameter Settings

Physical Layer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Operation Mode Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Line Rate Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Enable Autorate Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Transceiver Starting Channel Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Rx Elastic Buffer Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Transceiver Reference Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Data Link Layer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Include MAC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Include HDLC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Application Layer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Mapping Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Number of Antenna-Carrier Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Enable Internally-Clocked Synchronization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Chapter 4. Functional Description

Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Clocking Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

CPRI IP Core Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Clock Diagrams for the CPRI IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

Clock Diagrams for Most CPRI IP Core Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

Clock Diagram for CPRI IP Core Arria V GT Variations at 9830.4 Mbps . . . . . . . . . . . . . . . . . . . . 4–6

CPRI Communication Link Line Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

Reset Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

MAP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

MAP Interface Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

Basic AxC Mapping Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

iv ContentsContents

Advanced AxC Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15

MAP Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15

MAP Receiver Interface Signals in Different Synchronization Modes . . . . . . . . . . . . . . . . . . . . . 4–16

MAP Receiver in FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

MAP Receiver in Synchronous Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18

MAP Receiver in the Internally-Clocked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20

MAP Transmitter Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21

MAP Transmitter Interface Signals in Different Synchronization Modes . . . . . . . . . . . . . . . . . . 4–22

MAP Transmitter in FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23

MAP Transmitter in Synchronous Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24

MAP Transmitter in the Internally-clocked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

Auxiliary Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

AUX Receiver Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

AUX Transmitter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31

Media Independent Interface to an External Ethernet Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34

MII Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–35

MII Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–36

CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–38

Accessing the Hyperframe Control Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–39

Recording and Retrieving the Incoming Control Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40

Writing the Outgoing Control Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40

Control Word Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40

Control Word Transmission Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–41

Control Word Retrieval Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–41

Accessing the Ethernet Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–42

Transmitting Ethernet Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–42

Receiving Ethernet Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–43

Accessing the HDLC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–45

CPRI Protocol Interface Layer (Physical Layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–46

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–46

Physical Layer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–47

Ensuring the Physical Layer Routes Your Data as Expected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–47

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–48

High-Speed Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–48

Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–49

Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–49

Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–49

Alarm Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–50

Reset Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–51

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–52

Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53

Tx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53

High-Speed Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53

Chapter 5. Testing Features

Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Internal Reverse Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

Physical Layer Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

Reverse Loopback Through CPRI Rx and Tx Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

PRBS Generation and Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

CPRI MegaCore Function June 2012 Altera Corporation User Guide

ContentsContents v

Chapter 6. Signals

MAP Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

MAP Receiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

MAP Transmitter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

Auxiliary Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

AUX Receiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

AUX Transmitter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

Extended Rx Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

CPRI MII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

CPRI MII Receiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

CPRI MII Transmitter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

CPU Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Physical Layer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

CPRI Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

Layer 1 Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

Layer 1 Error Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

Autorate Negotiation Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

Transceiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Clock and Reset Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Chapter 7. Software Interface

CPRI Protocol Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2

MAP Interface and AUX Interface Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14

Ethernet Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21

HDLC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–26

Chapter 8. Testbenches

Test Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5

Reset, Frame Synchronization, and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6

Running the Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7

Appendix A. Initialization Sequence

Appendix B. Implementing CPRI Link Autorate Negotiation

Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1

Configuring the CPRI IP Core for Autorate Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3

Running Autorate Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3

Appendix C. Advanced AxC Mapping Modes

Backward Compability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1

Advanced Mapping Mode Similarities and Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–2

Fifteen-Bit Width Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–3

Sixteen-Bit Width Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–4

Appendix D. Delay Measurement and Calibration

Altera Delay Measurement and Calibration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1

Delay Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1

Rx Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–3

Rx Path Delay Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–3

Rx Transceiver Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–4

Rx Transceiver Latency in Most CPRI IP Core Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–5

Rx Transceiver Latency in Arria V GT Variations at CPRI Line Rate 9.8 Gbps . . . . . . . . . . . . . . D–5

Extended Rx Delay Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–5

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

vi ContentsContents

M/N Ratio Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–6

Arria V GT Variations with CPRI Line Rate 9.8 Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–6

CPRI Receive Buffer Delay Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–6

Round-Trip Calibration Delay in Rx Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–7

Fixed Rx Core Delay Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–8

Rx Path Delay to AUX Output: Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–8

Tx Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–9

Fixed Tx Core Delay Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–11

Extended Tx Delay Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–11

Tx Bitslip Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–12

Tx Transceiver Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–12

Tx Transceiver Latency in Most CPRI IP Core Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–12

Tx Transceiver Latency in Arria V GT Variations at CPRI Line Rate 9.8 Gbps . . . . . . . . . . . . . D–13

T14, Toffset, Round-Trip Delay, and Round-Trip Cable Delay Calculations . . . . . . . . . . . . . . . . . . . . D–13

Round-Trip and Cable Delay Calculations for a Single-Hop Configuration . . . . . . . . . . . . . . . . . D–14

Tx Bitslip Delay in the Round-Trip Delay Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–15

Single-Hop Round-Trip and Cable Delay Calculation Examples . . . . . . . . . . . . . . . . . . . . . . . . D–15

Dynamic Pipelining for Automatic Round-Trip Delay Calibration . . . . . . . . . . . . . . . . . . . . . . . . . D–21

Round-Trip Calculations for a Multihop Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–22

Multihop Round-Trip Delay Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–22

Multihop Round-Trip Cable Delay Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–23

Two-Hop Round-Trip and Cable Delay Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . D–23

Appendix E. Integrating the CPRI IP Core Timing Constraints in the Full Design

Appendix F. Porting a CPRI IP Core from the Previous Version of the Software

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–3

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–3

CPRI MegaCore Function June 2012 Altera Corporation User Guide

The Altera® CPRI MegaCore® function implements the Common Public Radio

CPRI

MegaCore Function

(RE Slave)

FPGA FPGA

CPRI

MegaCore Function

(RE Slave)

CPRI

MegaCore Function

(RE Master)

FPGA

CPRI

MegaCore Function

(REC)

Clock

Module

Base Band Module

Optical Link

CPRICPRICPRI

CPRI

Routing Layer

MAP MAPAUX AUX

Interface (CPRI) specification. CPRI is a high-speed serial interface designed for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE).

The CPRI IP core targets high-performance, remote, radio network applications. You can configure the CPRI IP core as an RE or an REC. Figure 1–1 shows an example system implementation with a two-hop daisy chain. Optical links between devices support high performance.

Figure 1–1. Typical CPRI Application on Altera Devices

1. About This MegaCore Function

General Description

June 2012 Altera Corporation CPRI MegaCore Function

The Altera CPRI IP core implements Layer 1 and Layer 2 of the CPRI V4.2 specification. It provides access to the Layer 2 access points through various interfaces:

■ IQ data access:

■ MAP antenna-carrier interfaces for easy IQ user data plane access based on

pre-configured antenna-carrier channels.

■ Auxiliary interface for full access to the user data plane.

User Guide

1–2 Chapter 1: About This MegaCore Function

General Description

■ Ethernet channel access:

■ Auxiliary interface for full access to the Ethernet space in the CPRI frame.

■ Register support for loading and unloading the Ethernet frame.

■ MI interface port for Ethernet Frame access.

■ HDLC channel access:

■ Auxiliary interface for full access to the high level data link control (HDLC)

space in the CPRI frame.

■ Register support for loading and unloading the HDLC frame.

■ Vendor-specific data (VSS):

■ Auxiliary interface for full access to control bytes.

■ Register support for loading and unloading VSS space.

■ Synchronization and Timing access:

■ Auxiliary interface for full access to synchronization and timing.

You configure the CPRI IP core to support either Ethernet communication with an Ethernet media access control (MAC) block included in the IP core, or communication with an external Ethernet module. The CPRI link line rate is configurable. For information about these interfaces and functionality, refer to Chapter 4, Functional

Description. For information about configuration options, refer to Chapter 3, Parameter Settings.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 1: About This MegaCore Function 1–3

tx_dataout

Transmitter Transceiver

Transmitter

rx_datain

CPRI LinkCPRI Link

Receiver

Transceiver

Receiver

Multiplexing

Time Division Multiplexing

Data

Full access

CPRI frame

Vendor

Specific

Inband

Protocol

HDLC (2) Ethernet (3)

MAP

Interface (1)

AUX

Interface

CPU

Interface

CPRI IP Core Features

Figure 1–2 shows the CPRI IP core interfaces. The IP core assembles the outbound

CPRI frame control words and data from all of these interfaces, and unloads and routes control words and data from the inbound CPRI frame to the appropriate interfaces, based on configuration and register settings.

Figure 1–2. CPRI IP Core Interfaces

Notes to Figure 1–2:

(1) You can configure your CPRI IP core with zero, one, or multiple antenna-carrier interfaces. If you configure zero antenna-carrier interfaces, the

MAP interface is not configured in your CPRI IP core. In that case you can communicate IQ data through the AUX interface to your user-defined

routing layer. (2) You can configure your CPRI IP core with or without a high-level data link control (HDLC) block. (3) You can configure your CPRI IP core with an Ethernet MAC block or a media-independent (MI) interface (MII) block. The two options are mutually

exclusive.

CPRI IP Core Features

The CPRI IP core has the following features:

■ Complies with the Common Public Radio Interface (CPRI) Specification V4.2

(2010-09-29) Interface Specification for wireless base station submodule

interconnections, without the full range of data sample widths.

■ Supports radio equipment controller (REC) and radio equipment (RE) module

configurations, including RE master, RE slave, and REC master ports.

■ Supports Universal Mobile Telecommunication System (UMTS) Terrestrial Radio

Access (UTRA) – frequency division duplexing (UTRA-FDD) (UMTS/Wideband Code Division Multiple Access (W-CDMA)), Evolved UTRA (E-UTRA) (3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) specification), and Worldwide interoperability for Microwave Access (WiMAX) (IEEE 802.16 standard).

June 2012 Altera Corporation CPRI MegaCore Function

■ Full access to CPRI frame.

User Guide

1–4 Chapter 1: About This MegaCore Function

CPRI IP Core Features

■ Supports the following additional CPRI link features:

■ Programmable CPRI communication line rate (to 614.4, 1228.8, 2457.6, 3072.0,

4915.2, 6144.0, or 9830.4 Mbps) using Altera on-chip high-speed transceivers.

■ Auto-rate negotiation support.

■ Scrambling and descrambling at 4915.2 Mbps, 6144.0 Mbps, and 9830.4 Mbps.

■ Rx delay measurement.

■ Tx delay calibration.

■ Programmable hardware processing of the reset request bit in the CPRI frame.

■ Vendor-specific subchannel (VSS) communication on the CPRI link.

■ Diagnostic parallel reverse loopback paths.

■ Includes the following additional interfaces:

■ Interface to external or on-chip processor, using the Altera Avalon

Memory-Mapped (Avalon-MM) interconnect specification.

■ Ethernet communication interfaces that support simultaneous Ethernet and

HDLC communication to and from the CPRI link.

■ Optional configuration of Ethernet MAC.

■ Optional Media-Independent Interface for Ethernet frame access.

■ Optional configuration of HDLC block.

■ Auxiliary interface provides full access to CPRI frame.

■ Supports data transfer to and from custom mapping functions.

■ Supports data transfer from slave to master ports to implement daisy-chain

topologies.

■ Supports custom IQ sample widths.

■ An IQ data interface with the following features:

■ Implements mapping methods in Sections 4.2.7.2.5 and 4.2.7.2.7 of the CPRI

V4.2 Specification, and mapping Options 1 and 2 in Sections 4.2.7.2.3 and

4.2.7.2.4 of the CPRI V4.2 Specification.

■ Implements WiMAX mapping methods described in Sections 4.2.7.2.2,

4.2.7.2.5, and 4.2.7.2.7 of the CPRI V4.2 Specification.

■ Implements UMTS/LTE mapping methods described in Section 4.2.7.2 of

the CPRI V4.2 Specification.

■ Implements WiMAX timing control methodology described in Section

4.2.8.2 of the CPRI V4.2 Specification.

■ Supports as many as 24 antenna-carrier interfaces.

■ Supports clocking antenna-carrier interfaces with external data channel

clocks or internal IP core clock.

■ Supports synchronous buffer or simple FIFO synchronization modes for

externally clocked antenna-carrier interfaces.

■ Supports independent sample rates for each antenna-carrier interface.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 1: About This MegaCore Function 1–5

Device Family Support

■ Supports 15- and 16-bit data sample widths on uplink and downlink using

the Altera Avalon Streaming (Avalon-ST) interconnect specification.

Device Family Support

Tab le 1– 1 defines the device support levels for Altera IP cores.

Table 1–1. Altera IP Core Device Support Levels

FPGA Device Families HardCopy Device Families

Preliminary support—The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.

Final support—The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

HardCopy Companion—The IP core is verified with preliminary timing models for the HardCopy companion device. The IP core meets all functional requirements, but might still be undergoing timing analysis for the HardCopy device family. It can be used in production designs with caution.

HardCopy Compilation—The IP core is verified with final timing models for the HardCopy device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Tab le 1– 2 lists the level of support offered by the CPRI IP core for each Altera device

family.

Table 1–2. Device Family Support

Arria

II (GX and GZ variants) Final

Arria V (GX and GT variants)

Cyclone

HardCopy

Stratix

IV GX Final

IV GX HardCopy Compilation

IV GX Final

Stratix V

Other device families No support

MegaCore Verification

Before releasing a version of the CPRI IP core, Altera runs comprehensive regression tests in the current version of the Quartus MegaWizard simulation and hardware to confirm functionality.

Device Family Support

Refer to the What’s New in Altera IP page of the Altera website.

™

Plug-In Manager to create the instance files. Altera tests these files in

II software. These tests use the

Altera tests and verifies the CPRI IP core in hardware, especially the deterministic latency feature, for different platforms and environments.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

1–6 Chapter 1: About This MegaCore Function

Performance and Resource Utilization

This section contains tables showing IP core variation size and performance examples. For resource utilization information for additional CPRI IP core variations, refer to the reports the Quartus II software generates during compilation.

Tab le 1– 3 lists the resources and expected performance for CPRI IP core variations

configured with the following features:

■ Operate in REC master mode

■ Include autorate negotiation support if it is available at the relevant line rate in the

device family (turned off in Arria V GT variations with CPRI line rate

9830.4 Mbps)

■ Provide Ethernet access through the MI interface

■ Do not provide an HDLC block

■ Use Basic mapping mode

■ Clock the AxC channels with independent clocks (the Enable MAP interface

synchronization with core clock parameter is turned off)

The numbers of combinational ALUTs and logic registers are rounded up to the nearest 100.

Tab le 1– 3 lists results obtained with the Quartus II software v12.0 for the following

devices:

■ Arria V GT (5AGTBD7E3F35I5)

■ Arria V GX (5AGXFB3H4F35C4 for 6144, 4915.2, and 3072 Mbps variations and

5AGXFB3H6F35C6 for other variations)

■ Stratix V GX (5SGXMA5N2F40I2 for 9830.4 Mbps variations and

5SGXMA5N2F40I4 for other variations)

Table 1–3. CPRI IP Core FPGA Resource Utilization (Part 1 of 2)

Parameters Memory

Device

Line Rate

(Mbps)

Number of

Antenna-Carrier

Interfaces

Combinational ALUTs

0 4300 4000 11 —

1 4800 4800 21 —

Arria V GT 9830.4

4 5400 5500 27 —

8 6000 6400 35 —

Logic

Registers

M10K or

M20K

Blocks

Memory

(1)

ALUTs

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 1: About This MegaCore Function 1–7

Performance and Resource Utilization

Table 1–3. CPRI IP Core FPGA Resource Utilization (Part 2 of 2)

Parameters Memory

Device

Line Rate

(Mbps)

Number of

Antenna-Carrier

Interfaces

Combinational ALUTs

0 3000 3100 5 —

1 3800 4000 15 —

614.4

2 3900 4200 17 —

3 4100 4500 19 —

Arria V GX

1228.8,

2457.6, 3072,

4915.2,

6144

4 4300 4800 21 —

0 3000 3100 5 —

1 3800 4200 15 —

4 4300 4800 21 —

8 5000 5800 29 —

0 3000 3100 4 9

1 3800 4000 11 9

614.4

2 4000 4300 13 9

3 4100 4500 15 9

Stratix V GX

1228.8,

2457.6, 3072,

4915.2, 6144,

9830.4

Note to Table 1–3:

(1) M10K blocks in Arria V devices and M20K blocks in Stratix V devices.

4 4300 4800 17 9

0 3100 3200 5 —

1 3800 4300 11 —

4 4400 5100 17 —

8 5000 6200 25 —

Logic

Registers

M10K or

M20K

Blocks

Memory

(1)

ALUTs

Tab le 1– 4 shows the slowest device family speed grade that supports each CPRI line

rate in each device family. Lower speed grade numbers correspond to faster devices.

Table 1–4. Slowest Recommended Device Family Speed Grades

Device Family

or Variant

614.4 1228.8 2457.6 3072.0 4915.2 6144 9830.4

ArriaIIGX –6–6–6–6I3

ArriaIIGZ –4–4–4–4–3–3

Arria V GX C6 C6 C6 I5 I5 I5

(1)

(Part 1 of 2)

CPRI Line Rate (Mbps)

(2)

(2) (3)

(3)

Arria V GT C6 C6 C6 I5 I5 I5 I5

Cyclone IV GX C8, I7 C8, I7 C8, I7 –7

StratixIVGX–4–4–4–4–4–3

June 2012 Altera Corporation CPRI MegaCore Function

(3) (3) (3)

(3)

User Guide

1–8 Chapter 1: About This MegaCore Function

Release Information

Table 1–4. Slowest Recommended Device Family Speed Grades

Device Family

or Variant

Stratix V GX –4 –4 –4 –4 –4 –4 -2

Notes to Table 1–4:

(1) The entry –x indicates that both the industrial speed grade Ix and the commercial speed grade Cx are supported for this device family and CPRI

line rate. (2) Only the I3 speed grade is available for a CPRI IP core that runs at this line rate and targets the Arria II GX device family. (3) This CPRI line rate is not supported for this device family.

614.4 1228.8 2457.6 3072.0 4915.2 6144 9830.4

(1)

(Part 2 of 2)

CPRI Line Rate (Mbps)

Release Information

Tab le 1– 5 provides information about this release of the CPRI IP core.

Table 1–5. CPRI Release Information

Item Description

Version 12.0

Release Date June 2012

Ordering Code IP-CPRI

Product ID 00CB

Vendor ID 6AF7

Altera verifies that the current version of the Quartus II software compiles the previous version of each Altera IP core. Any exceptions to this verification are reported in the MegaCore IP Library Release Notes and Errata. Altera does not verify compilation with IP core versions older than the previous release.

Installation and Licensing

The CPRI IP core is part of the MegaCore IP Library, which is distributed with the Quartus II software. The combined software is downloadable from the Altera website,

www.altera.com.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 1: About This MegaCore Function 1–9

Installation and Licensing

Figure 1–3 shows the directory structure after you install the CPRI IP core, where

path> is the installation directory. The default installation directory on Windows is

C:\altera\<version number>; on Linux it is /opt/altera<version number>.

Figure 1–3. Directory Structure

<path>

Installation directory

Contains the Altera MegaCore IP Library and third-party IP cores

altera

Contains the Altera MegaCore IP Library

common

Contains shared components

cpri

Contains the CPRI IP core files

src

Contains the CPRI IP core encrypted lower-level design files

constraints

Contains the Synopsys Design Constraints and Tcl constraints scripts for the CPRI IP core

cus_demo_tb

Contains the demonstration testbenches for the CPRI IP core

You can use Altera’s free OpenCore Plus evaluation feature to evaluate the CPRI IP core in simulation and in hardware before you purchase a license. You must purchase a license for the CPRI IP core only when you are satisfied with its functionality and performance, and you want to take your design to production.

After you purchase a license for the CPRI IP core, you can request a license file from the Altera website at www.altera.com/licensing and install it on your computer. When you request a license file, Altera emails you a license.dat file. If you do not have internet access, contact your local Altera representative.

OpenCore Plus Evaluation

With the Altera free OpenCore Plus evaluation feature, you can perform the following actions:

■ Simulate the behavior of a megafunction (Altera IP core or AMPP

megafunction) in your system using the Quartus II software and Altera-supported VHDL and Verilog HDL simulators

■ Verify the functionality of your design and evaluate its size and speed quickly and

easily

■ Generate time-limited device programming files for designs that include Altera IP

cores

■ Program a device and verify your design in hardware

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

1–10 Chapter 1: About This MegaCore Function

Installation and Licensing

OpenCore Plus Time-Out Behavior

OpenCore Plus hardware evaluation supports the following two operation modes:

■ Untethered—the design runs for a limited time.

■ Tethered—requires a connection between your board and the host computer. If

tethered mode is supported by all megafunctions in a design, the device can operate for a longer time or indefinitely.

All megafunctions in a device time out simultaneously when the most restrictive evaluation time is reached. If there is more than one megafunction in a design, a specific megafunction's time-out behavior might be masked by the time-out behavior of the other megafunctions.

1 For Altera IP cores, the untethered time-out is 1 hour; the tethered time-out value is

indefinite.

Your design stops working after the hardware evaluation time expires.

The CPRI IP core then behaves as if the

reset

and

cpu_reset

signals are asserted: the CPRI link and the CPU interface reset. The transceivers do not reset, because the transceiver quad might be shared with other designs, IP cores, and megafunctions. The CPRI IP core cannot achieve frame synchronization, and cannot participate in further CPRI communication.

f For information about installation and licensing, refer to Altera Software Installation and

Licensing. For information about the OpenCore Plus evaluation feature, refer to AN 320: OpenCore Plus Evaluation of Megafunctions.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

You can customize the CPRI IP core to support a wide variety of applications. You use

MegaWizard Plug-In

Manager Flow

Instantiate MegaCore

In Design

Specify Constraints

Specify Parameters

Generate

MegaCore Function

Compile Design

Program Device

Simulate with

T estbench

Generate

MegaCore Function

the MegaWizard Plug-In Manager in the Quartus II software to parameterize a custom IP core variation in a CPRI parameter editor. The CPRI parameter editor lets you interactively set parameter values and select optional ports.

MegaWizard Plug-In Manager Design Flow

Figure 2–1 shows the stages for creating a system with the CPRI IP core and the

Quartus II software. Each stage is described in detail in subsequent sections.

Figure 2–1. CPRI Design Flow

2. Getting Started

The MegaWizard Plug-In Manager flow allows you to customize the CPRI IP core, and manually integrate the function in your design.

Specifying Parameters

To specify CPRI IP core parameters using the MegaWizard Plug-In Manager, perform the following steps:

1. Create a Quartus II project using the New Project Wizard available from the File

menu.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

2–2 Chapter 2: Getting Started

MegaWizard Plug-In Manager Design Flow

2. Launch the MegaWizard Plug-In Manager from the Tools menu, and follow the

prompts in the MegaWizard Plug-In Manager interface to create a custom CPRI IP core variation.

To select the CPRI IP core, click Installed Plug-Ins > Interfaces > CPRI > CPRI v12.0.

3. Specify the parameters. For details about these parameters, refer to Chapter 3,

Parameter Settings.

As you specify parameters, the CPRI parameter editor displays messages about the variation that your current settings define. If your settings define a variation for which a testbench is automatically generated when the CPRI IP core is generated, an information message tells you the name of the relevant testbench. For more information about the testbenches and the variations that provide them, refer to Chapter 8, Testbenches.

4. Click Finish to generate the CPRI IP core and supporting files.

You might have to wait several minutes for file generation to complete.

5. When you are prompted to generate an example design, turn on Generate

Example Design. You must turn on this option to generate the testbenches described in Chapter 8, Testbenches.

6. Click Generate. Despite the moving progress bar, generation does not progress

until you click this button.

7. If you generate the CPRI IP core instance in a Quartus II project, you are prompted

to add the Quartus II IP File (.qip) to the current Quartus II project. You can also turn on Automatically add Quartus II IP Files to all projects.

The .qip file is generated by the parameter editor, and contains information about the generated IP core. In most cases, the .qip file contains all of the necessary assignments and information required to process the IP core or system in the Quartus II compiler. The parameter editor generates a single .qip file for each IP core.

Generating your custom CPRI IP core variation creates a set of HDL files and simulation models. You can now integrate your custom CPRI IP core variation in your design, simulate, and compile.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 2: Getting Started 2–3

MegaWizard Plug-In Manager Design Flow

When you integrate your CPRI IP core variation in your design, observe the following connection and I/O assignment requirements:

■ In Arria II, Cyclone IV GX, and Stratix IV GX designs:

■ Ensure that you connect the calibration clock (

signal with the appropriate frequency range of 10–125 MHz. The

gxb_cal_blk_clk

) to a clock

cal_blk_clk

ports on other components that use transceivers must be connected to the same clock signal.

■ Add a dynamic reconfiguration block (

altgx_reconfig

) and connect it as

specified in the Arria II Device Handbook, Cyclone IV Device Handbook, or

Stratix IV Device Handbook. This block supports offset cancellation to

compensate for analog voltages offset from required ranges due to process variations. The design compiles without the

altgx_reconfig

block, but it

cannot function correctly in hardware.

■ To support the correct signal connections from the CPRI IP core to the dynamic

reconfiguration block, in the ALTGX MegaWizard Plug-In Manager, on the Reconfiguration Settings tab, turn on Analog controls.

■ In Arria V and Stratix V designs, add an Altera Transceiver Reconfiguration

Controller and connect it as specified in the Altera Transceiver PHY IP Core User

Guide. This block supports offset cancellation to compensate for analog voltages

offset from required ranges due to process variations. The design does not compile without the Altera Transceiver Reconfiguration Controller, but it cannot function correctly in hardware.

Before you compile your system to generate a Programmable Object File (.pof) with which to configure your device, Altera recommends that you create assignments for the high-speed transceiver VCCH settings.

To create assignments for the high-speed transceiver VCCH settings, perform the following steps:

1. In the Quartus II window, on the Assignments menu, click Assignment Editor.

2. In the <<new>> cell in the To column, type the top-level signal name for your

CPRI IP core instance

3. Double-click in the Assignment Name column and click I/O Standard.

4. Double-click in the Val u e column and click your standard (for example, 1.5-V

PCML).

5. In the new <<new>> row, repeat steps 2 to 4 for your CPRI IP core instance

gxb_rxdatain

Simulation Files

Generating a CPRI IP core creates an <instance_name>_sim directory with a subdirectory for each of several different simulators. Each of the vendor-specific directories contains files and scripts to simulate your CPRI IP core with that vendor ’s simulation tools.

The <instance_name>_sim/altera_cpri directory contains the top-level simulation file for your CPRI IP core.

signal.

gxb_txdataout

signal.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

2–4 Chapter 2: Getting Started

MegaWizard Plug-In Manager Design Flow

Generating a CPRI IP core creates a more complex directory structure for Arria V and Stratix V variations than for variations that target other device families, because the Arria V and Stratix V variations instantiate an Altera Deterministic Latency PHY IP core or an Altera Native PHY IP core. In an Arria V or Stratix V variation, your <instance_name>_sim directory contains multiple subdirectories, one for each of the various components in the Arria V or Stratix V CPRI IP core, and individual directories for vendors for three different simulators. Each of the vendor-specific directories contains files and scripts to simulate your CPRI IP core with that vendor ’s simulation tools.

Figure 2–2 shows the directory structure of your CPRI IP core that contains a

Deterministic Latency PHY IP core and generates a VHDL testbench. For information about the CPRI IP core variations that provide a VHDL testbench, refer to “Simulating

the Design”.

Figure 2–2. Generated CPRI IP Core Directory Structure for Most Arria V and Stratix V Variations

Quartus II project working directory

CPRI IP core instance HDL files

The altera_xcvr_det_latency directory contains the files to simulate the Altera Deterministic Latency PHY IP core that is generated as part of your CPRI IP core. It also contains a mentor subdirectory with IEEE encrypted files to simulate the PHY IP core efficiently.

Simulating the Design

During the design process, to check your design quickly, you can simulate your CPRI IP core with any of several Altera-supported EDA simulation tools.

<instance name>_sim

CPRI IP core instance simulation files and scripts

altera_cpri

Contains the CPRI IP core instance top-level simulation file

altera_cpri_instance, altera_merlin_master_translator, altera_merlin_slave_translator, altera_xcvr-det_latency

Contain the CPRI IP core instance lower-level simulation files Vendor-specific directories contain simulation scripts

<instance name>_testbench

Contains the VHDL testbench simulation files

altera_cpri

Contains the lower-level testbench simulation files

f For more information about these tools and how to simulate designs created using the

Quartus II software, refer to the “Simulation” section in volume 3 of the Quartus II Handbook.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 2: Getting Started 2–5

Specifying Constraints

You can simulate your CPRI IP core variation using its IP functional simulation model and VHDL demonstration testbench. The IP functional simulation model, and testbench files for the CPRI IP core variations that support demonstration testbenches, are generated in your project directory when you generate your CPRI IP core. The testbench files include scripts to compile and run the demonstration testbench. The testbench demonstrates how to instantiate a model in a design and includes simple stimuli to control the user interfaces of the CPRI IP core.

1 A Verilog HDL testbench is not generated. If you specify Verilog HDL in the

MegaWizard Plug-In Manager, it generates a Verilog HDL IP functional simulation model for the CPRI IP core. If your CPRI IP core variation is listed in Table 2–1, the corresponding VHDL demonstration testbench is also generated. You can use this model with the VHDL demonstration testbench for simulation using a mixed-language simulator.

For a complete list of models or libraries required to simulate the CPRI IP core, refer to the compile[_<variation>]_<HDL>.do scripts provided with the demonstration testbenches described in Chapter 8, Testbenches.

Not all variations provide demonstration testbenches. To view example scripts and to run a demonstration testbench, you must generate a variation that provides a testbench. Tab le 2– 1 lists the CPRI variations that provide a testbench. Refer to

Chapter 8, Testbenches for information about the specific testbench generated for each

variation in Table 2–1. In addition to the variations specified in Table 8–4 on page 8–7, you generate VHDL testbenches with the corresponding Verilog HDL IP core variations, as shown in Tabl e 2 –1 .

Table 2–1. CPRI IP Core Variations that Provide a Demonstration Testbench

Properties

Common to all

Variations with

Testbench

REC master clocking,

0.6144 Gbps line rate, Include HDLC Block is Off, Enable MAP interface synchronization is Off

f For information about IP functional simulation models, refer to the Simulating Altera

Designs chapter in volume 3 of the Quartus II Handbook.

Specifying Constraints

Altera provides a Synopsys Design Constraints (.sdc) file that you must apply to ensure that the CPRI IP core meets design timing requirements. In most cases the script requires modification for your design. For modification guidelines, refer to

Appendix E, Integrating the CPRI IP Core Timing Constraints in the Full Design.

Device Family

Arria II

Arria V, Stratix V

Cyclone IV GX, Stratix IV GX

Enable

Autorate

Negotiation

Off — On or Off 3

Off — Off 0

Off

Off Off 0

On On 0

Off — On or Off 3

Off — Off 0

On — On 0

Reference

Clock

Frequency

61.44 MHz

Include

MAC Block

On or Off 3

Number of

Antenna-Carrier

Interfaces

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

2–6 Chapter 2: Getting Started

f For information about timing analyzers, refer to the Quartus II Help and the “Timing

Analysis” section in volume 3 of the Quartus II Handbook.

Compiling and Programming the Device

You can use the Start Compilation command on the Processing menu in the Quartus II software to compile your design. After successfully compiling your design, program the targeted Altera device with the Programmer and verify the design in hardware.

1 Before compiling your CPRI IP core or other incomplete CPRI design in the Quartus II

software, you must assign unconnected CPRI IP core signals to virtual pins.

f For information about compiling your design in the Quartus II software, refer to the

Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter in

volume 1 of the Quartus II Handbook. For information about programming an Altera device, refer to the “Device Programming” section in volume 3 of the Quartus II Handbook.

Instantiating Multiple CPRI IP Cores

If you want to instantiate multiple CPRI IP cores in an Arria II, Cyclone IV GX, or Stratix IV GX device, you must observe a few additional requirements.

When your design contains multiple IP cores, you must ensure that the

gxb_cal_blk_clk

requirements for your target device family, and that the instances each have different starting channel numbers.

You must ensure that a single calibration clock source drives the input to each CPRI IP core (or any other megafunction or user logic that uses the ALTGX megafunction).

When you merge multiple CPRI IP cores in a single transceiver block, the same signal must drive megafunctions, Altera IP cores, and user logic that use the ALTGX megafunction.

Multiple CPRI IP cores in a single device must use distinct transceiver channels. You enforce this restriction by specifying different starting channel numbers for the distinct CPRI IP cores. The starting channel number is a parameter whose value you specify for each CPRI IP core in the CPRI parameter editor. Refer to Chapter 3,

Parameter Settings.

To configure multiple CPRI IP cores in a single transceiver block, you must specify in your Quartus Settings File (.qsf) that these CPRI link data lines are configured in the same

GXB_TX_PLL_RECONFIG_GROUP

link

cN_gxb_txdataout

input and

gxb_powerdown

to each of the CPRI IP core variations and other

signals are connected according to the

gxb_cal_blk_clk

, using the following syntax for each outgoing CPRI

set_instance_assignment -name GXB_TX_PLL_RECONFIG_GROUP 1 -to cN_gxb_txdataout

CPRI MegaCore Function June 2012 Altera Corporation User Guide

3. Parameter Settings

You customize the CPRI IP core by specifying parameters in the CPRI parameter editor, which you access from the MegaWizard Plug-In Manager in the Quartus II software.

This chapter describes the parameters and how they affect the behavior of the CPRI IP core. You can modify parameter values to specify the following CPRI IP core properties:

■ Clocking mode—whether this CPRI IP core instance is configured with slave

clocking mode (RE slave) or with master clocking mode (REC or RE master).

■ Line rate.

■ Autorate negotiation—whether this CPRI IP core instance supports the connection

of external logic to implement autorate negotiation.

■ Starting channel number.

■ Depth of the low-level receiver elastic buffer.

■ Transceiver reference clock frequency. This option is available only in Arria V and

Stratix V devices.

■ Ethernet MAC—whether to include an internal Ethernet MAC block or provide an

MII to connect to an external Ethernet module. These two options are mutually exclusive.

■ HDLC block—whether to include an internal HDLC block or not.

■ Number of antenna-carrier interfaces.

■ Whether the antenna-carrier interfaces are clocked by the CPRI IP core clock

cpri_clkout

or by external clocks.

Physical Layer Parameters

This section lists the parameters that affect the configuration of the physical layer of the CPRI IP core.

Operation Mode Parameter

The Operation mode parameter specifies whether the CPRI IP core is configured with slave clocking mode or with master clocking mode. An REC is configured with master clocking mode.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

3–2 Chapter 3: Parameter Settings

Physical Layer Parameters

Line Rate Parameter

The Line rate parameter specifies the line rate on the CPRI link in gigabits per second (Gbps). Ta bl e 3 –1 lists the CPRI line rates that each device family supports. A checkmark indicates a supported variation.

Table 3–1. Device Family Support for CPRI Line Rates

Device Family

or Variant

Arria II GX vvvvv Arria II GZ vvvvvv— Arria V GX vvvvvv— Arria V GT vvvvvvv Cyclone IV GX vvvv——— Stratix IV GX vvvvvv— Stratix V GX vvvvvvv Stratix V GT vvvvvvv

Note to Tab le 3– 1:

(1) If you specify a CPRI line rate of 4.9152 or 6.144 Gbps for a variation that targets an Arria II GX device, your

Quartus II project must target an I3 speed grade device. The parameter editor does not enforce this restriction. However, if you violate this restriction, compilation fails because the design cannot meet timing in hardware.

614.4 1228.8 2457.6 3072.0 4915.2 6144 9830.4

Enable Autorate Negotiation

Autorate negotiation is the process of stepping down from a higher target CPRI line rate to a lower target CPRI line rate if you are unable to establish a link at the higher line rate. If your CPRI IP core has autorate negotiation enabled, and you program it to step down from its highest target CPRI line rate to its lower target CPRI line rates when it does not achieve frame synchronization, your CPRI IP core achieves frame synchronization at the highest possible CPRI line rate in its range of potential line rates, depending on the capability of its CPRI partner.

CPRI Line Rate (Mbps)

(1)

—

For information about the autorate negotiation feature, refer to Appendix B,

Implementing CPRI Link Autorate Negotiation.

In the current release, CPRI IP core variations configured at the CPRI line rate of

9830.4 Mbps that target an Arria V device do not support autorate negotiation.

Turn o n t he Enable auto-rate negotiation parameter to specify that your CPRI IP core supports autorate negotiation. By default, this parameter is turned off.

Transceiver Starting Channel Number

You can specify the starting number for the CPRI IP core transceiver. For a CPRI IP core master, the Master transceiver starting channel number specifies the starting channel number for the transceiver.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 3: Parameter Settings 3–3

Physical Layer Parameters

For a CPRI IP core configured with slave clocking mode, the Slave transmitter starting channel number and Slave receiver starting channel number are two

separate parameters. Both must have values that are starting channel numbers available in your design. The two numbers must be different but the Quartus II software creates an FPGA configuration with a single slave transceiver.

If you instantiate multiple CPRI IP cores on the same device, you must ensure each uses distinct transceiver channels.

These parameters are not available in Arria V and Stratix V devices.

Rx Elastic Buffer Depth

You can specify the depth of the Rx elastic buffer in the CPRI Receiver block. The Receiver buffer depth value is the log are 4 to 8, inclusive.

The default depth of the Rx elastic buffer is 64, specified by the Receiver buffer depth parameter default value of 6. For most systems, the default Rx elastic buffer depth is adequate to handle dispersion, jitter, and wander that can occur on the link while the system is running. However, the parameter is available for cases in which additional depth is required.

of the Rx elastic buffer depth. Allowed values

1 Altera recommends that you set Receiver buffer depth to 4 in CPRI RE slave

variations.

CPRI IP core variations configured at a CPRI line rate of 9830.4 Mbps that target an Arria V GT device do not include an Rx elastic buffer. However, this parameter affects the depth of the RX buffer between the soft PCS and the Altera Transceiver Native PHY IP core, instead. Refer to Figure 4–4 on page 4–7.

f For information about the Altera Transceiver Native PHY IP core, refer to the Altera

Transceiver PHY IP Core User Guide.

The value you specify for Receiver buffer depth is referred to as WIDTH_RX_BUF in this user guide.

For more information about the Rx elastic buffer, refer to “Rx Elastic Buffer” on

page 4–49.

Transceiver Reference Clock Frequency

If your CPRI variation targets an Arria V or a Stratix V device, the Transceiver reference clock frequency parameter is available. Use this parameter to modify the

expected frequency of the CPRI transceiver input reference clock to the frequency of an available clock for your design.

The frequency you specify is an input parameter to the Altera Deterministic Latency PHY IP core that is included in your Arria V or Stratix V CPRI variation. Values available at each CPRI line rate are the reference clock frequencies for which the Deterministic Latency PHY IP core supports the target CPRI line rate. The default value is 122.88 MHz.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

3–4 Chapter 3: Parameter Settings

f For more information about the Altera Deterministic Latency PHY IP core, refer to the

Altera Transceiver PHY IP Core User Guide.

Data Link Layer Parameters

This section lists the parameter that affects the configuration of the data link layer of the CPRI IP core.

Include MAC Block

Turn o n t he Include MAC block parameter to specify that your CPRI IP core includes an internal Ethernet MAC block. By default, this parameter is not turned on. If this parameter is not turned on, the CPRI IP core implements the media-independent (MI) interface (MII) to your own external Ethernet MAC, instead.

If this parameter is not turned on in your CPRI IP core, your application cannot access the Ethernet registers. Attempts to access these registers read zeroes and do not write successfully, as for a reserved register address.

For information about the internal Ethernet MAC block, refer to “Accessing the

Ethernet Channel” on page 4–42.

For information about the MII, refer to “Media Independent Interface to an External

Ethernet Block” on page 4–34.

Include HDLC Block

Turn o n t he Include HDLC block parameter to specify that your CPRI IP core includes an internal HDLC block. By default, this parameter is not turned on.

If this parameter is not turned on in your CPRI IP core, your application cannot access the HDLC registers. Attempts to access these registers read zeroes and do not write successfully, as for a reserved register address.

Application Layer Parameters

This section lists the parameters that affect the configuration of the application layer of the CPRI IP core.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 3: Parameter Settings 3–5

Application Layer Parameters

Mapping Mode

The Mapping mode(s) parameter specifies whether your CPRI IP core MAP interface supports a programmable AxC mapping mode or is configured with a specific mapping mode. Tab le 3– 2 lists the supported values.

Table 3–2. MAP Interface AxC Mapping Mode Support

Value Description

If you select this value, you configure a CPRI IP core which you can program dynamically to be in any mapping mode. In this case, you determine the current

All

Basic

Advanced 1

Advanced 2

Advanced 3

mapping mode for your CPRI IP core by programming the

CPRI_MAP_CONFIG

For backward compatibility with previous releases of the CPRI IP core, the value of All is the default value for this parameter.

For information about the

map_mode

page 7–14.

Your CPRI IP core MAP interface is configured to function in basic mapping mode only. This mapping mode has the following features:

■ Conforms to the description in Sections 4.2.7.2.2 and 4.2.7.2.3 of the CPRI

Specification V4.2 Interface Specification.

■ Supports communication that complies with the LTE/E-UTRA or UMTS/WCDMA

standard.

For information about the basic mapping mode in the CPRI IP core, refer to “MAP

Interface Mapping Modes” on page 4–11.

Your CPRI IP core MAP interface is configured in a single AxC mapping mode only, a mode that has the following features:

■ Conforms to Method 1: IQ Sample Based described in Section 4.2.7.2.5 of the

CPRI Specification V4.2 Interface Specification.

■ Supports communication that complies with the WiMAX standard.

For information about this AxC mapping mode, refer to Appendix C, Advanced AxC

Mapping Modes.

Your CPRI IP core MAP interface is configured in a single AxC mapping mode only, a mode that has the following features:

■ Conforms to Method 3: Backward Compatible described in Section 4.2.7.2.4 of

the CPRI Specification V4.2 Interface Specification.

■ Supports communication that complies with the WiMAX or LTE/E-UTRA

standard.

For information about this AxC mapping mode, refer to Appendix C, Advanced AxC

Mapping Modes.

Your CPRI IP core MAP interface is configured in a single AxC mapping mode only, a legacy mode that has the following features:

■ Conforms to Method 1: IQ Sample Based described in Section 4.2.7.2.5 of the

CPRI Specification V4.2 Interface Specification.

■ Supports communication that complies with the LTE/E-UTRA standard.

This mode does not support 16-bit wide IQ data samples. Refer to Table 7–31 on

page 7–14.

For information about this AxC mapping mode, refer to Appendix C, Advanced AxC

Mapping Modes.

map_mode

field of the

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

3–6 Chapter 3: Parameter Settings

Application Layer Parameters

Number of Antenna-Carrier Interfaces

The Number of antenna/carrier interfaces parameter specifies the number of antenna-carrier interfaces, or data channels, in your CPRI IP core. The supported values are 0 to 24. Set this parameter to the maximum number of data channels you expect your CPRI IP core to use at the same time.

If you set this parameter to zero, your CPRI IP core does not implement the CPRI MAP interface. For example, you might use this option if your CPRI IP core passes IQ data samples through the AUX interface to an external custom mapping function that you provide.

You can specify in software that some of the antenna-carrier interfaces that you configure in your CPRI IP core are not active. This feature allows you to change the number of active and enabled data channels dynamically.

The combination of CPRI IP core line rate, sampling width, and sampling rate restricts the number of active antenna-carrier interfaces your CPRI IP core can support. For example, if your CPRI IP core operates at line rate 3.072 Gbps, it can support as many as 20 active antenna-carrier interfaces, but if your CPRI IP core operates at line rate

1.2288 Gbps, it can support a maximum of eight active antenna-carrier interfaces. For details, refer to Tab le 4– 4 and Table 4–5 on page 4–14.

1 The software configuration feature allows you to modify the number of active

antenna-carrier interfaces; if you modify this number, you must keep in mind the restrictions for your current CPRI line rate. Otherwise, data is dropped in the mapping to and from the individual antenna-carrier interfaces.

If you set the lower than the value you specify for Number of antenna/carrier interfaces, then the first N data channels are active and the others are not. In addition, for each antenna-carrier interface you can use the relevant

CPRI_IQ_RX_BUF_CONTROL CPRI_IQ_TX_BUF_CONTROL

direction. A data channel must be configured, active, and enabled to function. If it is configured and active but not enabled, data to and from it is ignored.

The value you specify for Number of antenna/carrier interfaces is referred to as N_MAP in this user guide.

For more information about the antenna-carrier interfaces in a CPRI IP core, refer to

“MAP Interface” on page 4–10.

map_ac

field of the

CPRI_MAP_CNT_CONFIG

map_rx_enable bit

map_tx_enable

bit of the

Enable Internally-Clocked Synchronization Mode

If you configure one or more antenna-carrier interfaces, the option to Enable MAP interface synchronization with core clock is available. If you turn on this option, both

the MAP receiver interface and the MAP transmitter interface are clocked with the CPRI IP core internal clock, are clocked with individual Rx and Tx clocks for each antenna-carrier interface.

cpri_clkout

. If you turn off this option, these interfaces

of the

If you turn on this option, the CPRI IP core coordinates communication on these interfaces in the internally-clocked synchronization mode. Turning on this option simplifies synchronization of data transfers to and from the antenna-carrier interfaces.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 3: Parameter Settings 3–7

Application Layer Parameters

The Boolean value you specify for Enable MAP interface synchronization with core clock is referred to as SYNC_MAP in this user guide. Tab le 3 –3 shows the

correspondence between the parameter, the MAP interface synchronization mode, and the clocks that clock the antenna-carrier interfaces.

Table 3–3. Meaning of Enable Map Interface synchronization with core clock Parameter

Enable MAP interface

synchronization with core clock

On 1 Internally-clocked mode

Off 0

For more information about these clocks, refer to “Clocking Structure” on page 4–3. For more information about the synchronization modes for the Rx and Tx MAP interfaces, and how they vary depending on your selection of this option, refer to

“MAP Interface” on page 4–10.

SYNC_MAP

MAP Interface

Synchronization Mode

Synchronous buffer or

FIFO mode

Clocks for Antenna-Carrier Interfaces

cpri_clkout mapN_rx_clk, mapN_tx_clk

antenna-carrier interfaces

, for

= 1 ... (N_MAP – 1)

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

3–8 Chapter 3: Parameter Settings

Application Layer Parameters

CPRI MegaCore Function June 2012 Altera Corporation User Guide

4. Functional Description

The CPRI protocol interface complies with the CPRI Specification V4.2. The specification divides the protocol into a two-layer hierarchy: a physical layer (layer 1) and a data link layer (layer 2). The specification describes the following three communication planes:

■ User data

■ Control and management (C&M)

■ Timing synchronization information

f More detailed information about the CPRI specification is available from the CPRI

website at www.cpri.info.

The Altera CPRI IP core implements layer 1 and layer 2 of the specification in the CPRI protocol interface module. This chapter describes the individual data and control interfaces available to you and how the data on these interfaces is loaded and unloaded from the CPRI frame.

This chapter contains the following sections:

■ Architecture Overview

■ Clocking Structure

■ Reset Requirements

■ MAP Interface

■ Auxiliary Interface

■ Media Independent Interface to an External Ethernet Block

■ CPU Interface

■ Accessing the Hyperframe Control Words

■ Accessing the Ethernet Channel

■ Accessing the HDLC Channel

■ CPRI Protocol Interface Layer (Physical Layer)

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–2 Chapter 4: Functional Description

AxC

(1)

AxC

(1)

...

CPU Interface Module

Registers

tx_dataout

AUX Interface

IQ Data Channels

(Optional) CPU InterfaceMI Interface

Transmitter

Transceiver

Transmitter

rx_datain

CPRI LinkCPRI Link

Receiver

Transceiver

Receiver

Physical Layer

Ethernet

(2)

MII

(2)

VSS/

Inband/

Alarms

HDLC

(3)

Control and Management

Module

CPRI MAP

Interface Module

RX Delay Measurement

and TX Calibration

Block

AUX

Module

Architecture Overview

Figure 4–1 shows the main blocks of the CPRI IP core.

Figure 4–1. CPRI IP Core Block Diagram

Notes to Figure 4–1:

(1) You can configure your CPRI IP core with zero, one, or multiple IQ data channels. (2) You can configure your CPRI IP core with an Ethernet MAC block or an MII block. The two options are mutually exclusive. (3) You can configure your CPRI IP core with or without a High-Level Data Link Controller (HDLC) block.

CPRI MegaCore Function June 2012 Altera Corporation

The Altera CPRI IP core supports the following interfaces:

■ MAP Interface

■ Auxiliary Interface

■ Media Independent Interface to an External Ethernet Block

■ CPU Interface

■ CPRI link interface described in CPRI Protocol Interface Layer (Physical Layer)

Information about the signals on the individual interfaces is available in the following sections and in Chapter 6, Signals.

The following sections describe the individual interfaces and clocks.

User Guide

Chapter 4: Functional Description 4–3

Clocking Structure

The CPRI IP core has a variable number of clock domains. The clock domains in your CPRI IP core variation depend on the following factors:

■ Number of antenna-carrier interfaces.

■ Whether the MII is configured.

■ Whether the antenna-carrier interfaces are clocked internally. Refer to “Enable

Internally-Clocked Synchronization Mode” on page 3–6.

■ Targe t d e vi ce fa mi ly.

■ In one case, different CPRI line rates.

The input clock frequency requirements depend on the target device family and CPRI line rate. Refer to Table 4–2 on page 4–8 for these requirements.

You can configure a CPRI IP core in master or slave clocking mode, as described in

“Operation Mode Parameter” on page 3–1. REC configurations and RE master

configurations use master clocking mode, and RE slave configurations use slave clocking mode. Your design must handle some of the transceiver input clocks differently in the two different clocking modes.

Tab le 4– 1 describes the individual clocks. The clocking diagrams in Figure 4–2 on page 4–5 to Figure 4–4 on page 4–7 show the clocks and clock domain boundaries. Table 4–2 on page 4–8 lists the clock frequencies for the different CPRI IP core

variations.

CPRI IP Core Clocks

Tab le 4– 1 describes the clock domains in the CPRI IP core.

For more information about these clocks, including driver requirements, refer to

Chapter 6, Signals. For expected input clock frequencies refer to Chapter 6, Signals

and to Table 4–2 on page 4–8.

Table 4–1. CPRI IP Core Clocks (Part 1 of 2)

Clock Name Direction

cpri_clkout

mapN_tx_clk

for N in

..(N_MAP–1)

mapN_rx_clk

for N in

..(N_MAP–1)

Output

Input

Configuration

Requirements

Present in all CPRI IP cores

Present in variations configured with N_MAP > 0 antenna-carrier interfaces and with Enable MAP

interface synchronization with core clock

turned off

Description

Main clock for the CPRI IP core. The CPRI IP core derives this clock from the transceiver transmit PLL, and the frequency of this clock depends on the CPRI line rate. For more information refer to “CPRI

Communication Link Line Rates” on page 4–7.

Expected rate of received data on antenna-carrier interface N. The frequency of this clock is the sample rate on the incoming antenna-carrier interface. For more information about data channel sample rates, refer to Table 4–4 and Table 4–5 on page 4–14.

Clocks the transmissions of antenna-carrier interface N. The frequency of this clock is the sample rate on the outgoing antenna-carrier interface. For more information about data channel sample rates, refer to Table 4–4 and Table 4–5 on page 4–14.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–4 Chapter 4: Functional Description

Clocking Structure

Table 4–1. CPRI IP Core Clocks (Part 2 of 2)

Clock Name Direction

clk_ex_delay

cpri_mii_txclk

cpri_mii_rxclk

cpu_clk

gxb_refclk

gxb_cal_blk_clk

reconfig_clk

gxb_pll_inclk

pll_clkout

usr_pma_clk

usr_clk

Input

Output

Input

Output

Input

Configuration Requirements

Present in all CPRI IP cores

Present in variations configured with an MI interface

Present in all CPRI IP cores

Not present in variations that target an Arria V or Stratix V device

Present in all CPRI IP cores

Present in variations configured at

9830.4 Gbps that target an Arria V GT device

Description

Clock for extended delay measurement. For more information refer to

“Extended Rx Delay Measurement” on page D–5.

Clocks the MII transmitter module. This clock has the same frequency as the

cpri_clkout

clock. The frequency depends on the CPRI line data rate. Refer to “CPRI Communication Link Line Rates”

on page 4–7.

Clocks the MII receiver module. This clock has the same frequency as the

cpri_clkout

clock. The frequency depends on the CPRI line data rate. Refer to “CPRI Communication Link Line Rates” on

page 4–7.

Clock that controls the input to the CPU interface of the CPRI IP core and drives the CPU interface. Assumed to be asynchronous with the

cpri_clkout

clock. The maximum frequency is constrained by f

MAX

and can vary based on the device family and speed grade.

Reference clock for the transceiver PLLs. In master clocking mode, this clock drives both the receiver PLL and the transmitter PLL in the transceiver. In slave clocking mode, this clock drives the receiver PLL.

Transceiver calibration-block clock.

Transceiver dynamic reconfiguration block clock.

Input clock to the transmitter PLL in a CPRI IP core configured in slave clocking mode. If the CPRI IP core is configured in master clocking mode, it does not use this clock. In master clocking mode, you must tie this input low.

Generated from transceiver clock data recovery circuit. Intended to connect to an external PLL for jitter clean-up in slave clocking mode.

Extra clock signal required to drive the PMA in these CPRI IP core variations. Refer to Table 6–15 on page 6–17 for driver frequency and synchronization requirements.

Extra clock signal required to drive the PCS in these CPRI IP core variations. Refer to Table 6–15 on page 6–17 for driver frequency and synchronization requirements.

Clock Diagrams for the CPRI IP Core

Figure 4–2 and Figure 4–3 show the clocking schemes for CPRI IP cores configured as

RE slaves, RE masters, and REC masters that do not target an Arria V GT device or that are not configured with a CPRI line rate of 9830.4 Mbps.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–5

Clocking Structure

Figure 4–4 on page 4–7 shows the clocking schemes for CPRI IP cores configured as

RE slaves, RE masters, and REC masters with a CPRI line rate of 9830.4 Mbps that target an Arria V GT device. These variations have no clock divider and no Tx elastic buffer or Rx elastic buffer. However, they require two additional synchronized input clocks,

usr_clk,

usr_pma_clk

, which you must drive at the frequency of 122.88 MHz, and

which you must drive at the frequency of 245.76 MHz. Recall that these

variations do not support autorate negotiation.

Clock Diagrams for Most CPRI IP Core Variations

Figure 4–2 shows the clock diagram for a CPRI IP core configured as an RE slave,

unless the IP core is configured with CPRI line rate 9.830.4 Mbps and targets an Arria V GT device.

Figure 4–2. CPRI IP Core Slave Clocking Except for Arria V GT 9.8 Gbps Variations

gxb_refclk

Transceiver

CDR

tx_clkout

rx_clkout

gxb_pll_inclkpll_clkout

Clean-Up PLL

Clock

Divider

(1)

cpri_clkout

clk_ex_delay

Tx Elastic

Sync Buffer

CPRI TX

CPRI RX

Rx Elastic

Sync Buffer

CPRI MegaCore Function

cpri_clkout

Clock

Domain

CPRI Tx

MAP

Interface

FIFO

Buffer

MII Interface

CPU

Interface

FIFO

Buffer

CPRI Rx

MAP

Interface

mapXX_tx_clk

cpri_mii_txclk

cpri_mii_rxclk

cpu_clk

mapXX_rx_clk

Note to Table 4–2:

(1) The clock divider factor depends on the device family. In device families with a factor of 1, the divider is not configured. Table 4–15 on page 4–53

lists the datapath width and clock divider by device family.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–6 Chapter 4: Functional Description

Transceiver

CPRI TX

MII Interface

CPU

Interface

Rx Elastic

Sync Buffer

Tx Elastic

Sync Buffer

CPRI RX

CDR

FIFO

Buffer

CPRI MegaCore Function

Clock

Divider

(1)

cpu_clk

gxb_pll_inclkpll_clkout

tx_clkout

cpri_clkout

Clock

Domain

rx_clkout

gxb_refclk

mapXX_tx_clk

clk_ex_delay

FIFO

Buffer

mapXX_rx_clk

CPRI Rx

MAP

Interface

CPRI Tx

MAP

Interface

cpri_mii_txclk

cpri_mii_rxclk

Clocking Structure

Figure 4–3 shows the clock diagram for a CPRI IP core configured as an REC master

or as an RE master, unless the IP core is configured with CPRI line rate 9830.4 Mbps and targets an Arria V GT device.

Figure 4–3. CPRI IP Core Master Clocking Except for Arria V GT 9.8 Gbps Variations

Note to Table 4–3:

(1) The clock divider factor depends on the device family. In device families with a factor of 1, the divider is not configured. Table 4–15 on page 4–53

lists the datapath width and clock divider by device family.

Clock Diagram for CPRI IP Core Arria V GT Variations at 9830.4 Mbps

CPRI IP core variations with a CPRI line rate of 9830.4 Mbps that target an Arria V GT device have a different clocking scheme. These variations have no clock divider, and have neither an RX elastic buffer nor a TX elastic buffer. They use two additional input clock signals, requirements for these two input clock signals.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

usr_clk

and

usr_pma_clk

. Table 6–15 on page 6–17 describes the

Chapter 4: Functional Description 4–7

Transceiver

CPRI TX

MII Interface

CPU

Interface

CPRI RX

CDR

FIFO

Buffer

CPRI MegaCore Function

cpu_clk

usr_clk

pll_clkout

cpri_clkout

Clock

Domain

rx_clkout

gxb_refclk

mapXX_tx

usr_pma_clk

FIFO

Buffer

mapXX_rx

CPRI Rx

MAP

Interface

CPRI Tx

MAP

Interface

cpri_mii_tx

cpri_mii_rx

Clean-Up PLL

gxb_pll_inclk

clk_ex_delay

Clocking Structure

Figure 4–4 shows the clocking scheme for a CPRI IP core with a CPRI line rate of

9830.4 Mbps that targets an Arria V GT device. The figure notes describe the differences between the input clock requirements for the REC and RE master variations, which are configured in master clocking mode, and the input clock requirements for the RE slave variations, which are configured in slave clocking mode.

Figure 4–4. CPRI IP Core Clocking in Arria V GT 9.8 Gbps Variations

(1),(2),(3)

Notes to Figure 4–4:

(1) The cleanup PLL is relevant only for variations configured in slave clocking mode. (2) In variations configured in slave clocking mode, the

usr_pma_clk

input clocks must be driven by a common source from the

usr_clk

and

cleanup PLL. For additional constraints these clocks require, refer to Table 6–15 on page 6–17.

gxb_pll_inclk

(3) In variations configured in master clocking mode, you must tie the

CPRI Communication Link Line Rates

June 2012 Altera Corporation CPRI MegaCore Function

The CPRI specification specifies line rates of n × 614.4 Mbps for various values of n. The CPRI IP core supports different ranges of line rates in different device families.

Table 3–1 on page 3–2 lists the CPRI line rate support available in the different device

families.

input signal low.

User Guide

4–8 Chapter 4: Functional Description

Clocking Structure

Tab le 4– 2 shows the relationship between line rates, default transceiver reference

clock ( clock (

gxb_refclk cpri_clkout

) rates, parallel recovered clock (

) rates.

pll_clkout

) rates, and internal

Table 4–2. CPRI Link Line Rates and Clock Rates for CPRI MegaCore Function

(1)

Clock Frequency (MHz)

Line Rate

(Mbps)

Default gxb_refclk Frequency

(If line rate is supported)

Arria II GX

Arria II GZ

and

Cyclone IV GX

Devices

Stratix IV GX

Devices

and

Arria V

and

Stratix V

Devices

cpri_clkout

Frequency

(If line rate is

supported)

Arria II GX and

Cyclone IV GX

pll_clkout Frequency

(If line rate is supported)

Arria II GZ,

Arria V, and

Devices

Stratix IV GX

Stratix V

Devices

614.4 61.44 61.44 122.88 15.36 61.44 61.44 61.44

1228.8 61.44 61.44 122.88 30.72 61.44 30.72 30.72

2457.6 122.88 61.44 122.88 61.44 122.88 61.44 61.44

3072 153.60 76.80 122.88 76.80 153.60 76.80 76.80

(2)

4915.2

(2)

6144

(3)

9830.4

Notes to Table 4–2:

(1) In this table, device families can be grouped with other device families that do not support all of the same CPRI line rates. The values apply only

for supported CPRI line rates for each device family. (2) The CPRI IP core does not support CPRI line rates 4915.2 Mbps and 6144 Mbps in variations that target Cyclone IV GX devices. (3) The CPRI IP core supports CPRI line rate 9830.4 Mbps in variations that target Stratix V (GX or GT) and Arria V GT devices. The CPRI IP core

does not support CPRI line rate 9830.4 Mbps for any other devices, including Arria V GX devices.

245.76 122.88 122.88 122.88 245.76 122.88 122.88

307.20 153.60 122.88 153.60 307.20 153.60 153.60

— — 122.88 245.76 — 122.88 245.76

cpri_clkout

The

frequency depends only on the CPRI line rate. The

pll_clkout

frequency depends on the CPRI line rate and on the datapath width through the transceiver, except in Arria V and Stratix V devices. The datapath width is determined by device family, as shown in Table 4–15 on page 4–53.

The

gxb_refclk

Altera allows you to program the transceiver to work with any of a set of

clock is the incoming reference clock for the device transceiver’s PLL.

gxb_refclk

frequencies that the PLL in the transceiver can convert to the required internal clock speed for the CPRI IP core line rate. The parameter editor in which you configure the

gxb_refclk

frequency depends on the target device family for your CPRI IP core

variation.

When you generate a CPRI IP core variation that targets an Arria II, Cyclone IV GX, or Stratix IV GX device, you generate an ALTGX megafunction with specific default settings. These default transceiver settings configure a transceiver that works correctly with the CPRI IP core when the input

gxb_refclk

clock has the frequency shown in Tab le 4– 2. However, you can edit the ALTGX megafunction instance to specify a different example, to enable you to use an existing clock in your system as the

gxb_refclk

frequency that is more convenient for your design, for

gxb_refclk

reference clock.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–9

Reset Requirements

When you generate a CPRI IP core variation that targets an Arria V or Stratix V device, you generate an Altera Deterministic Latency PHY IP core or Altera Native PHY IP core with specific default settings. However, you set the

gxb_refclk

frequency in the CPRI parameter editor. As described in Chapter 3, Parameter

Settings, for these target devices the CPRI parameter editor provides a list of potential

transceiver reference clock frequencies from which you select the frequency that is most convenient for your design.

Reset Requirements

The CPRI IP core has multiple independent reset signals.To reset the CPRI IP core completely, you must assert all the reset signals.

You can assert all reset signals asynchronously to any clock. However, each reset signal must be asserted for at least one full clock period of a specific clock, and be deasserted synchronously to the rising edge of that clock. For example, the CPU interface reset signal,

Tab le 4– 3 lists the reset signals and their corresponding clock domains.

Table 4–3. Reset Signals and Corresponding Clock Domains

cpu_reset

, must be deasserted on the rising edge of

cpu_clk

Reset Signal Clock Domain Description

reset reconfig_clk

gxb_powerdown

reset_ex_delay clk_ex_delay config_reset cpri_clkout cpu_reset cpu_clk

mapN_rx_reset mapN_rx_clk

mapN_tx_reset mapN_tx_clk

—

Resets the CPRI protocol interface. Drives the reset controller.

Powers down and resets the high-speed transceiver block. For setup and hold times, refer to the relevant device handbook. This signal is not present in CPRI IP core variations that target an Arria V or Stratix V device.

Resets the extended delay measurement block.

Resets the registers to their default values.

Resets the CPU interface.

Resets the MAP Channel N receiver block in FIFO or synchronous buffer MAP synchronization mode.

Resets the MAP Channel N transmitter block in FIFO or synchronous buffer MAP synchronization mode.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–10 Chapter 4: Functional Description

DDQ

rstrst

clk

rst

reset

CPRI

MegaCore

Function

MAP Interface

You must implement logic to ensure the minimal hold time and synchronous deassertion of each reset input signal to the CPRI IP core. Figure 4–5 shows a circuit that ensures these conditions for one reset signal.

Figure 4–5. Circuit to Ensure Synchronous Deassertion of Reset Signal

For more information about the requirements for reset signals, refer to Chapter 6,

Signals.

The CPRI IP core has a dedicated reset control module to enforce the specific reset requirements of the high-speed transceiver module. This reset controller generates the recommended reset sequence for the transceiver. The

reset

signal controls the reset

control module.

MAP Interface

f For information about the Avalon-ST interface, refer to Avalon Interface Specifications.

In Arria V and Stratix V devices, the Altera Deterministic Latency PHY IP core or Altera Native PHY IP core that is generated with the CPRI IP core implements the reset controller. In earlier device families, the reset control module is internal to the CPRI IP core, but external to the ALTGX megafunction instance generated with the CPRI IP core.

After reset, your software must perform link synchronization and other initialization tasks. For information about the required initialization sequence following CPRI IP core reset, refer to Appendix A, Initialization Sequence.

The CPRI IP core MAP interface comprises the individual antenna-carrier interfaces, or data channels, through which the CPRI IP core transfers IQ sample data to and from the RF implementation. The MAP interface is implemented as an incoming and an outgoing Avalon-ST interface. The Avalon-ST interface provides a standard, flexible, and modular protocol for data transfers from a source interface to a sink interface.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–11

MAP Interface

The CPRI IP core communicates with the RF implementations (antenna-carriers) through multiple AxC interfaces, or data channels. A CPRI IP core configured with a MAP interface module can have as many as 24 data channels, and as few as one data channel. If a CPRI IP core is configured with zero data channels, it does not have a MAP interface module. The Number of antenna/carrier interfaces value you set in the parameter editor determines the number of channels in your CPRI IP core configuration. Each data channel communicates with the corresponding RF implementation using two 32-bit Avalon-ST interfaces, one interface for incoming communication and one interface for outgoing communication.

The MAP interface module controls transmission and reception of data on the AxC interfaces.

This section contains the following topics:

■ MAP Interface Mapping Modes

■ MAP Receiver Interface

■ MAP Transmitter Interface

MAP Interface Mapping Modes

The CPRI IP core supports basic and advanced MAP interface mapping modes.

In the basic mapping mode, all of the AxC interfaces use the same sample rate and sample width, and the uplink and downlink sample rates are identical.

In the advanced mapping modes, different data channels can use different sample rates, and the sample rates need not be integer multiples of 3.84 MHz. However, all data channels use the same sample width.

If you select All as the value for Mapping mode(s) in the CPRI parameter editor, the

map_mode

field of the

CPRI_MAP_CONFIG

register determines the mapping mode your CPRI IP core implements currently. Otherwise, the value you specify for this parameter determines the single mapping mode your CPRI IP core implements.

The CPRI IP core supports the following MAP interface mapping modes:

■ Basic mapping mode—This mode is programmed with the value of 2’b00 in the

map_mode

■ Advanced 1—This mode is programmed with the value of 2’b01 in the

map_mode

■ Advanced 2—This mode is programmed with the value of 2’b10 in the

map_mode

■ Advanced 3—This mode is programmed with the value of 2’b11 in the

map_mode

Basic AxC Mapping Mode

The basic mapping mode supports the LTE/E-UTRA and UMTS/WCDMA standards. This mapping mode is implemented when you configure and program your CPRI IP core in either of the following ways:

■ If you select Basic as the value for Mapping mode(s) in the CPRI parameter editor.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–12 Chapter 4: Functional Description

Control

Words

AxC

Container

AxC

Container

...

AxC

Container

map_ac

Reserved

Bits

IQ Data Block

Basic Frame

AxC

Interface

Data

AxC

Interface

Data

AxC

Interface

map_ac

Data

...

Data Word 1

Data Word 2

Data Word

map_n_ac

...

Data Word 1

Data Word 2

Data Word

map_n_ac

...

Data Word 1

Data Word 2

Data Word

map_n_ac

...

■ If you select All as the value for Mapping mode(s) in the CPRI parameter editor

and you program the

map_mode

field of the

CPRI_MAP_CONFIG

MAP Interface

value of 2’b00.

In this basic mapping mode, all of the AxC interfaces use the same sample rate and sample width. The CPRI IP core supports sample rates of 3.84 × 10

30.72 × 10

(3.84 × 106× 8) samples per second, in increments of 3.84 × 106, and sample

widths of 15 bits and 16 bits. The uplink and downlink sample rates are identical.

In this mode, the number of active data channels, that is, those that have a corresponding AxC container in the IQ data block of each basic frame. This number must be less than or equal to the N_MAP value you selected for Number of antenna/carrier interfaces in the parameter editor, which is the number of channels configured in the CPRI IP core instance. The oversampling factor for the data channels. This value is an integer from 1 to 8. The sample rate—number of samples per second—is the product of 3.84 × 10 oversampling factor.

In the basic mapping mode, AxC containers are packed in the IQ data block in the packed position (Option 1) illustrated in Section 4.2.7.2.3 of the CPRI V4.2 Specification. Figure 4–6 shows how the AxC containers map to the individual active data channels. The oversampling factor is the number of 32-bit data words in each AxC container.

Figure 4–6. CPRI Basic Mapping Mode

map_ac

map_n_ac

field of the

CPRI_MAP_CNT_CONFIG

through

and the

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–13

MAP Interface

1 The CPRI IP core does not support AxC interface reordering. When the value of

map_ac

is less than N_MAP, the first

map_ac

AxC interfaces, of the existing N_MAP interfaces, are active. Note that an active AxC interface transmits and receives data on its data channel based on the values of the relevant

CPRI_IQ_RX_BUF_CONTROL CPRI_IQ_TX_BUF_CONTROL

map_rx_enable

map_tx_enable

bit of the

disabled channel is ignored, and an incoming AxC container designated from a disabled channel is ignored.

The

map_15bit_mode

field of the

CPRI_MAP_CONFIG

register specifies the sample width. The sample width is the number of significant bits —15 or 16—in each 16-bit half (originally, I- or Q-sample) of the 32-bit data word on the Avalon-ST data channel. In 15-bit mode, the least significant bit in each half of the 32-bit word is ignored when received from the data channel on input signal when transmitted on the data channel in output signal

mapN_tx_data[31:0]

mapN_rx_data[31:0]

, and is set to 0

. Therefore, bit 15 and bit 31 of the data word correspond to bit 14 of the I and Q samples, respectively; bit 1 and bit 17 of the data word correspond to bit 0 of the I and Q samples, respectively; and bits 0 and 16 of the data word are ignored. In 16-bit mode, bit 15 and bit 31 of the data word correspond to bit 15 of the I and Q samples, respectively, and bit 0 and bit 16 of the data word correspond to bit 0 of the I and Q samples, respectively. Figure 4–7 shows the bit correspondence for both sample widths.

Figure 4–7. Bit Correspondence Between IQ Sample and 32-Bit Avalon-ST Data

16-Bit Width IQ Sample:

Q: I: 15 1 0 15 2 1 0

Avalon-ST Data Word in AxC Container:

31 17 16 15 2 1 0

15-Bit Width IQ Sample:

Q: I: 14 0 14 210

You set the oversampling factor to match the frequency of your active data channels. The CPRI line rate determines the number of bits in the IQ data block of each basic frame. If your CPRI IP core has a high line rate and a low oversampling factor, it can accommodate a larger number of active data channels than if the line rate were lower or the oversampling factor higher.

In 15-bit mode, inside the CPRI IP core, bits 0 and 16 of the Avalon-ST data are absent from the compact IQ data word representation. Therefore, despite the fact that in 15-bit mode the IQ data goes out on the data channel in 32-bit words, formatted as

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–14 Chapter 4: Functional Description

MAP Interface

shown in Figure 4–7, the maximum number of active data channels is higher in 15-bit mode. Table 4–4 shows the correspondence between these frequency factors in 16-bit mode, and Table 4–5 shows the correspondence between these factors in 15-bit mode.

Table 4–4. Maximum Number of Active Data Channels in 16-Bit Mode

Maximum Number of Active Data Channels in 16-Bit Mode

CPRI

Line Rate

(Mbps)

Number of Bits

IQ Data Block

Data Channel Bandwidth LTE (MHz)

Sample Rate

Sample/Sec)

(10

2.5 5 10 15 20

3.84 7.68 15.36 23.04 30.72

614.4 120 3 1 — — —

1228.8 240 7321—

2456.7 480 15 7321

3072 600 189432

4915.2 960 30

6144 1200 37

9830.4 1920 60

Note to Table 4–4:

(1) The maximum number of data channels supported by the CPRI IP core is 24. The numbers in the table that are larger than 24 are hypothetical;

the CPRI IP core cannot implement them.

(1)

15753

18964

(1)

15 10 7

Table 4–5. Maximum Number of Active Data Channels in 15-Bit Mode

Maximum Number of Active Data Channels in 15-Bit Mode

CPRI

Line Rate

(Mbps)

Number of Bits

IQ Data Block

Data Channel Bandwidth LTE

2.5 5 10 15 20

(MHz)

Sample Rate

Sample/Sec)

(10

3.84 7.68 15.36 23.04 30.72

614.4 120 4 2 1 — —

1228.8 240 84211

2456.7 480 16 8422

3072 600 20 10 5 3 2

4915.2 960 32

6144 1200 40

9830.4 1920 64

Note to Table 4–5:

(1) The maximum number of data channels supported by the CPRI IP core is 24. The numbers in the table that are larger than 24 are hypothetical;

the CPRI IP core cannot implement them.

(1)

16854

20 10 6 5

(1)

16 10 8

In 16-bit mode, the total number of bits in all the AxC containers in a basic frame is

2 × 16 ×

map_n_ac

map_ac

In 15-bit mode, the total number of bits in all the AxC containers in a basic frame is

2 × 15 ×

CPRI MegaCore Function June 2012 Altera Corporation User Guide

map_n_ac

map_ac

Chapter 4: Functional Description 4–15

MAP Interface

This value must be no larger than the number of bits in the IQ data block. The number of bits in an IQ data block depends on the CPRI line rate, as shown in Tab le 4– 4 and

Tab le 4– 5.

1 If the combination of CPRI line rate,

map_n_ac

value, and

map_ac

value requires more data bits than the number of data bits that fit in the IQ data block, the data for the first active data channels is transferred correctly, but the data for data channels beyond the number indicated in Tab le 4 –4 or Tab le 4 –5 is not transferred correctly.

The following CPRI IP core registers are ignored in basic mapping mode:

■

CPRI_MAP_TBL_CONFIG

■

CPRI_MAP_TBL_INDEX

■

CPRI_MAP_TBL_RX

■

CPRI_MAP_TBL_TX

Advanced AxC Mapping Modes

The CPRI IP core provides advanced AxC mapping modes to support the following mapping methods from the CPRI V4.2 Specification:

■ Method 1: IQ Sample Based, described in Section 4.2.7.2.5 of the CPRI V4.2

Specification.

■ Method 3: Backward Compatible, described in Section 4.2.7.2.7 of the CPRI V4.2

Specification.

Your CPRI IP core implements one of the advanced AxC mapping modes when you configure and program your CPRI IP core in any of the following ways:

■ If you select Advanced 1, Advanced 2, or Advanced 3 as the value for Mapping

mode(s) in the CPRI parameter editor.

■ If you select All as the value for Mapping mode(s) in the CPRI parameter editor

and you program the value of 2’b01, 2’b10, or 2’b11.

For more information about the advanced AxC mapping modes in the Altera CPRI IP core, refer to Appendix C, Advanced AxC Mapping Modes.

MAP Receiver Interface

The CPRI IP core MAP receiver interface presents the IQ data that the CPRI IP core unloads from the CPRI frame received on the CPRI link. The MAP receiver implements an Avalon-ST interface protocol. Refer to “MAP Receiver Signals” on

page 6–1 for details of the interface communication signals.

map_mode

field of the

CPRI_MAP_CONFIG

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–16 Chapter 4: Functional Description

MAP Interface

The MAP receiver interface presents the IQ data on each antenna-carrier interface according to one of three different synchronization modes. The synchronization mode is determined by your selection in the CPRI parameter editor and by the value you program in the

map_rx_sync_mode

field of the

CPRI_MAP_CONFIG

page 7–14), as shown in Tab le 4– 6.

Table 4–6. MAP Rx Synchronization Mode Determined by CPRI_MAP_CONFIG Register Bits

SYNC_MAP

(1)

map_rx_sync_mode

(register bit [2])

Rx Synchronization Mode

0 0 FIFO mode (page 4–17)

0 1 Synchronous buffer mode (page 4–18)

1—

Notes to Table 4–6:

(1) You determine the value of SYNC_MAP when you generate your CPRI IP core. Refer to Chapter 3, Parameter

Settings.

(2) When SYNC_MAP has the value of 1, the value in the

is ignored.

(2)

map_rx_sync_mode

Internally-clocked mode (page 4–20)

bit of the

CPRI_MAP_CONFIG

Tab le 4 –7 lists the clocks for the AxC interfaces in the different Rx synchronization

modes.

Table 4–7. MAP Rx Interface Clocks Determined by Rx Synchronization Mode

Rx Synchronization Mode AxC Channel Clocks

FIFO mode

Synchronous buffer mode

Internally-clocked mode

Each AxC Rx interface is clocked by its own

mapN_rx_clk

driven by the application.

Every AxC interface is clocked by the CPRI IP core clock,

cpri_clkout

clock

You determine the AxC interface clocks when you turn the Enable MAP interface synchronization with core clock parameter on (SYNC_MAP = 1) or off (SYNC_MAP

= 0) in the CPRI parameter editor before you generate your CPRI IP core.

MAP Receiver Interface Signals in Different Synchronization Modes

The different CPRI IP core MAP synchronization modes use different interface signals. Tab le 4 –8 lists the MAP receiver interface signals used in each of these modes. Table notes indicate the correct interpretation of the different symbols.

(1)

Table 4–8. MAP Receiver Interface Signals by Synchronization Mode

Available in Synchronization Mode

Signal Name Direction

FIFO

map{23…0}_rx_clk map{23…0}_rx_reset map{23…0}_rx_ready map{23…0}_rx_data[31:0] map{23…0}_rx_valid map{23…0}_rx_resync

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Input vv— Input vv—

Input v 1 Output vvv Output v —

Input —

(2)

(Part 1 of 2)

Synchronous

Buffer

(3)

(2)

v —

Internally

Clocked

(2)

(2), (4)

—

(2)

Chapter 4: Functional Description 4–17

MAP Interface

Table 4–8. MAP Receiver Interface Signals by Synchronization Mode

(1)

(Part 2 of 2)

Available in Synchronization Mode

Signal Name Direction

FIFO

map{23…0}_rx_start map{23…0}_rx_status_data

[2:0]

Notes to Table 4–8:

(1) A checkmark indicates the signal is used in a synchronization mode, and a dash indicates the signal is not used in

that synchronization mode.

(2) An entry with a dash indicates a signal that does not participate in the MAP receiver interface communication in

Refer to Table 6–1 on page 6–1 for information about the case that is relevant for each signal. (3) A zero or one indicates the application must hold this input signal low or high, respectively. (4) Altera recommends that you tie the

than leave them floating.

Output —

Output vvv

mapN_rx_ready

signals high or low in your internally-clocked variation, rather

(2)

Synchronous

Buffer

(2)

—

Internally

Clocked

For descriptions of the signals in Ta bl e 4– 8, refer to Table 6–1 on page 6–1 and to the following sections.

MAP Receiver in FIFO Mode

In FIFO mode, each data channel, or AxC interface, is clocked by an application-driven clock

mapN_rx_valid

. Each AxC interface N asserts its data available to send on this data channel—when the buffer level is above the threshold indicated in the

mapN_rx_clk

, and has an output data-available signal,

CPRI_MAP_RX_READY_THR

mapN_rx_valid

signal when it has

For details about the behavior of the individual signals in FIFO mode, refer to “MAP

Receiver Signals” on page 6–1. Figure 4–8 shows the typical behavior of the MAP Rx

signals in this synchronization mode.

Figure 4–8. MAP Receiver Interface in FIFO Mode

mapN_rx_clk

mapN_rx_ready

mapN_rx_valid

mapN_rx_data[31:0]

When the application is ready to receive data on the data channel, it asserts the

mapN_rx_ready

the

mapN_rx_ready

mapN_rx_data[31:0]

signal. While the CPRI IP core asserts the

signal is not asserted, the CPRI IP core holds the data value on

. The application must assert the

mapN Rx buffer overflows, to avoid data corruption. While the

mapN_rx_valid

mapN_rx_ready

signal and

signal before the

signal

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–18 Chapter 4: Functional Description

cpri_clkout

cpri_rx_start

mapN_rx_clk

mapN_rx_ready

mapN_rx_resync

mapN_rx_data[31:0]

MAP Interface

is not yet asserted, the mapN Rx buffer continues to fill. When it overflows, the new data overwrites current data in the mapN Rx buffer. Each mapN Rx buffer is implemented as a circular buffer, so the data is overwritten starting at the current head of the mapN Rx buffer, that is, starting from the initial data not yet sent out on the data channel.

FIFO-based communication is simple but does not allow easy control of buffer delay. The delay through each mapN Rx buffer depends on your programmed threshold value and the application. Data is not sent to a data channel before the buffer threshold is reached, so the delay through the buffer depends on the fill level. Each AxC interface has the same buffer threshold, but each Rx buffer reaches that threshold independently.

MAP Receiver in Synchronous Buffer Mode

In synchronous buffer mode, each AxC interface has a resynchronization signal,

mapN_rx_resync

resynchronization signal synchronously with the application asserts the resynchronization signal, it begins reading data on the

mapN_rx_data[31:0]

. The application that controls the data channel asserts its

mapN_rx_clk

clock. After the

data bus for the individual AxC interface.

In synchronous buffer mode, the application should ignore the signals and hold the the

mapN_rx_valid

application does not hold the

mapN_rx_ready

output signals in response to the

mapN_rx_ready

MAP Rx interface does not function correctly.

For details about the behavior of the individual signals in synchronous buffer mode, refer to “MAP Receiver Signals” on page 6–1.

Figure 4–9 shows the behavior of the MAP Rx signals in synchronous buffer mode. In

this example, the CPRI line rate is 2457.6 Mbps. The for the duration of a single frame, and the CPRI line rate determines the duration of a basic frame in

cpri_clkout

cycles. At 2457.6 Mbps, a basic frame is 16 cycles. At this line rate, as shown in Table 4–2 on page 4–8, the is 61.44 MHz. The approximately 0.125 times the

Figure 4–9. MAP Receiver Interface in Synchronous Buffer Mode

mapN_rx_clk

frequency is 7.68 MHz (oversampling rate 2),

cpri_clkout

mapN_rx_valid

output

input signals high. The CPRI IP core does assert

mapN_rx_ready

signals. If the

input signals high, the CPRI IP core

cpri_rx_start

signal is asserted

cpri_clkout

frequency

frequency.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–19

MAP Interface

1 To ensure IP core control over the resynchronization signal timing, Altera

recommends that your application trigger the IP core output signal

cpri_rx_start

user-programmable

cpri_rx_start

. The CPRI AUX interface asserts the

signal according to the offset value specified in the

CPRI_START_OFFSET_RX

mapN_rx_resync

signal with the CPRI

mapN_rx_resync

signals to ensure that the IP

core accommodates your application-specific constraints.

Figure 4–10 shows the roles of the

CPRI_START_OFFSET_RX

and

registers in ensuring correct alignment.

Figure 4–10. User-Controlled Delays to the AxC Data Channels in Rx Synchronous Buffer Mode

cpri_rx_rfp / _hfp

Write to mapN Rx buffer according to CPRI_MAP_OFFSET_RX value:

CPRI_MAP_OFFSET_RX

cpri_rx_start

mapN_rx_resync

Read from mapN Rx buffer in the first read cycle after the resync signal:

CPRI_START_OFFSET_RX

The values programmed in the the

cpri_rx_start

and

start_rx_offset_seq

signal. The values in the

sample 0 sample 1 sample 2 sample 3 sample 4 sample 5 sample 6

CPRI_START_OFFSET_RX

start_rx_offset_z, start_rx_offset_x

fields specify a hyperframe number, basic frame number,

and word number in the basic frame, respectively, within the 10 ms frame.

The CPRI master transmitter loads the AxC container block on the CPRI link at a specific location in the 10 ms frame; the system programs the information for this location in the location of the AxC container block from the

CPRI_START_OFFSET_RX

CPRI_MAP_OFFSET_RX

For example, if the 0x00020001, the CPRI receiver asserts the

CPRI_START_OFFSET_RX

cpri_rx_start

signal at word index 2 of basic frame 1 of hyperframe 0 in the 10ms frame. The data channel application samples the received IQ sample to the RX MAP AxC interface by asserting the signal. Assertion of the antenna-carrier interface (mapN) Rx buffer to zero. The sampled by the data channel one cycle after the

The offset programmed in the

cpri_rx_start

mapN_rx_resync

signal, detects it is asserted, and then synchronizes the

mapN_rx_resync

signal resets the read pointer of current

mapN_rx_resync

CPRI_MAP_OFFSET_RX

mapN_rx_data

can safely be

signal is asserted.

interface when to reset the write pointer of the Rx buffer: when the internal counters match the value in the

CPRI_MAP_OFFSET_RX

register, the write pointer resets. If the offset in this register has the value of zero, the write pointer resets at the start of every 10 ms radio frame. After the MAP receiver block resets the write pointer, it begins transferring IQ data from the CPRI frame to the Rx buffer.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–20 Chapter 4: Functional Description

MAP Interface

1 In advanced mapping modes, the K counter is reset to zero at the same time, so that it

advances from zero with the transfer of the data to the MAP Rx buffer, tracking the packing of the CPRI data contents into the AxC container block.

Because the mapN Rx buffer should not be read before it is written, the offset specified in the

CPRI_START_OFFSET_RX

underflow (in the

page 7–21, as reported in the

CPRI_MAP_OFFSET_RX

CPRI_IQ_RX_BUF_STATUS

mapN_rx_status_data

output signals described in

Table 6–1 on page 6–1), but it does not prevent them from occurring. Altera

recommends that you implement a separate tracking protocol to ensure you do not overflow or underflow the mapN Rx buffer.

You set the values in the

CPRI_START_OFFSET_RX

and

CPRI_MAP_OFFSET_RX

registers to specify the timeslot in the 10 ms radio frame in which your application expects to sample the data on the antenna-carrier interface.

In synchronous buffer mode, because programmed offsets control the mapN Rx buffer pointers, the delay through each mapN Rx buffer can be quantified.

1 In synchronous buffer mode, Altera recommends that you use sample rates that are

integer multiples of 3.84 MHz, or for implementing the WiMAX protocol, that you use sample rates that provide the exact frequency required.

MAP Receiver in the Internally-Clocked Mode

In the internally-clocked mode, contrast to the other two synchronization modes in which the antenna-carrier interfaces are clocked by the input two-stage buffer, and data passes quickly from the MAP block out to the individual data channels. Each AxC interface has a ready output signal, AxC interface asserts its ready signal when it first has data ready to transmit on this data channel.

The CPRI IP core asserts the simultaneously, synchronously with the available on the may also assert assert

mapN_rx_start

mapN_rx_data[31:0]

mapN_rx_valid

. In each 10 ms radio frame, for each antenna-carrier channel N, the application should ignore the CPRI IP core asserts the

mapN_rx_start

cpri_clkout

mapN_rx_clk

mapN_rx_start

drives the antenna-carrier interfaces, in

clocks. Each AxC interface has only a

mapN_rx_start

and

mapN_rx_valid

cpri_clkout

clock, when it makes data

signals

. Each

data bus for the individual AxC interface. It

before valid data is available. In that case, it does not

mapN_rx_valid

and

mapN_rx_data

signals until the

signal. Refer to Figure 4–11 for an example.

For details about the behavior of the individual signals in the internally-clocked mode, refer to “MAP Receiver Signals” on page 6–1.

Figure 4–11 shows an example of the behavior of the MAP Rx signals in this

synchronization mode in the basic mapping mode (

map_mode

= 2’b00). The example

CPRI IP core is configured and programmed with the following features:

■ CPRI line rate is 1228.8 Mbps. Therefore the duration of a basic frame is 8

cpri_clkout

■ Three active antenna-carrier interfaces.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

cycles.

Chapter 4: Functional Description 4–21

cpri_clkout

cpri_rx_hfn

cpri_rx_x

map0_rx_start

map0_rx_valid

map0_rx_data[31:0]

map1_rx_start

map1_rx_valid

map1_rx_data[31:0]

map2_rx_start

map2_rx_valid

map2_rx_data[31:0]

3 4 5 6

MAP Interface

■ In the

CPRI_MAP_OFFSET_RX

and the

cpri_rx_offset_x

field has the value of 4.

Figure 4–11. MAP Receiver Interface in the internally-Clocked Mode

cpri_rx_offset_z

field has the value of 3

In Figure 4–11, the edge of

map0_rx_valid

map0_rx_start

CPRI_MAP_OFFSET_RX

following the CPRI frame offset specified in the

signal pulses synchronously with the first rising

mapN_rx_valid

order, following the basic mapping mode.

The internally-clocked mode is useful only with the basic mapping mode. The advantage of the advanced mapping modes is their support for different clocks on different antenna-carrier interfaces, a feature not available with the internally-clocked synchronization mode.

MAP Transmitter Interface

The MAP transmitter interface receives data from the data channels and passes it to the CPRI protocol interface to transmit on the CPRI link. The MAP transmitter implements an Avalon-ST interface protocol. Refer to “MAP Transmitter Signals” on

page 6–3 for details of the interface communication signals.

signals are asserted in round-robin

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–22 Chapter 4: Functional Description

MAP Interface

MAP transmitter communication on the individual data map interfaces coordinates the transfer of data according to one of three different synchronization modes. The synchronization mode is determined by your selection in the CPRI parameter editor and by the value you program in the

map_tx_sync_mode

field of the

CPRI_MAP_CONFIG

Table 4–9. MAP Tx Synchronization Mode Determined by CPRI_MAP_CONFIG Register Bits

SYNC_MAP

(1)

map_tx_sync_mode

(register bit [3])

Tx Synchronization Mode

0 0 FIFO mode (page 4–23)

0 1 Synchronous buffer mode (page 4–24)

1—

Notes to Table 4–9:

(1) You determine the value of SYNC_MAP when you generate your CPRI IP core. Refer to Chapter 3, Parameter

Settings.

(2) When SYNC_MAP has the value of 1, the value in the

is ignored.

(2)

map_tx_sync_mode

Internally-clocked mode (page 4–26)

bit of the

CPRI_MAP_CONFIG

Tab le 4 –1 0 lists the clocks for the AxC interfaces in the different Tx synchronization

modes.

Table 4–10. MAP Tx Interface Clocks Determined by Tx Synchronization Mode

Tx Synchronization Mode AxC Channel Clocks

FIFO mode

Synchronous buffer mode

Internally-clocked mode

Each AxC Tx interface is clocked by its own

mapN_tx_clk

driven by the application.

Every AxC interface is clocked by the CPRI IP core clock,

cpri_clkout

clock

You determine the AxC interface clocks when you turn the Enable MAP interface synchronization with core clock parameter on (SYNC_MAP = 1) or off (SYNC_MAP

= 0) in the CPRI parameter editor before you generate your CPRI IP core.

MAP Transmitter Interface Signals in Different Synchronization Modes

The different CPRI IP core MAP synchronization modes use different interface signals. Table 4–11 lists the MAP transmitter interface signals used in each of these modes. Table notes indicate the correct interpretation of the different symbols.

(1)

Table 4–11. MAP Transmitter Interface Signals by Synchronization Mode

Available in Synchronization Mode

Signal Name Direction

FIFO

map{23…0}_tx_clk map{23…0}_tx_reset map{23…0}_tx_valid map{23…0}_tx_data[31:0] map{23…0}_tx_ready map{23…0}_tx_resync

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Input vv— Input vv— Input vvv Input vvv

Output v —

Input —

(2)

Synchronous

(Part 1 of 2)

Buffer

(2)

v —

Internally

Clocked

(2)

Chapter 4: Functional Description 4–23

mapN_tx_clk

mapN_tx_ready

mapN_tx_valid

mapN_tx_data[31:0]

MAP Interface

Table 4–11. MAP Transmitter Interface Signals by Synchronization Mode

(1)

(Part 2 of 2)

Available in Synchronization Mode

Signal Name Direction

FIFO

map{23…0}_tx_status_data [2:0]

Notes to Table 4–11:

(1) A checkmark indicates the signal is used in a synchronization mode, and a dash indicates the signal is not used in

that synchronization mode.

(2) An entry with a dash indicates a signal that does not participate in the MAP receiver interface communication in

this synchronization mode. The signal is either not present in the configuration or is ignored. An input signal that is ignored is ignored by the CPRI IP core. An output signal that is ignored should be ignored by the application. Refer to Table 6–2 on page 6–4 for information about the case that is relevant for each signal.

Output vvv

Synchronous

Buffer

Internally

Clocked

For descriptions of the signals in Ta bl e 4– 11, refer to Table 6–2 on page 6–4 and to the following sections.

MAP Transmitter in FIFO Mode

In FIFO mode, each data channel, or AxC interface, has an output ready signal,

mapN_tx_ready

data on this data channel for transmission to the CPRI protocol interface—when the buffer level is at or below the threshold indicated in the register.

. Each AxC interface asserts its ready signal when it is ready to receive

CPRI_MAP_TX_READY_THR

After the CPRI IP core asserts the respond by asserting the In every

mapN_tx_ready

data on

READY_LATENCY

mapN_tx_clk

is (becomes or remains) asserted, the application can present valid

mapN_tx_data

value 1.

mapN_tx_valid

cycle immediately following a

, as prescribed by the Avalon-ST specification with

For details about the behavior of the individual signals in FIFO mode, refer to “MAP

Transmitter Signals” on page 6–3. Figure 4–12 shows the expected typical behavior of

the MAP Tx signals in this synchronization mode.

Figure 4–12. MAP Transmitter Interface in FIFO Mode

FIFO-based communication is simple but does not allow easy control of buffer delay. The delay through each mapN Tx buffer depends on your programmed threshold value and the application. Data is not read from the mapN Tx buffer until the buffer threshold is reached, so the delay through the buffer depends on the fill level. Each AxC interface has the same buffer threshold, but each Tx buffer reaches that threshold independently.

mapN_tx_ready

signal, the application is expected to

signal and presenting data on

mapN_tx_clk

mapN_tx_data

cycle in which

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–24 Chapter 4: Functional Description

MAP Interface

MAP Transmitter in Synchronous Buffer Mode

In the synchronized communication, called synchronous buffer mode, each AxC interface has an incoming resynchronization signal, software asserts this resynchronization signal synchronously with the clock. When the application software asserts the resynchronization signal, it also asserts the

mapN_tx_data[31:0]

mapN_tx_valid

data bus for the individual AxC interface.

signal and begins sending valid data on the

mapN_tx_resync

. Application

mapN_tx_clk

In synchronous buffer mode, the application should ignore the signals. However, it should assert the valid data. The CPRI IP core holds the application must assert the asserts the

mapN_tx_valid

mapN_tx_resync

input signals in the same cycle as the

subsequently reasserts

mapN_tx_valid

signals. However, if the application does not assert the

mapN_tx_resync

mapN_tx_valid

mapN_tx_ready

input signals when sending

output signals high. The

input signals when or immediately after it

mapN_tx_resync

while

mapN_tx_valid

mapN_tx_ready

signals, and

is still high, data in

transition through the MAP Tx interface buffer is lost.

1 Altera recommends that your application assert the

when it asserts the

mapN_tx_resync

signals.

mapN_tx_valid

input signals

For details about the behavior of the individual signals in synchronous buffer mode, refer to “MAP Transmitter Signals” on page 6–3.

Figure 4–13 shows the expected typical behavior of the MAP Tx signals in this

synchronization mode. In this example, the CPRI line rate is 2457.6 Mbps. The

cpri_tx_start

rate determines the duration of a basic frame in basic frame is 16

page 4–8, the

7.68 MHz (oversampling rate 2), approximately 0.125 times the

signal is asserted for the duration of a single frame, and the CPRI line

cpri_clkout

cycles. At this line rate, as shown in Table 4–2 on

frequency is 61.44 MHz. The

cycles. At 2457.6 Mbps, a

mapN_tx_clk

frequency is

cpri_clkout

frequency.

output

Figure 4–13. MAP Transmitter Interface in Synchronous Buffer Mode

cpri_clkout

cpri_tx_start

mapN_tx_clk

mapN_tx_resync

mapN_tx_valid

mapN_tx_data[31:0]

1 To ensure IP core control over the resynchronization signal timing, Altera

recommends that your application trigger the IP core output signal

cpri_tx_start

user-programmable

CPRI MegaCore Function June 2012 Altera Corporation User Guide

cpri_tx_start

. The CPRI AUX interface asserts the

signal according to the offset value specified in the

CPRI_START_OFFSET_TX

mapN_tx_resync

signal with the CPRI

Chapter 4: Functional Description 4–25

cpri_tx_start

cpri_tx_rfp

cpri_tx_sync_rfp

mapN_tx_resync

CPRI_START_OFFSET_TX

CPRI_MAP_OFFSET_TX

sample 0 sample 1 sample 2 sample 3 sample 4 sample 5 sample 6

Write to mapN Tx buffer in the first write cycle after the resync signal:

Read from mapN Tx buffer according to CPRI_MAP_OFFSET_TX value:

MAP Interface

Asserting the resynchronization signal ensures correct alignment between the RF implementation and the CPRI basic frame at the appropriate offset from the start of the 10 ms radio frame. In addition to ensuring that application-specific constraints are accommodated, the system can set the

CPRI_START_OFFSET_TX

register to an offset that precedes the desired frame position in the CPRI transmission, in anticipation of the delays through the antenna-carrier interface Tx buffer and out to the CPRI Tx frame buffer. For information about these delays, refer to “Tx Path Delay” on page D–9.

Figure 4–14 shows the roles of the

CPRI_START_OFFSET_TX

and

CPRI_MAP_OFFSET_TX

registers in ensuring correct alignment.

Figure 4–14. User-Controlled Delays in Accepting Data From the AxC Data Channels in Synchronous Buffer Mode

The values programmed in the the

cpri_tx_start

signal by the CPRI transmitter. The values in the

start_tx_offset_z, start_tx_offset_x

CPRI_START_OFFSET_TX

, and

start_tx_offset_seq

fields specify a hyperframe number, basic frame number, and word (sequence) number in the basic frame, respectively, within the 10 ms frame.

The system source of the AxC payload transmits the AxC container block on the data channel to target a specific location in the 10 ms frame; the system programs the information for this location in the

CPRI_START_OFFSET_TX

and

CPRI_MAP_OFFSET_TX

registers. The CPRI transmitter learns the location of the AxC container block on the AxC interface from the

CPRI_START_OFFSET_TX

transmitter must assert the

CPRI_START_OFFSET_TX

cpri_tx_start

signal at word index 5 of basic frame 254 of hyperframe 149 in the 10ms frame. Altera recommends that the data channel application sample the signal is asserted, assert the

mapN_tx_data

can begin to fill the data words at the specified position in the CPRI

frame. Assertion of the

cpri_tx_start

mapN_tx_resync

signal, and when it detects the

cpri_tx_start

signal to indicate that the samples on

signal resets the write pointer of the current antenna-carrier interface (mapN) Tx buffer to zero, so that the entire buffer is available to receive the data from the data channel. The data on can safely be loaded in the mapN Tx buffer in the same cycle that the

mapN_tx_data[31:0]

mapN_tx_resync

signal is asserted.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–26 Chapter 4: Functional Description

MAP Interface

On the CPRI side of the mapN Tx buffer, the MAP transmitter interface reads data from the mapN Tx buffer and sends it to the CPRI transmitter interface. The offset programmed in the

CPRI_MAP_OFFSET_TX

register tells the MAP transmitter interface when to reset the read pointer of the mapN Tx buffer and start transferring data from the buffer to the CPRI transmitter interface. The K counter is reset to zero at the same time, so that it advances from zero with the transfer of the data to the CPRI transmitter interface, tracking the packing of the AxC container block contents into the CPRI frame.

Because the mapN Tx buffer should not be read before it is written, the offset specified in the

CPRI_START_OFFSET_TX

CPRI_MAP_OFFSET_TX

underflow (in the

CPRI_IQ_TX_BUF_STATUS

page 7–21 and as reported in the

mapN_tx_status_data

output vector described in

Table 6–2 on page 6–4), but it does not prevent them from occurring. Altera

recommends that you implement a separate tracking protocol to ensure you do not overflow or underflow the mapN Tx buffer.

In synchronous buffer mode, because programmed offsets control the mapN Tx buffer pointers, the delay through each mapN Tx buffer can be quantified.

MAP Transmitter in the Internally-clocked Mode

In the internally-clocked mode, each data channel, or AxC interface, has an output ready signal, ready to receive data on this data channel for transmission to the CPRI protocol interface—when the buffer level is at or below the threshold indicated in the

CPRI_MAP_TX_READY_THR

After the CPRI IP core asserts the respond by asserting the In every present valid data on

READY_LATENCY

For details about the behavior of the individual signals in the internally-clocked mode, refer to “MAP Transmitter Signals” on page 6–3.

mapN_tx_ready

cpri_clkout

value 1.

. Each AxC interface asserts its ready signal when it is

mapN_tx_ready

mapN_tx_valid

cycle in which

mapN_tx_data

signal, the application is expected to

signal and presenting data on

mapN_tx_ready

is asserted, the application can

mapN_tx_data

, as prescribed by the Avalon-ST specification with

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–27

Auxiliary Interface

Figure 4–15 shows an example of the behavior of the MAP Tx signals in this

synchronization mode in the basic mapping mode (

map_mode

= 2’b00).

Figure 4–15. MAP Transmitter Interface in the Internally-Clocked Mode

cpri_clkout

cpri_tx_hfn

cpri_tx_x

map0_tx_ready

map0_tx_valid

map0_tx_data[31:0]

map1_tx_ready

map1_tx_valid

map1_tx_data[31:0]

map2_tx_ready

map2_tx_valid

map2_tx_data[31:0]

4 5 67

CD EF GH

BC D E F

AB C D E F GH

In the internally-clocked mode the delay in the AxC interface block from each data channel can be quantified, because this delay is determined solely by the value in the

CPRI_MAP_OFFSET_TX

Auxiliary Interface

The CPRI auxiliary interface enables multi-hop routing applications and provides timing reference information for transmitted and received frames.

The auxiliary (AUX) interface allows you to connect CPRI IP core instances and other system components together by supporting a direct connection to a user-defined routing layer or custom mapping block. You implement this routing layer, which is not defined in the CPRI V4.2 Specification, outside the CPRI IP core. The AUX interface supports the transmission and reception of IQ data and timing information between an RE slave and an RE master, allowing you to define a custom routing layer that enables daisy-chain configurations of RE master and slave ports. Your custom routing layer determines the IQ sample data to pass to other REs to support multi-hop network configurations or to bypass the CPRI IP core MAP interface to implement custom mapping algorithms outside the IP core.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–28 Chapter 4: Functional Description

Auxiliary Interface

The CPRI IP core implements the AUX receiver and AUX transmitter interfaces as separate Avalon-ST interfaces. The AUX transmitter receives data to be transmitted on the outgoing CPRI link, and the AUX receiver transmits data received from the incoming CPRI link.

f For information about the Avalon-ST interface, refer to Avalon Interface Specifications.

AUX Receiver Module

The AUX receiver module transmits data that the CPRI IP core received on the CPRI link to the outgoing AUX Avalon-ST interface. In addition, it provides detailed information about the current state in the Rx CPRI frame synchronization state machine. This information is useful for custom user logic, including frame synchronization across hops in multihop configurations.

The AUX interface receiver module provides the following data and synchronization lines:

■

cpri_rx_sync_state

synchronization have been achieved in CPRI receiver frame synchronization

■

cpri_rx_start

offset defined in the

—when set, indicates that Rx, HFN, and BFN

—asserted for the duration of the first basic frame following the

CPRI_START_OFFSET_RX

■

cpri_rx_rfp

and

cpri_rx_hfp

—synchronization pulses for start of 10 ms radio

frame and start of hyperframe

■

cpri_rx_bfn

■

cpri_rx_x

■

cpri_rx_seq

■

cpri_rx_aux_data

and

cpri_rx_hfn

—current radio frame and hyperframe numbers

—index number of the current basic frame in the current hyperframe

—index number of the current 32-bit word in the current basic frame

—outgoing data port for sending data and control words

received on the CPRI link out on the AUX interface

The output synchronization signals are derived from the CPRI frame synchronization state machine. These signals are all fields in the

aux_rx_status_data

bus. For

additional information about the AUX receiver signals, refer to Table 6–3 on page 6–6.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–29

cpri_{rx,tx}_rfp

cpri_{rx,tx}_bfn

cpri_{rx,tx}_hfp

cpri_{rx,tx}_hfn

cpri_{rx,tx}_x

cpri_{rx,tx}_seq

0 1 ... NUM_SEQ - 1

2 ...

...210

255

149

n n + 1 n + 2

Hyperframe

Radio Frame (10 ms)

Basic Frame

Auxiliary Interface

Figure 4–16 shows the relationship between the synchronization pulses and numbers.

Figure 4–16. Synchronization Pulses and Numbers on the AUX Interfaces

The AUX receiver presents data on the AUX interface in fixed 32-bit words. The mapping to 32-bit words depends on the CPRI IP core line rate. Figure 4–17 shows how the data received from the CPRI protocol interface module is mapped to the AUX Avalon-ST 32-bit interface.

Figure 4–17. AUX Interface Data at Different CPRI Line Rates (Part 1 of 3)

614.4 Mbps Line Rate:

0123

[31:24]:

#Z.X.0.0

[23:16]: #Z.X.1.0 #Z.X.5.0 #Z.X.9.0 #Z.X.13.0

(1)

#Z.X.4.0 #Z.X.8.0 #Z.X.12.0

Sequence number on AUX interface

[15:8]: #Z.X.2.0 #Z.X.6.0 #Z.X.10.0 #Z.X.14.0

[7:0]: #Z.X.3.0 #Z.X.7.0 #Z.X.11.0 #Z.X.15.0

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–30 Chapter 4: Functional Description

Auxiliary Interface

Figure 4–17. AUX Interface Data at Different CPRI Line Rates (Part 2 of 3)

1228.8 Mbps Line Rate:

[31:24]:

[23:16]:

012 ... 7

#Z.X.0.0

#Z.X.0.1

(1)

#Z.X.2.0 #Z.X.4.0 ... #Z.X.14.0

#Z.X.2.1 #Z.X.4.1 ... #Z.X.14.1

Sequence number on AUX interface

[15:8]: #Z.X.1.0 #Z.X.3.0 #Z.X.5.0 ... #Z.X.15.0

[7:0]: #Z.X.1.1 #Z.X.3.1 #Z.X.5.1 ... #Z.X.15.1

2457.6 Mbps Line Rate:

[31:24]:

[23:16]:

[15:8]:

[7:0]:

3072.0 Mbps Line Rate:

[31:24]:

[23:16]:

[15:8]:

[7:0]:

012 ... 15

#Z.X.0.0

#Z.X.0.1

#Z.X.0.2

#Z.X.0.3

(1)

#Z.X.1.0 #Z.X.2.0 ... #Z.X.15.0

#Z.X.1.1 #Z.X.2.1 ... #Z.X.15.1

#Z.X.1.2 #Z.X.2.2 ... #Z.X.15.2

#Z.X.1.3 #Z.X.2.3 ... #Z.X.15.3

012 ... 1819

#Z.X.0.0

#Z.X.0.1

#Z.X.0.2

#Z.X.0.3

(1)

#Z.X.0.4

(1)

#Z.X.1.0 #Z.X.1.4 ... #Z.X.14.3 #Z.X.15.2

#Z.X.1.1 #Z.X.2.0 ... #Z.X.14.4 #Z.X.15.3

#Z.X.1.2 #Z.X.2.1 ... #Z.X.15.0 #Z.X.15.4

Sequence number on AUX interface

(1)

#Z.X.1.3 ... #Z.X.14.2 #Z.X.15.1

4915.0 Mbps Line Rate:

[31:24]:

[23:16]:

[15:8]:

[7:0]:

CPRI MegaCore Function June 2012 Altera Corporation User Guide

012 ... 3031

#Z.X.0.0

#Z.X.0.1

#Z.X.0.2

#Z.X.0.3

(1)

#Z.X.0.4

(1)

#Z.X.0.5

(1)

#Z.X.0.6

(1)

#Z.X.0.7

(1)

Sequence number on AUX interface

#Z.X.1.0 ... #Z.X.14.0 #Z.X.15.4

#Z.X.1.1 ... #Z.X.14.1 #Z.X.15.5

#Z.X.2.2 ... #Z.X.14.2 #Z.X.15.6

#Z.X.2.3 ... #Z.X.15.3 #Z.X.15.7

Chapter 4: Functional Description 4–31

Auxiliary Interface

Figure 4–17. AUX Interface Data at Different CPRI Line Rates (Part 3 of 3)

6144.0 Mbps Line Rate:

[31:24]:

[23:16]:

[15:8]:

[7:0]:

012 ... 3839

#Z.X.0.0

#Z.X.0.1

#Z.X.0.2

#Z.X.0.3

(1)

#Z.X.0.4

(1)

#Z.X.0.5

(1)

#Z.X.0.6

(1)

#Z.X.0.7

(1)

9830.4 Mbps Line Rate:

[31:24]:

[23:16]:

[15:8]:

[7:0]:

Note to Figure 4–17:

(1) Light blue table cells indicate control word bytes. White table cells indicate data word bytes.

0 1 2 3 ... 62 63

#Z.X.0.0

#Z.X.0.1

#Z.X.0.2

#Z.X.0.3

(1)

#Z.X.0.4

(1)

#Z.X.0.5

(1)

#Z.X.0.6

(1)

#Z.X.0.7

(1)

Sequence number on AUX interface

#Z.X.0.8

#Z.X.0.9

(1)

... #Z.X.15.2 #Z.X.15.6

... #Z.X.15.3 #Z.X.15.7

#Z.X.1.0 ... #Z.X.15.4 #Z.X.15.8

#Z.X.1.1 ... #Z.X.15.5 #Z.X.15.9

Sequence number on AUX interface

#Z.X.0.8

#Z.X.0.9

#Z.X.0.10

#Z.X.0.11

(1)

#Z.X.0.12

#Z.X.0.13

#Z.X.0.14

#Z.X.0.15

(1)

... #Z.X.15.8 #Z.X.15.12

... #Z.X.15.9 #Z.X.15.13

... #Z.X.15.10 #Z.X.15.14

... #Z.X.15.11 #Z.X.15.15

AUX Transmitter Module

The AUX transmitter module receives data on the incoming AUX Avalon-ST interface and sends it to the CPRI IP core physical layer to transmit on the CPRI link. In addition, it outputs CPRI link frame synchronization information, to enable synchronization of the AUX data.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–32 Chapter 4: Functional Description

cpri_tx_seq[5:0]

internal tx_seq value[5:0]

CPRI Frame

210 3 4

3938

3638

Ctrl Ctrl {Ctrl,feed}

0 1 2

37 3839

cpri_tx_aux_mask[31:0]

cpri_tx_aux_data[31:0]

(1)

00000000 00000000 00000000 ffffffff ffffffff0000ffff

00000000 00000000

00000000

00000000 00000000 0000feed

2 cpri_clkout cycles

Auxiliary Interface

The incoming data on the AUX interface must match the CPRI frame with a delay of exactly two the AUX Tx interface is two

cpri_clkout

clock cycles. The

cpri_clkout

cpri_tx_seq[5:0]

value that you read at

cycles ahead of the internal sequence number that tracks the CPRI frame. If you want your IQ sample to land at sequence number N of the CPRI frame, then you must present your sample at the AUX Tx interface when

cpri_tx_seq[5:0]

has the value of N+2. Figure 4–18 shows the expected timing on the incoming AUX connection in a variation with a CPRI line rate of 6144.4 Mbps.

Figure 4–18. Incoming AUX Link Synchronization

Note to Figure 4–18:

(1) The

cpri_tx_aux_data

and

cpri_tx_aux_mask

In Figure 4–18, the application presents data when 4, and sets the value of

signals are fields in the

cpri_tx_aux_mask

aux_tx_mask_data

input bus. Refer to Table 6–4 on page 6–7.

cpri_tx_seq[5:0]

has the value of

, to ensure the data is loaded in the CPRI frame immediately following the control word. Because the CPRI line rate in this example is 6144.4 Mbps, the length of the control word is ten bytes. Therefore, the application presents the data when

cpri_tx_seq[5:0]

has the value of 4 to ensure the

data is loaded in the CPRI frame at position 2.

In addition, to ensure the CPRI IP core transmits the incoming AUX data correctly on the CPRI link, you must format the incoming AUX data in the correct order to match the CPRI IP core internal data representation. If you connect two Altera CPRI IP cores through a routing layer, and your routing layer does not modify the data transmission order, then the correct order is guaranteed. However, if a different application transmits data to the CPRI IP core AUX interface, it must enforce the data order that the CPRI IP core expects.

Incoming AUX data to the CPRI IP core appears on called

aux_tx_mask_data[64:32]

[7:0] (39:32]) is transmitted last:

. Byte [31:24] (64:56]) is transmitted first, and byte

cpri_tx_aux_data[31:24]

cpri_tx_aux_data[31:0]

is byte 0 in the

, also

transmission order, and contains the least significant I- and Q-nibbles of the data sample. Figure 4–19 illustrates the required data order on this data bus.

Figure 4–19. Required Data Sample Order in aux_tx_mask_data[63:32] (cpri_tx_aux_data[31:0])

63 56 55 48 47 40 39 32

I[10]

Q[10]

I[9]

Q[9]

I[8]

Q[8]

I[15]

Q[15]

I[14]

Q[14]

I[13]

Q[13]

I[12]

I[3]

Q[3]

I[2]

Q[2]

I[1]

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Q[1]

I[0]

Q[0]

I[7]

Q[7]

I[6]

Q[6]

I[5]

Q[5]

I[4]

Q[4]

I[11]

Q[11]

Q[12]

Chapter 4: Functional Description 4–33

Auxiliary Interface

The CPRI IP core passes the incoming AUX data through to the CPRI link unmodified. You must ensure that the incoming AUX data bits already include any CRC values expected by the application at the other end of the CPRI link.

The CPRI transmitter frame synchronization state machine provides the following data and synchronization signals on the AUX interface to enable the required precise frame timing:

■

cpri_tx_start

offset defined in the

■

cpri_tx_rfp

—asserted for the duration of the first basic frame following the

and

cpri_tx_hfp

CPRI_START_OFFSET_TX

—synchronization pulses for start of 10 ms radio

frame and start of hyperframe

■

cpri_tx_bfn

■

cpri_tx_x

■

cpri_tx_seq

■

cpri_tx_aux_data

■

cpri_tx_aux_mask

and

cpri_tx_hfn

—current radio frame and hyperframe numbers

—index number of the current basic frame in the current hyperframe

—index number of the current 32-bit word in the current basic frame

—incoming data port for data on the AUX link

—incoming bit mask for AUX link data that indicates bits that

must be transmitted without changes to the CPRI link

The CPRI IP core layer 1 uses the

cpri_tx_aux_mask

to select the enabled bit values in the control transmit table. When mask bits are set, the corresponding data bits from the AUX interface fill the CPRI frame, overriding any internally-generated information. You must deassert all the mask bits during K28.5 character insertion in the outgoing CPRI frame (which occurs when Z=X=0). Otherwise, the CPRI IP core asserts an error signal following

cpri_clkout

clock cycle to indicate that the K28.5 character expected by

cpri_tx_error

on the

the CPRI link protocol has been overwritten. You must also ensure you do not override synchronization counter values in the control word.

The AUX transmitter module also receives a synchronization pulse in an REC master. Application software can pulse the

cpri_tx_sync_rfp

input signal to resynchronize the 10 ms radio frame. Asserting this signal resets the frame synchronization machine in an REC master.

In response to the rising edge of its (

aux_tx_mask_data[64]

The rising edge of the

cpri_clkout

pulse, the

cpri_tx_hfn

clock. On the seventh

cpri_tx_hfp

signals have the value 0, and the

), a CPRI REC master IP core restarts the 10 ms radio frame.

cpri_tx_sync_rfp

and

cpri_tx_rfp

cpri_tx_sync_rfp

input signal

signal must be synchronous with the

cpri_clkout

signals pulse, the

cycle following a

cpri_tx_x

cpri_tx_bfn

signal increments from its

cpri_tx_sync_rfp

and

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–34 Chapter 4: Functional Description

cpri_clkout

cpri_tx_sync_rfp

cpri_tx_seq

cpri_tx_x

cpri_tx_hfn

cpri_tx_bfn

cpri_tx_hfp

cpri_tx_start

cpri_tx_rfp

5 6 7 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6

3 4 0

Media Independent Interface to an External Ethernet Block

previous value. Figure 4–20 illustrates the behavior of the CPRI IP core signals in response to the

cpri_tx_sync_rfp

pulse.

Figure 4–20. CPRI REC Master Response to cpri_tx_sync_rfp Resynchronization Pulse

For more information about the relationships between the synchronization pulses and numbers, refer to Figure 4–16 on page 4–29. For the mapping of data between the AUX interface and the CPRI link, refer to Figure 4–17 on page 4–29.

The

cpri_tx_aux_data

aux_tx_mask_data

the

aux_tx_status_data

and

cpri_tx_aux_mask

signals are fields of the

bus. The other signals described in the preceding list are fields of

bus. For additional information about the AUX transmitter

signals, refer to Table 6–4 on page 6–7.

Media Independent Interface to an External Ethernet Block

The media independent (MI) interface, or MII, allows the CPRI IP core to communicate directly with an external Ethernet MAC block, replacing the internal Ethernet MAC. You specify in the CPRI parameter editor whether to implement this interface or to use the Ethernet MAC block available with the CPRI IP core. The two options are mutually exclusive.

If you configure the CPRI IP core with the MII, you must implement the Ethernet MAC block outside the CPRI IP core.

The MI interface is not a true media-independent interface, because it is clocked by the

cpri_clkout

signals directly), whose frequencies do not match the usual 2.5 MHz and 25 MHz frequencies of the media-independent protocol specification. If you use this interface, your external Ethernet block must communicate with the CPRI IP core synchronously with the

cpri_mii_txclk

The MII supports the bandwidth described in the CPRI V4.2 Specification in Table 12, Achievable Ethernet bit rates.

clock (which drives the

and

cpri_mii_rxclk

cpri_mii_txclk

clocks.

and

cpri_mii_rxclk

clock

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–35

Media Independent Interface to an External Ethernet Block

MII Transmitter

The MII transmitter module receives data from the external Ethernet MAC block and writes it to the CPRI transmitter module, which transmits it on the CPRI link. It performs 4B/5B encoding on the incoming data nibbles before sending them to the CPRI transmitter module.

After the CPRI IP core achieves frame synchronization, the MII transmitter module can accept incoming data on the MII. The MII transmitter module asserts the

cpri_mii_txrd

MAC block. After the asserts the transmitter module deasserts the cycle in which it receives data. It may remain deasserted for multiple cycles, to prevent buffer overflow. While the Ethernet block must maintain the data value on

signal to indicate it is ready to accept data from the external Ethernet

cpri_mii_txrd

cpri_mii_txen

signal to indicate it is ready to provide data. The MII

signal is asserted, the external Ethernet block

cpri_mii_txrd

signal in the cycle following each

signal remains low, the external

cpri_mii_txd

During the first

cpri_mii_txclk

cycle in which

cpri_mii_txen

is asserted, the MII module inserts an Ethernet J symbol (5’b11000) in the buffer of data to be transmitted to the CPRI link; during the second cycle in which

cpri_mii_txen

is asserted, the MII module inserts an Ethernet K symbol (5’b10001) in this buffer. These two symbols indicate Ethernet start-of-packet. While the CPRI MII transmitter is inserting the J and K symbols, it ignores incoming data on

Typically, the external Ethernet block asserts

cpri_mii_txrd

is asserted. While the transmitter module reads data on the data sequence, in the first two

cpri_mii_txclk

cpri_mii_txd

cpri_mii_txen

cpri_mii_txd

cycles in which the

. Refer to Figure 4–21.

one clock cycle after

signal remains asserted, the MII

input data bus. Following this

cpri_mii_txen

signal is not asserted, the MII module inserts an Ethernet end-of-packet symbol—T followed by R. While the CPRI MII transmitter is inserting the T and R symbols, it ignores incoming data on

While

cpri_mii_txen

current nibble on observes that both

cpri_mii_txclk

cpri_mii_txd

cpri_mii_txen

cycle, the MII module inserts an Ethernet HALT symbol (5’b00100).

Figure 4–23 on page 4–38 provides an example in which the

cpri_mii_txd

is asserted, the

is suspect. Therefore, if the MII transmitter module

and

. Refer to Figure 4–21.

cpri_mii_txer

input signal indicates that the

are asserted in the same

cpri_mii_txer

signal is asserted, and shows how the error indication propagates to the MII receiver module on the CPRI link slave.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–36 Chapter 4: Functional Description

Media Independent Interface to an External Ethernet Block

Figure 4–21 illustrates the MII transmitter protocol with no input errors. The

cpri_mii_txen

Although an Ethernet packet on transmitter can deassert

signal remains asserted for the duration of the packet transfer.

cpri_mii_txrd

can be reasserted every other cycle during transmission of

cpri_mii_txd

cpri_mii_txrd

, this need not always occur. The CPRI MII

for more than one cycle to backpressure the external Ethernet block. In that case, the external Ethernet block must maintain the data value on

cpri_mii_txd

until the cycle following reassertion of

cpri_mii_txrd

Figure 4–21. CPRI MII Transmitter Example

cpri_mii_txclk

cpri_mii_txrd

cpri_mii_txen

cpri_mii_txd[3:0]

cpri_mii_txer

decoded result

(conceptual)

txen is asserted

>1 cycle

after

txrd assertion

cpri_mii_txen

txen response

>1 cycle

without

> IDLEs

txen asserted

2 cycles in which

txrd is asserted

Idle J K D0D0D1D1D2D2D3

to backpressure the Ethernet block

is deasserted while

txrd is deasserted

an additional cycle

Ethernet packet

cpri_mii_txrd

reasserted in the cycle following the reassertion of

is deasserted, and is not

cpri_mii_txrd

No txen response

to 2 cycles

in which

txrd asserted

D5 T R Idle

, then the CPRI MII

txrd asserted

transmitter inserts a T symbol in the packet; therefore, the external Ethernet block must reassert during transmission of an Ethernet packet on

cpri_mii_txen

in the cycle following reassertion of

cpri_mii_txd

cpri_mii_txrd

For more information about the MII transmitter module, refer to “CPRI MII

Transmitter Signals” on page 6–10.

MII Receiver

The MII receiver module receives data from the CPRI link by reading it from the CPRI receiver module. It performs 4B/5B decoding on the 5-bit data values before transmitting them as 4-bit data values on the MII.

After the CPRI IP core achieves frame synchronization, the MII receiver module can send data to the external Ethernet block. The MII receiver module transmits the K nibble to indicate start-of-frame on the MII. The J nibble of the start-of-frame is consumed by the CPRI IP core, and is not transmitted on the MII.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–37

Media Independent Interface to an External Ethernet Block

The MII receiver module transmits the K nibble and then the data to the output data bus and asserts the currently on

cpri_mii_rxd

the first

cpri_mii_rxd

output data bus on the rising edge of the

cpri_mii_rxclk

receiver module asserts the completes sending data to the external Ethernet block, it deasserts the signal.

While frame synchronization is not achieved, the asserted and

cpri_mii_rxdv

Figure 4–22 illustrates the MII receiver protocol.

Figure 4–22. CPRI MII Receiver Example

cpri_mii_rxclk

cpri_mii_rxwr

cpri_mii_rxdv

cpri_mii_rxd[3:0]

reset

cpri_mii_rxdv

signal to indicate that the data

is valid. It sends the K nibble and the data to the

cpri_mii_rxclk

cycle of every new data value on

cpri_mii_rxwr

signal. After the MII receiver module

cpri_mii_rxer

cpri_mii_rxd

signal remains

remains deasserted.

D0 D1K D2 D3 D4 D5 D6 D7

cpri_mii_rxd

clock. During

, the MII

cpri_mii_rxdv

cpri_mii_rxer

Frame Synchronization

Achieved

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–38 Chapter 4: Functional Description

cpri_mii_txclk

cpri_mii_txrd

cpri_mii_txen

cpri_mii_txd[3:0]

cpri_mii_txer

cpri_mii_rxclk

cpri_mii_rxwr

cpri_mii_rxdv

cpri_mii_rxd[3:0]

D0 D1 D2 D3 D4 D5 D6 D7

D1 D2 D3 F D5 D6 D7

cpri_mii_rxer

CPU Interface

Figure 4–23 shows an example timing diagram in which an input error is noted on the

MII of a transmitting RE or REC master, and the data from the MII is transmitted on the CPRI link to a receiving RE slave. The timing diagram shows the MII signals on the transmitting master and the receiving slave. The data value captured on the MII transmitter module of the RE or REC master when

cpri_mii_txer

is asserted, is passed to the CPRI link as a 5-bit Ethernet HALT symbol (5’b00100). The RE slave MII receiver module decodes this symbol as an F (4’b1111) while the

cpri_mii_rxer

signal

is asserted.

Figure 4–23. CPRI MII Signals on Transmitting RE or REC Master and on Receiving RE Slave

For more information about the MII receiver module, refer to “CPRI MII Receiver

Signals” on page 6–10.

CPU Interface

Use the CPU interface to communicate the contents of the control word of a CPRI hyperframe — VSS, Ethernet, High-Level Data Link Controller (HDLC), and synchronization and timing information — and to access status and configuration information in the CPRI IP core registers. An on-chip processor such as the Nios II processor, or an external processor, can access the CPRI configuration address space using this interface.

The CPU interface provides an Avalon-MM slave interface that accesses all registers in

f For information about the Avalon-MM interface, refer to Avalon Interface Specifications.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

the CPRI IP core. The Avalon-MM slave executes transfers between the CPRI IP core and the user-defined logic in your design.

Chapter 4: Functional Description 4–39

CPU Interface

Each of the three sources of input to the CPU interface communicates with the CPRI IP core by reading and writing registers through a single Avalon-MM port on the CPU interface. Arbitration among the different sources must occur outside the CPRI IP core.

If the CPRI IP core is configured with an MII, the application cannot access the IP core’s Ethernet registers through the CPU interface. However, if the HDLC block is configured, you can access the IP core’s HDLC registers whether or not the MII is configured.

For more information about the CPRI IP core registers, refer to Chapter 7, Software

Interface.

Accessing the Hyperframe Control Words

You can access the 256 control words in a hyperframe through the CPRI IP core CPU interface. The register (Table 7–8 on page 7–4) support your application in reading the incoming control words, and the

CPRI_CTRL_INDEX

the application in writing to outgoing control words.

CPRI_CTRL_INDEX

CPRI_CONFIG

CPRI_TX_CTRL

CPRI_RX_CTRL

Register support only provides you access to the initial byte of each control word. You can access the full control words through the CPRI IP core AUX interface.

Tab le 4 –1 2 summarizes the relevant register fields. For complete information, refer to

the register tables in Chapter 7, Software Interface.

Table 4–12. Register Support for Control Word Access

CPRI_CTRL_INDEX (Table 7–7)

CPRI_RX_CTRL (Table 7–8

CPRI_TX_CTRL (Table 7–9

CPRI_CONFIG (Table 7–6

)

Bits

[7:0]

[8]

[7:0]

[0]

Field Name Description

cpri_ctrl_index

rx_control_data

tx_control_insert

tx_control_data

tx_ctrl_insert_en

Index for CPRI control byte monitoring and insertion. The value in this field determines the control receive and control transmit table entries that appear in the

CPRI_TX_CTRL

Most recent received CPRI control word from CPRI hyperframe position Z.x.0, where x is the index in the field of the

Control byte transmit enable.

CPRI control byte to be transmitted in CPRI hyperframe position Z.x.0, where x is the index in the

CPRI_CTRL_INDEX

Master enable for insertion of CPRI control word. This signal enables control bytes for which the

tx_control_insert

frame.

registers.

CPRI_CTRL_INDEX

CPRI_RX_CTRL

cpri_ctrl_index

tx_control_data

bit is high to be written to the CPRI

and

cpri_ctrl_index

field of the

contents in

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–40 Chapter 4: Functional Description

CPU Interface

Recording and Retrieving the Incoming Control Bytes

A control receive table contains a 1-byte entry for each of the 256 control words in the current hyperframe. To read a control byte, your application must write the control word number X to the control byte in the

CPRI_CTRL_INDEX

CPRI_RX_CTRL

can use this access method only to retrieve the first byte of a control word.

Writing the Outgoing Control Bytes

A control transmit table contains an entry for each of the 256 control words in the current hyperframe. Each control transmit table entry contains a control byte field and an enable bit. As the frame is created, if a control word entry is enabled, and the global

tx_ctrl_insert_en

writes the control byte to the first byte of the CPRI frame’s control word.

To write a control byte in the control transmit table, write the control word number X to the

CPRI_CTRL_INDEX

and set the

tx_control_insert

control transmit table, set the enable the CPRI IP core to write the values from the control transmit table to the control words in the outgoing CPRI frame.

bit in the

CPRI_CONTROL

bit in the

tx_ctrl_insert_en

CPRI_TX_CTRL

bit of the

CPRI_CONFIG

The

tx_control_insert

bit of the

CPRI_TX_CTRL

register enables or disables the transmission of the corresponding byte in the control transmit table in the CPRI frame. The when it is set, the CPRI IP core writes all table entries with the

tx_ctrl_insert_en

bit of the

CPRI_CONFIG

tx_control_insert

bit

set into the CPRI frame.

Control Word Order

The entries in the control receive and control transmit tables match the organization of control words in subchannels from the CPRI specification. Figure 4–24 shows this word order. The figure is Figure 15 of the CPRI V4.2 Specification.

Figure 4–24. Illustration of Subchannels in a Hyperframe (Part 1 of 2)

Xs == 0 1 2 3

Ns == 0

4 4: Reserved ...

5 ...

0: K28.5 Synchronization and Timing

1: HDLC link 65: HDLC 129: HDLC 193: HDLC

2: L1 In-band 66: L1 in-band 130: L1 in-band 194: P (20 = 0x14)

3: Reserved 67: Reserved

...

15 15: Reserved 79: Reserved 143: Reserved 207: Reserved

CPRI MegaCore Function June 2012 Altera Corporation User Guide

14: Reserved

Vendor-specific

...

Chapter 4: Functional Description 4–41

CPU Interface

Figure 4–24. Illustration of Subchannels in a Hyperframe (Part 2 of 2)

Pointer P --->

20: Ethernet

...

62 126 190 254

63 127 191 255

Figure 4–24 illustrates how the 256 control words in the hyperframe are organized as

64 subchannels of four control words each. The figure illustrates why the index X of a control word is Ns + 64 × Xs, where Ns is the subchannel index and Xs is the index of the control word within the subchannel.

Control Word Transmission Example

To write to the vendor-specific portion of the control word in a transmitted hyperframe, perform the following steps:

1. Identify the indices for the vendor-specific portion of the transmit control table,

using the formula X = Ns + 64 × Xs.

In the example, Ns = 16 and Xs = 0,1,2, and 3. Therefore, the indices to be written are 16, 80, 144, and 208.

2. For each value X in 16, 80, 144, and 208, perform the following steps:

a. Write the value X to the

cpri_ctrl_index

field of the

CPRI_CTRL_INDEX

b. Write the control byte to the

tx_control_insert

tx_control_data

field of the

CPRI_TX_CTRL

value of 1.

3. After you update the control transmit table with the control bytes, to insert the

data in the next outgoing CPRI frame, set the

CPRI_CONFIG

tx_ctrl_insert_en

field of the

Control Word Retrieval Example

To retrieve the first byte of the vendor-specific portion of a control word in the most recent received hyperframe, perform the following steps:

1. Identify the indices for the vendor-specific portion of the transmit control table,

using the formula X = Ns + 64 × Xs.

In the example, Ns = 16 and Xs = 0,1,2, and 3. Therefore, the indices to be read are 16, 80, 144, and 208.

2. For each value X in 16, 80, 144, and 208, perform the following steps:

a. Write the value X to the

b. In the following

field of the

cpu_clk

CPRI_RX_CTRL

cpri_ctrl_index

field of the

CPRI_CTRL_INDEX

cycle, read the control byte in the

rx_control_data

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–42 Chapter 4: Functional Description

CPU Interface

Accessing the Ethernet Channel

If you turn on the Include MAC block parameter, your CPRI IP core includes an internal Ethernet Media Access Controller (MAC). If you turn off this parameter, an MII is available for you to connect to your own external Ethernet MAC. In that case, the internal Ethernet MAC is not available and your application cannot access the Ethernet registers. If the internal Ethernet MAC is turned off, attempts to access these registers read zeroes and do not write successfully, as for a reserved register address.

The Ethernet MAC is responsible for processing the Ethernet frame. The Ethernet MAC unloads the Ethernet frame from the CPRI frame and stages it in the Ethernet registers, where it is accessible through the CPU interface. The Ethernet MAC also handles the flow of Ethernet data to the CPRI frame, by loading it from the Ethernet registers into the Ethernet space in the CPRI hyperframe.

The CPRI specification dictates that a CPRI hyperframe that contains Ethernet data also contain a pointer to the start of that data in control byte Z.194.0. The pointer value 0x0 indicates that no Ethernet channel is supported in the current hyperframe. A valid pointer holds a subchannel index value between 0x14 and 0x3F, inclusive. The length of the Ethernet data can extend beyond the end of the hyperframe; if a received Ethernet frame exceeds 1536 bytes, the Ethernet module resets, unless the

rx_long_frame_en

bit of the

ETH_CONFIG_1

The CPRI transmitter reads the pointer value from the

CPRI_CM_CONFIG

CPRI hyperframe. The

rx_fast_cm_ptr

field of the

tx_fast_cm_ptr

CPRI_CM_STATUS

field of the

register holds the current pointer value, determined during the software set-up sequence or by dynamic modification, in which the same new pointer value is received in CPRI control byte Z.194.0 four hyperframes in a row.

Software can configure the Ethernet channel by writing to the

ETH_CONFIG_1

register through the CPRI IP core Avalon-MM CPU interface. For additional information about this register, refer to Chapter 7, Software Interface.

Transmitting Ethernet Traffic

To transmit an Ethernet frame, the CPRI IP core must load the frame in a Tx Ethernet buffer. Application software can direct the CPRI IP core to load the Ethernet frame in the Tx Ethernet buffer by reading and writing the following registers:

■

ETH_CONFIG_2

CPRI IP core to automatically calculate the Frame check sequence and insert it at the end of the frame data, by setting the

■

ETH_TX_STATUS tx_ready_block

value of 1, you can load a 4-byte word to the Tx Ethernet buffer. If the

tx_ready_block

to the Tx Ethernet buffer without polling the between CPU write operations.

crc_enable

field in bit 0 of this register.

and

tx_ready

fields of this register. If the

tx_ready

field has a

field has a value of 1, you can load a block of eight 4-byte entries

tx_block_ready

tx_ready

bits

■

ETH_TX_DATA

register at offset 0x220 (Table 7–59 on page 7–24)—Load data in this register. To load a block of eight 4-byte entries to the Tx Ethernet buffer, you must execute eight CPU write operations to this register.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–43

CPU Interface

■

ETH_TX_CONTROL

load the final word of an Ethernet frame in the

ETH_TX_DATA_WAIT

write the

tx_length

ETH_TX_DATA

field of this register to indicate how many bytes in the final

tx_eop

field and

word are padding.

The Ethernet Tx buffer holds 64 4-byte entries, for a total of 256 bytes. When transmitting Ethernet frames larger than the capacity of the Tx Ethernet buffer, you must ensure you do not overflow or underflow the buffer. If the Ethernet transmitter module writes data to the ready, the

tx_abort

ETH_TX_DATA

bit is set in the

ETH_TX_STATUS

register and the current Ethernet packet is aborted. To prevent the Ethernet transmitter module from aborting a frame, you can write the data to the

ETH_TX_DATA_WAIT

You must write each frame’s data to the

ETH_TX_DATA

register continuously. The Ethernet transmitter module ensures the correct bit order for transmission on the CPRI link. If the

crc_enable

field of the

ETH_CONFIG_2

register has the value of 0, you must insert the CRC in the frame data, because the Ethernet receiver module checks CRC. In this case, you must reverse the bit order of the CRC bytes so that the most significant byte of the CRC is transmitted first.

1 If you set the

crc_enable

field of the

ETH_CONFIG_2

register to the value of 1, the Tx Ethernet automatically calculates the Frame check sequence and inserts it at the end of the Ethernet frame data in the Tx Ethernet buffer.

Software can set the causes the

tx_abort

transmitter module can also set the

tx_discard

bit in the

ETH_TX_CONTROL

ETH_TX_STATUS

tx_abort

bit directly.

The Tx Ethernet controller reads the Tx Ethernet buffer after you set the the

ETH_TX_CONTROL

you disable the store-and-forward feature by resetting the

ETH_FWD_CONFIG

ETH_TX_DATA

tx_st_fwd

field of the

register at offset 0x244 (Table 7–64 on page 7–25), the Tx Ethernet controller also reads the Tx Ethernet buffer whenever the number of words in the Tx Ethernet buffer is above a programmable threshold.

Interrupts

Software can enable interrupts by setting bits in the 0x208 (Table 7–53 on page 7–23). The enable and

intr_tx_en

is the Ethernet Tx interrupt enable. If both of these two bits are set, software can use the status in the For example, using the

tx_ready_block

intr_en

ETH_TX_STATUS

bit to generate an interrupt ensures that the

ETH_CONFIG_1

bit is the Ethernet global interrupt

CPU is interrupted only when a full 32-bit packet of data is ready to transfer to the Ethernet Tx buffer.

tx_eop

bit of

Receiving Ethernet Traffic

The Ethernet receiver module receives Ethernet data from the CPRI link by reading it from the Ethernet Rx buffer through an Ethernet register.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–44 Chapter 4: Functional Description

CPU Interface

This section describes how the Ethernet receiver module performs MAC address filtering according to the provides status information to the CPU interface in the

ETH_CONFIG_1, ETH_ADDR_LSB

, and

ETH_ADDR_MSB

ETH_RX_STATUS

registers,

allows the CPU interface to insert wait states in the Ethernet channel.

For additional information about the Ethernet receiver registers, refer to Chapter 7,

Software Interface.

MAC Address Filtering

To enable MAC address checking, set the If the

mac_check

bit is reset to the value of zero, the Ethernet receiver accepts all

mac_check

bit of the

ETH_CONFIG_1

received packets.

You can enable the following three MAC address filters:

■ Unicast filtering: check that the destination MAC address is the address specified

in the

ETH_ADDR_LSB

and

ETH_ADDR_MSB

registers. If the

mac_check

bit is not set, this

filter is disabled.

■ Multicast filtering: if the least significant bit of the first destination MAC address

byte, the group address bit, is set to 1, use the

ETH_HASH_TABLE

register to determine whether to accept this destination MAC address. Because the hash algorithm might not filter the destination address as intended, you must implement full address validation in software if you enable multicast filtering. To enable multicast filtering, set the

multicast_flt_en

bit of the

ETH_CONFIG_1

■ Broadcast filtering: accept all packets with destination MAC address

0xFFFFFFFFFFFF, the Ethernet broadcast address. To enable broadcast filtering, set the

broadcast_en

bit of the

ETH_CONFIG_1

Ethernet Rx Buffer Status

The CPRI IP core reports relevant Ethernet Rx buffer status to the CPU interface by updating the following fields of the

■ The

ETH_RX_STATUS rx_ready

ETH_RX_STATUS

bit indicates that at least one word of data is

available in the Ethernet Rx buffer and ready to be read.

■ The

ETH_RX_STATUS rx_eop

bit indicates that the next ready data word contains

the end-of-packet byte.

■ The

ETH_RX_STATUS rx_length

field indicates the number of valid bytes in the

end-of-packet word.

■ The

ETH_RX_STATUS rx_abort

bit indicates that the current received packet is

aborted.

■ The

ETH_RX_STATUS rx_ready_block

bit indicates that the next block of packet

data is ready to be read and does not contain the end-of-packet byte.

■ The

ETH_RX_STATUS rx_ready_end

bit indicates that the end-of-packet byte is

ready in the Ethernet Rx buffer.

Software can set the

ETH_RX_CONTROL rx_discard

bit to abort the current received packet. The Ethernet receiver ensures that following read from the Ethernet Rx buffer is a start-of-packet word.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–45

CPU Interface

Ethernet Data Transfer

The next ready data word is available in the registers. If no Ethernet data word is ready, reading from the

ETH_RX_DATA

and

ETH_RX_DATA_WAIT

ETH_RX_DATA

rx_abort

bit to be set. The CPU interface receiver module reads the Ethernet packet data one word at a time from one of these registers.

Accessing the HDLC Channel

If you turn on the Include HDLC block parameter, your CPRI IP core includes an internal High-Level Data Link Controller (HDLC) block. If you turn off this parameter, the internal HDLC block is not available and your application cannot access the HDLC registers. If the internal HDLC block is turned off, attempts to access these registers read zeroes and do not write successfully, as for a reserved register address.

In the CPRI IP core, the HDLC block, or slow data link layer, passes HDLC data between the CPU interface and the CPRI receiver and transmitter interfaces to the CPRI link. The CPRI specification dictates that the HDLC channel rate is specified in the three lowest bits of control byte Z.66.0. The value 3’b000 indicates that no HDLC channel is supported in the current hyperframe. Table 4–13 shows the possible rate configurations.

Table 4–13. HDLC Channel Bit Rates

Value in Z.66.0.0[2:0]

000 — 614.4

001 240 614.4

010 480 614.4

011 960 1228.8

100 1920 2457.6

101 2400 3072.0

110

111

Note to Tab le 4– 13:

(1) When Z.66.0.0[2:0] holds value 3’b111, the HDLC bit rate is the highest HDLC bit rate possible for the current CPRI

line rate. You can derive that bit rate from the other entries in this table.

HDLC Bit Rate

(Kbps)

3840 4915.2

4800 6144.0

7680 9830.4

Minimum CPRI Line Rate

(Mbps)

(1)

The HDLC channel rate is determined during the software set-up sequence or by dynamic modification, in which the same new pointer value is received in CPRI control byte Z.66.0 four hyperframes in a row. The accepted receive rate is specified in the

rx_slow_cm_rate

specified in the

field of the

tx_slow_cm_rate

CPRI_CM_STATUS

field of the

CPRI_CM_CONFIG

The CPU interface control for the HDLC channel is identical to the CPU interface control for the Ethernet channel, with the following exceptions:

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–46 Chapter 4: Functional Description

CPRI Protocol Interface Layer (Physical Layer)

■ HDLC register names replace

■ HDLC channel control has fewer configurations than the Ethernet channel control

■ HDLC channel control does not support address filtering

ETH

with

HDLC

1 The CPRI IP core implements the CRCDT CRC-16 allowed by the HDLC specification,

rather than the CRC-32.

CPRI Protocol Interface Layer (Physical Layer)

The physical layer of the CPRI protocol is also called layer 1. This layer controls the electrical characteristics of the CPRI link, the time-division multiplexing of the separate information flows in the protocol, and low-level signaling. The CPRI protocol interface module of the CPRI IP core incorporates Altera’s high-speed transceivers to implement layer 1. The transceivers are configured in deterministic latency mode, supporting the extended delay measurement requirements of the CPRI specification.

This section describes features and blocks of the CPRI protocol interface module.

Figure 4–25 shows a high-level block diagram of this module.

Features

The physical layer has the following features:

■ Frame synchronization

■ Transmitter and receiver with the following features:

■ High-speed data serialization and deserialization

■ Clock and data recovery (receiver)

■ 8B/10B encoding and decoding

■ Frame and control word assembly and delineation

■ Error detection

■ Deterministic latency

■ Software interface (status and control registers)

■ Error reporting

■ Clock decoupling

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–47

tx_dataout

CPRI Link

rx_datain

CPRI Link

Receiver Transceiver

Rx State Machine

and

Frame Alignment

DEMUX

Payload

Timing

I/Q

Payload

RFN + HFN

Recovery

Ethernet

Decode

HDLC

Bit-Destuff

VSS/L1/

Alarms

Low-Level Receiver

CPU IF Module

HDLC_RXETH_RXTiming

CPRI_RX_MAPAUX IF

Module

Transmitter Transceiver

Tx State Machine

MUX

Payload Ethernet

Encode

HDLC

Bit-Destuff

VSS/L1

Low-Level Transmitter

CPU IF Module

HDLC_TXETH_TX

Loop Data

CPRI_TX_MAPAUX IF

Module

I/Q

Payload

Elastic Buffer

CPRI Protocol Interface Layer (Physical Layer)

Physical Layer Architecture

Figure 4–25 shows the architecture of the physical layer.

Figure 4–25. Physical Layer High Level Block Diagram

Ensuring the Physical Layer Routes Your Data as Expected

Layer 1 routes data from the MAP, Auxiliary, and CPU interfaces to the outgoing CPRI frame, and routes data from the CPRI frame to the MAP, Auxiliary, and CPU interfaces. To ensure the data is routed as you intend, observe the following guidelines:

■ To configure a CPRI IP core variation that supports only the AUX interface, in the

CPRI parameter editor, set the number of antenna-carrier interfaces to the value of

■ To program a subset of the configured antenna-carrier channels as active

antenna-carrier channels, set the to the appropriate number of channels. Refer to “Number of Antenna-Carrier

Interfaces” on page 3–6. The combination of CPRI line rate, MAP interface sample

width (programmed in the and sampling rate (programmed in the register) restricts the number of active antenna-carrier interfaces your CPRI IP core can support without data corruption. Refer to Table 4–4 and Table 4–5 on

page 4–14. Programming these register fields affects how your AxC samples are

packed in the data channels. You can program these register fields, and they have

map_15bit_mode

map_ac

map_n_ac

field of the

CPRI_MAP_CNT_CONFIG

CPRI_MAP_CONFIG

CPRI_MAP_CNT_CONFIG

the same effect on the MAP interface, whether or not your CPRI IP core variation uses the AUX interface.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–48 Chapter 4: Functional Description

■ If your CPRI IP core variation and application support both an AUX interface and

a MAP interface, use the

aux_tx_mask_data[64:0]

cpri_tx_aux_mask

bus described in Table 6–4 on page 6–7) to override the

CPRI Protocol Interface Layer (Physical Layer)

mask signal (bits [31:0] of the

MAP interface (data) and CPU interface (control words) write access to the CPRI frame data per data bit. The mask signal is a MUX select. Setting a bit in the mask ensures the corresponding data bit inserted in the outgoing CPRI frame is data from the AUX interface. Resetting a bit in the mask ensures the corresponding bit inserted in the outgoing CPRI frame is data from the MAP interface or control words from the CPU interface.

■ The AUX interface routes raw data. It passes control words unexamined as if they

were data. Your application can separate the control and data words in the AUX stream if your application requires that they be separated.

■ When the source of the data for the CPRI frame is not the AUX interface, you must

ensure you deassert the bits in

cpri_tx_aux_mask

to prevent AUX data from being

inserted in the outgoing CPRI frame.

Receiver

The receiver in the low-level interface receives the input from the CPRI link, and performs the following tasks:

■ Converts the data to the main clock domain

■ Performs CPRI frame detection

■ Separates data and control words

■ Descrambles data at 4915.2 Mbps, 6144.0, and 9830.4 Mbps CPRI line rates

(optional)

■ Separates data for the MAP interface block, the AUX module, the Ethernet MAC

block or the MII module, and the HDLC module.

■ Detects loss of signal (LOS), loss of frame (LOF), remote alarm indication (RAI),

and service access point (SAP) defect indication (SDI) errors

High-Speed Transceiver

The high-speed transceiver on the CPRI IP core CPRI protocol interface is configured with the Altera ALTGX megafunction in Arria II, Cyclone IV GX, and Stratix IV GX devices, with the Altera Deterministic Latency PHY IP core in Arria V and Stratix V GX devices and in some variations in Stratix V GT devices, and with the Altera Native PHY IP core in variations with a CPRI line rate of 9830.4 Mbps in Stratix V GT devices.

The transceiver receiver implements 8B/10B decoding and the deterministic latency protocol. The deterministic latency protocol is designed to meet the 16.276 ns round-trip delay measurement accuracy requirements R21 and R21A of the CPRI specification.

f For information about the high-speed transceiver blocks, refer to volume 2 of the

Arria II Device Handbook, to volume 2 of the Cyclone IV Device Handbook, or to volume 2 and volume 3 of the Stratix IV Device Handbook.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–49

CPRI Protocol Interface Layer (Physical Layer)

f For information about the Altera Deterministic Latency PHY IP core and the Altera

Native PHY IP core, refer to the Altera Transceiver PHY IP Core User Guide.

Rx Elastic Buffer

The low-level interface receiver converts data from the transceiver clock domain and data width to the main CPRI IP core clock domain and data width using a synchronization FIFO called the Rx elastic buffer. The Rx elastic buffer data output is clocked with the with the

rx_clkout

is 32 bits, and the wide. For details, refer to “Clock Diagrams for the CPRI IP Core” on page 4–4.

The default depth of the Rx elastic buffer is 64 32-bit entries. For most systems, the default Rx elastic buffer depth is adequate to handle dispersion, jitter, and wander that can occur on the link while the system is running. However, the Receiver buffer depth parameter is available for cases in which additional depth is required.

1 Altera recommends that you set Receiver buffer depth to 4 in CPRI RE slave

variations, specifying a depth of 16 32-bit entries.

cpri_clkout

clock. The Rx elastic buffer data input is synchronous

clock from the transceiver. The width of an Rx elastic buffer entry

rx_clkout

clock clocks the transceiver data, which is 8, 16, or 32 bits

You must realign and resynchronize the Rx elastic buffer after a dynamic CPRI line rate change. Resynchronizing the Rx elastic buffer resets its pointers. Program the

CPRI_RX_DELAY_CTRL

The Rx elastic buffer adds variable delay to the Rx path through the CPRI IP core. Refer to “Extended Rx Delay Measurement” on page D–5.

Descrambling

If the

tx_prot_version

field of the

CPRI_TX_PROT_VER

page 7–12) holds the value 2, and the CPRI data rate is 4915.2 Mbps, 6144.0 Mbps, or

9830.4 Mbps, the low-level CPRI receiver may need to descramble the incoming data, depending on the values in the

When the

rx_scr_act_indication

CPRI_RX_SCR_SEED

field of the

CPRI_RX_SCR_SEED

on page 7–12) is set, the low-level CPRI receiver descrambles the data words

according to the CPRI V4.2 Specification, using the seed in the the

CPRI_RX_SCR_SEED

rx_scr_seed

field of

data is not scrambled.

Frame Synchronization

During frame synchronization, LOF is set to zero. LOS—the assertion of the signal—resets the frame synchronization state machine. Figure 4–26 shows the frame synchronization state machine. If scrambling is configured in the CPRI link partner (based on the value at Z.2.0 in the incoming CPRI communication), additional actions and conditions apply on the state machine transitions, according to the CPRI V4.2 Specification. The CPRI IP core sets the values in the

CPRI_RX_SCR_SEED

according to these conditions.

gxb_los

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–50 Chapter 4: Functional Description

XACQ1

XACQ2

XSYNC1

XSYNC2

HFNSYNC

W=X=0 and LOS=0 and

(Received K28.5 Byte when Y=0

and

Received Scrambled 0x50 Byte when Y=2..5)

W=X=0 and LOS=0 and

(Received K28.5 Byte when Y=0

and

Received Scrambled 0x50 Byte when Y=2..5)

W=X=0 and LOS=0 and

(Received K28.5 Byte when Y=0

and

Received Scrambled 0x50 Byte when Y=2..5)

Received K28.5 Byte/

Set Y:=W:=X:=0

W=X=0 and LOS=0 and

(Received K28.5 Byte when Y=0

and

Received Scrambled 0x50 Byte when Y=2..5)

LOS=1

B or LOS=1

LOF=1

LOF=0

Power Up or Reset

B or LOS=1

(2)

(3)

(2)

CPRI Protocol Interface Layer (Physical Layer)

Figure 4–26. CPRI Frame Synchronization Machine

(1)

Notes to Figure 4–26:

(1) If the tx_prot_version field of the CPRI_TX_PROT_VER register (Table 7–25 on page 7–12) holds the value 1, scrambling is not turned on. In this

case, the conditions when Y is in 2..5 are ignored. (2) LOS=1 returns the state machine to the XACQ1 state. This transition has highest priority. (3) Condition B is: Received byte not K28.5 when Y=W=X=0 or for some k in 2..5, received byte(unscrambled) not 0x50 when W=X=0 and Y=k.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Alarm Indications

The CPRI IP core can detect and report the following alarms:

■ Loss of signal (LOS)—the CPRI IP core reports this alarm in the

CPRI_STATUS

■ Loss of frame (LOF)—the CPRI IP core reports this alarm by resetting the

field of the

CPRI_STATUS

Your application detects the following alarms by reading the last received #Z.130.0 control byte in the

■ Remote alarm indication (RAI)

■ Service access point (SAP) defect indication (SDI) errors

■ Reset requests received over the CPRI link

CPRI_RX_CTRL

rx_los

field of the

rx_state

Chapter 4: Functional Description 4–51

CPRI Protocol Interface Layer (Physical Layer)

The frame synchronization machine detects LOS and LOF directly. You can program your application to detect and respond to RAI and SDI errors as appropriate. Refer to

“Accessing the Hyperframe Control Words” on page 4–39 for information about

retrieving these alarms from the hyperframe control word.

The CPRI IP core handles incoming reset requests on the CPRI link by signalling the application to assert the reset signal to reset the IP core. The application reads the requests using the CPU interface. The following section describes the additional support the CPRI IP core provides to process this special command.

Reset Control Word

A CPRI IP core in master clocking mode can send a reset request through the CPRI link and a CPRI IP core in slave clocking mode can receive a reset request through the CPRI link. As required by the CPRI specification, the reset control information is sent in bit 0 of the CPRI hyperframe control word Z.130.0. This reset bit communicates both reset request and reset acknowledge.

Tab le 4 –1 4 lists the signals and register fields that determine the CPRI IP core’s

response to a reset request received on the CPRI link and that determine whether it sends a reset request on the CPRI link.

Table 4–14. Conditions That Trigger a Reset Request or Enable a Reset Acknowledge on the CPRI Link

Name

CPRI_HW_RESET (Table 7–12)

hw_reset_assert (Table 6–15)

[0]

[1]

[3]

—— — 1

reset_gen_en reset_gen_force reset_hw_en

Trigger Conditions for Sending Reset

Request (Master) or ACK (Slave)

1—

A CPRI IP core in master mode transmits a reset request to the RE slave nodes to which it is connected under either of the trigger conditions shown in Table 4–14. The behavior of a CPRI IP core in slave mode that receives a reset request on the CPRI link depends on the same enable fields in its own

CPRI_HW_RESET

reset_gen_en

bit is ignored.

The CPRI specification requires that the Z.130.0 reset bit must be detected by the CPRI partner in ten consecutive hyperframes before the CPRI partner confirms the reset request. The reset generation request is in effect while the condition that triggered the reset request remains in effect, until the reset acknowledge control bit is detected on the incoming CPRI link.

To abort a reset request, set or reset a register field to negate the condition. Specifically, to abort a reset request made by asserting the

CPRI_HW_RESET

reset_gen_en

abort a reset request made by asserting the

reset_hw_en

bit of the

CPRI_HW_RESET

reset_gen_force

bit of the

CPRI_HW_RESET

hw_reset_assert

bit in the

input signal, set the

reset_hw_en

bit

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–52 Chapter 4: Functional Description

CPRI Protocol Interface Layer (Physical Layer)

To acknowledge the reset request, the CPRI transmitter must send a reset acknowledge on the CPRI link, by setting the Z.130.0 reset bit in five consecutive outgoing hyperframes. If one of the acknowledgement conditions in Table 4–14 holds, the CPRI transmitter sends the reset acknowledge on the CPRI link. If the

reset_out_en

external

bit of the

hw_reset_req

CPRI_HW_RESET

signal until the reset occurs. This signal informs the

application layer of the low-level reset request.

After it transmits the five consecutive reset acknowledge bits, the CPRI transmitter sets the register. If the set the

reset_gen_done

reset_hw_en

hw_reset_assert

and

reset_gen_done_hold

bit is set and the

hw_reset_req

bits of its own

CPRI_HW_RESET

signal is asserted, you must

signal, to tell the CPRI transmitter to send a reset

acknowledge on the CPRI link.

For more information about the

page 7–5. For more information about the Table 6–15 on page 6–17.

Transmitter

The transmitter in the low-level interface transmits output to the CPRI link. This module performs the following tasks:

■ Assembles data and control words in proper output format

■ Transmits standard frame sequence

■ Optionally scrambles the outgoing data transmission at 4915.2 Mbps,

■ Inserts the following control words in their appropriate locations in the outgoing

CPRI_HW_RESET

hw_reset_assert

input signal, refer to

6144.0 Mbps, and 9830.4 Mbps CPRI line rates

hyperframe:

■ Synchronization control byte (K28.5) and filler bytes (D16.2) in the

synchronization control word

■ Hyperframe number (HFN)

■ Basic frame number (BFN)

■ HDLC bit rate

■ Pointer to start of Ethernet data in current frame

■ 4B/5B-encoded fast C&M Ethernet frames

■ Bit-stuffed slow C&M HDLC frames

■ Enabled control transmit table entries

■ Converts the data to the transceiver clock domain.

When no data is available to transmit on the CPRI link, the transmitter transmits the standard frame sequence with zeroed control words and all-zero data.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 4: Functional Description 4–53

CPRI Protocol Interface Layer (Physical Layer)

Scrambling

When the

page 7–12) holds the value 2, the low-level CPRI transmitter scrambles the data words

according to the CPRI V4.2 Specification, using the seed in the the

tx_prot_version

CPRI_TX_SCR_SEED

field of the

CPRI_TX_PROT_VER

tx_scr_seed

field of

Tx Elastic Buffer

The low-level interface transmitter converts data from the main CPRI IP core clock domain and data width to the transceiver clock domain and data width using a synchronization FIFO called the Tx elastic buffer. The Tx elastic buffer data input is clocked with the

tx_clkout

the data bus to the transceiver is 8, 16, or 32 bits wide, depending on the target device family and the CPRI line rate. The CPRI IP core derives the the Tx output clock of the transceiver, divided as necessary to support the data width conversion to and from the 32-bit wide elastic buffers. Table 4–15 shows the data bus widths and clock divisors for the different device families and CPRI line rates.

Table 4–15. Transceiver Datapath Width and tx_clkout Divider

cpri_clkout

clock, and the buffer data output is clocked with the

clock from the transceiver. Data in the Tx elastic buffer is 32 bits wide, and

cpri_clkout

clock from

CPRI Line Rate

(Mbps)

614.4 All 8 4

Greater than 614.4

Device Family

Arria II GX, Cyclone IV GX 16 2

Arria II GZ, Arria V, Stratix IV GX, and Stratix V

Transceiver Datapath Width

(Bits)

32 1

tx_clkout Divider

High-Speed Transceiver

The transceiver transmitter implements 8B/10B encoding and the deterministic latency protocol. It transforms the 16-bit parallel input data to the Arria II GX or Cyclone IV GX transmitter, or 32-bit parallel input data to the Arria II GZ, Arria V, Stratix IV GX, or Stratix V transmitter, to 8-bit data before 8B/10B encoding. The 10bit encoded data is then serialized and sent to the CPRI link differential output pins.

The deterministic latency protocol is designed to meet the 16.276-ns round-trip delay measurement accuracy requirements R21 and R21A of the CPRI specification.

f For information about the high-speed transceiver blocks, refer to volume 2 of the

Arria II Device Handbook, to volume 2 of the Cyclone IV Device Handbook, or to volume 2 and volume 3 of the Stratix IV Device Handbook.

f For information about the Altera Deterministic Latency PHY IP core and the Altera

Native PHY IP core, refer to the Altera Transceiver PHY IP Core User Guide.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

4–54 Chapter 4: Functional Description

CPRI Protocol Interface Layer (Physical Layer)

CPRI MegaCore Function June 2012 Altera Corporation User Guide

This chapter describes the loopback and PRBS testing features of the CPRI IP core.

CPRI IP Core

CPRI Link

MAP

Module

PHY

Module

(1)

(2) (3)

CPRI Tx

CPRI Rx

Loopback Modes

The CPRI IP core supports multiple loopback modes to help you test your CPRI design. Figure 5–1 illustrates the supported loopback paths.

Figure 5–1. CPRI IP Core Supported Loopback Paths

5. Testing Features

Notes to Figure 5–1:

(1) External loopback mode to test a single CPRI REC master. (2) Internal reverse loopback mode configured in an RE slave’s (3) Internal reverse loopback mode configured in an RE slave’s

The following sections describe these loopback modes.

External Loopback

The CPRI IP core supports an external loopback configuration on the CPRI link. You can use this configuration to test the full Tx and Rx paths from an application, through the CPRI link, and back to the application.

The CPRI testbenches provided in your CPRI IP installation configure the DUT in this loopback mode. Refer to Chapter 8, Testbenches.

To configure this loopback mode, you connect a CPRI REC master ’s CPRI Tx interface to its CPRI Rx interface by physically connecting the CPRI IP core’s high-speed transceiver output pins to its high-speed transceiver input pins. As for any CPRI link, the connection medium must support the data rate requirements of the CPRI IP core. Altera recommends that you implement this type of loopback connection through an SFP cable.

Only an REC master can function correctly in a CPRI link external loopback configuration. An RE slave in external loopback configuration cannot achieve frame synchronization, because the CPRI Rx interface must lock on to the K28.5 character before the CPRI Tx interface can begin sending K28.5 characters. Therefore, no K28.5 character is ever transmitted on the RE slave loopback CPRI link.

CPRI_PHY_LOOP CPRI_CONFIG

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

5–2 Chapter 5: Testing Features

PRBS Generation and Validation

Internal Reverse Loopback

The CPRI IP core supports two different internal reverse loopback paths that you can configure in software in a CPRI RE slave, and multiple loopback modes along those paths. The following sections describe these modes.

Physical Layer Loopback Mode

In the physical layer reverse loopback mode, a CPRI RE slave sends CPRI frames of incoming CPRI data and control words from the PHY module back through the PHY module in outgoing CPRI communication. The PHY reverse loopback path is labeled

(2)

in Figure 5–1.

In this mode, the PHY reverse loopback path is active whether or not frame synchronization has been achieved. The path includes 8B10B encoding and decoding, but only enough core CPRI functionality to handle the transition from the receiver clock domain to the transmitter clock domain.

You configure a CPRI RE slave in physical layer loopback mode by setting the

loop_mode

this bit is set, the reverse loopback path through the CPRI Rx and Tx buffers is not active, irrespective of any setting that should activate that path.

bit in the

CPRI_PHY_LOOP

Reverse Loopback Through CPRI Rx and Tx Buffers

The CPRI IP core provides support for an additional, more comprehensive testing loopback path in several different modes. The testing loopback modes activate a reverse loopback path that sends incoming CPRI communication from the CPRI Rx buffer back through the CPRI Tx buffer and the PHY module to the CPRI link in outgoing CPRI communication. This testing loopback path is labeled

Several loopback modes are available on this reverse loopback path. You can specify that full CPRI frames, including all incoming CPRI data and control words, are sent back in outgoing CPRI communication. You can also specify that only data be looped back, or that only certain categories of control words be looped back. In these modes, the CPRI RE slave generates the remainder of the outgoing CPRI frame content locally.

You configure a CPRI RE slave in testing loopback mode by setting the appropriate value in the

page 7–3. The register description includes the full encodings to specify the different

loopback mode values.

loop_mode

field of the

PRBS Generation and Validation

The CPRI IP core supports generation and validation of several predetermined pseudo-random binary sequences (PRBS) for antenna-carrier interface and Rx and Tx path testing.

CPRI_CONFIG

(3)

in Figure 5–1.

1 The MAP interface module generates and checks the PRBS. If you configure no

antenna-carrier interfaces in your CPRI IP core, your IP core does not include a MAP block and therefore does not support PRBS testing.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 5: Testing Features 5–3

PRBS Generation and Validation

The value in the

prbs_mode

field of the

CPRI_PRBS_CONFIG

page 7–20) specifies whether the MAP interface module is in data mode or in PRBS

mode, and the generated pattern for loopback mode. The value applies to all AxC interfaces. The following

■ 00: Indicates that data samples, and not a PRBS test pattern, are expected on the

prbs_mode

values are available:

AxC interfaces. This value indicates the MAP interface module is not in PRBS mode.

■ 01: Indicates an incremental counter sequence, starting at zero at the start of a

10 ms radio frame, and counting to 255 before rolling over. The counter value appears in both halves of the 32-bit data word.

■ 10: Indicates an inverted 2

– 1 PRBS sequence. Each pattern appears in both

halves of the 32-bit data word.

The value 11 is reserved.

The

CPRI_PRBS_STATUS

detection status for each AxC interface.

You can perform PRBS testing with a single REC master across a CPRI link in loopback configuration, or across a CPRI link between two CPRI IP cores. To perform PRBS testing across a CPRI link between two CPRI IP cores, you must program the RE slave in reverse loopback mode and then program the REC master in PRBS mode.

To perform PRBS testing across a CPRI link, perform the following steps:

1. In the CPRI slave, program one of these registers to set up an internal reverse

loopback path:

■ Set the

loop_mode

field of the

CPRI_PHY_LOOP

page 5–1 and in Table 7–13 on page 7–6.

■ Set the

loop_mode

field of the

CPRI_CONFIG

register to the value of 2’b001 or 2’b010. The value of 2’b001 specifies that all data and control words are looped back. The value of 2’b010 specifies that all data is looped back, and that the CPRI RE slave generates the outgoing control words locally. The PRBS pattern is restricted to the data words in the incoming CPRI frame, so either of these two loopback modes is adequate to send the full PRBS pattern back to the generating CPRI REC master.

These loopback modes and the register are described in “Loopback Modes” on

page 5–1 and in Table 7–6 on page 7–3.

2. In the CPRI master, program the

prbs_mode

field of the

CPRI_PRBS_CONFIG

Table 7–44 on page 7–20.

The internal loopback mode you select determines the extent of the Rx and Tx path testing in the RE slave IP core. For information about the two internal reverse loopback modes and the differences between them, refer to “Loopback Modes” on

page 5–1.

To perform PRBS testing across a CPRI link in external loopback configuration, connect the CPRI IP core’s high-speed transceiver output to its high-speed transceiver input, and after the CPU interface is available for programming, perform step 2.

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

5–4 Chapter 5: Testing Features

PRBS Generation and Validation

Figure 5–2 shows the three different loopback modes that support PRBS testing.

Figure 5–2. CPRI IP Core Loopback Modes That Support PRBS Testing

RE SlaveREC Master

CPRI Link

MAP

Module

(1) (2) (3)

PHY

Module

Notes to Figure 5–2:

(1) External loopback mode to test a single CPRI REC master. (2) Internal reverse loopback mode (physical layer loopback mode) configured in the RE slave’s (3) Internal reverse loopback mode (testing loopback mode) configured in the RE slave’s

CPRI_CONFIG

CPRI_PHY_LOOP

MAP

Module

CPRI MegaCore Function June 2012 Altera Corporation User Guide

This chapter describes all the top-level signals of the Altera CPRI IP core.

MAP Interface Signals

Tab le 6 –1 and Tab le 6– 2 list the signals used by the MAP interface modules of the

CPRI IP core. The MAP interfaces are implemented as Avalon-ST interfaces.

f Refer to the Avalon Interface Specifications for details about the Avalon-ST interface.

MAP Receiver Signals

The behavior of many of the MAP receiver interface signals depends on the CPRI IP core’s current MAP Rx synchronization mode. The mode is determined by your selection in the CPRI parameter editor and by the (Table 7–31 on page 7–14), as shown in Table 4–6 on page 4–16.

CPRI_MAP_CONFIG

6. Signals

“MAP Receiver Interface” on page 4–15 includes a description of signal handshaking

in all three synchronization modes, and timing diagrams that illustrate the expected behavior of these signals.For a summary of signal availability in the different synchronization modes, refer to Table 4–8 on page 4–16.

Tab le 6 –1 lists the MAP receiver interface signals.

Table 6–1. MAP Receiver Interface Signals (Part 1 of 3)

Signal Direction Description

Clock signal for each antenna-carrier interface.

map{23…0}_rx_clk

map{23…0}_rx_reset

Input

These clocks are not supported in the internally-clocked mode. In the interally-clocked mode, interfaces.

Reset signal for each antenna-carrier interface in synchronous buffer mode and in FIFO mode. This reset is associated with the

mapN_rx_clk

These signals are not supported in the internally-clocked mode.

mapN_rx_reset

asserted at least one cycle of the associated clock and must be deasserted synchronously with that clock. Refer to Figure 4–5 on

page 4–10 for a circuit that shows how to enforce synchronous

deassertion of a reset signal.

cpri_clkout

clock.

can be asserted asynchronously, but must stay

clocks the antenna-carrier

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

6–2 Chapter 6: Signals

MAP Interface Signals

Table 6–1. MAP Receiver Interface Signals (Part 2 of 3)

Signal Direction Description

Read-ready signal for each antenna-carrier interface, in FIFO mode. Indicates to the CPRI IP core that the application is ready to receive data on the corresponding data channel in the next clock cycle. Asserted by the sink to mark ready cycles, which are cycles in which transfers can occur. If ready is asserted on cycle N, the cycle

map{23…0}_rx_ready

Input

(N+

READY_LATENCY

) is a ready cycle. The MAP receiver interface in

FIFO mode is designed for

READY_LATENCY

equal to 1.

In synchronous buffer mode, the application must hold the

mapN_rx_ready

signals high continuously.

In the internally-clocked mode, the CPRI IP core ignores this signal.

32-bit read data being transmitted on each antenna-carrier interface. Bits [15:0] are the I component of the IQ sample. Bits [31:16] are the Q component of the IQ sample.

In FIFO mode, data is valid as early as one

mapN_rx_clk

clock cycle

after the application asserts the read-ready input signal

map{23…0}_rx_data[31:0]

Output

mapN_rx_ready mapN_rx_valid signal

In synchronous buffer mode, data is valid one cycle after the application asserts the

, but is only valid while the CPRI IP core asserts the

mapN_rx_clk

mapN_rx_resync

clock

signal. To ensure valid data in synchronous buffer mode, the application should only assert the

cpri_rx_start

the

mapN_rx_resync

signal after the CPRI IP core asserts

signal. However, the CPRI IP core does not

enforce this requirement.

In the internally-clocked mode, data is valid one cycle after the CPRI IP core asserts the

mapN_rx_start

but is only valid while the CPRI IP core asserts the

signal

cpri_clkout

output signal,

mapN_rx_valid

clock

Valid signal for FIFO mode and for the internally-clocked synchronization mode.

In FIFO mode, this signal is asserted when the mapN Rx buffer

map{23…0}_rx_valid

Output

exceeds the threshold level in the

CPRI_MAP_RX_READY_THR

its own

map_rx_ready_thr

mapN_rx_valid

threshold value. This signal qualifies all the other

signal, all data channels use the same

output signals of the MAP receiver interface. On every rising edge of the clock at which

mapN_rx_valid

map_rx_ready_thr

field of the

is high,

mapN_rx_data

can be

sampled.

In the internally-clocked mode, the CPRI IP core asserts each

mapN_rx_valid

the corresponding

In synchronous buffer mode,the

signal one

cpri_clkout

mapN_rx_start

clock cycle after it asserts

signal.

map{23...0}_rx_valid

signals do not participate in data transfer synchronization, and the application should ignore these signals.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 6: Signals 6–3

MAP Interface Signals

Table 6–1. MAP Receiver Interface Signals (Part 3 of 3)

Signal Direction Description

Resynchronization signal for use in synchronous buffer mode. When this signal is asserted, the read pointer of the mapN Rx buffer is reset

map{23…0}_rx_resync

map{23…0}_rx_start

map{23…0}_rx_status_data[2:0]

Input

Output

to zero. This signal is synchronous to the

To ensure valid data in synchronous buffer mode, the application should only assert the asserts the not enforce this requirement.

In FIFO mode the in data transfer synchronization, and the CPRI IP core ignores these signals. In the internally-clocked mode, these signals are not present.

In the internally-clocked mode, the CPRI IP core asserts each

mapN_rx_start

corresponding antenna-carrier interface ( current 10 ms radio frame. This signal is synchronous with the

cpri_clkout

core also asserts the on the corresponding antenna-carrier interface.

In FIFO mode and in synchronous buffer mode, the

map{23...0}_rx_start

synchronization, and the application should ignore these signals.

This vector contains the following status bits:

[2]

[1]

[0]

cpri_rx_start

clock. When it asserts

cpri_map_rx_overflow

antenna-carrier interface. This signal is synchronous to the

cpri_clkout

buffer. This signal reflects the value in the appropriate bit of the

buffer_rx_overflow

cpri_map_rx_underflow

this antenna-carrier interface. This signal is synchronous to the

cpri_clkout

empty buffer. This signal reflects the value in the appropriate bit of the

buffer_rx_underflow

CPRI_IQ_RX_BUF_STATUS cpri_map_rx_en

is enabled. The value is determined in the

CPRI_IQ_RX_BUF_CONTROL

external logic for inactive AxC interfaces and to map interface clock gating to save power.

mapN_rx_resync

signal. However, the CPRI IP core does

map{23...0}_rx_resync

signal to indicate the start of valid data on the

mapN_rx_valid

signals do not participate in data transfer

: Rx FIFO overflow indicator for this

clock, and is asserted following a write to a full

field of the

clock, and is asserted following a read from an

: Indicates that this antenna-carrier interface

mapN_rx_clk

signal after the CPRI IP core

signals do not participate

mapN_rx_data

mapN_rx_start

signal and transmits valid data

CPRI_IQ_RX_BUF_STATUS

: Rx FIFO underflow indicator for

field of the

clock.

) in the

, the CPRI IP

MAP Transmitter Signals

The behavior of many of the MAP transmitter interface signals depends on the CPRI IP core’s current TX synchronization mode. The mode is determined by your selection in the CPRI parameter editor and by the

page 7–14), as shown in Table 4–9 on page 4–22.

“MAP Transmitter Interface” on page 4–21 includes a description of signal

handshaking in all three synchronization modes, and timing diagrams that illustrate the expected behavior of these signals. For a summary of signal availability in the different synchronization modes, refer to Table 4–11 on page 4–22.

June 2012 Altera Corporation CPRI MegaCore Function

CPRI_MAP_CONFIG

User Guide

6–4 Chapter 6: Signals

MAP Interface Signals

Tab le 6 –2 lists the MAP transmitter interface signals.

Table 6–2. MAP Transmitter Interface Signals (Part 1 of 2)

Signal Direction Description

Clock signal for each antenna-carrier interface.

map{23…0}_tx_clk

Input

These clocks are not supported in the internally-clocked mode. In the interally-clocked mode,

cpri_clkout

clocks the antenna-carrier interfaces.

Reset signal for each antenna-carrier interface in synchronous buffer mode and in FIFO mode. This reset is associated with the

mapN_tx_clk

clock.

These signals are not supported in the internally-clocked mode.

map{23…0}_tx_reset

Input

mapN_tx_reset

can be asserted asynchronously, but must stay asserted at least one cycle of the associated clock, and must be deasserted synchronously with that clock. Refer to Figure 4–5 on page 4–10 for a circuit that shows how to enforce synchronous deassertion of a reset signal.

Write-valid signal for each antenna-carrier interface. This signal qualifies all the other Avalon-ST input signals of the MAP transmitter interface. On every rising edge of the clock at which

mapN_tx_valid

is high, data is sampled by

the CPRI IP core.

map{23…0}_tx_valid

Input

In FIFO mode, the application can assert

mapN_tx_clk

the CPRI IP core asserts the

cycle immediately following a

mapN_tx_ready

antenna-carrier interface.

In synchronous buffer mode, the application must assert the

mapN_tx_valid

mapN_tx_resync

the

signal at the same time as or immediately after it asserts

resynchronization signal. However, Altera

mapN_tx_valid

mapN_tx_clk

in any

cycle in which

signal for the corresponding

recommends that the application assert these two signals simultaneously. Refer to “MAP Transmitter in Synchronous Buffer Mode” on page 4–24.

In the internally-clocked mode, the application must wait at least one

cpri_clkout

asserting the

cycle after the IP core asserts

mapN_tx_valid

signal;

READY_LATENCY

mapN_tx_ready

is 1.

before

32-bit write data from each antenna-carrier interface. Data is valid starting

map{23…0}_tx_data[31:0]

Input

mapN_tx_clk

one internally-clocked mode) after the write-valid bit is asserted. Bits [15:0] are

clock cycle (

cpri_clkout

clock cycle in the

the I component of the IQ sample. Bits [31:16] are the Q component of the IQ sample.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 6: Signals 6–5

Auxiliary Interface Signals

Table 6–2. MAP Transmitter Interface Signals (Part 2 of 2)

Signal Direction Description

Ready signal for each antenna-carrier interface.

In FIFO mode, the ready signal is asserted when the mapN Tx buffer falls

map{23…0}_tx_ready

map{23…0}_tx_resync

map{23…0}_tx_status_data

Output

Input

Output

below the threshold level in the

CPRI_MAP_TX_READY_THR mapN_tx_ready

threshold value. Indicates that the CPRI IP core is ready to receive data on the data channel in the current clock cycle. Asserted by the Avalon-ST sink to mark ready cycles, which are the cycles in which transfers can take place. If ready is asserted on cycle N, the cycle (N+

In the MAP transmitter interface in FIFO mode, 0, so the cycle on which

In the internally-clocked mode, the CPRI IP core asserts the ready signal one cycle before the antenna-carrier interface is ready to receive data on the data channel. In this mode,

In synchronous buffer mode, the participate in data transfer synchronization, and the application should ignore these signals.

Resynchronization signal for use in synchronous buffer mode. This signal is synchronous to the

In FIFO mode the data transfer synchronization, and the CPRI IP core ignores these signals. In the internally-clocked mode, these signals are not present.

This vector contains the following status bits:

[2]

cpri_map_tx_overflow

antenna-carrier interface. This signal is synchronous to the

cpri_clkout

buffer. This signal reflects the value in the appropriate bit of the

buffer_tx_overflow

[1]

cpri_map_tx_underflow

antenna-carrier interface. This signal is synchronous to the

cpri_clkout

buffer. This signal reflects the value in the appropriate bit of the

buffer_tx_underflow

[0]

cpri_map_tx_en

enabled. The value is determined in the register. Use this signal to disable external logic for inactive AxC interfaces and to map interface clock gating to save power.

signal, all data channels use the same

READY_LATENCY

mapN_tx_clk

map{23...0}_tx_resync

clock, and is asserted following a write to a full

clock, and is asserted following a read from an empty

map_tx_ready_thr

READY_LATENCY

mapN_tx_ready

map{23...0}_tx_ready

field of the

: Indicates that this antenna-carrier interface is

is asserted is the ready cycle.

is equal to 1.

clock.

: Tx FIFO overflow indicator for this

CPRI_IQ_TX_BUF_STATUS

: Tx FIFO underflow indicator for this

field of the

map_tx_ready_thr

) is a ready cycle.

READY_LATENCY

signals do not participate in

CPRI_IQ_TX_BUF_STATUS

CPRI_IQ_TX_BUF_CONTROL

is equal to

signals do not

Auxiliary Interface Signals

Tab le 6 –3 through Table 6–4 list the signals on the CPRI IP core auxiliary interface. All

the signals in Tab le 6 –3 through Table 6–4 are clocked by the internal clock visible on the

cpri_clkout

June 2012 Altera Corporation CPRI MegaCore Function

port.

User Guide

6–6 Chapter 6: Signals

Auxiliary Interface Signals

AUX Receiver Signals

Tab le 6 –3 lists the signals on the AUX receiver interface. For additional information

about these signals, refer to “AUX Receiver Module” on page 4–28.

Table 6–3. AUX Receiver Interface Signals

Signal Direction Bit Description

aux_rx_status_data [75:0]

Output [75]

[74]

[73]

[72:61]

[60:53]

[52:45]

[44:39]

[38:33]

[32]

[31:0]

cpri_rx_rfp

pulse occurs at the start of the radio frame on the CPRI receiver interface.

cpri_rx_start

interface, and can be used by an AxC software application to trigger the AxC-specific resynchronization signal used in the MAP interface synchronous buffer mode. The offset defined in the offset starts at the values set in the register. Refer to Table 7–39 on page 7–18. The signal is asserted for the duration of the basic frame.

cpri_rx_hfp

occurs at the start of the hyperframe on the CPRI receiver interface.

cpri_rx_bfn cpri_rx_hfn cpri_rx_x

hyperframe. Value is in the range 0–255.

cpri_rx_k

the AxC Container Block for mapping IQ samples when the

CPRI_MAP_CONFIG

map_mode

when

cpri_rx_seq

basic frame being transmitted on the AUX link. Depending on the CPRI line rate, this signal has the following range:

■ 614.4 Mbps line rate: range is 0 –3

■ 1228.8 Mbps line rate: range is 0–7

■ 2457.6 Mbps line rate: range is 0–15

■ 3072.2 Mbps line rate: range is 0–19

■ 4915.2 Mbps line rate: 0–31

■ 6144.0 Mbps line rate: 0–39

■ 9830.4 Mbps line rate: 0–63

cpri_rx_sync_state

synchronization have been achieved in CPRI receiver frame synchronization.

cpri_rx_aux_data

in 32-bit words. Byte [31:24] is transmitted first, and byte [7:0] is transmitted last.

: Synchronization pulse for start of 10 ms radio frame. The

: Indicates the start of the first basic frame on the AUX

cpri_rx_start

CPRI_START_OFFSET_RX

cpri_rx_rfp

cpri_rx_hfp

signal is asserted at the

pulse, depending on

: Synchronization pulse for start of hyperframe. The pulse

: Current radio frame number.

: Current hyperframe number. Value is in the range 0–149.

: Index number of the current basic frame in the current

: Sample counting K counter. Counts the basic frame position of

map_mode

field in

value is 00.

: Index number of the current 32-bit word in the current

: When set, indicates that Rx, HFN, and BFN

: Data transmitted on the AUX link. Data is transmitted

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 6: Signals 6–7

Auxiliary Interface Signals

AUX Transmitter Signals

Tab le 6 –4 lists the signals on the AUX transmitter interface. For additional

information about these signals, refer to “AUX Transmitter Module” on page 4–31.

Table 6–4. AUX Transmitter Interface Signals (Part 1 of 2)

Signal Direction Bits Description

aux_tx_status_data [43:0]

Output

[43]

[42:37]

[36:31]

[30:23]

[22:15]

[14:3]

[2]

[1]

[0]

cpri_tx_error cpri_tx_aux_mask[31:0]

character insertion in the outgoing CPRI frame (which occurs when Z=X=0).

cpri_tx_seq

two-cycle-offset basic frame to be received on the AUX link. Depending on the CPRI line rate, this signal has the following range:

■ 614.4 Mbps line rate: range is 0 –3

■ 1228.8 Mbps line rate: range is 0–7

■ 2457.6 Mbps line rate: range is 0–15

■ 3072.2 Mbps line rate: range is 0–19

■ 4915.2 Mbps line rate: 0–31

■ 6144.0 Mbps line rate: 0–39

■ 9830.4 Mbps line rate: 0–63

cpri_tx_k

of the AxC Container Block for mapping IQ samples when

CPRI_MAP_CONFIG

in the used when

cpri_tx_x

hyperframe. Value is in the range 0–255.

cpri_tx_hfn cpri_tx_bfn cpri_tx_hfp

occurs at the start of the hyperframe on the CPRI transmitter interface.

cpri_tx_start

interface, and can be used by an AxC software application to trigger the AxC-specific resynchronization signal used in MAP synchronous buffer mode. The

CPRI_START_OFFSET_TX cpri_tx_rfp

cpri_tx_rfp

pulse occurs at the start of the radio frame on the CPRI transmitter interface.

: Indicates that in the previous

cpri_clkout

cycle, the

mask bits were not deasserted during K28.5

: Index number of the current 32-bit word in the

: Sample counting K counter. Counts the basic frame position

map_mode

field

map_mode

value is 00.

: Index number of the current basic frame in the current

: Current hyperframe number. Value is in the range 0–149.

: Current radio frame number.

: Synchronization pulse for start of hyperframe. The pulse

: Indicates the start of the first basic frame on the AUX

cpri_tx_start

signal is asserted at the offset defined in the

cpri_tx_hfp

pulse, depending on values set in the

: Synchronization pulse for start of 10 ms radio frame. The

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

6–8 Chapter 6: Signals

Auxiliary Interface Signals

Table 6–4. AUX Transmitter Interface Signals (Part 2 of 2)

Signal Direction Bits Description

cpri_tx_sync_rfp

: Synchronization input used in REC master to control

the start of a new 10 ms radio frame. Asserting this signal resets the frame

[64]

synchronization machine. The CPRI IP core uses the rising edge of the pulse for synchronization. For information about the CPRI IP core response to a pulse on this signal, refer to Figure 4–20 on page 4–34 and surrounding text.

aux_tx_mask_data [64:0]

Input

[63:32]

cpri_tx_aux_data cpri_tx_seq

transmitted in 32-bit words. Byte [31:24] is transmitted first, and byte [7:0] is transmitted last.

cpri_tx_aux_mask cpri_tx_aux_data

: Data received on the AUX link, aligned with

with a delay of two

cpri_clkout

cycles. Data is

: Bit mask for insertion of data from

in the outgoing CPRI frame. Assertion of a bit in this mask overrides insertion of data to the corresponding bit in the outgoing CPRI frame from any other source. Therefore, the mask bits must be

[31:0]

deasserted during K28.5 character insertion in the outgoing CPRI frame, which occurs when Z=X=0. If you do not deassert the mask bits during K28.5 character insertion in the outgoing CPRI frame, the

cpri_tx_error

output signal is asserted in the following

cpri_clkout

cycle.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 6: Signals 6–9

Auxiliary Interface Signals

Extended Rx Status Signals

Tab le 6 –5 lists the signals on the extended Rx status interface. All of these signals

report on the status of the CPRI receiver frame synchronization machine.

Table 6–5. Extended Rx Status Signals

Signal Direction Bits Description

extended_rx_status_data [11:0]

Output

[11]

[10:8]

[7]

[6]

[5]

[4:2]

[1:0]

cpri_rx_los

bit reflects the value in the register (Table 7–4 on page 7–2).

cpri_rx_lcv

count in current clock cycle. This information enables CPRI link debug when the control word does not appear or is malformed.

cpri_rx_hfn_state

synchronization (HFN) has been achieved in CPRI receiver frame synchronization.

cpri_rx_bfn_state

synchronization (BFN) has been achieved in CPRI receiver frame synchronization.

cpri_rx_freq_alarm

frequency difference greater than four clock cycles between

cpri_clkout

receiver interface.

cpri_rx_cnt_sync

machine state number. Tracks the number of the current state in its state type. When the state machine is in state XACQ1, the value of

cpri_rx_cnt_sync cpri_rx_cnt_sync

Figure 4–26 on page 4–50.

cpri_rx_state

frame synchronization state machine. The following values are defined:

00 - LOS state

01 - XACQ state

10 - XSYNC state

11 - HFNSYNC state

In the HFNSYNC state (

cpri_rx_cnt_sync

been achieved, except for initialization of the hyperframe and basic frame numbers. You must wait for and

cpri_rx_bfn_state

hyperframe number and basic frame number are initialized.

: CPRI receiver LOS indication (active high). This

rx_los

field of the

: Current CPRI receiver 8B/10B line code violation

: When set, indicates that hyperframe

: When set, indicates that basic frame

: Frequency alarm. When set, indicates a

and the recovered received clock from the CPRI

: CPRI receiver frame synchronization state

cpri_rx_cnt_sync

has value 1; when the state is XSYNC1, has value 0; and so on. Refer to

: Indicates the type of state of the CPRI receiver

has value 0x1), Rx synchronization has

is 0; when the state is XACQ2,

cpri_rx_state

CPRI_INTR

has value 0x3 and

cpri_rx_hfn_state

to have value 1, indicating that the

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

6–10 Chapter 6: Signals

CPRI MII Signals

Tab le 6 –6 and Tab le 6– 7 list the signals used by the CPRI MII module of the CPRI IP

core. The CPRI MII is enabled if you turn off Include MAC block in the CPRI parameter editor. The CPRI MII signals are available only if you enable the CPRI MII. For information about the MII handshaking protocol implementation, refer to “Media

Independent Interface to an External Ethernet Block” on page 4–34.

CPRI MII Receiver Signals

Tab le 6 –6 lists the CPRI MII receiver signals.

Table 6–6. CPRI MII Receiver Interface Signals

Signal Direction Description

cpri_mii_rxclk

cpri_mii_rxwr

cpri_mii_rxdv

cpri_mii_rxer

cpri_mii_rxd[3:0]

Output Clocks the MII receiver interface. The

Ethernet write signal. Indicates the presence of a new K nibble or data value on

Output

cpri_mii_rxd[3:0]

cycle in which the K nibble or a new data value appears on

Ethernet receive data valid. Indicates the presence of valid data or initial K nibble on

cpri_mii_rxd[3:0]

Ethernet receive error. Indicates an error in the current nibble of indicates that the CPRI link is not initialized, and therefore an error might be present in the frame being transferred to the external Ethernet block. This signal is deasserted at reset, and asserted after reset until the CPRI IP core achieves frame synchronization.

Ethernet receive nibble data. Data bus for data from the CPRI IP core to the external Ethernet block. All bits are deasserted during reset, and all bits are asserted after reset until the CPRI IP core achieves frame synchronization.

. This signal is asserted during the first

cpri_clkout

clock drives this signal.

cpri_mii_rxclk

cpri_mii_rxd[3:0]

cpri_mii_rxd

CPRI MII Transmitter Signals

Tab le 6 –7 lists the CPRI MII transmitter signals. These signals are available if you

exclude the MAC block from the CPRI IP core.

Table 6–7. CPRI MII Transmitter Interface Signals (Part 1 of 2)

Signal Direction Description

cpri_mii_txclk

cpri_mii_txen

cpri_mii_txer

Output Clocks the MII transmitter interface. The

Valid signal from the external Ethernet block, indicating the presence of valid data on

Input

cpri_mii_txd[3:0]

block inserts J and K nibbles in the data stream to form the start-of-packet symbol. This signal is typically asserted one cycle after first cycle following the assertion of cpri_mii_txrd, if cpri_mii_txen is not yet asserted, the CPRI MII transmitter module inserts Idle cycles until the first cycle in which

cpri_mii_txen

deasserted while inserts the end-of-packet sequence.

Ethernet transmit coding error. When this signal is asserted, the CPRI IP core inserts an Ethernet HALT symbol in the data it passes to the CPRI link.

. This signal is also asserted while the CPRI MII transmitter

is asserted. If

cpri_mii_txrd

cpri_clkout

cpri_mii_txrd

cpri_mii_txen

remains asserted, the CPRI MII transmitter module

clock drives this signal.

is asserted. After that

is asserted and subsequently

CPRI MegaCore Function June 2012 Altera Corporation User Guide

Chapter 6: Signals 6–11

CPU Interface Signals

Table 6–7. CPRI MII Transmitter Interface Signals (Part 2 of 2)

Signal Direction Description

Ethernet transmit nibble data. The data transmitted from the external Ethernet block to

cpri_mii_txd[3:0]

cpri_mii_txrd

Input

Output

the CPRI IP core, for transmission on the CPRI link. This input bus is synchronous to the rising edge of the

Ethernet read request. Indicates that the MII block is ready to read data on

cpri_mii_txd[3:0] cpri_mii_txen

signal remains asserted for 2

cpri_mii_txen

asserted backpressures the external Ethernet block.

cpri_clkout

. Valid data is recognized 2

is asserted in response to

. Deasserting

clock.

cpri_mii_txclk

cpri_mii_txrd

cpri_mii_txclk

cpri_mii_txrd

cycles following deassertion of

while

cpri_mii_txen

cycles after

. The

cpri_mii_txrd

is still

CPU Interface Signals

Tab le 6 –8 lists the CPU interface signals. The CPU interface is implemented as an

Avalon-MM interface.

f Refer to the Avalon Interface Specifications for details about the Avalon-MM interface.

Table 6–8. CPU Interface Signals (Part 1 of 2)

Signal Direction Description

cpu_clk

cpu_reset

cpu_irq

cpu_irq_vector[4:0]

cpu_address[13:0]

cpu_write cpu_read

Input CPU clock signal.

Input

Output

Input

Input CPU write request.

Input CPU read request.

CPU peripheral reset. This reset is associated with the

cpu_reset

one Refer to Figure 4–5 on page 4–10 for a circuit that shows how to enforce synchronous deassertion of a reset signal.

Merged CPU interrupt indicator. This signal is the vector

This vector contains the following interrupt bits:

[4]

[3]

[2]

[1]

[0]

CPU word address. Corresponds to bits [15:2] of a byte address with LSBs 2’b00. If you connect an Avalon-MM interface to the CPU interface, connect bits [15:2] of the incoming Avalon-MM address to

can be asserted asynchronously, but must stay asserted at least

cpu_clk

cycle and must be de-asserted synchronously with

cpu_irq_vector

cpu_irq_cpri

the

of all three interrupt bits in the CPRI_INTR register.

cpu_irq_eth_rx cpu_irq_eth_tx cpu_irq_hdlc_rx cpu_irq_hdlc_tx

: Interrupt bit from

: Interrupt from the Ethernet receiver module.

: Interrupt from the Ethernet transmitter module.

: Interrupt from the HDLC receiver module.

: Interrupt from the HDLC transmitter module.

CPRI_INTR

cpu_clk

of all the bits in the

cpu_address

clock.

cpu_clk

June 2012 Altera Corporation CPRI MegaCore Function

User Guide

6–12 Chapter 6: Signals

Table 6–8. CPU Interface Signals (Part 2 of 2)

Signal Direction Description

CPU data byteenable signal. Enables specific byte lanes during transfers on

cpu_byteenable

and

cpu_readdata

cpu_byteenable[3:0]

cpu_writedata[31:0] cpu_readdata[31:0]

cpu_waitrequest

ports of width less than 32 bits. Each bit in the corresponds to a byte lane in significant bit of

Input

Input CPU write data.

Output CPU read data.

Output

data bus. The bit value 1 indicates an enabled byte lane, and the bit value 0 indicates a disabled byte lane. Enabled byte lanes must be adjacent: valid values of

For more information, refer to the definition of the byteenable signal in the Avalon-MM specification in the Avalon Interface Specifications.

Indicates that the CPU interface is busy executing an operation. When this signal is deasserted, the operation is complete and the data is valid.

cpu_byteenable

cpu_writedata

cpu_byteenable

include only a single sequence of 1’s.

corresponds to the lowest byte of each

Physical Layer Signals

signal

. The least

Physical Layer Signals

Tab le 6 –9 through Table 6–14 list the input and output signals of the physical layer of

the CPRI IP core. Refer to Figure 4–25 on page 4–47 for details of the I/O signals.

CPRI Data Signals

Tab le 6 –9 lists the CPRI data link signals.

Table 6–9. CPRI Protocol Interface

Signal Direction Description

gxb_rxdatain

gxb_txdataout

Input

Output

Receive unidirectional serial data. This signal is connected over the CPRI link to the

txdataout

Transmit unidirectional serial data. This signal is connected over the CPRI link to the

rxdatain

line of the transmitting device.

line of the receiving device.

Layer 1 Clock and Reset Signals

Tab le 6 –1 0 lists the layer 1 clock and reset signals.

Table 6–10. CPRI Reference Clock and Main Reset Signals

Signal Direction Description

gxb_refclk

reset

reset_done

Input

Output Indicates that the reset controller has completed the transceiver reset sequence.

Transceiver reference clock. In master clocking mode, this clock generates the internal clock

cpri_clkout

Transceiver reset. This reset is associated with the module propagates this reset to the CPRI IP core

reset

can be asserted asynchronously, but must stay asserted at least one clock cycle and must be de-asserted synchronously with the clock with which it is associated. Refer to

Figure 4–5 on page 4–10 for a circuit that shows how to enforce synchronous deassertion

reset

for the CPRI IP core and custom logic.

reconfig_clk

cpri_clkout

clock. A reset controller

clock domain as well.

CPRI MegaCore Function June 2012 Altera Corporation User Guide

ALTERA CPRI User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

1. About This MegaCore Function

General Description

CPRI IP Core Features

Device Family Support

MegaCore Verification

Performance and Resource Utilization

Release Information

Installation and Licensing

OpenCore Plus Evaluation

OpenCore Plus Time-Out Behavior

MegaWizard Plug-In Manager Design Flow

2. Getting Started

Specifying Parameters

Simulation Files

Simulating the Design

Specifying Constraints

Compiling and Programming the Device

Instantiating Multiple CPRI IP Cores

3. Parameter Settings

Physical Layer Parameters

Operation Mode Parameter

Line Rate Parameter

Enable Autorate Negotiation

Transceiver Starting Channel Number

Rx Elastic Buffer Depth

Transceiver Reference Clock Frequency

Data Link Layer Parameters

Include MAC Block

Include HDLC Block

Application Layer Parameters

Mapping Mode

Number of Antenna-Carrier Interfaces

Enable Internally-Clocked Synchronization Mode

4. Functional Description

Architecture Overview

Clocking Structure

CPRI IP Core Clocks

Clock Diagrams for the CPRI IP Core

Clock Diagrams for Most CPRI IP Core Variations

Clock Diagram for CPRI IP Core Arria V GT Variations at 9830.4 Mbps

CPRI Communication Link Line Rates

Reset Requirements

MAP Interface

MAP Interface Mapping Modes

Basic AxC Mapping Mode

Advanced AxC Mapping Modes

MAP Receiver Interface

MAP Receiver Interface Signals in Different Synchronization Modes

MAP Receiver in FIFO Mode

MAP Receiver in Synchronous Buffer Mode

MAP Receiver in the Internally-Clocked Mode

MAP Transmitter Interface

MAP Transmitter Interface Signals in Different Synchronization Modes

MAP Transmitter in FIFO Mode

MAP Transmitter in Synchronous Buffer Mode

MAP Transmitter in the Internally-clocked Mode

Auxiliary Interface

AUX Receiver Module

AUX Transmitter Module

Media Independent Interface to an External Ethernet Block

MII Transmitter

MII Receiver

CPU Interface

Accessing the Hyperframe Control Words

Recording and Retrieving the Incoming Control Bytes

Writing the Outgoing Control Bytes

Control Word Order

Control Word Transmission Example

Control Word Retrieval Example

Accessing the Ethernet Channel

Transmitting Ethernet Traffic

Receiving Ethernet Traffic

Accessing the HDLC Channel

CPRI Protocol Interface Layer (Physical Layer)

Features