Altera ASI MegaCore Function User Manual
Asynchronous Serial Interface (ASI) MegaCore Function
User Guide
Asynchronous Serial Interface (ASI) MegaCore Function
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
c The ASI MegaCore function is scheduled for product obsolescence and discontinued
support as described in PDN1306. Therefore, Altera does not recommend use of this IP
in new designs. For more information about Altera’s current IP offering, refer to Altera’s
Intellectual Property website.
UG-ASI0106-13.1
Document last updated for Altera Complete Design Suite version:
Document publication date:
January 2014
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Asynchronous Serial Interface (ASI) MegaCore Function User Guide January 2014 Altera Corporation
Contents
Chapter 1. About This MegaCore Function
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Chapter 2. Getting Started
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Simulate with IP Functional Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Simulate with the ModelSim Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Simulating in Third-Party Simulation Tools Using NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Compile the Design and Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Chapter 3. Parameter Settings
Chapter 4. Functional Description
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
8B10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
GX Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
GX Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Oversampling Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Word Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
8B10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Synchronization State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Packet Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Appendix A. Constraints
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Constraint Design With TimeQuest Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Specify Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Define the Setup and Hold Relationship between the 135-MHz Clocks and the 337.5-MHz
zero-degree Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Specify Clocks that are Exclusive or Asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
Minimize Timing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
January 2014 Altera Corporation Asynchronous Serial Interface (ASI) MegaCore Function User Guide
iv ContentsContents
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
Asynchronous Serial Interface (ASI) MegaCore Function User Guide January 2014 Altera Corporation
The Altera® Asynchronous Serial Interface (ASI) MegaCore® function implements a
receiver or transmitter digital video broadcast asynchronous serial interface
(DVB-ASI) that transports MPEG-2 packets over copper-based cables or optical
networks. DVB-ASI is used as a serial link between equipment in broadcast facilities.
Release Information
Tab le 1– 1 provides information about this release of the ASI MegaCore function.
Table 1–1. Release Information
Version 13.1
Release Date November 2013
Ordering Code IP-ASI
Product ID 00B9
Vendor ID 6AF7
1. About This MegaCore Function
Item Description
f For more information about this release, refer to the MegaCore IP Library Release Notes
and Errata.
Altera verifies that the current version of the Quartus
previous version of each MegaCore function. The MegaCore IP Library Release Notes
and Errata report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release.
Device Family Support
MegaCore functions provide the following support for Altera device families:
■ Preliminary support—Altera verifies the IP core with preliminary timing models for
this device family. The core meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be used in production
designs with caution.
■ Final support—Altera verifies the IP core with final timing models for this device
family. The core meets all functional and timing requirements for the device family
and can be used in production designs.
Tab le 1– 2 shows the level of support offered by the ASI MegaCore function to each
Altera device family.
Table 1–2. Device Family Support (Part 1 of 2)
®
II software compiles the
Device Family Support
®
II GX Preliminary
Arria
®
Cyclone
January 2014 Altera Corporation Asynchronous Serial Interface (ASI) MegaCore Function User Guide
III Final
1–2 Chapter 1: About This MegaCore Function
Table 1–2. Device Family Support (Part 2 of 2)
Device Family Support
Cyclone III LS (1) Preliminary
Cyclone IV GX (2) Preliminary
Cyclone IV E (1.2V) Preliminary
®
III (1) Final
Stratix
Stratix IV (3) Final
Other device families No support
Notes to Table 1–2:
(1) The Cyclone series of devices and the Stratix III devices only support soft SERDES.
(2) Cyclone IV GX support includes all density in the device family except the EP4CGX15, EP4CGX22, and EP4CGX30
(excluding the EP4CGX30F484 pin package) devices.
(3) Stratix IV GT only supports soft logic mode.
Features
Features
This section summarizes the features of the ASI MegaCore function.
■ IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
■ Easy-to-use MegaWizard
■ Support for OpenCore Plus evaluation
General Description
The ASI MegaCore function demonstrates how to transmit or receive packets over an
ASI. The ASI MegaCore function works with 270 megabits per second (Mbps) DVBASI, as defined by the DVB-ASI specification EN 50083-9 from CENELEC / December
2002 “Cable networks for television signals, sound signals and interactive services. Part 9:
Interfaces for CATV/SMATV head-ends and similar professional equipment for DVB/MPEG2
transport streams”.
f For information on ASI MegaCore function demonstration on the Altera Cyclone
Video Demonstration Board, refer to the Cyclone Video Demonstration Board Data Sheet.
MegaCore Verification
The ASI MegaCore verification involves the testing of the DVB-ASI specification
EN 50083-9 from CENELEC / December 2002 “Cable networks for television signals, sound
signals and interactive services. Part 9: Interfaces for CATV/SMATV head-ends and similar
professional equipment for DVB/MPEG2 transport streams”.
TM
interface
Asynchronous Serial Interface (ASI) MegaCore Function User Guide January 2014 Altera Corporation
Chapter 1: About This MegaCore Function 1–3
Resource Utilization
Resource Utilization
Tab le 1– 3 shows estimated resource usage for the ASI MegaCore function, with the
Quartus II software version 13.1.
Table 1–3. Resource Usage
Device Family Parameters LEs
Cyclone III
Cyclone III LS
Cyclone IV GX
Stratix III
Stratix IV
Installation and Licensing
The ASI MegaCore function is part of the MegaCore IP Library, which is distributed
with the Quartus II software and downloadable from the Altera website,
www.altera.com.
f For system requirements and installation instructions, refer to Altera Software
Installation & Licensing.
Combinational
ALUTs
Receiver 577 — —
Transmitter 78 — —
Receiver 587 — —
Transmitter 78 — —
Receiver 564 — —
Transmitter 78 — —
Receiver — 321 241
Transmitter — 47 49
Receiver — 328 191
Transmitter — 65 62
Logic
Registers
January 2014 Altera Corporation Asynchronous Serial Interface (ASI) MegaCore Function User Guide
1–4 Chapter 1: About This MegaCore Function
example
Contains an example design, see AN 344: ASI Demonstration.
ip
Contains the Altera MegaCore IP Library and third-party IP cores.
<path>
Installation directory.
altera
Contains the Altera MegaCore IP Library.
common
Contains shared components.
asi
Contains the ASI MegaCore function files.
lib
Contains encrypted lower-level design files and other support files.
simulation
Contains simulation files.
asi_mc_build
Contains the MegaCore function function files for the testbench.
ts_packet_gen
Contains the TS packet generator files for the testbench.
modelsim
Contains the Altera MegaCore IP Library and third-party IP cores.
modelsim
Contains the Modelsim simulation files.
testbench
Contains the testbench files.
quartus
Contains the Quartus II NativeLink project.
Installation and Licensing
Figure 1–1 on page 1–4 shows the directory structure after you install the ASI
MegaCore function, where
<
path> is the installation directory. The default installation
directory on Windows is c:\altera\<version>; on Linux it is /opt/altera<version>.
Figure 1–1. Directory Structure
Asynchronous Serial Interface (ASI) MegaCore Function User Guide January 2014 Altera Corporation
OpenCore Plus Evaluation
You need to obtain a license for the MegaCore function only when you are completely
satisfied with its functionality and performance, and want to take your design to
production.
After you obtain a license for ASI, you can request a license file from the Altera web
site at www.altera.com/licensing and install it on your computer. When you request a
license file, Altera emails you a license.dat file. If you do not have Internet access,
contact your local Altera representative.
With Altera’s free OpenCore Plus evaluation feature, you can perform the following
actions:
■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP
megafunction) within your system
■ Verify the functionality of your design, as well as evaluate its size and speed
quickly and easily
SM
Chapter 1: About This MegaCore Function 1–5
Installation and Licensing
■ Generate time-limited device programming files for designs that include
megafunctions
■ Program a device and verify your design in hardware
You only need to obtain a license for the megafunction when you are completely
satisfied with its functionality and performance, and want to take your design to
production.
f For more information on OpenCore Plus hardware evaluation using the ASI, refer to
AN 320: OpenCore Plus Evaluation of Megafunctions.
OpenCore Plus Time-Out Behavior
OpenCore Plus hardware evaluation can support the following two modes of
operation:
■ Untethered—the design runs for a limited time
■ Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely
All megafunctions in a device time out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction’s time-out behavior may be masked by the time-out behavior of
the other megafunctions.
1 For MegaCore functions, the untethered time-out is 1 hour; the tethered time-out
value is indefinite.
Your design stops working after the hardware evaluation time expires and the
rst
signal goes high.
January 2014 Altera Corporation Asynchronous Serial Interface (ASI) MegaCore Function User Guide
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