Altera Arria V SoC Development Board User Manual

Arria V SoC Development Board Reference Manual

Arria V SoC Development Board

Reference Manual

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www.altera.com

MNL-01080-1.2

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© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

The Arria V SoC development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Arria V SoC. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V SoC designs.

f For more information about the Arria V device family, refer to the Arria V Device

Handbook.

Board Component Blocks

1. Overview

The development board features the following major component blocks:

■ One Arria V SoC (5ASTFD5K3F40I3) in a 1517-pin FBGA package

■ FPGA configuration circuitry

■ Active Serial (AS) x1 or x4 configuration (EPCQ256SI16N)

■ MAX

®

V CPLD (5M2210ZF256) in a 256-pin FBGA package as the System

Controller

■ Flash fast passive parallel (FPP) configuration

■ MAX II CPLD (EPM570GF100) as part of the on-board USB-Blaster

with the Quartus

■ Clocking circuitry

■ Si570, Si571, and Si5338 programmable oscillators

■ 50-MHz, 66-MHz, 100-MHz, 125-MHz programmable oscillators

■ SMA input (LVCMOS)

®

II Programmer

TM

II for use

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Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

■ Memory

■ One 1,024-Mbyte (MB) HPS DDR3 SDRAM with error correction code (ECC)

support

■ Two 1,024-MB FPGA DDR3 SDRAM

■ One 512-Megabit (Mb) quad serial peripheral interface (QSPI) flash

■ One 512-Mb CFI synchronous flash

■ One 256-Mb NOR flash (EPCQ device)

■ One 32-Kilobit (Kb) I

■ One Micro SD flash memory card

■ Communication Ports

■ One PCI Express x4 Gen1/Gen2 socket

■ Two FPGA mezzanine card (FMC) ports

■ One USB 2.0 on-the-go (OTG) port

■ One Gigabit Ethernet port

2

C serial electrically erasable PROM (EEPROM)

■ Two 10/100 Ethernet ports

■ Two S F P+ po rt s

■ Two RS-232 UART (through the mini-USB port)

■ One real-time clock

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ General user input/output

■ LEDs and displays

■ Eight user LEDs

■ One configuration load LED

■ One configuration done LED

■ One error LED

■ Three configuration select LEDs

■ Four on-board USB-Blaster II status LEDs

■ Two FMC interface LEDs

■ Two UART data transmit and receive LEDs

■ One power on LED

■ One two-line character LCD display

■ Push buttons

■ One CPU reset push button

■ One MAX V reset push button

■ One program select push button

■ One program configuration push button

■ Eight general user push buttons

■ DIP switches

■ One JTAG chain control DIP switch

■ One board settings DIP switch

■ One FPGA configuration mode DIP switch

■ One general user DIP switch

■ Power supply

■ 14–20-V (laptop) DC input

■ Mechanical

■ 7.175" × 9" rectangular form factor

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Reference Manual

1–4 Chapter 1: Overview

DDR3 1GB

533 MHz (x32)

DDR3 1GB

533 MHz (x32)

Clock

Cleaner

Jitter

Clean Up

Buttons

Switches

LEDs

Buttons

Switches

LEDs

CSEL BSEL

HMC

10/100 Dual

Ethernet PHY

SFP+ x2

FMC x2

MAX V

CPLD

PCIe Gen2

x4

Parallel

Configuration

Flash

DDR3 1GB

533 MHz + ECC

QSPI Flash

256 MB

Micro SD Card

USB 2.0

OTG PHY

10/100/1000

Ethernet PHY

UART to USB

I2C

Powe r

Management

Measurement

Serial

EPROM

RTC

2x16

Character

LCD

MAC Address

Storage

FPGA HPS

JTAG JTAG

USB-Blaster II USB 2.0

MAX II

CPLD

Mictor

Connector

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Arria V SoC development board.

Figure 1–1. Arria V SoC Development Board Block Diagram

Handling the Board

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

anti-static handling precautions when touching the board.

2. Board Components

This chapter introduces the major components on the Arria V SoC development board. Figure 2–1 illustrates the component locations and Tab le 2– 1 provides a brief description of all component features of the board.

1 A complete set of schematics, a physical layout database, and fabrication files for the

development board reside in the Arria V SoC development kit board design files directory.

f For information about powering up the board and installing the demonstration

software, refer to the Arria V SoC Development Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Arria V SoC” on page 2–5

■ “MAX V CPLD 5M2210 System Controller” on page 2–5

■ “FPGA Configuration” on page 2–10

■ “General User Input/Output” on page 2–19

■ “Clock Circuitry” on page 2–21

■ “Components and Interfaces” on page 2–23

■ “Memory” on page 2–39

■ “Power Supply” on page 2–53

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

2–2 Chapter 2: Board Components

Board Overview

This section provides an overview of the Arria V SoC development board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features.

Figure 2–1. Overview of the Arria V SoC Development Board

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U41 FPGA Arria V SoC, 5ASTFD5K3F40I3, 1517-pin FBGA.

U27 CPLD MAX V CPLD, 5M2210ZF256, 256-pin FBGA.

Configuration, Status, and Setup Elements

J35 JTAG chain header

SW4 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.

J50 Mini-USB header

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Provides access to the JTAG chain and disables the On-board USB-Blaster II when using an external USB-Blaster cable.

USB interface for FPGA programming and debugging through the Onboard USB-Blaster II JTAG via a type-B USB cable.

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Board Components (Part 2 of 3)

Board Reference Type Description

Controls the MAX V CPLD 5M2210 System Controller functions such

SW2 Board settings DIP switch

as clock enable, SMA clock input control, and which image to load from flash memory at power-up.

SW3 MSEL DIP switch

S13 Program select push button

S12 Configure push button

Controls the configuration scheme on the board. MSEL pins 0, 1, 2, 3, and 4 connects to the DIP switch.

Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA.

Load image from flash memory to the FPGA based on the settings of the program select LEDs.

D38 Configuration done LED Illuminates when the FPGA is configured.

D40 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.

D39 Error LED Illuminates when the FPGA configuration from flash memory fails.

D37 Power LED Illuminates when 5.0-V power is present.

Indicate the transmit or receive activity of the JTAG chain. The TX and

D35, D36 JTAG TX/RX LEDs

RX LEDs would flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle.

Illuminates to show which flash memory image loads to the FPGA

D41–D43 Program select LEDs

when you press the program select push button. Refer to Table 2–5 for the LED settings.

D8, D20 FMC port present LEDs Illuminates when a daughter card is plugged into the FMC port.

D21–D24 UART LEDs Illuminates when UART transmitter and receiver are in use.

Clock Circuitry

Si570 programmable oscillator with a default frequency of 100 MHz.

X2 Programmable oscillator

The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

Si571 programmable oscillator with a default frequency of 148.5 MHz.

X3 148.5-MHz oscillator

The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

X5 125-MHz oscillator 125.000-MHz crystal oscillator for general purpose logic.

J15 Clock input SMA connector Drive LVCMOS-compatible clock input into the dedicated clock pin.

J49 HPS SMA clock Drive LVCMOS to HPS clock multiplexer.

U35 Multi-output oscillator

Si5338A quad-output fixed oscillator with 25M, 25M, 100M, and 100M outputs.

General User Input/Output

D9–D16 User LEDs Four user LEDs and four HPS LEDs. Illuminates when driven low.

SW1 User DIP switch User DIP switch. When the switch is ON, a logic 0 is selected.

S14 CPU reset push button Reset the FPGA logic.

S11 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.

S1–S8 General user push buttons

Four user push buttons and four HPS push buttons. Driven low when pressed.

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2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Board Components (Part 3 of 3)

Board Reference Type Description

Memory Devices

U29, U37, U43, U49,

U38, U44, U51

DDR3 SDRAM

Four 128-MB DDR3 SDRAM with a 16-bit data bus for the FPGA and three 128-MB DDR3 SDRAM with a 16-bit data plus ECC bus for the HPS.

U19 QSPI flash 1-Gb serial NOR flash with 4-bit data bus.

U28 EPCQ flash

U13 Synchronous flash

2

U31 I

C EEPROM 32-Kb I2C serial EEPROM.

128-Mb synchronous flash devices with a 16-bit data bus for non-volatile memory.

Communication Ports

J42 PCI Express socket PCI Express Gen1/Gen2 ×4 socket.

J4, J26 FMC port Two FMC ports

J43, J44 SFP+ port Two SFP+ ports

RJ-45 connectors which provides a 10/100/1000 Ethernet connection

U7, J13 Gigabit Ethernet port

via a Micrel KSZ9021RN PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode (for HPS).

U55, J47, J48 Dual Ethernet port

J22, U25

J27, U36

USB-UART ports USB connector with USB-to-UART bridge for serial UART interface.

RJ-45 connector which provides a 10/100 Ethernet connection via a Renesas uPD60620 PHY in MII mode (for FPGA).

J1, U4 USB OTG port USB 2.0 on-the-go interface.

DS1339 device with built-in power sense circuit that detects power

U11 Real-time clock

failures and automatically switches to backup battery supply, maintaining time.

J5 Micro SD card socket Micro SD card interface with 4-bit data line.

Video and Display Ports

J29 Character LCD

Connector that interfaces to a provided 16 character × 2 line LCD module along with two standoffs.

Power Supply

J34 DC input jack Accepts 16-V DC power supply.

SW5 Power switch

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Switch to power on or off the board when power is supplied from the DC input jack.

Chapter 2: Board Components 2–5

Featured Device: Arria V SoC

The Arria V SoC development board features a Arria V SoC 5ASTFD5K3F40I3 device (U41) that includes a hard processor system (HPS) with integrated ARM

®

Cortex®-A9

MPCore processor.

f For more information about Arria V device family, refer to the Arria V Device

Handbook.

Tab le 2– 2 describes the features of the Arria V SoC device.

Table 2–2. Arria V SoC Features

Resource 5ASTFD5K3F40I3

LE (K) 462

ALM 174,340

Register 697,360

Memory (Kb)

18-bit × 18-bit Multiplier 2,180

PLLs

Transceivers

M10K 22,820

MLAB 2,658

FPGA 14

HPS 3

6 Gbps 30

10 Gbps 16

I/O Resources

The Arria V SoC 5ASTFD5K3F40I3 device has 540 general purpose FPGA I/O pins and 210 general purpose HPS I/O pins.

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210ZF256 System Controller, an Altera MAX V CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Control and status registers (CSR) for remote system update

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

2–6 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram

MAX V CPLD System Controller

PC

Embedded

USB-Blaster II

Encoder

JTAG Control

SLD-HUB

Virtual-JTAG

Decoder

Information

Register

Control

Register

PFL

SPI Bus

FPGA

GPIO

LTC 2978

Power

Controllers

2

C

I

Controller

Tab le 2– 3 lists the I/O signals present on the MAX V CPLD System Controller. The

signal names and functions are relative to the MAX V device.

Table 2–3. MAX V CPLD System Controller Device Pin-Out (Part 1 of 5)

Board

Reference (U27)

B9

E9

J5

J12

D10

N11

T13

T15

A2

R14

N12

F11

N14

D14

P15

P14

D13

N15

E14

Schematic Signal Name I/O Standard Description

CLK125A_EN

CLK50_EN

CLK_100M_MAX

CLK_50M_MAX

CPU_RESETN

EXTRA_SIG0

EXTRA_SIG1

EXTRA_SIG2

FACTORY_LOAD

FACTORY_REQUEST

FACTORY_STATUS

FLASH_ADVN

FLASH_CEN0

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FM_A0

2.5-V 125 MHz oscillator enable

2.5-V 50 MHz oscillator enable

2.5-V 100 MHz clock input

1.8-V 50 MHz clock input

2.5-V FPGA reset push button

1.5-V On-board USB-Blaster II interface. Reserved for future use

2.5-V DIP switch to load factory or user design at power-up

1.5-V On-board USB-Blaster II request to send FACTORY command

1.5-V On-board USB-Blaster II FACTORY command status

1.8-V FSM bus flash memory address valid

1.8-V FSM bus flash memory chip enable

1.8-V FSM bus flash memory clock

1.8-V FSM bus flash memory output enable

1.8-V FSM bus flash memory ready

1.8-V FSM bus flash memory reset

1.8-V FSM bus flash memory write enable

1.8-V FM address bus

Oscillator Controller

Si570, Si571,

Si5338

Programmable

Oscillator

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–7

MAX V CPLD 5M2210 System Controller

Table 2–3. MAX V CPLD System Controller Device Pin-Out (Part 2 of 5)

Board

Reference (U27)

C14

C15

E13

E12

D15

F14

D16

F13

E15

E16

F15

G14

F16

G13

G15

G12

G16

H14

H15

H13

H16

J13

J16

K12

M14

N13

J14

J15

K16

K13

K15

K14

L16

L11

L15

L12

M16

L13

M15

Schematic Signal Name I/O Standard Description

FM_A1

FM_A2

FM_A3

FM_A4

FM_A5

FM_A6

FM_A7

FM_A8

FM_A9

FM_A10

FM_A11

FM_A12

FM_A13

FM_A14

FM_A15

FM_A16

FM_A17

FM_A18

FM_A19

FM_A20

FM_A21

FM_A22

FM_A23

FM_A24

FM_A25

FM_A26

FM_D0

FM_D1

FM_D2

FM_D3

FM_D4

FM_D5

FM_D6

FM_D7

FM_D8

FM_D9

FM_D10

FM_D11

FM_D12

1.8-V FM address bus

1.8-V FM data bus

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2–8 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–3. MAX V CPLD System Controller Device Pin-Out (Part 3 of 5)

Board

Reference (U27)

L14

N16

M13

M3

N2

K1

D3

C2

C3

E3

D2

E4

D1

E5

F3

E1

F4

F2

F1

F6

G2

G3

N3

J3

N1

J4

H1

P2

E2

F5

B11

M1

M2

L6

M5

N4

P3

P11

Schematic Signal Name I/O Standard Description

FM_D13

FM_D14

FM_D15

FMC_C2M_PG

FMCB_C2M_PG

FPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D1

FPGA_CONFIG_D2

FPGA_CONFIG_D3

FPGA_CONFIG_D4

FPGA_CONFIG_D5

FPGA_CONFIG_D6

FPGA_CONFIG_D7

FPGA_CONFIG_D8

FPGA_CONFIG_D9

FPGA_CONFIG_D10

FPGA_CONFIG_D11

FPGA_CONFIG_D12

FPGA_CONFIG_D13

FPGA_CONFIG_D14

FPGA_CONFIG_D15

FPGA_CVP_CONFDONE

FPGA_DCLK

FPGA_NCONFIG

FPGA_NSTATUS

FPGA_PR_DONE

FPGA_PR_ERROR

FPGA_PR_READY

FPGA_PR_REQUEST

HPS_RESETN

I2C_SCL_MAX

I2C_SDA_MAX

JTAG_MAX_TDI

JTAG_MAX_TDO

JTAG_MAX_TMS

JTAG_MUX_TCK

M570_CLOCK

1.8-V FM data bus

2.5-V FMC port A power good output

2.5-V FMC port B power good output

2.5-V FPGA configuration done LED

2.5-V FPGA configuration data

2.5-V FPGA Configuration via Protocol (CvP) done

2.5-V FPGA configuration clock

2.5-V FPGA configuration active

2.5-V FPGA configuration ready

2.5-V FPGA partial reconfiguration done

2.5-V FPGA partial reconfiguration error

2.5-V FPGA partial reconfiguration ready

2.5-V FPGA partial reconfiguration request

2.5-V HPS reset push button

2.5-V Programmable oscillator I2C clock

2.5-V Programmable oscillator I2C data

2.5-V JTAG chain data in

2.5-V JTAG chain data out

2.5-V JTAG chain mode

2.5-V JTAG chain clock

1.5-V

25-MHz clock to on-board USB-Blaster II for sending FACTORY command

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

Table 2–3. MAX V CPLD System Controller Device Pin-Out (Part 4 of 5)

Board

Reference (U27)

L5

H2

E11

A4

G4

G1

H3

G5

A6

K2

M9

B10

B3

C10

C12

C6

E10

D12

B14

C13

B16

B13

P13

R12

A10

D4

R16

H5

R4

T4

P8

T7

N8

R8

T8

T9

R9

Schematic Signal Name I/O Standard Description

M570_PCIE_JTAG_EN

MAX_AS_CONF

MAX_CONF_DONE

MAX_ERROR

MAX_FPGA_MISO

MAX_FPGA_MOSI

MAX_FPGA_SCK

MAX_FPGA_SSEL

MAX_LOAD

MAX_QSPI_RSTN

MAX_RESETN

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

OVERTEMP

PGM_CONFIG

PGM_LED0

PGM_LED1

PGM_LED2

PGM_SEL

RST

SECURITY_MODE

SI570_EN

SI571_EN

TRST

USB_B2_CLK

USB_CFG0

USB_CFG1

USB_CFG2

USB_CFG3

USB_CFG4

USB_CFG5

USB_CFG6

USB_CFG7

USB_CFG8

2.5-V PCI Express JTAG enable for the on-board USB-Blaster II

2.5-V

Driven low to enable AS configuration from the EPCQ flash through U13 to the FPGA

2.5-V On-board USB-Blaster II configuration done LED

2.5-V FPGA configuration error LED

2.5-V FPGA to MAX V SPI bus data output

2.5-V FPGA to MAX V SPI bus data input

2.5-V FPGA to MAX V SPI bus clock

2.5-V FPGA to MAX V SPI bus slave select

2.5-V FPGA configuration active LED

2.5-V QSPI reset

2.5-V MAX V reset push button

2.5-V FPGA MSEL0 setting

2.5-V FPGA MSEL1 setting

2.5-V FPGA MSEL2 setting

2.5-V FPGA MSEL3 setting

2.5-V FPGA MSEL4 setting

2.5-V Temperature monitor fan enable

2.5-V Load the flash memory image identified by the PGM LEDs

2.5-V Flash memory PGM select indicator 0

2.5-V Flash memory PGM select indicator 1

2.5-V Flash memory PGM select indicator 2

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

1.5-V Reset input

1.5-V

DIP switch for the On-board USB-Blaster II to send FACTORY command at power up

2.5-V Si570 programmable clock enable

2.5-V Si571 programmable clock enable

1.5-V Reset output

2.5-V On-board USB-Blaster II interface clock

1.5-V On-board USB-Blaster II interface (reserved for future use)

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Table 2–3. MAX V CPLD System Controller Device Pin-Out (Part 5 of 5)

FPGA Configuration

Board

Reference (U27)

P9

M8

T10

A13

A11

Schematic Signal Name I/O Standard Description

USB_CFG9

USB_CFG10

USB_CFG11

USB_FPGA_RESET

USB_RESET

FPGA Configuration

This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System Controller device programming methods supported by the Arria V SoC development board.

The Arria V SoC development board supports the following configuration methods:

■ JTAG

■ On-board USB-Blaster II is the default method for configuring the FPGA using

the Quartus II Programmer in JTAG mode with the supplied USB cable.

■ External Mictor connector for configuring the HPS using the ARM DS-5 Altera

Edition software and DSTREAM or Lauterbach cables.

■ External USB-Blaster for configuring the FPGA when you connect the external

USB-Blaster to the JTAG header (J35).

1.5-V On-board USB-Blaster II interface (reserved for future use)

2.5-V On-board USB-Blaster II interface FPGA reset

2.5-V On-board USB-Blaster II interface reset

■ Flash memory download for configuring the FPGA using stored images from the

flash memory on either power-up or pressing the configure push button (S12).

FPGA Programming over On-Board USB-Blaster II

This configuration method implements a mini-USB connector (J50), a USB 2.0 PHY device (U61), and an Altera MAX II CPLD EPM570GF100I5N (U56) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB connector on the board and a USB port on a PC running the Quartus II software.

The on-board USB-Blaster II in the MAX II CPLD EPM570GF100I5N normally masters the JTAG chain. The on-board USB-Blaster II shares the pins with the external header. and is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG header (J35). In addition to JTAG interface, the on-board USBBlaster II has trace capabilities for HPS debug purposes. The trace interface from the HPS routes to the on-board USB-Blaster II connection pins through the FPGA.

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Chapter 2: Board Components 2–11

1

2.5 V

1

2.5 V

Disable

Trace

TCK

TMS

TDI

TDO

TRST

Cypress On-Board

USB-Blaster II

TCK

TMS

TDI

TDO

10-Pin

JTAG Header

TCK

TMS

TDI

TDO

TRST

Mictor-38

Header

TCK TMS TDI TDO

TRST

Arria V ST HPS

TCK TMS TDI TDO

TRST

Arria V ST FPGA

FMC Port A

FMC Port B

TCK TMS TDI TDO

MAX V CPLD 5M2210

System Controller

Flash

Memory

TCK TMS TDI TDO

FPGA Configuration

Figure 2–3 illustrates the JTAG chain.

Figure 2–3. JTAG Chain

The JTAG chain control DIP switch (SW4) controls the jumpers shown in Figure 2–3. To connect a device or interface to the chain, their corresponding switch must be in the OFF position. Slide all the switches in the ON position to only have the FPGA in the chain.

1 The MAX V CPLD 5M2210 System Controller must be in the JTAG chain to use some

of the GUI interfaces.

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2–12 Chapter 2: Board Components

FPGA Configuration

The MAX II CPLD (EPM570GF100) is dedicated to the on-board USB-Blaster II functionality only, connecting to the USB 2.0 PHY device on one side and drives JTAG signals out the other side on the GPIO pins. This device's own dedicated JTAG interface are routed to a small surface-mount header only intended for debugging of first article prototypes.

A USB 2.0 Cypress EZ-USB CY7C68013A device (U61) in a 56-pin VBGA package interfaces to a mini-USB connector.

Tab le 2– 4 lists the USB 2.0 PHY schematic signal names and their corresponding

MAX II CPLD pin numbers.

Table 2–4. USB 2.0 PHY Schematic Signal Names and Functions (Part 1 of 2)

Board Reference

(U61)

C1

C2

E1

E2

H7

G7

H8

G6

F8

F7

F6

C8

C7

C6

H3

F4

H4

G4

H5

G5

F5

H6

A8

A7

B6

A6

B3

A3

C3

A2

Schematic

Signal Name

24M_XTALIN

24M_XTALOUT

FX2_D_N

FX2_D_P

FX2_FLAGA

FX2_FLAGB

FX2_FLAGC

FX2_PA1

FX2_PA2

FX2_PA3

FX2_PA4

FX2_PA5

FX2_PA6

FX2_PA7

FX2_PB0

FX2_PB1

FX2_PB2

FX2_PB3

FX2_PB4

FX2_PB5

FX2_PB6

FX2_PB7

FX2_PD0

FX2_PD1

FX2_PD2

FX2_PD3

FX2_PD4

FX2_PD5

FX2_PD6

FX2_PD7

MAX II CPLD Pin

Number

I/O Standard Description

— 3.3-V Crystal oscillator input

— 3.3-V Crystal oscillator output

— 3.3-V USB 2.0 PHY data

D1 3.3-V Slave FIFO output status

G1 3.3-V Slave FIFO output status

C1 3.3-V Slave FIFO output status

G3 3.3-V USB 2.0 PHY port A interface

B1 3.3-V USB 2.0 PHY port A interface

D2 3.3-V USB 2.0 PHY port A interface

D3 3.3-V USB 2.0 PHY port A interface

K4 3.3-V USB 2.0 PHY port A interface

F2 3.3-V USB 2.0 PHY port A interface

C2 3.3-V USB 2.0 PHY port A interface

G2 3.3-V USB 2.0 PHY port B interface

H8 3.3-V USB 2.0 PHY port B interface

F3 3.3-V USB 2.0 PHY port B interface

J3 3.3-V USB 2.0 PHY port B interface

F1 3.3-V USB 2.0 PHY port B interface

H1 3.3-V USB 2.0 PHY port B interface

H7 3.3-V USB 2.0 PHY port B interface

E1 3.3-V USB 2.0 PHY port B interface

H3 3.3-V USB 2.0 PHY port D interface

H2 3.3-V USB 2.0 PHY port D interface

J2 3.3-V USB 2.0 PHY port D interface

J1 3.3-V USB 2.0 PHY port D interface

J6 3.3-V USB 2.0 PHY port D interface

K3 3.3-V USB 2.0 PHY port D interface

J5 3.3-V USB 2.0 PHY port D interface

K2 3.3-V USB 2.0 PHY port D interface

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–13

FPGA Configuration

Table 2–4. USB 2.0 PHY Schematic Signal Names and Functions (Part 2 of 2)

Board Reference

(U61)

B8

F3

G3

A1

B1

B7

G2

FPGA Programming from Flash Memory

Schematic

Signal Name

FX2_RESETN

FX2_SCL

FX2_SDA

FX2_SLRDN

FX2_SLWRN

FX2_WAKEUP

USB_B2_CLK

MAX II CPLD Pin

Number

K9 3.3-V On-board USB-Blaster hard reset

J4 3.3-V USB 2.0 PHY serial clock

— 3.3-V USB 2.0 PHY serial data

K1 3.3-V Read strobe for slave FIFO

J9 3.3-V Write strobe for slave FIFO

— 3.3-V USB 2.0 PHY wake signal

E2 3.3-V USB 2.0 PHY 48-MHz interface clock

I/O Standard Description

Flash memory programming is possible through a variety of methods. The default method is to use the factory design—Golden Hardware Reference Design. This design contains an on-board web server, which serves the Board Update Portal (BUP) web application. The web page allows you to link to SoC-related web pages and to control some user I/O and LCD on the development board.

On either power-up or by pressing the program configuration push button,

PGM_CONFIG

(S12), the MAX V CPLD 5M2210 System Controller's PFL configures the FPGA from the flash memory. The PFL megafunction reads 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 16-bit data is then written to the dedicated configuration pins in the FPGA during configuration.

Pressing the based on which

Tab le 2– 5 lists the design that loads when you press the

Table 2–5. PGM_LED Settings

PGM_LED0 (D43) PGM_LED1 (D42) PGM_LED2 (D41) Design

Note to Tab le 2– 5:

(1) ON indicates a setting of ’0’ while OFF indicates a setting of ’1’.

PGM_CONFIG

PGM_LED[2:0]

ON OFF OFF Factory hardware

OFF ON OFF User hardware 1

OFF OFF ON User hardware 2

push button (S12) loads the FPGA with a hardware page

(D41, D42, D43) illuminates.

PGM_CONFIG

(1)

push button.

A EPCQ device is used for FPGA configuration in Active Serial (AS) mode on powerup. The EPCQ device with non-volatile memory features a simple six-pin interface and a small form factor. The EPCQ supports AS x1 and x4 modes.

By default, this board has a FPP configuration scheme setting. The

MAX_AS_CONF

pin needs to be driven from the MAX V CPLD to enable the bus switch to isolate the EPCQ flash (U28) from the configuration bus. This happens when the MSEL is 10010 or 10011.

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

Altera Arria V SoC Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

Board Component Blocks

1. Overview

Development Board Block Diagram

Handling the Board

2. Board Components

Board Overview

Featured Device: Arria V SoC

I/O Resources

MAX V CPLD 5M2210 System Controller

FPGA Configuration

FPGA Programming over On-Board USB-Blaster II

FPGA Programming from Flash Memory