Altera Arria V SoC Development Board User Manual

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Arria V SoC Development Board Reference Manual

Arria V SoC Development Board

Reference Manual

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© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Arria V SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

MAX V CPLD 5M2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

FPGA Programming over On-Board USB-Blaster II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

JTAG Chain Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

FPGA Configuration Mode DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

HPS Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Program Configuration Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Program Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Off-Board Input/Output Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

10/100/1000 Ethernet (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

10/100 Ethernet (FPGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

RS-232 UART (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Real-Time Clock (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

SFP+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

DDR3 SDRAM (FPGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

DDR3 SDRAM (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45

QSPI Flash (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50

EPCQ Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50

Synchronous Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–51

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iv ContentsContents

Micro SD Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–52

C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–53

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–53

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–54

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–55

Chapter 3. Board Components Reference

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

CE EMI Conformity Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Additional Information

Board Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

This document describes the hardware features of the Arria® V SoC development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Arria V SoC development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Arria V SoC. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V SoC designs.

f For more information about the Arria V device family, refer to the Arria V Device

Handbook.

Board Component Blocks

1. Overview

The development board features the following major component blocks:

■ One Arria V SoC (5ASTFD5K3F40I3) in a 1517-pin FBGA package

■ FPGA configuration circuitry

■ Active Serial (AS) x1 or x4 configuration (EPCQ256SI16N)

■ MAX

V CPLD (5M2210ZF256) in a 256-pin FBGA package as the System

Controller

■ Flash fast passive parallel (FPP) configuration

■ MAX II CPLD (EPM570GF100) as part of the on-board USB-Blaster

with the Quartus

■ Clocking circuitry

■ Si570, Si571, and Si5338 programmable oscillators

■ 50-MHz, 66-MHz, 100-MHz, 125-MHz programmable oscillators

■ SMA input (LVCMOS)

II Programmer

II for use

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1–2 Chapter 1: Overview

Board Component Blocks

■ Memory

■ One 1,024-Mbyte (MB) HPS DDR3 SDRAM with error correction code (ECC)

support

■ Two 1,024-MB FPGA DDR3 SDRAM

■ One 512-Megabit (Mb) quad serial peripheral interface (QSPI) flash

■ One 512-Mb CFI synchronous flash

■ One 256-Mb NOR flash (EPCQ device)

■ One 32-Kilobit (Kb) I

■ One Micro SD flash memory card

■ Communication Ports

■ One PCI Express x4 Gen1/Gen2 socket

■ Two FPGA mezzanine card (FMC) ports

■ One USB 2.0 on-the-go (OTG) port

■ One Gigabit Ethernet port

C serial electrically erasable PROM (EEPROM)

■ Two 10/100 Ethernet ports

■ Two S F P+ po rt s

■ Two RS-232 UART (through the mini-USB port)

■ One real-time clock

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ General user input/output

■ LEDs and displays

■ Eight user LEDs

■ One configuration load LED

■ One configuration done LED

■ One error LED

■ Three configuration select LEDs

■ Four on-board USB-Blaster II status LEDs

■ Two FMC interface LEDs

■ Two UART data transmit and receive LEDs

■ One power on LED

■ One two-line character LCD display

■ Push buttons

■ One CPU reset push button

■ One MAX V reset push button

■ One program select push button

■ One program configuration push button

■ Eight general user push buttons

■ DIP switches

■ One JTAG chain control DIP switch

■ One board settings DIP switch

■ One FPGA configuration mode DIP switch

■ One general user DIP switch

■ Power supply

■ 14–20-V (laptop) DC input

■ Mechanical

■ 7.175" × 9" rectangular form factor

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1–4 Chapter 1: Overview

DDR3 1GB

533 MHz (x32)

DDR3 1GB

533 MHz (x32)

Clock

Cleaner

Jitter

Clean Up

Buttons

Switches

LEDs

Buttons

Switches

LEDs

CSEL BSEL

HMC

10/100 Dual

Ethernet PHY

SFP+ x2

FMC x2

MAX V

CPLD

PCIe Gen2

Parallel

Configuration

Flash

DDR3 1GB

533 MHz + ECC

QSPI Flash

256 MB

Micro SD Card

USB 2.0

OTG PHY

10/100/1000

Ethernet PHY

UART to USB

I2C

Powe r

Management

Measurement

Serial

EPROM

RTC

2x16

Character

LCD

MAC Address

Storage

FPGA HPS

JTAG JTAG

USB-Blaster II USB 2.0

MAX II

CPLD

Mictor

Connector

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Arria V SoC development board.

Figure 1–1. Arria V SoC Development Board Block Diagram

Handling the Board

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

anti-static handling precautions when touching the board.

2. Board Components

This chapter introduces the major components on the Arria V SoC development board. Figure 2–1 illustrates the component locations and Tab le 2– 1 provides a brief description of all component features of the board.

1 A complete set of schematics, a physical layout database, and fabrication files for the

development board reside in the Arria V SoC development kit board design files directory.

f For information about powering up the board and installing the demonstration

software, refer to the Arria V SoC Development Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Arria V SoC” on page 2–5

■ “MAX V CPLD 5M2210 System Controller” on page 2–5

■ “FPGA Configuration” on page 2–10

■ “General User Input/Output” on page 2–19

■ “Clock Circuitry” on page 2–21

■ “Components and Interfaces” on page 2–23

■ “Memory” on page 2–39

■ “Power Supply” on page 2–53

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2–2 Chapter 2: Board Components

Board Overview

This section provides an overview of the Arria V SoC development board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features.

Figure 2–1. Overview of the Arria V SoC Development Board

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U41 FPGA Arria V SoC, 5ASTFD5K3F40I3, 1517-pin FBGA.

U27 CPLD MAX V CPLD, 5M2210ZF256, 256-pin FBGA.

Configuration, Status, and Setup Elements

J35 JTAG chain header

SW4 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.

J50 Mini-USB header

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Provides access to the JTAG chain and disables the On-board USB-Blaster II when using an external USB-Blaster cable.

USB interface for FPGA programming and debugging through the Onboard USB-Blaster II JTAG via a type-B USB cable.

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Board Components (Part 2 of 3)

Board Reference Type Description

Controls the MAX V CPLD 5M2210 System Controller functions such

SW2 Board settings DIP switch

as clock enable, SMA clock input control, and which image to load from flash memory at power-up.

SW3 MSEL DIP switch

S13 Program select push button

S12 Configure push button

Controls the configuration scheme on the board. MSEL pins 0, 1, 2, 3, and 4 connects to the DIP switch.

Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA.

Load image from flash memory to the FPGA based on the settings of the program select LEDs.

D38 Configuration done LED Illuminates when the FPGA is configured.

D40 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.

D39 Error LED Illuminates when the FPGA configuration from flash memory fails.

D37 Power LED Illuminates when 5.0-V power is present.

Indicate the transmit or receive activity of the JTAG chain. The TX and

D35, D36 JTAG TX/RX LEDs

RX LEDs would flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle.

Illuminates to show which flash memory image loads to the FPGA

D41–D43 Program select LEDs

when you press the program select push button. Refer to Table 2–5 for the LED settings.

D8, D20 FMC port present LEDs Illuminates when a daughter card is plugged into the FMC port.

D21–D24 UART LEDs Illuminates when UART transmitter and receiver are in use.

Clock Circuitry

Si570 programmable oscillator with a default frequency of 100 MHz.

X2 Programmable oscillator

The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

Si571 programmable oscillator with a default frequency of 148.5 MHz.

X3 148.5-MHz oscillator

The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

X5 125-MHz oscillator 125.000-MHz crystal oscillator for general purpose logic.

J15 Clock input SMA connector Drive LVCMOS-compatible clock input into the dedicated clock pin.

J49 HPS SMA clock Drive LVCMOS to HPS clock multiplexer.

U35 Multi-output oscillator

Si5338A quad-output fixed oscillator with 25M, 25M, 100M, and 100M outputs.

General User Input/Output

D9–D16 User LEDs Four user LEDs and four HPS LEDs. Illuminates when driven low.

SW1 User DIP switch User DIP switch. When the switch is ON, a logic 0 is selected.

S14 CPU reset push button Reset the FPGA logic.

S11 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.

S1–S8 General user push buttons

Four user push buttons and four HPS push buttons. Driven low when pressed.

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Board Overview

Table 2–1. Board Components (Part 3 of 3)

Board Reference Type Description

Memory Devices

U29, U37, U43, U49,

U38, U44, U51

DDR3 SDRAM

Four 128-MB DDR3 SDRAM with a 16-bit data bus for the FPGA and three 128-MB DDR3 SDRAM with a 16-bit data plus ECC bus for the HPS.

U19 QSPI flash 1-Gb serial NOR flash with 4-bit data bus.

U28 EPCQ flash

U13 Synchronous flash

U31 I

C EEPROM 32-Kb I2C serial EEPROM.

128-Mb synchronous flash devices with a 16-bit data bus for non-volatile memory.

Communication Ports

J42 PCI Express socket PCI Express Gen1/Gen2 ×4 socket.

J4, J26 FMC port Two FMC ports

J43, J44 SFP+ port Two SFP+ ports

RJ-45 connectors which provides a 10/100/1000 Ethernet connection

U7, J13 Gigabit Ethernet port

via a Micrel KSZ9021RN PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode (for HPS).

U55, J47, J48 Dual Ethernet port

J22, U25

J27, U36

USB-UART ports USB connector with USB-to-UART bridge for serial UART interface.

RJ-45 connector which provides a 10/100 Ethernet connection via a Renesas uPD60620 PHY in MII mode (for FPGA).

J1, U4 USB OTG port USB 2.0 on-the-go interface.

DS1339 device with built-in power sense circuit that detects power

U11 Real-time clock

failures and automatically switches to backup battery supply, maintaining time.

J5 Micro SD card socket Micro SD card interface with 4-bit data line.

Video and Display Ports

J29 Character LCD

Connector that interfaces to a provided 16 character × 2 line LCD module along with two standoffs.

Power Supply

J34 DC input jack Accepts 16-V DC power supply.

SW5 Power switch

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Switch to power on or off the board when power is supplied from the DC input jack.

Chapter 2: Board Components 2–5

Featured Device: Arria V SoC

The Arria V SoC development board features a Arria V SoC 5ASTFD5K3F40I3 device (U41) that includes a hard processor system (HPS) with integrated ARM

Cortex®-A9

MPCore processor.

f For more information about Arria V device family, refer to the Arria V Device

Handbook.

Tab le 2– 2 describes the features of the Arria V SoC device.

Table 2–2. Arria V SoC Features

Resource 5ASTFD5K3F40I3

LE (K) 462

ALM 174,340

Memory (Kb)

18-bit × 18-bit Multiplier 2,180

PLLs

Transceivers

M10K 22,820

MLAB 2,658

FPGA 14

HPS 3

6 Gbps 30

10 Gbps 16

I/O Resources

The Arria V SoC 5ASTFD5K3F40I3 device has 540 general purpose FPGA I/O pins and 210 general purpose HPS I/O pins.

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210ZF256 System Controller, an Altera MAX V CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Control and status registers (CSR) for remote system update

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2–6 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram

MAX V CPLD System Controller

Embedded

USB-Blaster II

Encoder

JTAG Control

SLD-HUB

Virtual-JTAG

Decoder

Information

Control

PFL

SPI Bus

FPGA

GPIO

LTC 2978

Power

Controllers

Controller

Tab le 2– 3 lists the I/O signals present on the MAX V CPLD System Controller. The

signal names and functions are relative to the MAX V device.

Table 2–3. MAX V CPLD System Controller Device Pin-Out (Part 1 of 5)

Board

Reference (U27)

J12

D10

N11

T13

T15

R14

N12

F11

N14

D14

P15

P14

D13

N15

E14

Schematic Signal Name I/O Standard Description

CLK125A_EN

CLK50_EN

CLK_100M_MAX

CLK_50M_MAX

CPU_RESETN

EXTRA_SIG0

EXTRA_SIG1

EXTRA_SIG2

FACTORY_LOAD

FACTORY_REQUEST

FACTORY_STATUS

FLASH_ADVN

FLASH_CEN0

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FM_A0

2.5-V 125 MHz oscillator enable

2.5-V 50 MHz oscillator enable

2.5-V 100 MHz clock input

1.8-V 50 MHz clock input

2.5-V FPGA reset push button

1.5-V On-board USB-Blaster II interface. Reserved for future use

2.5-V DIP switch to load factory or user design at power-up

1.5-V On-board USB-Blaster II request to send FACTORY command

1.5-V On-board USB-Blaster II FACTORY command status

1.8-V FSM bus flash memory address valid

1.8-V FSM bus flash memory chip enable

1.8-V FSM bus flash memory clock

1.8-V FSM bus flash memory output enable

1.8-V FSM bus flash memory ready

1.8-V FSM bus flash memory reset

1.8-V FSM bus flash memory write enable

1.8-V FM address bus

Oscillator Controller

Si570, Si571,

Si5338

Programmable

Oscillator

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MAX V CPLD 5M2210 System Controller

Table 2–3. MAX V CPLD System Controller Device Pin-Out (Part 2 of 5)

Board

Reference (U27)

C14

C15

E13

E12

D15

F14

D16

F13

E15

E16

F15

G14

F16

G13

G15

G12

G16

H14

H15

H13

H16

J13

J16

K12

M14

N13

J14

J15

K16

K13

K15

K14

L16

L11

L15

L12

M16

L13

M15

Schematic Signal Name I/O Standard Description

FM_A1

FM_A2

FM_A3

FM_A4

FM_A5

FM_A6

FM_A7

FM_A8

FM_A9

FM_A10

FM_A11

FM_A12

FM_A13

FM_A14

FM_A15

FM_A16

FM_A17

FM_A18

FM_A19

FM_A20

FM_A21

FM_A22

FM_A23

FM_A24

FM_A25

FM_A26

FM_D0

FM_D1

FM_D2

FM_D3

FM_D4

FM_D5

FM_D6

FM_D7

FM_D8

FM_D9

FM_D10

FM_D11

FM_D12

1.8-V FM address bus

1.8-V FM data bus

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MAX V CPLD 5M2210 System Controller

Table 2–3. MAX V CPLD System Controller Device Pin-Out (Part 3 of 5)

Board

Reference (U27)

L14

N16

M13

B11

P11

Schematic Signal Name I/O Standard Description

FM_D13

FM_D14

FM_D15

FMC_C2M_PG

FMCB_C2M_PG

FPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D1

FPGA_CONFIG_D2

FPGA_CONFIG_D3

FPGA_CONFIG_D4

FPGA_CONFIG_D5

FPGA_CONFIG_D6

FPGA_CONFIG_D7

FPGA_CONFIG_D8

FPGA_CONFIG_D9

FPGA_CONFIG_D10

FPGA_CONFIG_D11

FPGA_CONFIG_D12

FPGA_CONFIG_D13

FPGA_CONFIG_D14

FPGA_CONFIG_D15

FPGA_CVP_CONFDONE

FPGA_DCLK

FPGA_NCONFIG

FPGA_NSTATUS

FPGA_PR_DONE

FPGA_PR_ERROR

FPGA_PR_READY

FPGA_PR_REQUEST

HPS_RESETN

I2C_SCL_MAX

I2C_SDA_MAX

JTAG_MAX_TDI

JTAG_MAX_TDO

JTAG_MAX_TMS

JTAG_MUX_TCK

M570_CLOCK

1.8-V FM data bus

2.5-V FMC port A power good output

2.5-V FMC port B power good output

2.5-V FPGA configuration done LED

2.5-V FPGA configuration data

2.5-V FPGA Configuration via Protocol (CvP) done

2.5-V FPGA configuration clock

2.5-V FPGA configuration active

2.5-V FPGA configuration ready

2.5-V FPGA partial reconfiguration done

2.5-V FPGA partial reconfiguration error

2.5-V FPGA partial reconfiguration ready

2.5-V FPGA partial reconfiguration request

2.5-V HPS reset push button

2.5-V Programmable oscillator I2C clock

2.5-V Programmable oscillator I2C data

2.5-V JTAG chain data in

2.5-V JTAG chain data out

2.5-V JTAG chain mode

2.5-V JTAG chain clock

1.5-V

25-MHz clock to on-board USB-Blaster II for sending FACTORY command

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Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

Table 2–3. MAX V CPLD System Controller Device Pin-Out (Part 4 of 5)

Board

Reference (U27)

E11

B10

C10

C12

E10

D12

B14

C13

B16

B13

P13

R12

A10

R16

Schematic Signal Name I/O Standard Description

M570_PCIE_JTAG_EN

MAX_AS_CONF

MAX_CONF_DONE

MAX_ERROR

MAX_FPGA_MISO

MAX_FPGA_MOSI

MAX_FPGA_SCK

MAX_FPGA_SSEL

MAX_LOAD

MAX_QSPI_RSTN

MAX_RESETN

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

OVERTEMP

PGM_CONFIG

PGM_LED0

PGM_LED1

PGM_LED2

PGM_SEL

RST

SECURITY_MODE

SI570_EN

SI571_EN

TRST

USB_B2_CLK

USB_CFG0

USB_CFG1

USB_CFG2

USB_CFG3

USB_CFG4

USB_CFG5

USB_CFG6

USB_CFG7

USB_CFG8

2.5-V PCI Express JTAG enable for the on-board USB-Blaster II

2.5-V

Driven low to enable AS configuration from the EPCQ flash through U13 to the FPGA

2.5-V On-board USB-Blaster II configuration done LED

2.5-V FPGA configuration error LED

2.5-V FPGA to MAX V SPI bus data output

2.5-V FPGA to MAX V SPI bus data input

2.5-V FPGA to MAX V SPI bus clock

2.5-V FPGA to MAX V SPI bus slave select

2.5-V FPGA configuration active LED

2.5-V QSPI reset

2.5-V MAX V reset push button

2.5-V FPGA MSEL0 setting

2.5-V FPGA MSEL1 setting

2.5-V FPGA MSEL2 setting

2.5-V FPGA MSEL3 setting

2.5-V FPGA MSEL4 setting

2.5-V Temperature monitor fan enable

2.5-V Load the flash memory image identified by the PGM LEDs

2.5-V Flash memory PGM select indicator 0

2.5-V Flash memory PGM select indicator 1

2.5-V Flash memory PGM select indicator 2

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

1.5-V Reset input

1.5-V

DIP switch for the On-board USB-Blaster II to send FACTORY command at power up

2.5-V Si570 programmable clock enable

2.5-V Si571 programmable clock enable

1.5-V Reset output

2.5-V On-board USB-Blaster II interface clock

1.5-V On-board USB-Blaster II interface (reserved for future use)

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Table 2–3. MAX V CPLD System Controller Device Pin-Out (Part 5 of 5)

FPGA Configuration

Board

Reference (U27)

T10

A13

A11

Schematic Signal Name I/O Standard Description

USB_CFG9

USB_CFG10

USB_CFG11

USB_FPGA_RESET

USB_RESET

FPGA Configuration

This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System Controller device programming methods supported by the Arria V SoC development board.

The Arria V SoC development board supports the following configuration methods:

■ JTAG

■ On-board USB-Blaster II is the default method for configuring the FPGA using

the Quartus II Programmer in JTAG mode with the supplied USB cable.

■ External Mictor connector for configuring the HPS using the ARM DS-5 Altera

Edition software and DSTREAM or Lauterbach cables.

■ External USB-Blaster for configuring the FPGA when you connect the external

USB-Blaster to the JTAG header (J35).

1.5-V On-board USB-Blaster II interface (reserved for future use)

2.5-V On-board USB-Blaster II interface FPGA reset

2.5-V On-board USB-Blaster II interface reset

■ Flash memory download for configuring the FPGA using stored images from the

flash memory on either power-up or pressing the configure push button (S12).

FPGA Programming over On-Board USB-Blaster II

This configuration method implements a mini-USB connector (J50), a USB 2.0 PHY device (U61), and an Altera MAX II CPLD EPM570GF100I5N (U56) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB connector on the board and a USB port on a PC running the Quartus II software.

The on-board USB-Blaster II in the MAX II CPLD EPM570GF100I5N normally masters the JTAG chain. The on-board USB-Blaster II shares the pins with the external header. and is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG header (J35). In addition to JTAG interface, the on-board USBBlaster II has trace capabilities for HPS debug purposes. The trace interface from the HPS routes to the on-board USB-Blaster II connection pins through the FPGA.

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Chapter 2: Board Components 2–11

2.5 V

Disable

Trace

TCK

TMS

TDI

TDO

TRST

Cypress On-Board

USB-Blaster II

TCK

TMS

TDI

TDO

10-Pin

JTAG Header

TCK

TMS

TDI

TDO

TRST

Mictor-38

Header

TCK TMS TDI TDO

TRST

Arria V ST HPS

TCK TMS TDI TDO

TRST

Arria V ST FPGA

FMC Port A

FMC Port B

TCK TMS TDI TDO

MAX V CPLD 5M2210

System Controller

Flash

Memory

TCK TMS TDI TDO

FPGA Configuration

Figure 2–3 illustrates the JTAG chain.

Figure 2–3. JTAG Chain

The JTAG chain control DIP switch (SW4) controls the jumpers shown in Figure 2–3. To connect a device or interface to the chain, their corresponding switch must be in the OFF position. Slide all the switches in the ON position to only have the FPGA in the chain.

1 The MAX V CPLD 5M2210 System Controller must be in the JTAG chain to use some

of the GUI interfaces.

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FPGA Configuration

The MAX II CPLD (EPM570GF100) is dedicated to the on-board USB-Blaster II functionality only, connecting to the USB 2.0 PHY device on one side and drives JTAG signals out the other side on the GPIO pins. This device's own dedicated JTAG interface are routed to a small surface-mount header only intended for debugging of first article prototypes.

A USB 2.0 Cypress EZ-USB CY7C68013A device (U61) in a 56-pin VBGA package interfaces to a mini-USB connector.

Tab le 2– 4 lists the USB 2.0 PHY schematic signal names and their corresponding

MAX II CPLD pin numbers.

Table 2–4. USB 2.0 PHY Schematic Signal Names and Functions (Part 1 of 2)

Board Reference

(U61)

Schematic

Signal Name

24M_XTALIN

24M_XTALOUT

FX2_D_N

FX2_D_P

FX2_FLAGA

FX2_FLAGB

FX2_FLAGC

FX2_PA1

FX2_PA2

FX2_PA3

FX2_PA4

FX2_PA5

FX2_PA6

FX2_PA7

FX2_PB0

FX2_PB1

FX2_PB2

FX2_PB3

FX2_PB4

FX2_PB5

FX2_PB6

FX2_PB7

FX2_PD0

FX2_PD1

FX2_PD2

FX2_PD3

FX2_PD4

FX2_PD5

FX2_PD6

FX2_PD7

MAX II CPLD Pin

Number

I/O Standard Description

— 3.3-V Crystal oscillator input

— 3.3-V Crystal oscillator output

— 3.3-V USB 2.0 PHY data

D1 3.3-V Slave FIFO output status

G1 3.3-V Slave FIFO output status

C1 3.3-V Slave FIFO output status

G3 3.3-V USB 2.0 PHY port A interface

B1 3.3-V USB 2.0 PHY port A interface

D2 3.3-V USB 2.0 PHY port A interface

D3 3.3-V USB 2.0 PHY port A interface

K4 3.3-V USB 2.0 PHY port A interface

F2 3.3-V USB 2.0 PHY port A interface

C2 3.3-V USB 2.0 PHY port A interface

G2 3.3-V USB 2.0 PHY port B interface

H8 3.3-V USB 2.0 PHY port B interface

F3 3.3-V USB 2.0 PHY port B interface

J3 3.3-V USB 2.0 PHY port B interface

F1 3.3-V USB 2.0 PHY port B interface

H1 3.3-V USB 2.0 PHY port B interface

H7 3.3-V USB 2.0 PHY port B interface

E1 3.3-V USB 2.0 PHY port B interface

H3 3.3-V USB 2.0 PHY port D interface

H2 3.3-V USB 2.0 PHY port D interface

J2 3.3-V USB 2.0 PHY port D interface

J1 3.3-V USB 2.0 PHY port D interface

J6 3.3-V USB 2.0 PHY port D interface

K3 3.3-V USB 2.0 PHY port D interface

J5 3.3-V USB 2.0 PHY port D interface

K2 3.3-V USB 2.0 PHY port D interface

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Chapter 2: Board Components 2–13

FPGA Configuration

Table 2–4. USB 2.0 PHY Schematic Signal Names and Functions (Part 2 of 2)

Board Reference

(U61)

FPGA Programming from Flash Memory

Schematic

Signal Name

FX2_RESETN

FX2_SCL

FX2_SDA

FX2_SLRDN

FX2_SLWRN

FX2_WAKEUP

USB_B2_CLK

MAX II CPLD Pin

Number

K9 3.3-V On-board USB-Blaster hard reset

J4 3.3-V USB 2.0 PHY serial clock

— 3.3-V USB 2.0 PHY serial data

K1 3.3-V Read strobe for slave FIFO

J9 3.3-V Write strobe for slave FIFO

— 3.3-V USB 2.0 PHY wake signal

E2 3.3-V USB 2.0 PHY 48-MHz interface clock

I/O Standard Description

Flash memory programming is possible through a variety of methods. The default method is to use the factory design—Golden Hardware Reference Design. This design contains an on-board web server, which serves the Board Update Portal (BUP) web application. The web page allows you to link to SoC-related web pages and to control some user I/O and LCD on the development board.

On either power-up or by pressing the program configuration push button,

PGM_CONFIG

(S12), the MAX V CPLD 5M2210 System Controller's PFL configures the FPGA from the flash memory. The PFL megafunction reads 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 16-bit data is then written to the dedicated configuration pins in the FPGA during configuration.

Pressing the based on which

Tab le 2– 5 lists the design that loads when you press the

Table 2–5. PGM_LED Settings

PGM_LED0 (D43) PGM_LED1 (D42) PGM_LED2 (D41) Design

Note to Tab le 2– 5:

(1) ON indicates a setting of ’0’ while OFF indicates a setting of ’1’.

PGM_CONFIG

PGM_LED[2:0]

ON OFF OFF Factory hardware

OFF ON OFF User hardware 1

OFF OFF ON User hardware 2

push button (S12) loads the FPGA with a hardware page

(D41, D42, D43) illuminates.

PGM_CONFIG

(1)

push button.

A EPCQ device is used for FPGA configuration in Active Serial (AS) mode on powerup. The EPCQ device with non-volatile memory features a simple six-pin interface and a small form factor. The EPCQ supports AS x1 and x4 modes.

By default, this board has a FPP configuration scheme setting. The

MAX_AS_CONF

pin needs to be driven from the MAX V CPLD to enable the bus switch to isolate the EPCQ flash (U28) from the configuration bus. This happens when the MSEL is 10010 or 10011.

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2–14 Chapter 2: Board Components

MAX V CPLD

5M2210 System Controller

FPGA_DATA [3:0]

FPGA_DCLK

EPCQ_nCS

FLASH_A [25:1]

FLASH_D [15:0]

DATA [3:0]

DCLK

nSTATUS

nCONFIG

CONF_DONE

MSEL4 MSEL3 MSEL2 MSEL1

MSEL[4:0] and BOOTSEL[3:0] also connects to the MAX V CPLD

2.5 V

10 kΩ

nCE

DATA [3:0] DCLK nCE

CFI Flash

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_A [25:0]

FLASH_D [15:0]

FLASH_CEn FLASH_OEn

FLASH_WEn

FLASH_WPn

FLASH_ADVn

FPGA_nCONFIG

FPGA_CONF_DONE

FLASH_RYBSYn

FPGA_nSTATUS

2.5 V

10 kΩ

FLASH_ADVn

CVP_CONF_DONE

2.5 V

FLASH_CLK

FLASH_RSTn

FLASH_RESETn

FPGA_DATA [4] DATA [4]

FPGA_DATA [7:5] DATA [7:5]

PS PORT

EPCQ

56.2 Ω

100 Ω56.2 Ω

56.2 Ω

50 MHz

100 MHz

INIT_DONE

CVP_CONFDONE

FPGA_INIT_DONE

FPGA_CVP_DONE

2.5 V

2.5 V 2.5 V

MAX_ERROR

MAX_LOAD

FACTORY

USB_BLASTER

USB_SELECT

USER_PGM

CLK_ENABLE

CLK_SEL

CONFIG_RESETn

HPS_RESET

PGM_SEL

PGM_LED0

PGM_LED1

PGM_LED2

DIP Switch

BOOTSEL0 BOOTSEL1 BOOTSEL2

DIP Switch

10 kΩ

Arria V SoC FPGA

FPGA Configuration

In AS configuration scheme, the data is read from the EPCQ flash and directly sent to the FPGA. The MAX V CPLD 5M2210 System Controller controls the nCS line of the EPCQ to avoid line contention on the data line due to functionality sharing. In order to program non-volatile memory, CFI Flash or EPCQ special programming functionality design should be loaded into the FPGA or MAX V CPLD to allow programming using the Quartus II Programmer.

Figure 2–4 shows the PFL configuration.

Figure 2–4. PFL Configuration

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

f For more information on the following topics, refer to the respective documents:

■ Board Update Portal, PFL design, and flash memory map storage, refer to the

■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.

Arria V SoC Development Kit User Guide.

Chapter 2: Board Components 2–15

Status Elements

FPGA Programming over External USB-Blaster

The JTAG chain header provides another method for configuring the FPGA using an external USB-Blaster device with the Quartus II Programmer running on a PC. To prevent contention between the JTAG masters, the on-board USB-Blaster is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG chain header.

Status Elements

The development board includes status LEDs. This section describes the status elements.

Tab le 2– 6 lists the LED board references, names, and functional descriptions.

Table 2–6. Board-Specific LEDs

Board

Reference

D37

D38

D39

D40

D43

D42

D41

D20, D8

D35, D36

D34, D33

D21, D22

D23, D24

Schematic Signal Name

Power

MAX_CONF_DONE

MAX_ERROR

MAX_LOAD

PGM_LED[0]

PGM_LED[1]

PGM_LED[2]

FMC_PRSNTn, FMCB_PRSNTn

JTAG_RX, JTAG_TX

SC_RX, SC_TX

UARTA_RX_LED, UARTA_TX_LED

UARTB_RX_LED, UARTB_TX_LED

I/O

Standard

5.0-V Blue LED. Illuminates when 5.0 V power is active.

Green LED. Illuminates when the FPGA is successfully

3.3-V

2.5-V

1.8-V

3.3-V

configured. Driven by the MAX V CPLD 5M2210 System Controller.

Red LED. Illuminates when the MAX V CPLD 5M2210 System Controller fails to configure the FPGA. Driven by the MAX V CPLD 5M2210 System Controller.

Green LED. Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA. Driven by the MAX V CPLD 5M2210 System Controller.

Green LEDs. Illuminates to indicate which hardware page loads from flash memory when you press the button.

Green LED. Illuminates when the FMC port has a board or cable plugged-in. Driven by the add-in card.

Green LEDs. Illuminates to indicate USB-Blaster II receive and transmit activities.

Green LED. Illuminates to indicate UART port A receive and transmit activities.

Green LED. Illuminates to indicate UART port B receive and transmit activities.

Description

PGM_SEL

push

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Setup Elements

The development board includes several different kinds of setup elements. This section describes the following setup elements:

■ Board settings DIP switch

■ JTAG chain control DIP switch

■ FPGA configuration mode DIP switch

■ HPS jumpers

■ CPU reset push button

■ MAX V reset push button

■ Program configuration push button

■ Program select push button

f For more information about the default settings of the DIP switches, refer to the

Arria V SoC Development Kit User Guide.

Board Settings DIP Switch

The board settings DIP switch (SW2) controls various features specific to the board and the MAX V CPLD 5M2210 System Controller logic design. Tab le 2 –7 lists the switch controls and descriptions.

Table 2–7. Board Settings DIP Switch Controls

Switch Schematic Signal Name Description

CLK125A_EN

Si570_EN

FACTORY_LOAD

SECURITY_MODE

ON: Enable 125 MHz on-board oscillator

OFF: Disable 125 MHz on-board oscillator

ON: Disable programmable oscillator

OFF: Enable programmable oscillator

ON: Load the factory design from flash on power-up

OFF: PFL disabled. Do not load any design from flash on power-up

ON: On-board USB-Blaster II sends FACTORY command on power-up

OFF: On-board USB-Blaster II will not send FACTORY command on power-up

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Setup Elements

JTAG Chain Control DIP Switch

The JTAG chain control DIP switch (SW4) either removes or includes devices in the active JTAG chain. Ta bl e 2 –8 lists the switch controls and its descriptions.

Table 2–8. JTAG Chain Control DIP Switch

Switch

Schematic Signal

HPS_JTAG_EN

FPGA_JTAG_EN

FMC_JTAG_EN

MAX_JTAG_EN

Name

ON: Do not Include HPS in the JTAG chain.

OFF: Include HPS in the JTAG chain.

ON: Do not Include the FPGA in the JTAG chain.

OFF: Include the FPGA in the JTAG chain.

ON: Do not include the FMCA connector in the JTAG chain.

OFF: Include the FMCA connector in the JTAG chain.

ON: Do not include the MAX V system controller in the JTAG chain.

OFF: Include the MAX V system controller in the JTAG chain.

FPGA Configuration Mode DIP Switch

The FPGA configuration mode DIP switch (SW3) defines the mode to use to configure the FPGA. Table 2–9 lists the switch controls and its descriptions. All switches at the ON position will select the default FPP x16 mode.

Table 2–9. FPGA Configuration Mode DIP Switch

Switch

Schematic Signal

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

Name

ON: Select logic 0

OFF: Select logic 1

ON: Select logic 0

OFF: Select logic 1

ON: Select logic 0

OFF: Select logic 1

ON: Select logic 0

OFF: Select logic 1

ON: Select logic 0

OFF: Select logic 1

Description

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Setup Elements

HPS Jumpers

The HPS jumpers define the bootstrap options for the HPS—boot source, mode, HPS clocks settings, power-on-reset (POR) mode and peripherals selection. Table 2–10 lists the jumper settings and its descriptions.

Table 2–10. HPS Jumpers

Board

Reference

J39, J40, J41

J37, J38

J45, J46

J19

J21

Schematic Signal

Name

HPS_BSEL[2:0]

HPS_CSEL[1:0]

OSC2_CLK_SEL[1:0]

JTAG_HPS_SEL

JTAG_SEL

Description

Selects the boot mode and source for the HPS.

■ 0x1—FPGA

■ 0x3—NAND flash (not supported on this board)

■ 0x5—Micro SD card

■ 0x7—QSPI flash

All the other modes are reserved.

Selects the HPS clock settings. The actual clock settings are also dependent on the

HPS_BSEL[2:0]

selection.

Selects the source of OSC2 clock.

■ 00—Select on-board clock generator.

■ 01—Select external source via SMA connector.

■ 10—Select 33 MHz on-board oscillator

HPS in JTAG chain or only connect HPS to MICTOR.

Selects the source to control the HPS.

■ ON: Select on-board USB-Blaster II as the JTAG

master.

■ OFF: Select MICTOR-based JTAG master, such as

DSTREAM or Lauterbach programming cables. Also, sets SW4.1 to ON to remove the on-board USB Blaster II from driving the HPS JTAG input port in this mode.

Selects the source of the JTAG chain.

■ ON: Select on-board USB-Blaster II as the source.

■ OFF: Select MICTOR as the source.

CPU Reset Push Button

The CPU reset push button, an open-drain I/O from the MAX V CPLD System Controller. This push button is the default reset for both the HPS and CPLD logic. The MAX V CPLD 5M2210 also drives this push button during POR mode.

CPU_RESETn

(S4), is an input to the Arria V HPS pin and is

MAX V Reset Push Button

The MAX V reset push button, 5M2210 System Controller. This push button is the default reset for the CPLD logic.

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

MAX_RESETn

(S11), is an input to the MAX V CPLD

Chapter 2: Board Components 2–19

General User Input/Output

Program Configuration Push Button

The program configuration push button, CPLD 5M2210 System Controller. This input forces a FPGA reconfiguration from the flash memory. The location in the flash memory is based on the settings of

PGM_LED[2:0]

, which is controlled by the program select push button, Valid settings include memory reserved for FPGA designs.

Program Select Push Button

The program select push button, System Controller. This push button toggles the which location in the flash memory is used to configure the FPGA. Refer to Table 2–5

on page 2–13 for the

General User Input/Output

This section describes the user I/O interface to the FPGA, including the push buttons, DIP switches, LEDs, expansion header, and character LCD.

User-Defined Push Buttons

The development board includes eight user-defined push buttons. For information about the system and safe reset push buttons, refer to “Setup Elements” on page 2–16.

PGM_LED0, PGM_LED1

PGM_SEL

PGM_LED[2:0]

sequence definitions.

PGM_CONFIG

, or

PGM_LED2

(S12), is an input to the MAX V

PGM_SEL

(S13).

on the three pages in flash

(S13), is an input to the MAX V CPLD

PGM_LED[2:0]

sequence that selects

Board references S1–S8 are push buttons for controlling the FPGA designs that loads into the Arria V SoC device. Push buttons S1–S4 connect to the FPGA while push buttons S5–S8 connect to the HPS. When you press and hold down the switch, the device pin is set to logic 0; when you release the switch, the device pin is set to logic 1. There are no board-specific functions for these general user push buttons.

Tab le 2 –11 lists the user-defined push button schematic signal names and their

corresponding Arria V SoC pin numbers.

Table 2–11. User-Defined Push Button Schematic Signal Names and Functions

Board Reference Schematic Signal Name

USER_PB_FPGA0

USER_PB_FPGA1

USER_PB_FPGA2

USER_PB_FPGA3

USER_PB_HPS0

USER_PB_HPS1

USER_PB_HPS2

USER_PB_HPS3

Arria V SoC Pin

Number

AT23 1.5-V

AP24 1.5-V

AW24 1.5-V

AW23 1.5-V

E15 2.5-V

G16 2.5-V

E16 2.5-V

H16 2.5-V

I/O Standard

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General User Input/Output

User-Defined DIP Switch

Board reference SW1 is a eight-pin DIP switch. This switch is user-defined and provides additional FPGA or HPS input control. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected. There are no board-specific functions for this switch.

Tab le 2 –1 2 lists the user-defined DIP switch schematic signal names and their

corresponding Arria V SoC pin numbers.

Table 2–12. User-Defined DIP Switch Schematic Signal Names and Functions

Board Reference Schematic Signal Name

User-Defined LEDs

Board references D1–D8 are eight user-defined LEDs. The status and debugging signals are driven to the LEDs from the FPGA or HPS designs loaded into the Arria V SoC. Driving a logic 0 on the I/O port turns the LED on while driving a logic 1 turns the LED off. There are no board-specific functions for these LEDs.

Tab le 2 –1 3 lists the general LED schematic signal names and their corresponding

Arria V SoC pin numbers.

Table 2–13. General LED Schematic Signal Names and Functions

USER_DIPSW_HPS0

USER_DIPSW_HPS1

USER_DIPSW_HPS2

USER_DIPSW_HPS3

USER_DIPSW_FPGA0

USER_DIPSW_FPGA1

USER_DIPSW_FPGA2

USER_DIPSW_FPGA3

Arria V SoC Pin Number

L15 3.3-V

K15 3.3-V

K14 3.3-V

C15 3.3-V

AL24 2.5-V

AF24 2.5-V

AE24 2.5-V

AU23 2.5-V

I/O Standard

Board Reference

D12

D11

D10

D16

D15

D14

D13

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

USER_LED_FPGA0

USER_LED_FPGA1

USER_LED_FPGA2

USER_LED_FPGA3

USER_LED_HPS0

USER_LED_HPS1

USER_LED_HPS2

USER_LED_HPS3

Schematic

Signal Name

Arria V SoC

Pin Number

AH24 2.5-V

AU24 2.5-V

AT24 2.5-V

AD24 2.5-V

R17 3.3-V

F16 3.3-V

R15 3.3-V

C16 3.3-V

I/O Standard

Chapter 2: Board Components 2–21

Arria V ST I3

Bank 8 HPS Peripherals

HPS Core

HPS Memory InterfaceBank R1

Bank 3 Bank 4

Bank 0L Bank 1L Bank 2L

REFCLKL5

Si571

148.5 MHz/I

REFCLKL3

PCIe

Socket

LMK04828

Cleaner

Si5338

SMA

CLK_OSC2

REFCLKR3

REFCLKR2

25 MHz

CLK16-19pFMC CLK20-23pFMCB

REFCLKR0

Dual ENET PHY, 25 MHz

MAX V, 100 MHz

CLK0p 100 MHz

CLK1p 156.25 MHz

CLK2p CLK_ENET_PHY 25 MHz

CLK3p 50 MHz

CLK4p CLK_ENET_FPGA 125 MHz

CLK6p CLEAN_CLK

CLK8p SYSREF

CLK10p 100 MHz

CLK11p SMA

SL 18860C

Si570

CLK_OSC1 25 MHz

SMA

Bank R0

FMCA FMCB

FMCA

REFCLKL2

REFCLKL1

FMCB

REFCLKL0

REFCLKL4

FMCA FMCB

100 MHz/I2C

Si52112

100 MHz

Si5335

125 MHz

MAX V

50 MHz

33 MHz

Clock Circuitry

Character LCD

The development board includes a single 10-pin 0.1" pitch single-row header that interfaces to a 2 line × 16 character Lumex character LCD using standard I connected to the HPS. The character LCD has a two headers that mount directly to the board's 10-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging, I

f For more information such as timing, character maps, interface guidelines, and other

related documentation, visit www.newhavendisplay.com.

Clock Circuitry

This section describes the board's clock inputs and outputs.

On-Board Oscillators

Figure 2–5 shows the default frequencies of all external clocks going to the

Arria V SoC development board.

Figure 2–5. Arria V SoC Development Board Clocks

C interface

C expansion, or other purposes.

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2–22 Chapter 2: Board Components

Clock Circuitry

Off-Board Input/Output Clock

The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.

Tab le 2 –1 4 lists the clock inputs for the development board.

Table 2–14. Off-Board Clock Inputs

Source Schematic Signal Name I/O Standard

SMA

FMC Port A

FMC Port B

SMA_CLKIN

OSC2_CLK_SMA

FMC_CLK_M2C_P[1:0]

FMC_CLK_M2C_N[1:0]

FMC_LA_RX_CLK_P

FMC_LA_RX_CLK_N

FMC_LA_RX_P7

FMC_LA_RX_N7

FMC_GBTCLK_M2C_P[1:0]

FMC_GBTCLK_M2C_N[1:0]

FMCB_CLK_M2C_P[1:0]

FMCB_CLK_M2C_N[1:0]

FMCB_LA_RX_CLK_P

FMCB_LA_RX_CLK_N

FMCB_LA_RX_P7

FMCB_LA_RX_N7

FMCB_GBTCLK_M2C_P[1:0]

FMCB_GBTCLK_M2C_N[1:0]

2.5-V CMOS — Clock input to the global clock network.

2.5-V CMOS —

LVDS B22, A22

LVDS C22, A21

LVDS H21

LVDS J 21

LVDS C2 0

LVDS D20

LVDS AC31, AA31

LVDS AC32, AA32

LVDS C34, G34

LVDS D34, H34

LVDS E34

LVDS F 34

LVDS N34

LVDS N33

LVDS AG32, AE31

LVDS AG33, AE32

Arria V SoC Pin Number

Description

Multiplexed clock input to OSC2 of the HPS.

LVDS input from the installed FMC card to global clock inputs.

LVDS input from the installed FMC card to dedicated reference clock inputs.

LVDS input from the installed FMC card to global clock inputs.

LVDS input from the installed FMC card to dedicated reference clock inputs.

Tab le 2 –1 5 lists the clock outputs for the development board.

Table 2–15. Off-Board Clock Outputs

Source

FMC Port A

FMC Port B

PCI Express Socket

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Schematic Signal

Name

FMC_LA_TX_CLK_P

FMC_LA_TX_CLK_N

FMCB_LA_TX_CLK_P

FMCB_LA_TX_CLK_N

PCIE_REFCLK_SYN_P

PCIE_REFCLK_SYN_N

I/O Standard

LVDS M23

LVDS N23

LVDS L30

LVDS M30

HCSL AF8

HCSL AF7

Arria V SoC

Pin Number

Description

LVDS output.

HCSL output to the PCI Express socket.

Chapter 2: Board Components 2–23

VMAX = 1.15 V

CROSS MAX = 550 mV

CROSS MIN = 250 mV

VMIN = –0.30 V

REFCLK –

REFCLK +

Components and Interfaces

This section describes the development board's communication ports and interface cards relative to the Arria V SoC device. The development board supports the following communication ports:

■ PCI Express

■ 10/100/1000 Ethernet (HPS)

■ 10/100 Ethernet (FPGA)

■ FMC

■ RS-232 UART (HPS)

■ Real-Time clock (HPS)

■ SFP+

■ I

C interface

PCI Express

The PCI Express interface on the development board supports auto-negotiating channel width from ×1 to ×4 with the following connection speeds:

■ Gen1 at 2.5 Gbps/lane for a maximum of 10 Gbps bandwidth

■ Gen2 at 5 Gbps/lane for a maximum of 20 Gbps bandwidth

The

PCIE_REFCLK_P/N

signal is a 100-MHz differential input that is driven to the daughter card through the PCI Express edge connector. This signal connects directly to a Arria V SoC

REFCLK

input pin pair using DC coupling. The I/O standard is

High-Speed Current Steering Logic (HCSL).

Figure 2–6 shows the PCI Express reference clock levels.

Figure 2–6. PCI Express Reference Clock Levels

The PCI Express edge connector also has a presence detect feature for the motherboard to determine if a card is installed. A jumper is provided to optionally connect

PRSNT1n

to any of the three

PRSNT2n

pins found within the x4 connector definition. This is to address issues on some PC systems that would base the link-width capability on the presence detect pins versus a query operation.

Tab le 2 –1 6 summarizes the PCI Express pin assignments. The signal names and

directions are relative to the Arria V SoC.

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Components and Interfaces

Table 2–16. PCI Express Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J42)

A11

B17

B31

A14

A13

B11

A17

A22

A26

A30

A16

A21

A25

A29

B15

B20

B24

B28

B14

B19

B23

B27

Schematic Signal

Name

PCIE_PERSTN

PCIE_PRSNT2N_X1

PCIE_PRSNT2N_X4

PCIE_REFCLK_SYN_N

PCIE_REFCLK_SYN_P

PCIE_SMCLK

PCIE_SMDAT

PCIE_WAKEN

PCIE_RX_N0

PCIE_RX_N1

PCIE_RX_N2

PCIE_RX_N3

PCIE_RX_P0

PCIE_RX_P1

PCIE_RX_P2

PCIE_RX_P3

PCIE_TX_N0

PCIE_TX_N1

PCIE_TX_N2

PCIE_TX_N3

PCIE_TX_P0

PCIE_TX_P1

PCIE_TX_P2

PCIE_TX_P3

I/O Standard

Arria V SoC Device Pin

Number

Description

LVTTL AK6 Reset

LVTTL AC22 Presence detect DIP switch

LVTTL AD21 Presence detect DIP switch

HCSL AF7 Motherboard reference clock

HCSL AF8 Motherboard reference clock

LVTTL AG20 SMB clock

LVTTL AG23 SMB data

LVTTL AL6 Wake signal

1.5-V PCML AU2 Receive bus

1.5-V PCML AR2 Receive bus

1.5-V PCML AN2 Receive bus

1.5-V PCML AL2 Receive bus

1.5-V PCML AU1 Receive bus

1.5-V PCML AR1 Receive bus

1.5-V PCML AN1 Receive bus

1.5-V PCML AL1 Receive bus

1.5-V PCML AT4 Transmit bus

1.5-V PCML AP4 Transmit bus

1.5-V PCML AM4 Transmit bus

1.5-V PCML AK4 Transmit bus

1.5-V PCML AT3 Transmit bus

1.5-V PCML AP3 Transmit bus

1.5-V PCML AM3 Transmit bus

1.5-V PCML AK3 Transmit bus

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Chapter 2: Board Components 2–25

RGMII

Mac

Single-Port RGMII

Micrel KSZ9021RN

RJ-45

Components and Interfaces

10/100/1000 Ethernet (HPS)

The development board supports an RJ-45 10/100/1000 base-T Ethernet using an external Micrel KSZ9021RN PHY and the HPS EMAC function from the Altera Triple-Speed Ethernet MegaCore MAC function. The PHY-to-MAC interface employs RGMII connection using four data lines at 250 Mbps each for a connection speed of 1Gbps.

The Micrel KSZ9021RN PHY uses 2.5-V or 3.3-V power rails. The PHY interfaces to an RJ-45 model with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Figure 2–7 shows the RGMII interface between the HPS (MAC) and Micrel

KSZ9021RN PHY.

Figure 2–7. RGMII Interface between HPS (MAC) and PHY

Tab le 2 –1 7 lists the HPS Ethernet PHY interface pin assignments.

Table 2–17. Ethernet PHY (HPS) Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference (U7)

Schematic Signal Name

CLK125_NDO_LED_MODE

ENET_HPS_GTX_CLK

ENET_HPS_INTN

ENET_HPS_LED1_LINK

ENET_HPS_LED2_LINK

ENET_HPS_MDC

ENET_HPS_MDIO

ENET_HPS_RESETN

ENET_HPS_RSET

ENET_HPS_RX_CLK

ENET_HPS_RX_DV

ENET_HPS_RXD0

ENET_HPS_RXD1

ENET_HPS_RXD2

ENET_HPS_RXD3

ENET_HPS_TX_EN

ENET_HPS_TXD0

ENET_HPS_TXD1

Arria V SoC Pin

Number

— — Clock out 125-MHz LED mode

D19 3.3-V CMOS 125-MHz RGMII transmit clock

A18 3.3-V CMOS Management bus interrupt

— 3.3-V CMOS Receive data active LED

— 3.3-V CMOS Transmit data active LED

L18 3.3-V CMOS Management bus data clock

J18 3.3-V CMOS Management bus data

— 3.3-V CMOS Device reset

— 3.3-V CMOS Device interrupt

G21 3.3-V CMOS RGMII receive clock

H19 3.3-V CMOS RGMII receive data valid

E19 3.3-V CMOS RGMII receive data bus

M17 3.3-V CMOS RGMII receive data bus

G20 3.3-V CMOS RGMII receive data bus

G19 3.3-V CMOS RGMII receive data bus

N18 3.3-V CMOS RGMII transmit enable

H18 3.3-V CMOS RGMII transmit data bus

F19 3.3-V CMOS RGMII transmit data bus

I/O Standard Description

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Table 2–17. Ethernet PHY (HPS) Pin Assignments, Signal Names and Functions (Part 2 of 2)

Components and Interfaces

Board

Reference (U7)

Schematic Signal Name

ENET_HPS_TXD2

ENET_HPS_TXD3

MDI_HPS_N0

MDI_HPS_N1

MDI_HPS_N2

MDI_HPS_N3

MDI_HPS_P0

MDI_HPS_P1

MDI_HPS_P2

MDI_HPS_P3

Arria V SoC Pin

Number

K18 3.3-V CMOS RGMII transmit data bus

M18 3.3-V CMOS RGMII transmit data bus

— 3.3-V CMOS Media dependent interface

I/O Standard Description

The Micrel KSZ9021RN PHY uses a multi-level POR bootstrap encoding scheme to allow a small set of I/O pins (7) to set up a very large number of default settings within the device. The related I/O pins have integrated pull-up or pull-down resistors to configure the device. Table 2–18 lists the level encoding scheme.

Table 2–18. Ethernet PHY (HPS) Bootstrap Encoding Scheme

Board Reference

(U7)

Schematic Signal Name Description Strapping Option

ENET_HPS_LED1_LINK

ENET_HPS_LED2_LINK

ENET_HPS_RXD0

ENET_HPS_RXD1

ENET_HPS_RXD2

ENET_HPS_RXD3

ENET_HPS_RX_CLK

ENET_HPS_RX_DV

CLK125_NDO_LED_MODE

PHY address bit 0 Pulled low

PHY address bit 1 Pulled low

Mode 0 Pulled high

Mode 1 Pulled high

Mode 2 Pulled high

Mode 3 Pulled high

PHY address bit 2 Pulled high

Clock enable Pulled low

Single LED mode Pulled high

10/100 Ethernet (FPGA)

The development board supports an RJ-45 10/100 base-T Ethernet using an external Renesas uPD60620 PHY. This PHY supports EtherCAT, Ethernet IRT and DLR features using a third party MAC IP. The PHY-to-MAC interface employs MII connection using four data lines at 25 Mbps each for a connection speed of 100 Mbps.

The PHY uses 3.3-V power rails and requires a 25 MHz reference clock to be driven from a dedicated oscillator. The PHY interfaces to a dual RJ-45 model with internal magnetics that can be used for driving copper lines with Ethernet traffic.

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Chapter 2: Board Components 2–27

FPGA MII

Mac

Dual-Port RGMII

Renesas

uPD60620

RJ-45

Components and Interfaces

Figure 2–8 shows the MII interface between the FPGA (MAC) and Renesas uPD60620

PHY.

Figure 2–8. MII Interface between FPGA (MAC) and PHY

Tab le 2 –1 9 lists the Ethernet PHY interface pin assignments.

Table 2–19. Ethernet PHY (FPGA) Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference

(U55)

Schematic Signal Name

ENET1_ACT_LED

ENET1_LINK_LED

ENET1_MDI_RX_N

ENET1_MDI_RX_P

ENET1_MDI_TX_N

ENET1_MDI_TX_P

ENET1_RX_CLK

ENET1_RX_D0

ENET1_RX_D1

ENET1_RX_D2

ENET1_RX_D3

ENET1_RX_DV

ENET1_RX_ERROR

ENET1_TX_CLK_FB

ENET1_TX_D0

ENET1_TX_D1

ENET1_TX_D2

ENET1_TX_D3

ENET1_TX_EN

ENET2_ACT_LED

ENET2_LINK_LED

ENET2_MDI_RX_N

ENET2_MDI_RX_P

ENET2_MDI_TX_N

Arria V SoC Pin

Number

I/O Standard Description

— 2.5-V Receive data active LED

— 2.5-V Transmit data active LED

— 2.5-V Media dependent interface

AE22 2.5-V MII receive clock

AL23 2.5-V MII receive data bus

AW22 2.5-V MII receive data bus

AW21 2.5-V MII receive data bus

AV21 2.5-V MII receive data bus

AF22 2.5-V MII receive data valid

AH23 2.5-V MII receive error

AN23 2.5-V 25-MHz MII transmit clock

AU22 2.5-V MII transmit data bus

AT22 2.5-V MII transmit data bus

AE23 2.5-V MII transmit data bus

AD22 2.5-V MII transmit data bus

AP23 2.5-V MII transmit enable

— 2.5-V Receive data active LED

— 2.5-V Transmit data active LED

— 2.5-V Media dependent interface

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Components and Interfaces

Table 2–19. Ethernet PHY (FPGA) Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board

Reference

(U55)

Schematic Signal Name

ENET2_MDI_TX_P

ENET2_RX_CLK

ENET2_RX_D0

ENET2_RX_D1

ENET2_RX_D2

ENET2_RX_D3

ENET2_RX_DV

ENET2_RX_ERROR

ENET2_TX_CLK_FB

ENET2_TX_D0

ENET2_TX_D1

ENET2_TX_D2

ENET2_TX_D3

ENET2_TX_EN

ENET_DUAL_RESETN

ENET_FPGA_MDC

ENET_FPGA_MDIO

Arria V SoC Pin

Number

I/O Standard Description

— 2.5-V Media dependent interface

AT20 2.5-V MII receive clock

AW19 2.5-V MII receive data bus

AL22 2.5-V MII receive data bus

AH22 2.5-V MII receive data bus

AU20 2.5-V MII receive data bus

AP20 2.5-V MII receive data valid

AN22 2.5-V MII receive error

AN21 2.5-V 25-MHz MII transmit clock

AT21 2.5-V MII transmit data bus

AR21 2.5-V MII transmit data bus

AK21 2.5-V MII transmit data bus

AP22 2.5-V MII transmit data bus

AW20 2.5-V MII transmit enable

AV22 2.5-V Device reset

AG22 2.5-V Management bus data clock

AK22 2.5-V Management bus data

The PHY uses a multi-level POR bootstrap encoding scheme to allow a small set of I/O pins to set up a very large number of default settings within the device. The related I/O pins have integrated pull-up or pull-down resistors to configure the device. To change the configuration, connect an external resistor of maximum 5 k to the pin. Table 2–20 lists the level encoding scheme.

Table 2–20. Ethernet PHY (FPGA) Bootstrap Encoding Scheme

Board Reference

(U55)

Schematic Signal Name Description Strapping Option

ENET2_RX_D1

ENET2_RX_D0

ENET2_RX_CLK

ENET1_RX_ERROR

ENET1_RX_CLK

ENET2_RX_DV

ENET1_RX_D0

ENET1_RX_D1

Auto-negotiation disabled. 100 base-T default.

Pulled low

Full duplex operation Pulled high

Disable quick auto negotiation Pulled low

MII mode operation Pulled low

AUTOMDI-X enabled Pulled high

Transmit mode for PHY1 Pulled high

Auto-negotiation disabled. 10 base-T default.

Pulled low

Address for SMI Pulled low

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Chapter 2: Board Components 2–29

Components and Interfaces

FMC

The development board contains two high pin count (HPC) FPGA mezzanine card (FMC) ports that functions with a quadrature amplitude modulation (QAM) digitalto-analog converter (DAC) FMC module or daughter card. This pinout satisfies a QAM DAC that requires 58 LVDS data output pairs, one LVDS input clock pair, and three low-voltage differential signaling (LVDS) control pairs from the Arria V. These pins also have the option to be used as single-ended I/O pins. The VCCIO supply for FMC bank A in the low pin count (LPC) and HPC provide a variable voltage of 1.5 V,

1.8 V, 2.5 V (default), or 3.3 V. The VCCIO supply for FMC bank B in the HPC provides a variable voltage from 1.2 V to 3.3 V, which can be supplied by the FMC module. For device safety concerns, a jumper is available for you to connect this bank to the same VCCIO used for FMC bank A. This allows the VCCIO pins on the FPGA to be tied to a known power. The VCCIO pins also allows you the option to perform a manual check for the module’s input voltage before connecting to the FPGA. This is to ensure that the module does not exceed the power supply maximum voltage rating.

Tab le 2 –2 1 lists the FMC port A pin assignments, signal names, and functions.

Table 2–21. FMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5)

Board

Reference

(J26)

A23

A27

A31

A35

A39

B37

B33

A22

A26

A30

A34

A38

B36

B32

Schematic

Signal Name

FMC_C2M_PG

FMC_CLK_M2C_P0

FMC_CLK_M2C_N0

FMC_CLK_M2C_P1

FMC_CLK_M2C_N1

FMC_DP_C2M_N0

FMC_DP_C2M_N1

FMC_DP_C2M_N2

FMC_DP_C2M_N3

FMC_DP_C2M_N4

FMC_DP_C2M_N5

FMC_DP_C2M_N6

FMC_DP_C2M_N7

FMC_DP_C2M_P0

FMC_DP_C2M_P1

FMC_DP_C2M_P2

FMC_DP_C2M_P3

FMC_DP_C2M_P4

FMC_DP_C2M_P5

FMC_DP_C2M_P6

FMC_DP_C2M_P7

FMC_DP_M2C_N0

FMC_DP_M2C_N1

Arria V SoC

Pin Number

— 2.5-V CMOS Power good output

B22 LVDS Clock input 0

C22 LVDS Clock input 0

A22 LVDS Clock input 1

A21 LVDS Clock input 1

AE36 PCML Transmit channel

AA36 PCML Transmit channel

W36 PCML Transmit channel

R36 PCML Transmit channel

N36 PCML Transmit channel

J36 PCML Transmit channel

G36 PCML Transmit channel

C36 PCML Transmit channel

AE37 PCML Transmit channel

AA37 PCML Transmit channel

W37 PCML Transmit channel

R37 PCML Transmit channel

N37 PCML Transmit channel

J37 PCML Transmit channel

G37 PCML Transmit channel

C37 PCML Transmit channel

AF38 PCML Receive channel

AB38 PCML Receive channel

I/O Standard Description

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

2–30 Chapter 2: Board Components

Components and Interfaces

Table 2–21. FMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)

Board

Reference

(J26)

A11

A15

A19

B17

B13

A10

A14

A18

B16

B12

C34

D35

B20

B21

E18

E19

K19

K20

J21

J22

K22

K23

D30

D31

D33

D34

Schematic

Signal Name

FMC_DP_M2C_N2

FMC_DP_M2C_N3

FMC_DP_M2C_N4

FMC_DP_M2C_N5

FMC_DP_M2C_N6

FMC_DP_M2C_N7

FMC_DP_M2C_P0

FMC_DP_M2C_P1

FMC_DP_M2C_P2

FMC_DP_M2C_P3

FMC_DP_M2C_P4

FMC_DP_M2C_P5

FMC_DP_M2C_P6

FMC_DP_M2C_P7

FMC_GA0

FMC_GA1

FMC_GBTCLK_M2C_P0

FMC_GBTCLK_M2C_N0

FMC_GBTCLK_M2C_P1

FMC_GBTCLK_M2C_N1

FMC_GPIO0

FMC_GPIO1

FMC_GPIO2

FMC_GPIO3

FMC_GPIO4

FMC_GPIO5

FMC_GPIO6

FMC_GPIO7

FMC_JTAG_TDI

FMC_JTAG_TDO

FMC_JTAG_TMS

FMC_JTAG_RST

Arria V SoC Pin Number

I/O Standard Description

Y38 PCML Receive channel

T38 PCML Receive channel

P38 PCML Receive channel

K38 PCML Receive channel

H38 PCML Receive channel

D38 PCML Receive channel

AF39 PCML Receive channel

AB39 PCML Receive channel

Y39 PCML Receive channel

T39 PCML Receive channel

P39 PCML Receive channel

K39 PCML Receive channel

H39 PCML Receive channel

D39 PCML Receive channel

C23 2.5-V CMOS FMC geographical address 0

P25 2.5-V CMOS FMC geographical address 1

AC31 LVDS Transceiver reference clock 0

AC32 LVDS Transceiver reference clock 0

AA31 LVDS Transceiver reference clock 1

AA32 LVDS Transceiver reference clock 1

B24 2.5-V CMOS

C24 2.5-V CMOS

F24 2.5-V CMOS

G24 2.5-V CMOS

H24 2.5-V CMOS

J24 2.5-V CMOS

B27 2.5-V CMOS

C27 2.5-V CMOS

FMC general purpose IO bit 0 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 1 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 2 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 3 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 4 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 5 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 6 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 7 (part of the partially populated HPS connector signal group)

— 2.5-V CMOS JTAG data in

— 2.5-V CMOS JTAG data out

— 2.5-V CMOS JTAG mode select

— 2.5-V CMOS JTAG mode reset

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–31

Components and Interfaces

Table 2–21. FMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)

Board

Reference

(J26)

G10

C11

F11

C15

G16

C19

G19

D21

G22

G25

G28

D24

G31

G34

G37

F20

C10

F10

C14

G15

C18

G18

D20

G21

G24

G27

D23

G30

G33

G36

F19

H11

Schematic

Signal Name

FMC_LA_RX_CLK_P

FMC_LA_RX_CLK_N

FMC_LA_RX_N0

FMC_LA_RX_N1

FMC_LA_RX_N2

FMC_LA_RX_N3

FMC_LA_RX_N4

FMC_LA_RX_N5

FMC_LA_RX_N6

FMC_LA_RX_N7

FMC_LA_RX_N8

FMC_LA_RX_N9

FMC_LA_RX_N10

FMC_LA_RX_N11

FMC_LA_RX_N12

FMC_LA_RX_N13

FMC_LA_RX_N14

FMC_LA_RX_N15

FMC_LA_RX_P0

FMC_LA_RX_P1

FMC_LA_RX_P2

FMC_LA_RX_P3

FMC_LA_RX_P4

FMC_LA_RX_P5

FMC_LA_RX_P6

FMC_LA_RX_P7

FMC_LA_RX_P8

FMC_LA_RX_P9

FMC_LA_RX_P10

FMC_LA_RX_P11

FMC_LA_RX_P12

FMC_LA_RX_P13

FMC_LA_RX_P14

FMC_LA_RX_P15

FMC_LA_TX_CLK_P

FMC_LA_TX_CLK_N

FMC_LA_TX_N0

FMC_LA_TX_N1

Arria V SoC Pin Number

I/O Standard Description

H21 LVDS Secondary carrier-bound clock

J21 LVDS Secondary carrier-bound clock

T28 2.5-V CMOS FMC data bus

R27 2.5-V CMOS FMC data bus

N27 2.5-V CMOS FMC data bus

N26 2.5-V CMOS FMC data bus

D26 2.5-V CMOS FMC data bus

T27 2.5-V CMOS FMC data bus

G26 2.5-V CMOS FMC data bus

D20 2.5-V CMOS FMC data bus

F22 2.5-V CMOS FMC data bus

P22 2.5-V CMOS FMC data bus

B25 2.5-V CMOS FMC data bus

T25 2.5-V CMOS FMC data bus

P24 2.5-V CMOS FMC data bus

E25 2.5-V CMOS FMC data bus

E24 2.5-V CMOS FMC data bus

G23 2.5-V CMOS FMC data bus

R28 2.5-V CMOS FMC data bus

P27 2.5-V CMOS FMC data bus

M27 2.5-V CMOS FMC data bus

M26 2.5-V CMOS FMC data bus

C26 2.5-V CMOS FMC data bus

R26 2.5-V CMOS FMC data bus

F26 2.5-V CMOS FMC data bus

C20 2.5-V CMOS FMC data bus

E22 2.5-V CMOS FMC data bus

N22 2.5-V CMOS FMC data bus

A25 2.5-V CMOS FMC data bus

T26 2.5-V CMOS FMC data bus

N24 2.5-V CMOS FMC data bus

D25 2.5-V CMOS FMC data bus

D24 2.5-V CMOS FMC data bus

F23 2.5-V CMOS FMC data bus

M23 2.5-V CMOS Mezzanine-bound clock

N23 2.5-V CMOS Mezzanine-bound clock

J27 2.5-V CMOS FMC data bus

K26 2.5-V CMOS FMC data bus

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Reference Manual

2–32 Chapter 2: Board Components

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Table 2–21. FMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)

Board

Reference

(J26)

D12

H14

D15

H17

D18

H20

H23

H26

H29

D27

H35

H38

G13

H32

H10

D11

H13

D14

H16

D17

H19

H22

H25

H28

D26

H34

H37

G12

H31

C30

C31

D29

C23

C22

Schematic

Signal Name

FMC_LA_TX_N2

FMC_LA_TX_N3

FMC_LA_TX_N4

FMC_LA_TX_N5

FMC_LA_TX_N6

FMC_LA_TX_N7

FMC_LA_TX_N9

FMC_LA_TX_N10

FMC_LA_TX_N12

FMC_LA_TX_N13

FMC_LA_TX_N14

FMC_LA_TX_N15

FMC_LA_TX_N16

FMC_LA_TX_N17

FMC_LA_TX_P0

FMC_LA_TX_P1

FMC_LA_TX_P2

FMC_LA_TX_P3

FMC_LA_TX_P4

FMC_LA_TX_P5

FMC_LA_TX_P6

FMC_LA_TX_P7

FMC_LA_TX_P9

FMC_LA_TX_P10

FMC_LA_TX_P12

FMC_LA_TX_P13

FMC_LA_TX_P14

FMC_LA_TX_P15

FMC_LA_TX_P16

FMC_LA_TX_P17

FMC_M2C_PG

FMC_PRSNT

FMC_SCL

FMC_SDA

JTAG_MUX_TCK

LMK_CLK_FMC_N

LMK_CLK_FMC_P

Arria V SoC Pin Number

I/O Standard Description

F27 2.5-V CMOS FMC data bus

P28 2.5-V CMOS FMC data bus

A27 2.5-V CMOS FMC data bus

N25 2.5-V CMOS FMC data bus

L27 2.5-V CMOS FMC data bus

P21 2.5-V CMOS FMC data bus

T21 2.5-V CMOS FMC data bus

A24 2.5-V CMOS FMC data bus

T22 2.5-V CMOS FMC data bus

L24 2.5-V CMOS FMC data bus

H25 2.5-V CMOS FMC data bus

T24 2.5-V CMOS FMC data bus

T23 2.5-V CMOS FMC data bus

K23 2.5-V CMOS FMC data bus

H27 2.5-V CMOS FMC data bus

J26 2.5-V CMOS FMC data bus

E27 2.5-V CMOS FMC data bus

N28 2.5-V CMOS FMC data bus

A26 2.5-V CMOS FMC data bus

M25 2.5-V CMOS FMC data bus

K27 2.5-V CMOS FMC data bus

N21 2.5-V CMOS FMC data bus

R21 2.5-V CMOS FMC data bus

A23 2.5-V CMOS FMC data bus

R22 2.5-V CMOS FMC data bus

K24 2.5-V CMOS FMC data bus

G25 2.5-V CMOS FMC data bus

R24 2.5-V CMOS FMC data bus

R23 2.5-V CMOS FMC data bus

J23 2.5-V CMOS FMC data bus

— 2.5-V CMOS Power good input

K25 2.5-V CMOS FMC module present

J22 2.5-V CMOS Management serial clock line

D23 2.5-V CMOS Management serial data line

AV34 2.5-V CMOS JTAG chain clock

— 2.5-V CMOS Alternate mezzanine-bound clock (from LMK device)

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–33

Components and Interfaces

Table 2–21. FMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)

Board

Reference

(J26)

C27

C26

Schematic

Signal Name

LMK_SYSREF_FMC_N

LMK_SYSREF_FMC_P

Arria V SoC Pin Number

I/O Standard Description

—2.5-V CMOS

Alternate mezzanine-bound SYSREF signal (from LMK device)

Tab le 2 –2 2 lists the FMC port B pin assignments, signal names, and functions.

Table 2–22. FMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference

(J4)

A23

A27

A31

A22

A26

A30

A11

A10

C34

D35

B20

B21

E18

Schematic Signal Name

FMCB_C2M_PG

FMCB_CLK_M2C_P0

FMCB_CLK_M2C_N0

FMCB_CLK_M2C_P1

FMCB_CLK_M2C_N1

FMCB_DP_C2M_N0

FMCB_DP_C2M_N1

FMCB_DP_C2M_N2

FMCB_DP_C2M_N3

FMCB_DP_C2M_P0

FMCB_DP_C2M_P1

FMCB_DP_C2M_P2

FMCB_DP_C2M_P3

FMCB_DP_M2C_N0

FMCB_DP_M2C_N1

FMCB_DP_M2C_N2

FMCB_DP_M2C_N3

FMCB_DP_M2C_P0

FMCB_DP_M2C_P1

FMCB_DP_M2C_P2

FMCB_DP_M2C_P3

FMCB_GA0

FMCB_GA1

FMCB_GBTCLK_M2C_P0

FMCB_GBTCLK_M2C_N0

FMCB_GBTCLK_M2C_P1

FMCB_GBTCLK_M2C_N1

FMCB_GPIO0

Arria V SoC

Pin Number

I/O Standard Description

— 2.5-V CMOS Power good output

C34 LVDS Clock input 0

D34 LVDS Clock input 0

G34 LVDS Clock input 1

H34 LVDS Clock input 1

AU36 PCML Transmit channel

AN36 PCML Transmit channel

AL36 PCML Transmit channel

AG36 PCML Transmit channel

AU37 PCML Transmit channel

AN37 PCML Transmit channel

AL37 PCML Transmit channel

AG37 PCML Transmit channel

AW36 PCML Receive channel

AP38 PCML Receive channel

AM38 PCML Receive channel

AH38 PCML Receive channel

AW37 PCML Receive channel

AP39 PCML Receive channel

AM39 PCML Receive channel

AH39 PCML Receive channel

J33 2.5-V CMOS FMC geographical address 0

R30 2.5-V CMOS FMC geographical address 1

AG32 LVDS Transceiver reference clock 0

AG33 LVDS Transceiver reference clock 0

AE31 LVDS Transceiver reference clock 1

AE32 LVDS Transceiver reference clock 1

F32 2.5-V CMOS

FMC general purpose IO bit 0 (part of the partially populated HPS connector signal group)

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

2–34 Chapter 2: Board Components

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Table 2–22. FMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

(J4)

E19

K19

K20

J21

J22

K22

K23

D30

D31

D33

D34

G31

G25

G22

F11

G19

D24

G16

C15

C11

G34

G37

D21

G10

G28

F20

C19

G30

G24

G21

F10

Schematic Signal Name

FMCB_GPIO1

FMCB_GPIO2

FMCB_GPIO3

FMCB_GPIO4

FMCB_GPIO5

FMCB_GPIO6

FMCB_GPIO7

FMCB_JTAG_TDI

FMCB_JTAG_TDO

FMCB_JTAG_TMS

FMCB_JTAG_RST

FMCB_LA_RX_CLK_P

FMCB_LA_RX_CLK_N

FMCB_LA_RX_N0

FMCB_LA_RX_N1

FMCB_LA_RX_N2

FMCB_LA_RX_N3

FMCB_LA_RX_N4

FMCB_LA_RX_N5

FMCB_LA_RX_N6

FMCB_LA_RX_N7

FMCB_LA_RX_N8

FMCB_LA_RX_N9

FMCB_LA_RX_N10

FMCB_LA_RX_N11

FMCB_LA_RX_N12

FMCB_LA_RX_N13

FMCB_LA_RX_N14

FMCB_LA_RX_N15

FMCB_LA_RX_P0

FMCB_LA_RX_P1

FMCB_LA_RX_P2

FMCB_LA_RX_P3

Arria V SoC Pin Number

G32 2.5-V CMOS

U19 2.5-V CMOS

U20 2.5-V CMOS

P20 2.5-V CMOS

R20 2.5-V CMOS

L20 2.5-V CMOS

M20 2.5-V CMOS

I/O Standard Description

FMC general purpose IO bit 1 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 2 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 3 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 4 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 5 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 6 (part of the partially populated HPS connector signal group)

FMC general purpose IO bit 7 (part of the partially populated HPS connector signal group)

— 2.5-V CMOS JTAG data in

— 2.5-V CMOS JTAG data out

— 2.5-V CMOS JTAG mode select

— 2.5-V CMOS JTAG mode reset

E34 LVDS Secondary carrier-bound clock

F34 LVDS Secondary carrier-bound clock

A30 2.5-V CMOS FMC data bus

B33 2.5-V CMOS FMC data bus

D31 2.5-V CMOS FMC data bus

P31 2.5-V CMOS FMC data bus

N32 2.5-V CMOS FMC data bus

C30 2.5-V CMOS FMC data bus

M33 2.5-V CMOS FMC data bus

N33 2.5-V CMOS FMC data bus

P30 2.5-V CMOS FMC data bus

C29 2.5-V CMOS FMC data bus

A28 2.5-V CMOS FMC data bus

D29 2.5-V CMOS FMC data bus

T29 2.5-V CMOS FMC data bus

A35 2.5-V CMOS FMC data bus

D28 2.5-V CMOS FMC data bus

N29 2.5-V CMOS FMC data bus

B31 2.5-V CMOS FMC data bus

A33 2.5-V CMOS FMC data bus

C31 2.5-V CMOS FMC data bus

N31 2.5-V CMOS FMC data bus

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–35

Components and Interfaces

Table 2–22. FMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference

(J4)

G18

D23

G15

C14

C10

G33

G36

D20

G27

F19

C18

D15

H23

H38

H20

H17

H32

G13

H11

H29

H14

H26

D12

D27

D18

H35

D14

H22

H37

H19

H16

H31

G12

H10

Schematic Signal Name

FMCB_LA_RX_P4

FMCB_LA_RX_P5

FMCB_LA_RX_P6

FMCB_LA_RX_P7

FMCB_LA_RX_P8

FMCB_LA_RX_P9

FMCB_LA_RX_P10

FMCB_LA_RX_P11

FMCB_LA_RX_P12

FMCB_LA_RX_P13

FMCB_LA_RX_P14

FMCB_LA_RX_P15

FMCB_LA_TX_CLK_P

FMCB_LA_TX_CLK_N

FMCB_LA_TX_N0

FMCB_LA_TX_N1

FMCB_LA_TX_N2

FMCB_LA_TX_N3

FMCB_LA_TX_N4

FMCB_LA_TX_N5

FMCB_LA_TX_N6

FMCB_LA_TX_N7

FMCB_LA_TX_N9

FMCB_LA_TX_N10

FMCB_LA_TX_N12

FMCB_LA_TX_N13

FMCB_LA_TX_N14

FMCB_LA_TX_N15

FMCB_LA_TX_N16

FMCB_LA_TX_N17

FMCB_LA_TX_P0

FMCB_LA_TX_P1

FMCB_LA_TX_P2

FMCB_LA_TX_P3

FMCB_LA_TX_P4

FMCB_LA_TX_P5

FMCB_LA_TX_P6

FMCB_LA_TX_P7

Arria V SoC Pin Number

I/O Standard Description

M32 2.5-V CMOS FMC data bus

B30 2.5-V CMOS FMC data bus

L33 2.5-V CMOS FMC data bus

N34 2.5-V CMOS FMC data bus

N30 2.5-V CMOS FMC data bus

B28 2.5-V CMOS FMC data bus

A29 2.5-V CMOS FMC data bus

D30 2.5-V CMOS FMC data bus

R29 2.5-V CMOS FMC data bus

B34 2.5-V CMOS FMC data bus

C28 2.5-V CMOS FMC data bus

M29 2.5-V CMOS FMC data bus

L30 2.5-V CMOS Mezzanine-bound clock

M30 2.5-V CMOS Mezzanine-bound clock

A32 2.5-V CMOS FMC data bus

J31 2.5-V CMOS FMC data bus

D32 2.5-V CMOS FMC data bus

K32 2.5-V CMOS FMC data bus

K34 2.5-V CMOS FMC data bus

F31 2.5-V CMOS FMC data bus

M34 2.5-V CMOS FMC data bus

M31 2.5-V CMOS FMC data bus

F33 2.5-V CMOS FMC data bus

K30 2.5-V CMOS FMC data bus

G30 2.5-V CMOS FMC data bus

J28 2.5-V CMOS FMC data bus

G28 2.5-V CMOS FMC data bus

G29 2.5-V CMOS FMC data bus

K29 2.5-V CMOS FMC data bus

D33 2.5-V CMOS FMC data bus

A31 2.5-V CMOS FMC data bus

H31 2.5-V CMOS FMC data bus

C32 2.5-V CMOS FMC data bus

J32 2.5-V CMOS FMC data bus

J34 2.5-V CMOS FMC data bus

E31 2.5-V CMOS FMC data bus

L34 2.5-V CMOS FMC data bus

L31 2.5-V CMOS FMC data bus

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

2–36 Chapter 2: Board Components

Components and Interfaces

Table 2–22. FMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board

Reference

(J4)

H28

H13

H25

D11

D26

D17

H34

C30

C31

D29

C23

C22

C27

C26

Schematic Signal Name

FMCB_LA_TX_P9

FMCB_LA_TX_P10

FMCB_LA_TX_P12

FMCB_LA_TX_P13

FMCB_LA_TX_P14

FMCB_LA_TX_P15

FMCB_LA_TX_P16

FMCB_LA_TX_P17

FMCB_M2C_PG

FMCB_PRSNT

FMCB_SCL

FMCB_SDA

JTAG_MUX_TCK

LMK_CLK_FMCB_N

LMK_CLK_FMCB_P

LMK_SYSREF_FMCB_N

LMK_SYSREF_FMCB_P

Arria V SoC Pin Number

I/O Standard Description

E33 2.5-V CMOS FMC data bus

J30 2.5-V CMOS FMC data bus

F30 2.5-V CMOS FMC data bus

H28 2.5-V CMOS FMC data bus

F28 2.5-V CMOS FMC data bus

F29 2.5-V CMOS FMC data bus

J29 2.5-V CMOS FMC data bus

C33 2.5-V CMOS FMC data bus

— 2.5-V CMOS Power good input

L19 2.5-V CMOS FMC module present

N19 2.5-V CMOS Management serial clock line

M19 2.5-V CMOS Management serial data line

AV34 2.5-V CMOS JTAG chain clock

— 2.5-V CMOS Alternate mezzanine-bound clock (from LMK device)

—2.5-V CMOS

Alternate mezzanine-bound SYSREF signal (from LMK device)

RS-232 UART (HPS)

The development board supports two UART interfaces that connect to a mini-USB connector (J27) using a FT232RQ-REEL USB-to-UART bridge. The maximum supported rate for this interface is 1 Mbps. Board reference D21–D24 are the UART LEDs that illuminate to indicate TX and RX activity.

Tab le 2 –2 3 lists the RS-232 UART pin assignments, signal names, and functions. The

signal names and types are relative to the Arria V SoC in terms of I/O setting and direction.

Table 2–23. RS-232 UART Schematic Signal Names and Functions

Board Reference

UART Port A (U25)

UART Port B (U36)

Schematic Signal

Name

UARTA_TX

UARTA_RX

RESET_HPS_UARTA_N

POWER_ENA

UARTB_TX

UARTB_RX

Arria V SoC Pin

Number

M13 3.3-V Transmit data

M12 3.3-V Receive data

— 3.3-V Reset

—3.3-VPower

N13 3.3-V Transmit data

G13 3.3-V Receive data

I/O Standard Description

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–37

Components and Interfaces

Table 2–23. RS-232 UART Schematic Signal Names and Functions

Board Reference

Schematic Signal

Name

RESET_HPS_UARTB_N

POWER_ENB

Arria V SoC Pin

Number

— 3.3-V Reset

—3.3-VPower

Real-Time Clock (HPS)

The HPS system has a battery-backed real-time clock (RTC) connected through the I2C interface. The RTC is implemented using a DS1339 device from Maxim Semiconductor. The device has a built-in power sense circuit that detects power failures and automatically switches to backup battery supply, maintaining time. The device uses a CR1225 lithium coin battery with a nominal voltage of 3 V. Using typical current capacity, the RTC is expected to have 120,000 backup hours. The battery is mounted inside a holder attached to the board to allow battery replacement or removal.

Tab le 2 –2 4 lists the RTC device pin assignments, signal names, and functions. The

signal names and types are relative to the Arria V SoC in terms of I/O setting and direction.

Table 2–24. RTC Device Schematic Signal Names and Functions

Board

Reference (U11)

Schematic Signal

Name

I2C_SDA_HPS

I2C_SCL_HPS

Arria V SoC Pin

Number

C13 3.3-V Management serial data

L13 3.3-V Management serial clock

I/O Standard Description

SFP+

The development board include two SFP+ ports that uses two transceiver channels from the FPGA. These ports takes in serial data from the FPGA and transform them into optical signals. Both SFP+ ports are active and include the SFP+ cage assembly.

Tab le 2 –2 5 list the SFP+ ports interface pin assignments, signal names, and functions.

Table 2–25. SFP+ Ports Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference

SFP+ Port A (J44)

Schematic

Signal Name

SFPA_MOD0_PRSNTn

SFPA_LOS

SFPA_TXFAULT

SFPA_RX_N

SFPA_RX_P

SFPA_MOD1_SCL

SFPA_MOD1_SDA

SFPA_TXDISABLE

SFPA_TX_N

Arria V SoC Pin Number

AR9 3.3-V LVTTL Module present indicator

AV7 3.3-V LVTTL Signal present indicator

AL9 3.3-V LVTTL Transmitter fault indicator

AE2 PCML Receiver data

AE1 PCML Receiver data

AT8 3.3-V LVTTL Serial 2-wire clock

AH8 3.3-V LVTTL Serial 2-wire data

AP7 3.3-V LVTTL Drive low to disable transmitter

AD4 PCML Transmitter data

I/O Standard Description

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

2–38 Chapter 2: Board Components

Components and Interfaces

Table 2–25. SFP+ Ports Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Board

Reference

SFP+ Port B (J43)

Schematic

Signal Name

SFPA_TX_P

SFPA_RATESEL0

SFPA_RATESEL1

SFPB_MOD0_PRSNTn

SFPB_LOS

SFPB_TXFAULT

SFPB_RX_N

SFPB_RX_P

SFPB_MOD1_SCL

SFPB_MOD1_SDA

SFPB_TXDISABLE

SFPB_TX_N

SFPB_TX_P

SFPB_RATESEL0

SFPB_RATESEL1

Arria V SoC Pin Number

I/O Standard Description

AD3 PCML Transmitter data

AU6 3.3-V LVTTL Rate select

AL8 3.3-V LVTTL Rate select

AP8 3.3-V LVTTL Module present indicator

AG21 3.3-V LVTTL Signal present indicator

AK20 3.3-V LVTTL Transmitter fault indicator

W2 PCML Receiver data

W1 PCML Receiver data

AN8 3.3-V LVTTL Serial 2-wire clock

AJ7 3.3-V LVTTL Serial 2-wire data

AT6 3.3-V LVTTL Drive low to disable transmitter

Y4 PCML Rate select

Y3 PCML Rate select

AK8 3.3-V LVTTL Reserved

AN7 3.3-V LVTTL Reserved

I2C Interface

The HPS system has one I2C interface for communicating with the on-board and external components using a data rate of 400 Kbps.

Tab le 2 –2 6 lists the I

Table 2–26. I2C interface address map

C interface address map.

Address Device

0x68 Real-time clock

0x50 LCD

0x51 EEPROM

0x5C HPS power monitor

0x5E FPGA power monitor 1

0x62 FPGA power monitor 2

0x55 Si571 programmable oscillator

0x66 Si570 programmable oscillator

0x70 Si5338 quad-programmable clock

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–39

Memory

This section describes the development board’s memory interface support and also their signal names, types, and connectivity relative to the Arria V SoC. The development board has the following memory interfaces:

■ DDR3 SDRAM (FPGA)

■ DDR3 SDRAM (HPS)

■ QSPI flash (HPS)

■ EPCQ flash

■ Synchronous flash

■ Micro SD flash memory

■ I

C EEPROM

f For more information about the memory interfaces, refer to the following documents:

■ Timing Analysis section in the External Memory Interface Handbook.

■ DDR, DDR2, and DDR3 SDRAM Design Tutorials section in the External Memory

Interface Handbook.

DDR3 SDRAM (FPGA)

The development board supports two 32Mx16x8 DDR3 SDRAM interface for very high-speed sequential memory access. The 32-bit data bus comprises of two ×16 devices with a single address or command bus. This interface connects to the dedicated HMC I/O banks on the bottom edge of the FPGA.

The DDR3 device shipped with this board are running at 533 MHz, for a total theoretical bandwidth of over 25.6 Gbps. The speed grade of this DDR3 device is 800 MHz with a CAS latency of 9.

Tab le 2 –2 7 lists the DDR3 SDRAM pin assignments, signal names, and functions. The

signal names and types are relative to the Arria V SoC in terms of I/O setting and direction.

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 7)

Board

Reference

DDR3 x32 (U37)

Schematic

Signal Name

DDR3A_A0

DDR3A_A1

DDR3A_A2

DDR3A_A3

DDR3A_A4

DDR3A_A5

DDR3A_A6

DDR3A_A7

Arria V SoC Pin

Number

I/O Standard Description

AU29 1.5-V SSTL Class I Address bus

AT29 1.5-V SSTL Class I Address bus

AV30 1.5-V SSTL Class I Address bus

AU30 1.5-V SSTL Class I Address bus

AT30 1.5-V SSTL Class I Address bus

AR30 1.5-V SSTL Class I Address bus

AL30 1.5-V SSTL Class I Address bus

AK30 1.5-V SSTL Class I Address bus

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

2–40 Chapter 2: Board Components

Memory

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 7)

Board

Reference

Schematic

Signal Name

DDR3A_A8

DDR3A_A9

DDR3A_A10

DDR3A_A11

DDR3A_A12

DDR3A_A13

DDR3A_A14

DDR3A_BA0

DDR3A_BA1

DDR3A_BA2

DDR3A_CASN

DDR3A_CKE

DDR3A_CLK_P

DDR3A_CLK_N

DDR3A_CSN

DDR3A_DM2

DDR3A_DM3

DDR3A_DQ16

DDR3A_DQ17

DDR3A_DQ18

DDR3A_DQ19

DDR3A_DQ20

DDR3A_DQ21

DDR3A_DQ22

DDR3A_DQ23

DDR3A_DQ24

DDR3A_DQ25

DDR3A_DQ26

DDR3A_DQ27

DDR3A_DQ28

DDR3A_DQ29

DDR3A_DQ30

DDR3A_DQ31

DDR3A_DQS_P2

DDR3A_DQS_N2

Arria V SoC Pin

Number

I/O Standard Description

AW31 1.5-V SSTL Class I Address bus

AW30 1.5-V SSTL Class I Address bus

AV31 1.5-V SSTL Class I Address bus

AU31 1.5-V SSTL Class I Address bus

AH30 1.5-V SSTL Class I Address bus

AG30 1.5-V SSTL Class I Address bus

AE29 1.5-V SSTL Class I Address bus

AT31 1.5-V SSTL Class I Bank address bus

AR31 1.5-V SSTL Class I Bank address bus

AP31 1.5-V SSTL Class I Bank address bus

AW32 1.5-V SSTL Class I Row address select

AP30 1.5-V SSTL Class I Column address select

AP29

AN29

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential output clock

AP32 1.5-V SSTL Class I Chip select

AF27 1.5-V SSTL Class I Write mask byte lane

AK25 1.5-V SSTL Class I Write mask byte lane

AH25 1.5-V SSTL Class I Data bus

AG25 1.5-V SSTL Class I Data bus

AE26 1.5-V SSTL Class I Data bus

AH26 1.5-V SSTL Class I Data bus

AG26 1.5-V SSTL Class I Data bus

AD25 1.5-V SSTL Class I Data bus

AC25 1.5-V SSTL Class I Data bus

AB25 1.5-V SSTL Class I Data bus

AV24 1.5-V SSTL Class I Data bus

AV25 1.5-V SSTL Class I Data bus

AL26 1.5-V SSTL Class I Data bus

AW26 1.5-V SSTL Class I Data bus

AW25 1.5-V SSTL Class I Data bus

AT25 1.5-V SSTL Class I Data bus

AN25 1.5-V SSTL Class I Data bus

AM25 1.5-V SSTL Class I Data bus

AF25

AE25

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 2

Data strobe N byte lane 2

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–41

Memory

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 7)

Board

Reference

DDR3 x16 (U29)

Schematic

Signal Name

DDR3A_DQS_P3

DDR3A_DQS_N3

DDR3A_ODT

DDR3A_RASN

DDR3A_RESETN

DDR3A_WEN

DDR3A_ZQ1

DDR3A_A0

DDR3A_A1

DDR3A_A2

DDR3A_A3

DDR3A_A4

DDR3A_A5

DDR3A_A6

DDR3A_A7

DDR3A_A8

DDR3A_A9

DDR3A_A10

DDR3A_A11

DDR3A_A12

DDR3A_A13

DDR3A_A14

DDR3A_BA0

DDR3A_BA1

DDR3A_BA2

DDR3A_CASN

DDR3A_CKE

DDR3A_CLK_P

DDR3A_CLK_N

DDR3A_CSN

DDR3A_DM0

DDR3A_DM1

DDR3A_DQ0

DDR3A_DQ1

DDR3A_DQ2

DDR3A_DQ3

Arria V SoC Pin

Number

AU26

AT26

I/O Standard Description

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 3

Data strobe N byte lane 3

AM31 1.5-V SSTL Class I On-die termination enable

AN31 1.5-V SSTL Class I Row address select

AB29 1.5-V SSTL Class I Reset

AW33 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

AU29 1.5-V SSTL Class I Address bus

AT29 1.5-V SSTL Class I Address bus

AV30 1.5-V SSTL Class I Address bus

AU30 1.5-V SSTL Class I Address bus

AT30 1.5-V SSTL Class I Address bus

AR30 1.5-V SSTL Class I Address bus

AL30 1.5-V SSTL Class I Address bus

AK30 1.5-V SSTL Class I Address bus

AW31 1.5-V SSTL Class I Address bus

AW30 1.5-V SSTL Class I Address bus

AV31 1.5-V SSTL Class I Address bus

AU31 1.5-V SSTL Class I Address bus

AH30 1.5-V SSTL Class I Address bus

AG30 1.5-V SSTL Class I Address bus

AE29 1.5-V SSTL Class I Address bus

AT31 1.5-V SSTL Class I Bank address bus

AR31 1.5-V SSTL Class I Bank address bus

AP31 1.5-V SSTL Class I Bank address bus

AW32 1.5-V SSTL Class I Row address select

AP30 1.5-V SSTL Class I Column address select

AP29 1.5-V SSTL Class I Differential output clock

AN29 1.5-V SSTL Class I Differential output clock

AP32 1.5-V SSTL Class I Chip select

AF27 1.5-V SSTL Class I Write mask byte lane

AK25 1.5-V SSTL Class I Write mask byte lane

AH25 1.5-V SSTL Class I Data bus

AG25 1.5-V SSTL Class I Data bus

AE26 1.5-V SSTL Class I Data bus

AH26 1.5-V SSTL Class I Data bus

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Reference Manual

2–42 Chapter 2: Board Components

Memory

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 7)

Board

Reference

Schematic

Signal Name

DDR3A_DQ4

DDR3A_DQ5

DDR3A_DQ6

DDR3A_DQ7

DDR3A_DQ8

DDR3A_DQ9

DDR3A_DQ10

DDR3A_DQ11

DDR3A_DQ12

DDR3A_DQ13

DDR3A_DQ14

DDR3A_DQ15

DDR3A_DQS_P0

DDR3A_DQS_N0

DDR3A_DQS_P1

DDR3A_DQS_N1

DDR3A_ODT

DDR3A_RASN

DDR3A_RESETN

DDR3A_WEN

DDR3A_ZQ

Arria V SoC Pin

Number

I/O Standard Description

AG26 1.5-V SSTL Class I Data bus

AD25 1.5-V SSTL Class I Data bus

AC25 1.5-V SSTL Class I Data bus

AB25 1.5-V SSTL Class I Data bus

AV24 1.5-V SSTL Class I Data bus

AV25 1.5-V SSTL Class I Data bus

AL26 1.5-V SSTL Class I Data bus

AW26 1.5-V SSTL Class I Data bus

AW25 1.5-V SSTL Class I Data bus

AT25 1.5-V SSTL Class I Data bus

AN25 1.5-V SSTL Class I Data bus

AM25 1.5-V SSTL Class I Data bus

AF25

AE25

AU26

AT26

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 0

Data strobe N byte lane 0

Data strobe P byte lane 1

Data strobe N byte lane 1

AM31 1.5-V SSTL Class I On-die termination enable

AN31 1.5-V SSTL Class I Row address select

AB29 1.5-V SSTL Class I Reset

AW33 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x32 (U49)

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

DDR3B_A0

DDR3B_A1

DDR3B_A2

DDR3B_A3

DDR3B_A4

DDR3B_A5

DDR3B_A6

DDR3B_A7

DDR3B_A8

DDR3B_A9

DDR3B_A10

DDR3B_A11

DDR3B_A12

AP16 1.5-V SSTL Class I Address bus

AN16 1.5-V SSTL Class I Address bus

AK16 1.5-V SSTL Class I Address bus

AJ16 1.5-V SSTL Class I Address bus

AV16 1.5-V SSTL Class I Address bus

AU16 1.5-V SSTL Class I Address bus

AT16 1.5-V SSTL Class I Address bus

AR16 1.5-V SSTL Class I Address bus

AP17 1.5-V SSTL Class I Address bus

AN17 1.5-V SSTL Class I Address bus

AH17 1.5-V SSTL Class I Address bus

AG17 1.5-V SSTL Class I Address bus

AM18 1.5-V SSTL Class I Address bus

Chapter 2: Board Components 2–43

Memory

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 7)

Board

Reference

Schematic

Signal Name

DDR3B_A13

DDR3B_A14

DDR3B_BA0

DDR3B_BA1

DDR3B_BA2

DDR3B_CASN

DDR3B_CKE

DDR3B_CLK_P

DDR3B_CLK_N

DDR3B_CSN

DDR3B_DM2

DDR3B_DM3

DDR3B_DQ16

DDR3B_DQ17

DDR3B_DQ18

DDR3B_DQ19

DDR3B_DQ20

DDR3B_DQ21

DDR3B_DQ22

DDR3B_DQ23

DDR3B_DQ24

DDR3B_DQ25

DDR3B_DQ26

DDR3B_DQ27

DDR3B_DQ28

DDR3B_DQ29

DDR3B_DQ30

DDR3B_DQ31

DDR3B_DQS_P2

DDR3B_DQS_N2

DDR3B_DQS_P3

DDR3B_DQS_N3

DDR3B_ODT

DDR3B_RASN

Arria V SoC Pin

Number

I/O Standard Description

AL18 1.5-V SSTL Class I Address bus

AG18 1.5-V SSTL Class I Address bus

AE18 1.5-V SSTL Class I Bank address bus

AD18 1.5-V SSTL Class I Bank address bus

AC18 1.5-V SSTL Class I Bank address bus

AR18 1.5-V SSTL Class I Row address select

AM16 1.5-V SSTL Class I Column address select

AF16

AE17

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential output clock

AL17 1.5-V SSTL Class I Chip select

AU12 1.5-V SSTL Class I Write mask byte lane

AV10 1.5-V SSTL Class I Write mask byte lane

AJ13 1.5-V SSTL Class I Data bus

AH13 1.5-V SSTL Class I Data bus

AP12 1.5-V SSTL Class I Data bus

AW11 1.5-V SSTL Class I Data bus

AW10 1.5-V SSTL Class I Data bus

AM13 1.5-V SSTL Class I Data bus

AE13 1.5-V SSTL Class I Data bus

AE14 1.5-V SSTL Class I Data bus

AW9 1.5-V SSTL Class I Data bus

AV9 1.5-V SSTL Class I Data bus

AP11 1.5-V SSTL Class I Data bus

AD13 1.5-V SSTL Class I Data bus

AC13 1.5-V SSTL Class I Data bus

AL12 1.5-V SSTL Class I Data bus

AG13 1.5-V SSTL Class I Data bus

AF13 1.5-V SSTL Class I Data bus

AW12

AV12

AU11

AT11

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 2

Data strobe N byte lane 2

Data strobe P byte lane 3

Data strobe N byte lane 3

AD19 1.5-V SSTL Class I On-die termination enable

AD17 1.5-V SSTL Class I Row address select

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

2–44 Chapter 2: Board Components

Memory

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 7)

Board

Reference

DDR3 x16 (U43)

Schematic

Signal Name

DDR3B_RESETN

DDR3B_WEN

DDR3B_ZQ1

DDR3B_A0

DDR3B_A1

DDR3B_A2

DDR3B_A3

DDR3B_A4

DDR3B_A5

DDR3B_A6

DDR3B_A7

DDR3B_A8

DDR3B_A9

DDR3B_A10

DDR3B_A11

DDR3B_A12

DDR3B_A13

DDR3B_A14

DDR3B_BA0

DDR3B_BA1

DDR3B_BA2

DDR3B_CASN

DDR3B_CKE

DDR3B_CLK_P

DDR3B_CLK_N

DDR3B_CSN

DDR3B_DM0

DDR3B_DM1

DDR3B_DQ0

DDR3B_DQ1

DDR3B_DQ2

DDR3B_DQ3

DDR3B_DQ4

DDR3B_DQ5

DDR3B_DQ6

DDR3B_DQ7

DDR3B_DQ8

Arria V SoC Pin

Number

I/O Standard Description

AN15 1.5-V SSTL Class I Reset

AP18 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

AP16 1.5-V SSTL Class I Address bus

AN16 1.5-V SSTL Class I Address bus

AK16 1.5-V SSTL Class I Address bus

AJ16 1.5-V SSTL Class I Address bus

AV16 1.5-V SSTL Class I Address bus

AU16 1.5-V SSTL Class I Address bus

AT16 1.5-V SSTL Class I Address bus

AR16 1.5-V SSTL Class I Address bus

AP17 1.5-V SSTL Class I Address bus

AN17 1.5-V SSTL Class I Address bus

AH17 1.5-V SSTL Class I Address bus

AG17 1.5-V SSTL Class I Address bus

AM18 1.5-V SSTL Class I Address bus

AL18 1.5-V SSTL Class I Address bus

AG18 1.5-V SSTL Class I Address bus

AE18 1.5-V SSTL Class I Bank address bus

AD18 1.5-V SSTL Class I Bank address bus

AC18 1.5-V SSTL Class I Bank address bus

AR18 1.5-V SSTL Class I Row address select

AM16 1.5-V SSTL Class I Column address select

AF16 1.5-V SSTL Class I Differential output clock

AE17 1.5-V SSTL Class I Differential output clock

AL17 1.5-V SSTL Class I Chip select

AD16 1.5-V SSTL Class I Write mask byte lane

AU13 1.5-V SSTL Class I Write mask byte lane

AU15 1.5-V SSTL Class I Data bus

AT15 1.5-V SSTL Class I Data bus

AH15 1.5-V SSTL Class I Data bus

AW13 1.5-V SSTL Class I Data bus

AV13 1.5-V SSTL Class I Data bus

AL15 1.5-V SSTL Class I Data bus

AW15 1.5-V SSTL Class I Data bus

AW14 1.5-V SSTL Class I Data bus

AE15 1.5-V SSTL Class I Data bus

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–45

Memory

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 7 of 7)

Board

Reference

Schematic

Signal Name

DDR3B_DQ9

DDR3B_DQ10

DDR3B_DQ11

DDR3B_DQ12

DDR3B_DQ13

DDR3B_DQ14

DDR3B_DQ15

DDR3B_DQS_P0

DDR3B_DQS_N0

DDR3B_DQS_P1

DDR3B_DQS_N1

DDR3B_ODT

DDR3B_RASN

DDR3B_RESETN

DDR3B_WEN

DDR3B_ZQ

Arria V SoC Pin

Number

AD15 1.5-V SSTL Class I Data bus

AH14 1.5-V SSTL Class I Data bus

AP14 1.5-V SSTL Class I Data bus

AN14 1.5-V SSTL Class I Data bus

AL14 1.5-V SSTL Class I Data bus

AU14 1.5-V SSTL Class I Data bus

AT14 1.5-V SSTL Class I Data bus

AH16

AG16

AF15

AE16

AD19 1.5-V SSTL Class I On-die termination enable

AD17 1.5-V SSTL Class I Row address select

AN15 1.5-V SSTL Class I Reset

AP18 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

I/O Standard Description

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 0

Data strobe N byte lane 0

Data strobe P byte lane 1

Data strobe N byte lane 1

DDR3 SDRAM (HPS)

The development board supports three 32Mx16x8 banks DDR3 SDRAM interface with ECC for very high-speed sequential memory access. The 40-bit data bus comprises of three ×16 devices with a single address or command bus. This interface connects to the dedicated HMC for HPS I/O banks on the top edge of the FPGA.

The DDR3 device shipped with this board are running at 533 MHz, for a total theoretical bandwidth of over 25.6 Gbps. The speed grade of this DDR3 device is 800 MHz with a CAS latency of 9.

Tab le 2 –2 7 lists the DDR3 SDRAM pin assignments, signal names, and functions. The

signal names and types are relative to the Arria V SoC in terms of I/O setting and direction.

Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5)

Board

Reference

DDR3 x16 (U51)

Schematic

Signal Name

DDR3_HPS_A0

DDR3_HPS_A1

DDR3_HPS_A2

DDR3_HPS_A3

Arria V SoC Pin

Number

N9 1.5-V SSTL Class I Address bus

M9 1.5-V SSTL Class I Address bus

N10 1.5-V SSTL Class I Address bus

M10 1.5-V SSTL Class I Address bus

I/O Standard Description

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

2–46 Chapter 2: Board Components

Memory

Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)

Board

Reference

Schematic

Signal Name

DDR3_HPS_A4

DDR3_HPS_A5

DDR3_HPS_A6

DDR3_HPS_A7

DDR3_HPS_A8

DDR3_HPS_A9

DDR3_HPS_A10

DDR3_HPS_A11

DDR3_HPS_A12

DDR3_HPS_A13

DDR3_HPS_A14

DDR3_HPS_BA0

DDR3_HPS_BA1

DDR3_HPS_BA2

DDR3_HPS_CASN

DDR3_HPS_CKE

DDR3_HPS_CLK_P

DDR3_HPS_CLK_N

DDR3_HPS_CSN

DDR3_HPS_DM4

DDR3_HPS_DQ32

DDR3_HPS_DQ33

DDR3_HPS_DQ34

DDR3_HPS_DQ35

DDR3_HPS_DQ36

DDR3_HPS_DQ37

DDR3_HPS_DQ38

DDR3_HPS_DQ39

DDR3_HPS_DQS_P4

DDR3_HPS_DQS_N4

DDR3_HPS_ODT

DDR3_HPS_RASN

DDR3_HPS_RESETN

DDR3_HPS_WEN

DDR3_HPS_ZQ01

Arria V SoC Pin

Number

I/O Standard Description

A8 1.5-V SSTL Class I Address bus

B7 1.5-V SSTL Class I Address bus

B9 1.5-V SSTL Class I Address bus

A9 1.5-V SSTL Class I Address bus

D9 1.5-V SSTL Class I Address bus

C10 1.5-V SSTL Class I Address bus

K7 1.5-V SSTL Class I Address bus

J7 1.5-V SSTL Class I Address bus

F9 1.5-V SSTL Class I Address bus

E9 1.5-V SSTL Class I Address bus

D11 1.5-V SSTL Class I Address bus

L7 1.5-V SSTL Class I Bank address bus

C9 1.5-V SSTL Class I Bank address bus

D8 1.5-V SSTL Class I Bank address bus

G9 1.5-V SSTL Class I Row address select

R8 1.5-V SSTL Class I Column address select

A11

B10

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential output clock

H9 1.5-V SSTL Class I Chip select

T7 1.5-V SSTL Class I Write mask byte lane

G1 1.5-V SSTL Class I Data bus

F1 1.5-V SSTL Class I Data bus

P6 1.5-V SSTL Class I Data bus

L1 1.5-V SSTL Class I Data bus

M2 1.5-V SSTL Class I Data bus

M1 1.5-V SSTL Class I Data bus

N1 1.5-V SSTL Class I Data bus

R6 1.5-V SSTL Class I Data bus

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 4

Data strobe N byte lane 4

H7 1.5-V SSTL Class I On-die termination enable

G8 1.5-V SSTL Class I Row address select

E3 1.5-V SSTL Class I Reset

J8 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–47

Memory

Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)

Board

Reference

DDR3 x16 (U44)

Schematic

Signal Name

DDR3_HPS_A0

DDR3_HPS_A1

DDR3_HPS_A2

DDR3_HPS_A3

DDR3_HPS_A4

DDR3_HPS_A5

DDR3_HPS_A6

DDR3_HPS_A7

DDR3_HPS_A8

DDR3_HPS_A9

DDR3_HPS_A10

DDR3_HPS_A11

DDR3_HPS_A12

DDR3_HPS_A13

DDR3_HPS_A14

DDR3_HPS_BA0

DDR3_HPS_BA1

DDR3_HPS_BA2

DDR3_HPS_CASN

DDR3_HPS_CKE

DDR3_HPS_CLK_P

DDR3_HPS_CLK_N

DDR3_HPS_CSN

DDR3_HPS_DM2

DDR3_HPS_DM3

DDR3_HPS_DQ16

DDR3_HPS_DQ17

DDR3_HPS_DQ18

DDR3_HPS_DQ19

DDR3_HPS_DQ20

DDR3_HPS_DQ21

DDR3_HPS_DQ22

DDR3_HPS_DQ23

DDR3_HPS_DQ24

DDR3_HPS_DQ25

DDR3_HPS_DQ26

DDR3_HPS_DQ27

Arria V SoC Pin

Number

I/O Standard Description

N9 1.5-V SSTL Class I Address bus

M9 1.5-V SSTL Class I Address bus

N10 1.5-V SSTL Class I Address bus

M10 1.5-V SSTL Class I Address bus

A8 1.5-V SSTL Class I Address bus

B7 1.5-V SSTL Class I Address bus

B9 1.5-V SSTL Class I Address bus

A9 1.5-V SSTL Class I Address bus

D9 1.5-V SSTL Class I Address bus

C10 1.5-V SSTL Class I Address bus

K7 1.5-V SSTL Class I Address bus

J7 1.5-V SSTL Class I Address bus

F9 1.5-V SSTL Class I Address bus

E9 1.5-V SSTL Class I Address bus

D11 1.5-V SSTL Class I Address bus

L7 1.5-V SSTL Class I Bank address bus

C9 1.5-V SSTL Class I Bank address bus

D8 1.5-V SSTL Class I Bank address bus

G9 1.5-V SSTL Class I Row address select

R8 1.5-V SSTL Class I Column address select

A11 1.5-V SSTL Class I Differential output clock

B10 1.5-V SSTL Class I Differential output clock

H9 1.5-V SSTL Class I Chip select

D3 1.5-V SSTL Class I Write mask byte lane

D1 1.5-V SSTL Class I Write mask byte lane

J5 1.5-V SSTL Class I Data bus

K5 1.5-V SSTL Class I Data bus

N7 1.5-V SSTL Class I Data bus

F3 1.5-V SSTL Class I Data bus

H3 1.5-V SSTL Class I Data bus

J4 1.5-V SSTL Class I Data bus

M5 1.5-V SSTL Class I Data bus

C3 1.5-V SSTL Class I Data bus

A2 1.5-V SSTL Class I Data bus

A3 1.5-V SSTL Class I Data bus

P7 1.5-V SSTL Class I Data bus

C1 1.5-V SSTL Class I Data bus

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

2–48 Chapter 2: Board Components

Memory

Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)

Board

Reference

DDR3 x16 (U38)

Schematic

Signal Name

DDR3_HPS_DQ28

DDR3_HPS_DQ29

DDR3_HPS_DQ30

DDR3_HPS_DQ31

DDR3_HPS_DQS_P2

DDR3_HPS_DQS_N2

DDR3_HPS_DQS_P3

DDR3_HPS_DQS_N3

DDR3_HPS_ODT

DDR3_HPS_RASN

DDR3_HPS_RESETN

DDR3_HPS_WEN

DDR3_HPS_ZQ2

DDR3_HPS_A0

DDR3_HPS_A1

DDR3_HPS_A2

DDR3_HPS_A3

DDR3_HPS_A4

DDR3_HPS_A5

DDR3_HPS_A6

DDR3_HPS_A7

DDR3_HPS_A8

DDR3_HPS_A9

DDR3_HPS_A10

DDR3_HPS_A11

DDR3_HPS_A12

DDR3_HPS_A13

DDR3_HPS_A14

DDR3_HPS_BA0

DDR3_HPS_BA1

DDR3_HPS_BA2

DDR3_HPS_CASN

DDR3_HPS_CKE

DDR3_HPS_CLK_P

Arria V SoC Pin

Number

I/O Standard Description

G2 1.5-V SSTL Class I Data bus

F2 1.5-V SSTL Class I Data bus

M3 1.5-V SSTL Class I Data bus

E1 1.5-V SSTL Class I Data bus

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 1

Data strobe P byte lane 0

Data strobe N byte lane 1

Data strobe N byte lane 0

H7 1.5-V SSTL Class I On-die termination enable

G8 1.5-V SSTL Class I Row address select

E3 1.5-V SSTL Class I Reset

J8 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

N9 1.5-V SSTL Class I Address bus

M9 1.5-V SSTL Class I Address bus

N10 1.5-V SSTL Class I Address bus

M10 1.5-V SSTL Class I Address bus

A8 1.5-V SSTL Class I Address bus

B7 1.5-V SSTL Class I Address bus

B9 1.5-V SSTL Class I Address bus

A9 1.5-V SSTL Class I Address bus

D9 1.5-V SSTL Class I Address bus

C10 1.5-V SSTL Class I Address bus

K7 1.5-V SSTL Class I Address bus

J7 1.5-V SSTL Class I Address bus

F9 1.5-V SSTL Class I Address bus

E9 1.5-V SSTL Class I Address bus

D11 1.5-V SSTL Class I Address bus

L7 1.5-V SSTL Class I Bank address bus

C9 1.5-V SSTL Class I Bank address bus

D8 1.5-V SSTL Class I Bank address bus

G9 1.5-V SSTL Class I Row address select

R8 1.5-V SSTL Class I Column address select

A11 1.5-V SSTL Class I Differential output clock

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–49

Memory

Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)

Board

Reference

Schematic

Signal Name

DDR3_HPS_CLK_N

DDR3_HPS_CSN

DDR3_HPS_DM0

DDR3_HPS_DM1

DDR3_HPS_DQ0

DDR3_HPS_DQ1

DDR3_HPS_DQ2

DDR3_HPS_DQ3

DDR3_HPS_DQ4

DDR3_HPS_DQ5

DDR3_HPS_DQ6

DDR3_HPS_DQ7

DDR3_HPS_DQ8

DDR3_HPS_DQ9

DDR3_HPS_DQ10

DDR3_HPS_DQ11

DDR3_HPS_DQ12

DDR3_HPS_DQ13

DDR3_HPS_DQ14

DDR3_HPS_DQ15

DDR3_HPS_DQS_P0

DDR3_HPS_DQS_N0

DDR3_HPS_DQS_P1

DDR3_HPS_DQS_N1

DDR3_HPS_ODT

DDR3_HPS_RASN

DDR3_HPS_RESETN

DDR3_HPS_WEN

DDR3_HPS_ZQ

Arria V SoC Pin

Number

I/O Standard Description

B10 1.5-V SSTL Class I Differential output clock

H9 1.5-V SSTL Class I Chip select

C6 1.5-V SSTL Class I Write mask byte lane

E4 1.5-V SSTL Class I Write mask byte lane

D7 1.5-V SSTL Class I Data bus

C7 1.5-V SSTL Class I Data bus

R10 1.5-V SSTL Class I Data bus

G7 1.5-V SSTL Class I Data bus

A6 1.5-V SSTL Class I Data bus

A7 1.5-V SSTL Class I Data bus

L6 1.5-V SSTL Class I Data bus

D6 1.5-V SSTL Class I Data bus

H6 1.5-V SSTL Class I Data bus

G6 1.5-V SSTL Class I Data bus

N8 1.5-V SSTL Class I Data bus

G5 1.5-V SSTL Class I Data bus

A4 1.5-V SSTL Class I Data bus

A5 1.5-V SSTL Class I Data bus

R9 1.5-V SSTL Class I Data bus

F4 1.5-V SSTL Class I Data bus

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 1

Data strobe P byte lane 0

Data strobe N byte lane 1

Data strobe N byte lane 0

H7 1.5-V SSTL Class I On-die termination enable

G8 1.5-V SSTL Class I Row address select

E3 1.5-V SSTL Class I Reset

J8 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

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2–50 Chapter 2: Board Components

Memory

QSPI Flash (HPS)

The development board supports one 1-Gb serial NOR flash device for non-volatile storage of the HPS boot code, user data, and program. The device connects to the HPS dedicated interface and may contain a secondary boot code.

This 4-bit data memory interface can sustain burst read operations at up to 108 MHz for a throughput of 54 MBps. Erase capability is at 4 KB, 64 KB, and 32 MB.

Tab le 2 –2 9 lists the QSPI flash pin assignments, signal names, and functions. The

signal names and types are relative to the Arria V SoC in terms of I/O setting and direction.

Table 2–29. QSPI Flash Schematic Signal Names and Functions

Board

Reference (U19)

EPCQ Flash

Schematic

Signal Name

QSPI_CLK

QSPI_IO0

QSPI_IO1

QSPI_IO2

QSPI_IO3

QSPI_SS0

MAX_QSPI_RSTN

Arria V SoC Pin

Number

F15 3.3-V Clock

D15 3.3-V Data bus

G15 3.3-V Data bus

M15 3.3-V Data bus

H15 3.3-V Data bus

N15 3.3-V Chip enable

— 3.3-V Reset

I/O Standard Description

The development board supports one 256-Mb serial/quad-serial NOR flash device for non-volatile storage of the FPGA configuration image. The device connects to the FPGA dedicated interface through the IDTQS3861 device.

Tab le 2 –3 0 lists the EPCQ flash pin assignments, signal names, and functions. The

signal names and types are relative to the MAX V CPLD 5M2210 System Controller in terms of I/O setting and direction. Some pins are used in other interfaces as well due to functionality sharing.

Table 2–30. EPCQ Flash Schematic Signal Names and Functions

Board

Reference (U28)

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Schematic Signal Name I/O Standard Description

FPGA_DCLK

FPGA_AS_DATA0

FPGA_AS_DATA1

FPGA_AS_DATA2

FPGA_AS_DATA3

FPGA_NCS0

3.3-V Clock

3.3-V Data bus

3.3-V Chip enable

Chapter 2: Board Components 2–51

Memory

Synchronous Flash

The development board supports a 512-Mb CFI-compatible synchronous flash device for non-volatile storage of FPGA configuration data, board information, and test application data. This device connects to the MAX V CPLD 5M2210 System Controller for FPGA configuration in FPP and PS modes.

This 16-bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps per device. The write performance is 270 µs for a single word buffer while the erase time is 800 ms for a 128 K array block.

Tab le 2 –3 1 lists the flash pin assignments, signal names, and functions. The signal

names and types are relative to the MAX V CPLD 5M2210 System Controller in terms of I/O setting and direction.

Table 2–31. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference (U13)

Schematic Signal Name I/O Standard Description

FLASH_ADVN

FLASH_CEN0

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FLASH_WPN

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

1.8-V Address valid

1.8-V Chip enable

1.8-V Clock

1.8-V Output enable

1.8-V Ready

1.8-V Reset

1.8-V Write enable

1.8-V Write protect

1.8-V Address bus

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

2–52 Chapter 2: Board Components

Table 2–31. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Memory

Board

Reference (U13)

Schematic Signal Name I/O Standard Description

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_A26

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

1.8-V Address bus

1.8-V Data bus

Micro SD Flash Memory

The development board supports a micro SD card interface using x4 data lines. The HPS dedicated interface and the USB 2.0 OTG interface are mutually exclusive since both interfaces share some pins. The interface selection is done using the DIP switch. The data and control lines are multiplexed or demultiplexed using on the board’s analog switches. The micro SD card interface may contain secondary boot code.

This 4-bit data interface can sustain burst read operations at up to 50 MHz for a throughput of 25 MBps.

Tab le 2 –3 2 lists the micro SD flash memory interface pin assignments, signal names,

and functions. The signal names and types are relative to the Arria V SoC in terms of I/O setting and direction.

Table 2–32. Micro SD Flash Memory Interface Schematic Signal Names and Functions (Part 1 of 2)

Board

Reference (J5)

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Schematic Signal

Name

SD_CLK

SD_DAT0

Arria V SoC Pin

Number

L16 3.3-V Clock

C17 3.3-V Data bus

I/O Standard Description

Chapter 2: Board Components 2–53

Power Supply

Table 2–32. Micro SD Flash Memory Interface Schematic Signal Names and Functions (Part 2 of 2)

Board

Reference (J5)

Schematic Signal

Name

SD_DAT1

SD_DAT2

SD_CD_DAT3

SD_CMD

Arria V SoC Pin

Number

N16 3.3-V Data bus

J16 3.3-V Data bus

M16 3.3-V Control or data bus

D16 3.3-V Control

I2C EEPROM

This board includes a 32 Kb EEPROM device. This device has a 2-wire I2C serial interface bus and is organized as four blocks of 4K x 8-bit memory. The main function of the device is for EtherCAT IP usage, but it can be used for other storage purposes as well.

Tab le 2 –3 3 lists the I

signal names and types are relative to the Arria V SoC in terms of I/O setting and direction.

Table 2–33. I2C EEPROM Schematic Signal Names and Functions

Board

Reference (U34)

Schematic Signal

Name

I2C_SCL_HPS

I2C_SDA_HPS

C EEPROM pin assignments, signal names, and functions. The

Arria V SoC Pin

Number

L13 3.3-V Management serial clock

C13 3.3-V Management serial data

I/O Standard Description

Power Supply

You can power up the development board from a laptop-style DC power input or through the DC auxiliary connector. The Arria V SoC is designed in such way that the power rails for the HPS and FPGA are independent, allowing power down for the FPGA side when the HPS side is running. This eliminates power consumption on the FPGA part when not in use.

Tab le 2 –3 4 lists the maximum allowed draws of the power input.

Table 2–34. Power Input Maximum Allowed Draws

Source Voltage (V) Wattage (W)

Laptop Supply—DC input

DC auxiliary connector 12.0 200

16.0 300

20.0 200

An on-board multi-channel analog-to-digital converter (ADC) measures the current for several specific board rails.

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2–54 Chapter 2: Board Components

1.5V_HPS

A5ST HPS VCC

1.15 V, 1.0824 A

LTC3605 (5 A)

Switching Regulator (+/- 2%)

0.130 A

1.5V_HPS

VCCIO HPS, VDD DDR3

LTC3605 (5 A)

Switching Regulator (+/- 2%)

0.003 A

1.5 V, 0.021 A

3.3V_HPS

VCCPD, VCCIO, VDD ENET,

EZ-USB, VDD-USB2OTG,

VCC-RS232, VCC-CAN, VDD-QSPI Flash, VCC/Q

Flash, VCC-SDCARD,

VCC-EPCQ

LTC3605 (5 A)

Switching Regulator (+/- 2%)

0.043 A

3.3 V, 0.125 A

2.5V_HPS

VCCPD, VCCIO, VCCRST-CLK,

VCCIO-MAXV, VCCIO-EPM570,

AVDD, VDDO-ENET, Clocks

LTC3605 (5 A)

Switching Regulator (+/- 2%)

0.593 A

2.5 V, 2.278 A

2.5V_HPS_FILT

VCCPLL, VCCAUX

BEAD

2.5V_VCCAUX_SHARED

HPS VCCAUX_SHARED

BEAD

0.760 A

0.001 A

0.767 A

1.2 V,

0.75 A

DVD_ENET

DVD D

LTC3022

1 A LDO

LTC3866 (30 A)

Switching Regulator (+/- 2%)

2.509 A

1.15 V, 20.946 A

1.15V_VCCP

VCCP

BEAD

19.12 A

1.826 A

1.5V_VCC

A5ST FPGA VCC

LTC3605 (5 A)

Switching Regulator (+/- 2%)

0.107 A

1.5 V, 0.890 A

1.5V_FPGA

VCCIO, VDD DDR3

LTC3605 (5 A)

Switching Regulator (+/- 2%)

0.426 A

2.5 V, 1.634 A

2.5V_FPGA_AUX

VCC_FPLL, VCCA, VCC_AUX

BEAD

0.867 A

0.767 A

2.5V_FPGA

VCCPD, VCCPGM, VCCIO

LTM8025 (3 A)

Switching Regulator (+/- 2%)

0.592 A

2.5 V (Default)

2.301 A

FMC

BEAD

0.301 A

2.000 A

VAR_VCCIO

VCCIO FMC

Ideal Diode

Multiplexer

LTC3855 Dual

Channel

Controller

DC Input

19 V

DC AUX

12 V,

7.553 A

124 W Total

5.0V

USB, LTCEXT

12V_EXP

PCIe, FMC

3.3V

PCIe, ECAT-VDD, FMC

1V8

VCCINT/IO-MAXV, VCC-CFI

Flash, VCCINT-EMP570

LTC3509 (Dual 0.7 A)

Switching Regulator (+/- 2%)

0.150 A

5 V, 0.200 A

1.8 V, 0.200 A

12 V, 3.000 A

3.3 V, 8.830 A

3.3 V

10.200 A

LTC3026 (1.5 A) Linear Regulator

0.860 A

1.15V_GXB

VCCR_VCCL_GXB

LTC3026 (1.5 A) Linear Regulator

0.370 A

1.15V_VCCT

VCCT_GXB

LTC3026 (1.5 A) Linear Regulator

0.140 A

1.5V_VCCD/VCCH

VCCD, VCCH

Power Supply

Power Distribution System

Figure 2–9 shows the power distribution system on the development board. Regulator

inefficiencies and sharing are reflected in the currents shown, which are conservative absolute maximum levels.

Figure 2–9. Power Distribution System

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–55

SCK

SPI Bus

DSI

DSO

CSn

8 Ch.

Power Supply Load #0-6

SENSE

MAX V CPLD

5M2210

System

Controller

Arria V SoC

To User PC

JTAG Chain

Feedback

14-pin

2x16

Character

LCD

E RW RS D(0:7)

Supply

#0-6

EPM570

USB PHY

Embedded

USB-Blaster II

Power Supply

Power Measurement

There are eleven power supply rails that have on-board current sense capabilities using 16-bit differential ADC devices. Precision sense resistors split the ADC devices and rails from the primary supply plane for the ADC to measure current.

Figure 2–10 shows the block diagram for the power measurement circuitry.

Figure 2–10. Power Measurement Circuit

Tab le 2 –3 5 lists the targeted rails. The schematic signal name column specifies the

name of the rail being measured while the device pin column specifies the devices attached to the rail.

Table 2–35. Power Measurement Rails (Part 1 of 2)

Channel Schematic Signal Name Voltage (V) Device Pin Description

VCCIO

2.5V_FPGA

2.5

I/O, FPGA internal and peripheral devices VCCPD

VCC

1.5V_FPGA

1.15V_VCC

VAR_VCCIO

1.15V_GXB

1.15V_VCCT

1.5V_VCCD/VCCH

1.15V_HPS

1.5V_HPS

1.5 VCCIO I/O and DDR3 devices

1.15 VCC FPGA core power, transceiver, and clock

2.5, 1.8, 1.5,

1.2

1.15

1.15 VCCT_GXB Transmitter power

1.5

1.15 VCC_HPS HPS core power

VCCIO FMC I/O

VCCR_GXB Receiver power

VCCL_GXB Transceiver clock network

VCCD_FPLL Phase-locked loop (PLL) digital power

VCCH_GXB Transmitter output buffer power

1.5 VCCIO_HPS I/O and DDR3 devices

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Power Supply

Table 2–35. Power Measurement Rails (Part 2 of 2)

Channel Schematic Signal Name Voltage (V) Device Pin Description

VCCPD_HPS

2.5V_HPS

2.5

I/O, HPS internal and peripheral devices VCCIO_HPS

VCC_AUX

3.3V_HPS

3.3

VCCPD_HPS

VCCIO_HPS

I/O and HPS peripheral devices

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

3. Board Components Reference

This chapter lists the component reference and manufacturing information of all the components on the Arria V SoC development board.

Table 3–1. Component Reference and Manufacturing Information

Board

Reference

U41

U27

Component Manufacturer

Arria V SoC FPGA F1517, 462,000 LEs, lead free

MAX V CPLD 5M2210 System Controller

Corporation 5ASTFD5K3F40I3 www.altera.com

Altera

Corporation 5M2210ZF256 www.altera.com

Altera

Manufacturing

Part Number

Manufacturer

Website

U61 High-Speed USB peripheral controller Cypress CY7C68013A www.cypress.com

D9-D16, D20-D24, D33-D36,

Green LEDs Lumex Inc. SML-LXT0805GW-TR www.lumex.com

D38-D43,

D39 Red LED Lumex Inc. SML-LXT0805IW-TR www.lumex.com

D37 Blue LED Lumex Inc. SML-LX0805USBC-TR www.lumex.com

SW2, SW4 Four-position DIP switches

C&K Components/

ITT Industries

TDA04H0SB1

SW1, SW3 Eight-Position DIP switch C & K Components TDA08H0SB1

S1-S9,

S12-S14

Push buttons Panasonic EVQPAC07K www.panasonic.com

www.ck-

components.com

www.ck-

components.com

J17 External Mictor 38-pin connector Tyco Electronics 2-767004-2 www.te.com

X4 50 MHz 1.8-V oscillator ECS, Inc. ECS-3518-500-B-xx www.ecsxtal.com

X5 125.00 MHz LVDS crystal oscillator Epson

C 0x70,

Silicon Labs Si5338C-A01917-GM www.silabs.com

U35

Programmable quad clock, I defaults LVDS 156.25 MHz, 25 MHz,

EG-2121CA

125.0000M-LGPNL3

www.eea.epson.com

25 MHz, 100 MHz default

IC - Pre-programmed (quad clock

U42

generator), 25, 25, 100, 100 MHZ

Silicon Labs Si5335A-B02062-GM www.silabs.com

LVCMOS, 1.8V, 2.5V

U59

IC - PCIE Gen 1/2 dual output clock generator

Silicon Labs SI52112-B3-GM2 www.silabs.com

U30 1 to 3 single-ended clock buffer Silicon Labs SL18860DC www.silabs.com

J29

Programmable LVDS clock 100M defaults

Programmable LVDS clock 148.5M defaults

Silicon Labs 570FAB000973DG www.silabs.com

Silicon Labs 571FAB000973DG www.silabs.com

2×7 pin LCD socket strip Samtec TSM-107-07-G-D www.samtec.com

2×16 character LCD, 5×8 dot matrix Lumex Inc. LCM-S01602DSR/C www.lumex.com

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

3–2 Chapter 3: Board Components Reference

Table 3–1. Component Reference and Manufacturing Information

Board

Reference

Component Manufacturer

U7, U55 Ethernet PHY BASE-T devices

J13

J47, J48

MagJack 1000BaseT, 1×1 integrated connector module (ICM)

RJ45 connector with integrated transformer

Marvell

Semiconductor

Bel Fuse L829-1J1T-43 www.belfuse.com

Wurth Elektronik 7499011121A www.we-online.com

Manufacturing

Part Number

88E1111-B2-

CAA1C000

Manufacturer

Website

www.marvell.com

J42 PCIE socket ×4 Samtec PCIE-064-02-F-D-TH www.samtec.com

FMC 0.050 pitch socket array

J4, J26

assembly, 400 I/O, 40 x 10

Samtec ASP-134486-01 www.samtec.com

configuration

B5 SFP+ right-angle, press-fit cage Molex 74754-0101 www.molex.com

J443, J44

SFP+ right-angle, 20-pin SMT connector

Samtec

MECT-110-01-M-D-

RA1

www.samtec.com

Future Technology

U25, U26 USB to serial UART interface

Devices

FT232RQ www.ftdichip.com

International Ltd.

U11 Real-time clock Maxim DS1339C www.maxim-ic.com

U29, U37, U38, U43,

U44, U51

32M × 16 × 8, 1024-MB DDR3 SDRAM

Micron

MT41K256M16HA-

125:E

www.micron.com

U49

U19 256-Mb QSPI flash Micron N25Q00AA13GSF40F www.micron.com

U13 512-Mb CFI synchronous flash Numonyx PC28F512P30BF www.numonyx.com

U28 256-Mb NOR flash Altera Corporation EPCQ256SI16N www.altera.com

U34 32-Kb I

C EEPROM Microchip 24LC32A www.microchip.com

J5 Micro SD card socket Wurth Elektronik 693 071 010 811 www.we-online.com

U26, U34

Octal digital power supply manager with EEPROM

Linear Technology LTC2978 www.linear.com

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Chapter 3: Board Components Reference 3–3

Statement of China-RoHS Compliance

Tab le 3 –2 lists hazardous substances included with the kit.

Table 3–2. Table of Hazardous Substances’ Name and Concentration Notes

Part Name

Arria V SoC development board X* 0 0 0 0 0

16 V power supply 0 0 0 0 0 0

Type A-B USB cable 0 0 0 0 0 0

User guide 0 0 0 0 0 0

Notes to Table 3–2:

(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the

SJ/T11363-2006 standard.

(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant

threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.

Lead

(Pb)

Cadmium

(Cd)

Hexavalent

Chromium

(Cr6+)

(1), (2)

Mercury

(Hg)

Polybrominated biphenyls (PBB)

Polybrominated diphenyl Ethers

(PBDE)

CE EMI Conformity Caution

This development kit is delivered conforming to relevant standards mandated by Directive 2004/108/EC. Because of the nature of programmable logic devices, it is possible for the user to modify the kit in such a way as to generate electromagnetic interference (EMI) that exceeds the limits established for this equipment. Any EMI caused as the result of modifications to the delivered material is the responsibility of the user.

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

3–4 Chapter 3: Board Components Reference

CE EMI Conformity Caution

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

This chapter provides additional information about the board, document and Altera.

Board Revision History

The following table lists the versions of all releases of the Arria V SoC development board.

Release Date Version Description

December 2013 Engineering silicon Initial release.

Document Revision History

The following table lists the revision history for this document.

Additional Information

Date Version Changes

July 2014 1.2 Added information for PCIe Gen2.

April 2014 1.1

December 2013 1.0 Initial release.

■ Corrected reference manual to include proper F1517 info.

■ Corrected Table 2–8 ON/OFF descriptions.

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the following table.

Contact

Technical support Website www.altera.com/support

Technical training

Product literature Website www.altera.com/literature

Nontechnical support (general) Email nacomp@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

(1)

(software licensing) Email authorization@altera.com

Contact Method Address

Website www.altera.com/training

Email custrain@altera.com

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

Info–2 Additional InformationAdditional Information

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

italic type

Initial Capital Letters

“Subheading Title”

Courier type

r An angled arrow instructs you to press the Enter key.

1., 2., 3., and a., b., c., and so on

■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.

1 The hand points to information that requires special attention. h The question mark directs you to a software help system with related information. f The feet direct you to another document or website with related information. m The multimedia icon directs you to a related multimedia presentation.

Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

Indicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

Indicate keyboard keys and menu names. For example, the Delete key and the Options menu.

Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example,

tdi

, and

input

. The suffix n denotes an active-low signal. For example,

data1

resetn

Indicates command line commands and anything that must be typed exactly as it appears. For example,

c:\qdesigns\tutorial\chiptrip.gdf

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword

TRI

example,

SUBDESIGN

), and logic function names (for

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.

Arria V SoC Development Board July 2014 Altera Corporation Reference Manual

Altera Arria V SoC Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

Board Component Blocks

1. Overview

Development Board Block Diagram

Handling the Board

2. Board Components

Board Overview

Featured Device: Arria V SoC

I/O Resources

MAX V CPLD 5M2210 System Controller

FPGA Configuration

FPGA Programming over On-Board USB-Blaster II

FPGA Programming from Flash Memory

Status Elements

FPGA Programming over External USB-Blaster

Setup Elements

Board Settings DIP Switch

JTAG Chain Control DIP Switch

FPGA Configuration Mode DIP Switch

HPS Jumpers

CPU Reset Push Button

MAX V Reset Push Button

General User Input/Output

Program Configuration Push Button

Program Select Push Button

User-Defined Push Buttons

User-Defined DIP Switch

User-Defined LEDs

Clock Circuitry

Character LCD

On-Board Oscillators

Off-Board Input/Output Clock

Components and Interfaces

PCI Express

10/100/1000 Ethernet (HPS)

10/100 Ethernet (FPGA)

RS-232 UART (HPS)

Real-Time Clock (HPS)

SFP+

I2C Interface

Memory

DDR3 SDRAM (FPGA)

DDR3 SDRAM (HPS)

QSPI Flash (HPS)

EPCQ Flash

Synchronous Flash

Micro SD Flash Memory

Power Supply

I2C EEPROM

Power Distribution System

Power Measurement

3. Board Components Reference

Statement of China-RoHS Compliance

CE EMI Conformity Caution

Board Revision History

Document Revision History

Additional Information

How to Contact Altera

Typographic Conventions