Altera Arria V SoC User Manual
Arria V SoC Development Kit User Guide
Arria V SoC Development Kit
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-01147-1.1
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described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
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June 2014 Altera Corporation Arria V SoC Development Kit
User Guide
Contents
Chapter 1. About This Kit
Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Inspect the Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Chapter 2. Software Installation
About the Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Installing the Quartus II Subscription Edition Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Activating Your License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Installing the Altera SoC Embedded Development Suite (EDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Installing the Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Installing the USB-Blaster II Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Chapter 3. Board Setup and Defaults
Setting Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Factory Default Switch and Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Restoring the MAX V CPLD to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Restoring the CFI Flash Device to the Factory Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Chapter 4. Board Update Portal
Connecting to the Board Update Portal Web Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Chapter 5. Board Test System
Preparing the Board for the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Running the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Using the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
The Configure Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
The System Info Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
The GPIO Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
The I2C Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
The DDR3 A and DDR3 B Tabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Number of Addresses to Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
The XCVR Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
SFP A, SFP B, SMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
The FMC A Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
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iv Contents
XCVR 10G and CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
The FMC B Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14
FMC 10G, FMC 6G, CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14
The Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
U46, U60, U50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
The Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
fXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
Target Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
Set New Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
Configuring the FPGA Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
Before Configuring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
Appendix A. Programming Flash Memory
CFI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
CFI Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Programming CFI Flash Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Converting .sof to .pof . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
Quad SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
Programming Quad SPI Flash using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
SD Card Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
The SD Card Default HPS Boot Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Arria V SoC Development Kit June 2014 Altera Corporation
User Guide
Kit Features
f For a complete list of this kit’s contents and capabilities, refer to the Arria V SoC
1. About This Kit
The Altera® Arria®V system on a chip (SoC) Development Kit is a complete design
environment that includes both the hardware and software you need to develop
Arria V SoC designs.
This section briefly describes the kit contents.
Development Kit page.
The Arria V SoC Development Kit includes the following hardware:
■ Arria V development board—A development platform that allows you to develop
and prototype hardware designs running on the Arria V SoC.
■ MicroSD flash memory card.
■ Loopback FPGA mezzanine card (FMC) daughter card.
■ Power supply and cables—The kit includes the following items:
Before You Begin
Before using the kit or installing the software, check the kit contents and inspect the
boards to verify that you received all of the items listed in Quick Start Guide printout in
the box. If any of the items are missing, contact Altera before you proceed.
Inspect the Boards
To inspect each board, perform these steps:
f For detailed information about the board components and interfaces, refer
to the Arria V SoC Development Board Reference Manual.
■ Power supply and AC adapters for North America/Japan, Europe, and the
United Kingdom.
■ One micro USB and two mini USB cables.
■ Ethernet cable.
1. Place the board on an anti-static surface and inspect it to ensure that it has not been
damaged during shipment.
c Without proper anti-static handling, you can damage the board.
2. Verify that all components on the boards appear in place and intact.
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Before You Begin
1 In smaller applications with the Arria V development board, a heat sink is not
necessary. However, under extreme conditions (or for engineering sample silicon), the
board might require additional cooling to stay within operating temperature
guidelines. The board has two holes near the FPGA that accommodate many different
heat sinks, including the Dynatron V31G. You can perform power consumption and
thermal modeling to determine whether your application requires additional cooling.
For information about measuring board and FPGA power in real time, refer to “The
Power Monitor” on page 5–16.
f For more information about power consumption and thermal modeling,
refer to AN 358: Thermal Management for FPGAs.
References
Use the following links in Tab le 1– 1 to check the Altera website for other related
information:
Table 1–1. Related Links and Documents
Altera Website Link Information
Arria V SoC Development Kit page Latest board design files and reference designs.
Open-source community website supporting SoC
RocketBoards.org
ARM Cortex-A (SoC) On the dual-core ARM Cortex-A9 MPCore processor.
Getting Started for Software Developers Developing software for the Arria V SoC.
SoC Development Kit Hardware Developer
Resource Center
Altera SoC Embedded Design Suite User
Guide
GSRD User Manual page on
RocketBoards.org
ARM Development Studio 5 (DS-5) Altera
Edition Toolkit
Arria V SoC Development Board Reference
Manual
Development Board Daughtercards Additional daughter cards available for purchase.
Documentation: Arria V Devices Arria V device documentation.
Devices Purchase devices from the eStore.
Capture CIS Symbols Arria V OrCAD symbols.
Embedded Processing Nios II 32-bit embedded processor solutions.
development including Altera and Partner SoC
development kit targets and related designs and
documentation.
Developing SoC Hardware designs on the
development kit.
Includes information on the Installing the SoC EDS
and ARM DS-5. Preloader user guide. Hard
Processor System (HPS) Flash programmer. Bare
Metal and Linux Compiler. Yocto plugin. Debugging.
The Golden System Reference Design (GSRD)
demonstrates the HPS ability to communicate
between HPS to the FPGA logic via the AXI Bridge
interfaces.
As a part of the Altera SoC EDS, the ARM DS-5 Altera
Edition Toolkit provides a comprehensive set of
embedded development tools for Altera SoCs.
Complete information about the development board.
Arria V SoC Development Kit June 2014 Altera Corporation
User Guide
This chapter explains how to install the following software:
■ Quartus II Subscription Edition Software (optional)
■ Altera SoC Embedded Development Suite (EDS)
■ Arria V SoC Development Kit software
■ On-Board USB-Blaster™ II driver
1 If you do not need to develop FPGA designs, you do not need to download the
Quartus II software. For example, when you only want to write software for the SoC
HPS. Installing the SoC EDS software, along with USB-II Blaster drivers, provides a
development kit JTAG programming environment.
About the Quartus II Software
Your kit includes a license for the Development Kit Edition (DKE) of the Quartus II
software (Windows platform only). For one year, this license entitles you to most of
the features of the Subscription Edition (excluding the IP Base Suite).
2. Software Installation
1 After the year, your DKE license will no longer be valid and you will not be permitted
to use this version of the Quartus II software. To continue using the Quartus II
software, you should download the free Quartus II Web edition or purchase a
subscription to Quartus II software. For more information, refer to the Design
Software page of the Altera website.
The Quartus II Development Kit Edition (DKE) software includes the following items:
■ Quartus II Software—The Quartus II software, including the Qsys system
integration tool, provides a comprehensive environment for network on a chip
(NoC) design. The Quartus II software integrates into nearly any design
environment and provides interfaces to industry-standard EDA tools.
■ MegaCore
®
IP Library—A library that contains Altera IP MegaCore functions. You
can evaluate MegaCore functions by using the OpenCore Plus feature to do the
following:
■ Simulate behavior of a MegaCore function within your system.
■ Verify functionality of your design, and quickly and easily evaluate its size and
speed.
■ Generate time-limited device programming files for designs that include
MegaCore functions.
■ Program a device and verify your design in hardware.
1 The OpenCore Plus hardware evaluation feature is an evaluation tool for
prototyping only. You must purchase a license to use a MegaCore function
in production.
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f For more information about OpenCore Plus, refer to AN 320: OpenCore Plus
Evaluation of Megafunctions.
Installing the Quartus II Subscription Edition Software
f Nios
®
II Embedded Design Suite (EDS)—A full-featured set of tools that
allows you to develop embedded software for the Nios II processor, which
you can include in your Altera FPGA designs.
Installing the Quartus II Subscription Edition Software
Included in the Quartus II Subscription Edition Software are the Quartus II software
(including Qsys), the Nios II EDS, and the MegaCore IP Library. To install the Altera
development tools, perform the following steps:
1. Download the Quartus II Subscription Edition Software from the Quartus II
Subscription Edition Software page of the Altera website. Alternatively, you can
request a DVD from the Altera IP and Software DVD Request Form page of the
Altera website.
2. Follow the on-screen instructions to complete the installation process.
f If you have difficulty installing the Quartus II software, refer to the Altera Software
Installation and Licensing Manual.
Activating Your License
Purchasing this kit entitles you to a one-year license for the Development Kit Edition
(DKE) of the Quartus II software.
1 After the year, your DKE license will no longer be valid and you will not be permitted
to use this version of the Quartus II software. To continue using the Quartus II
software, you should download the free Quartus II Web Edition or purchase a
subscription to Quartus II software.
Before using the Quartus II software, you must activate your license, identify specific
users and computers, and obtain and install a license file.
If you already have a licensed version of the subscription edition, you can use that
license file with this kit. If not, follow these steps:
1. Log on at the myAltera Account Sign In web page, and click Sign In.
2. On the myAltera Home web page, click the Self-Service Licensing Center link.
3. Locate the serial number printed on the side of the development kit box below the
bottom bar code.
The number consists of alphanumeric characters and does not contain hyphens:
for example, 5xxxSoCxxxxxxx.
4. On the Self-Service Licensing Center web page, click the Find it with your License
Activation Code link.
5. In the Find/Activate Products dialog box, enter your development kit serial
number and click Search.
6. When your product appears, turn on the check box next to the product name.
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User Guide
Chapter 2: Software Installation 2–3
Installing the Altera SoC Embedded Development Suite (EDS)
7. Click Activate Selected Products, and click Close.
8. When licensing is complete, Altera emails a license.dat file to you. Store the file on
your computer and use the License Setup page of the Options dialog box in the
Quartus II software to enable the software.
To license the Quartus II software, you need your computer’s network interface
card (NIC) ID, a number that uniquely identifies your computer. On the computer
you use to run the Quartus II software, type
to determine the NIC ID. Your NIC ID is the 12-digit hexadecimal number on the
Physical Address line.
For complete licensing details, refer to the Altera Software Installation and Licensing
Manual.
ipconfig /all
at a command prompt
Installing the Altera SoC Embedded Development Suite (EDS)
The Altera SoC EDS is a comprehensive tool suite for embedded software
development on Altera SoC devices. It contains development tools, utility programs,
run-time software, and application examples to expedite firmware and application
software of SoC embedded systems.
As a part of the Altera SoC EDS, the ARM DS-5 Altera Edition Toolkit provides a
comprehensive set of embedded development tools for Altera SoCs.
f For more information, refer to the ARM Development Studio 5 (DS-5) Altera Edition
Toolkit.
f For the steps to install the SoC EDS Tool Suite, refer to the Altera SoC Embedded
Design Suite User Guide.
Installing the Development Kit
Perform these steps:
1. Download the Arria V SoC Development Kit installer from the Arria V SoC
Development Kit page of the Altera website. Alternatively, you can request a
development kit DVD from the Altera Kit Installations DVD Request Form page of
the Altera website.
2. Start the Arria V SoC Development Kit installer .exe for Windows, or unzip the
installation image for Linux.
3. Choose an installation directory that is relative to the Quartus II software
installation directory. Follow the on-screen instructions to complete the
installation process.
4. For the latest issues and release notes, Altera recommends that you review the
readme.txt located in the root directory of the kit installation.
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<install dir>
documents
board_design_files
The default Windows installation directory is C:\altera\
<version>
\.
examples
factory_recovery
demos
kits
arriaVST_5astfd5kf40es_soc
Installing the USB-Blaster II Driver
The installation program creates the Arria V SoC Development Kit directory structure
shown in Figure 2–1.
Figure 2–1. Arria V SoC Development Kit Installed Directory Structure
Note to Figure 2–1:
(1) Early-release versions might have slightly different directory names.
Tab le 2– 1 lists the file directory names and a description of their contents.
Table 2–1. Installed Directory Contents
Directory Name Description of Contents
board_design_files
Contains schematic, layout, assembly, and bill of material board design files. Use these files as a
starting point for a new prototype board design.
demos Contains demonstration applications.
documents Contains the kit documentation.
examples Contains the sample design files for the Arria V SoC Development Kit.
factory_recovery
Contains the original data programmed onto the board before shipment. Use this data to restore
the board with its original factory contents.
(1)
Installing the USB-Blaster II Driver
The Arria V development board includes integrated USB-Blaster circuitry for FPGA
programming. However, for the host computer and board to communicate, you must
install the On-Board USB-Blaster II driver on the host computer.
f Installation instructions for the On-Board USB-Blaster II driver for your operating
system are available on the Altera website. On the Altera Programming Cable Driver
Arria V SoC Development Kit June 2014 Altera Corporation
User Guide
f For USB-Blaster II configuration details, refer to the On-Board USB-Blaster II page.
Information page of the Altera website, locate the table entry for your configuration
and click the link to access the instructions.
This chapter explains how to set up the Arria V SoC development board and restore
defaults.
Setting Up the Board
To prepare the board, perform these steps:
1. The development board ships with its board switches preconfigured to support
the design examples in the kit. If you suspect your board might not be currently
configured with the default settings, follow the instructions in “Factory Default
Switch and Jumper Settings” on page 3–1 to return the board to its factory settings
before proceeding.
The development board ships with the Golden System Reference Design binaries
stored in the microSD card.
The microSD card also includes the following:
3. Board Setup and Defaults
■ Hardware reference design FPGA image, Raw Binary File (.rbf) file
■ HPS image preloader U-Boot and Linux images
■ File system and software examples
2. Power up the development board by using the included laptop power supply
plugged into the board.
c Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage, and a
lower-rated power supply may not be able to provide enough power for the
board.
Alternatively, you can use the an ATX power from a PC by plugging a 4-pin
output from that supply to J33 on the development board.
c Make sure that the ATX supply is off when connecting to the board. Hot-
swap is not supported and may damage the board's power supplies and
other downstream devices.
When configuration is complete, the Config Done LED (D38) illuminates, signaling
that the Arria V device configured successfully.
Factory Default Switch and Jumper Settings
This section shows the factory settings (Figure 3–1) for the Arria V SoC development
board. These settings ensure that the Board Update Portal and Golden System
Reference design function properly.
June 2014 Altera Corporation Arria V SoC Development Kit
User Guide
3–2 Chapter 3: Board Setup and Defaults
Arria V SoC
J37
1
0
1
01
0
1
0
J38 J39 J40 J41
CSEL0
J45
SEL1
J46
SEL0
CLK OSC2
CSEL1 BSEL0 BSEL1 BSEL2
1
0
J6
1.2V
FMC VAR
1.5V
1.8V
2.5V
HPS
FPGA
FMC
MAX
SW4
1 2 3 4
ON
SW1
3 2 1 0 3 2 1 0
HPS
J18
J23
J30
Not a jumper
Not a jumper
Not a jumper
Not a jumper
FPGA
ON
1 2 3 4 5 6 7 8
J3
FMCB_JTAG_EN
SW2
1 2 3 4
SECURITY
FACT LOAD
Si570
CLK125A
ON
SW3
FMCB
FMCA
01234
MSEL
ON
1 2 3 4 5 6
J7
LMK_OSC_SEL
J28
JTAG_MIC_SEL
J19
JTAG
HPS SEL
J21
JTAG
SEL
Factory Default Switch and Jumper Settings
1 The SD card, Max V system controller, and CFI flash are already programmed with
the factory default files. For more information, refer to Appendix A, Programming
Flash Memory.
Figure 3–1. Switch Locations and Default Settings
Arria V SoC Development Kit June 2014 Altera Corporation
User Guide
Chapter 3: Board Setup and Defaults 3–3
Factory Default Switch and Jumper Settings
To restore the switches to their factory default settings, perform these steps:
1. Set the DIP switch bank (SW2) to match Table 3–1 and Figure 3–1.
In the following table, ON indicates the switch is to the left according to the board
orientation as shown in Figure 3–1.
Table 3–1. SW2 DIP Switch Settings
Switch
Board
Label
1 CLK125A
2 Si570
3FACT LOAD
4 Security
Function
Switch 1 has the following options:
■ ON (0) = On-board oscillator is disabled.
■ OFF (1) = On-board oscillator is enabled.
Switch 2 has the following options:
■ ON (0) = On-board programmable oscillator is
enabled.
■ OFF (1) = On-board programmable oscillator is
disabled.
Switch 3 has the following options:
■ ON (0) = Load the user design from flash at
power up.
■ OFF (1) = Load the user factory from flash at
power up.
Switch 4 has the following options:
■ ON (0) = On-Board USB Blaster II sends
FACTORY command at power up
■ OFF (1) = On-Board USB Blaster II does not
send FACTORY command at power up
Default
Position
OFF
ON
OFF
OFF
2. Set the DIP switch bank (SW3) to match Table 3–2 and Figure 3–1.
In the following table, up and down indicates the position of the switch with the
board orientation as shown in Figure 3–1.
Important: The default MSEL pin settings are set to all zeroes (ON) to select the fast
passive parallel x16 mode. For power-up configuration from MAX V and CFI
flash, ensure that the MAX V design uses this same mode as does in the design in
the <install dir>\kits\arriaVST_5astfd5kf40es_soc\examples\max5 directory.
Table 3–2. SW3 DIP Switch Settings (Part 1 of 2)
Switch
Board
Label
Function
Default
Position
Switch 1 has the following options:
1 MSEL0
■ ON (up) = MSEL0 is 0.
■ OFF (down) = MSEL0 is 1.
Switch 2 has the following options:
2 MSEL1
■ ON (up) = MSEL1 is 0.
■ OFF (down) = MSEL1 is 1.
ON
ON
June 2014 Altera Corporation Arria V SoC Development Kit
User Guide
3–4 Chapter 3: Board Setup and Defaults
Factory Default Switch and Jumper Settings
Table 3–2. SW3 DIP Switch Settings (Part 2 of 2)
Switch
Board
Label
Function
Switch 3 has the following options:
3 MSEL2
■ ON (up) = MSEL2 is 0.
■ OFF (down) = MSEL2 is 1.
Switch 4 has the following options:
4 MSEL3
■ ON (up) = MSEL3 is 0.
■ OFF (down) = MSEL3 is 1.
Switch 5 has the following options:
5 MSEL4
■ ON (up) = MSEL4 is 0.
■ OFF (down) = MSEL4 is 1.
3. Set the DIP switch bank (SW4) to match Table 3–3 and Figure 3–1.
In the following table, up and down indicates the position of the switch with the
board orientation as shown in Figure 3–1.
Table 3–3. SW4 JTAG DIP Switch Settings
Switch
1HPS
2FPGA
3FMCA
Board
Label
Function
■ ON (up) = Do not Include HPS in the JTAG chain.
■ OFF (down) = Include HPS in the JTAG chain
■ ON (up) = Do not Include the FPGA in the JTAG
chain.
■ OFF (down) = Include the FPGA in the JTAG chain.
■ ON (up) = Do not include the FMCA connector in the
JTAG chain.
■ OFF (down) = Include the FMCA connector in the
JTAG chain.
■ ON (up) = Do not include the MAX V system
4MAX
controller in the JTAG chain.
■ OFF (down) = Include the MAX V system controller in
the JTAG chain.
Default
Position
ON
ON
ON
Default
Position
OFF
OFF
ON
OFF
Arria V SoC Development Kit June 2014 Altera Corporation
User Guide
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