Altera Arria V GZ Avalon-ST User Manual

Arria V GZ Avalon-ST Interface for PCIe Solutions

User Guide

Last updated for Altera Complete Design Suite: 14.1

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Application

Layer

(User Logic)

Avalon-ST

Interface

PCIe Hard IP

Block

PIPE

Interface

PHY IP Core

for PCIe

(PCS/PMA)

Serial Data

Transmission

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Arria V GZ Avalon-ST Interface for PCIe Datasheet

Altera® Arria V GZ® V FPGAs include a configurable, hardened protocol stack for PCI Express compliant with PCI Express Base Specification 2.1 or 3.0. The Hard IP for PCI Express using the Avalon Streaming (Avalon-ST) interface is the most flexible variant. However, this variant requires a thorough understanding of the PCIe

Protocol.

Figure 1-1: Arria V GZ PCIe Variant with Avalon-ST Interface

Table 1-1: PCI Express Data Throughput

The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4, and 8 lanes. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and 8.0 giga-transfers per second for Gen3. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to less than 1%.

that is

PCI Express Gen1 (2.5 Gbps)

PCI Express Gen2 (5.0 Gbps)

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Link Width

×1 ×2 ×4 ×8

2 4 8 16

4 8 16 32

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Features

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Link Width

×1 ×2 ×4 ×8

PCI Express Gen3 (8.0 Gbps)

Refer to the AN 690: PCI Express DMA Reference Design for Stratix V Devices for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs, including the Arria V GZ Hard IP for PCI Express IP core.

Devices

Related Information

• PCI Express Base Specification 2.1 or 3.0

• AN 690: PCI Express DMA Reference Design for Stratix V Devices

• Creating a System with Qsys

Features

New features in the Quartus® II 14.1 software release:

• Reduced Quartus II compilation warnings by 50%. The Arria V GZ Hard IP for PCI Express supports the following features:

• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.

• Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Root Ports and Endpoints.

• Dedicated 16 KByte receive buffer.

• Optional hard reset controller for Gen2.

• Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core bitstreams to be stored separately.

• Qsys example designs demonstrating parameterization, design modules, and connectivity.

• Extended credit allocation settings to better optimize the RX buffer space based on application type.

• Support for multiple packets per cycle with the 256-bit Avalon-ST interface.

• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.

• Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions.

• Support for Gen3 PIPE simulation.

• Easy to use:

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• Flexible configuration.

• Substantial on-chip resource savings and guaranteed timing closure.

• No license requirement.

• Example designs to get started.

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Table 1-2: Feature Comparison for all Hard IP for PCI Express IP Cores

The table compares the features of the four Hard IP for PCI Express IP Cores.

Features

1-3

Feature Avalon‑ST Interface Avalon‑MM

Interface

Avalon‑MM DMA Avalon‑ST Interface with SR-

IP Core License Free Free Free Free

Native

Supported Supported Supported Supported

Endpoint

Legacy Endpoint

(1)

Supported Not Supported Not Supported Not Supported

Root port Supported Supported Not Supported Not Supported

Gen1 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 Not Supported

Gen2 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 ×4, ×8

Gen3 ×1, ×2, ×4, ×8 ×1, ×2, ×4 ×4, ×8

64-bit Applica‐

Supported Supported Not supported Not supported

×8

×4, ×8

×2, ×4, ×8

tion Layer interface

IOV

128-bit

Supported Supported Supported Supported Application Layer interface

256-bit

Supported Not Supported Supported Supported Application Layer interface

(1)

Not recommended for new designs.

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Features

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Feature Avalon‑ST Interface Avalon‑MM

Interface

Transaction Layer Packet type (TLP)

• Memory Read Request

• Memory Read RequestLocked

• Memory Write Request

• I/O Read Request

• I/O Write Request

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Message Request

• Message Request with Data Payload

• Completion Message

• Completion with Data

• Memory Read Request

• Memory Write Request

• I/O Read Request—Root Port only

• I/O Write Request—Root Port only

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Completion Message

• Completion with Data

• Memory Read Request (single dword)

• Memory Write Request (single dword)

• Completion for Locked Read without Data

Avalon‑MM DMA Avalon‑ST Interface with SR-

IOV

• Memory Read Request

• Memory Write Request

• Completion Message

• Completion with Data

• Memory Read Request

• Memory Write Request

• Configuration Read Request (from Root Port)

• Configuration Write Request (from Root Port)

• Message Request

• Completion Message

• Completion with Data

Payload size

Number of tags supported for non-posted requests

62.5 MHz clock Supported Supported Not Supported Not Supported

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128–2048 bytes 128–256 bytes 128, 256, 512 bytes 128–256 bytes

256 8 16 256

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Features

1-5

Feature Avalon‑ST Interface Avalon‑MM

Interface

Out-of-order

Not supported Supported Supported Not supported completions (transparent to the Application Layer)

Requests that

Not supported Supported Supported Supported cross 4 KByte address boundary (transparent to the Application Layer)

Polarity

Supported Supported Supported Supported Inversion of PIPE interface signals

Avalon‑MM DMA Avalon‑ST Interface with SR-

IOV

ECRC

Supported Not supported Not supported Not supported forwarding on RX and TX

Number of MSI requests

1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 (for

Physical Functions)

MSI-X Supported Supported Supported Supported

Legacy

Supported Supported Supported Supported interrupts

Expansion

Supported Not supported Not supported Not supported ROM

The Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide explains how to use this IP core and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this document only in conjunction with an understanding of the PCI Express Base Specification.

Note:

This release provides separate user guides for the different variants. The Related Information provides links to all versions.

Related Information

Datasheet

• Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide

• Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide

• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

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Release Information

Table 1-3: Hard IP for PCI Express Release Information

Item Description

Version 14.1

Release Date December 2014

Ordering Codes No ordering code is required

Product IDs There are no encrypted files for the Arria V GZ

Hard IP for PCI Express. The Product ID and

Vendor ID

Vendor ID are not required because this IP core does not require a license.

Device Family Support

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Table 1-4: Device Family Support

Device Family Support

Arria V GZ Final. The IP core is verified with final timing

models. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Other device families Refer to the Related Information below for other

device families:

Related Information

• Arria V Avalon-MM Interface for PCIe Solutions User Guide

• Arria V Avalon-ST Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide

• Arria 10 Avalon-ST Interface for PCIe Solutions User Guide

• Cyclone V Avalon-MM Interface for PCIe Solutions User Guide

• Cyclone V Avalon-ST Interface for PCIe Solutions User Guide

• IP Compiler for PCI Express User Guide

• Stratix V Avalon-MM Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface with SR-IOV for PCIe Solutions User Guide

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Altera FPGA

User Application

Logic

PCIe

Hard IP

PCIe

Hard IP

User Application

Logic

PCI Express Link

Altera FPGA

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Configurations

The Arria V GZ Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack including the following layers:

• Physical (PHY), including:

• Media Access Control (MAC)

• Data Link Layer (DL)

• Transaction Layer (TL) The Hard IP supports all memory, I/O, configuration, and message transactions. It is optimized for Altera

devices. The Application Layer interface is also optimized to achieve maximum effective throughput. You can customize the Hard IP to meet your design requirements.

Figure 1-2: PCI Express Application with a Single Root Port and Endpoint

The following figure shows a PCI Express link between two Arria V GZ FPGAs.

• Physical Media Attachment (PMA)

• Physical Coding Sublayer (PCS)

Configurations

1-7

Datasheet

Figure 1-3: PCI Express Application Using Configuration via Protocol

The Arria V GZ design below includes the following components:

• A Root Port that connects directly to a second FPGA that includes an Endpoint.

• Two Endpoints that connect to a PCIe switch.

• A host CPU that implements CvP using the PCI Express link connects through the switch. For more

information about configuration over a PCI Express link, refer to Configuration via Protocol (CvP) on page 14-1.

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PCIe Link

PCIe Hard IP

Switch

PCIe

Hard IP

User Application

Logic

PCIe Hard IP

PCIe Link

User Application

Logic

Altera FPGA Hard IP for PCI Express

Altera FPGA with Hard IP for PCI Express

Active Serial or

Active Quad

Device Configuration

Configuration via Protocol (CvP)

using the PCI Express Link

Serial or

Quad Flash

USB

Download

cable

PCIe

Hard IP

User

Application

Logic

Altera FPGA with Hard IP for PCI Express

Config Control

CVP

USB

Host CPU

PCIe

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Avalon-ST Example Designs

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Related Information

Configuration via Protocol (CvP)Implementation in Altera FPGAs User Guide

Avalon-ST Example Designs

Altera provides example designs to familiarize you with the available functionality. Each design connects the device under test (DUT) to an application programming platform (APP), labeled APPs in the figure below. Certain critical parameters of the APPs component are set to match the values of the DUT. If you change these parameters, you must change the APPs component to match. You can change the values for all other parameters of the DUT without editing the APPs component.

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Figure 1-4: Example Design Preset Parameters

Avalon-ST Example Designs

1-9

In this example design, the following parameters must be set to match the values set in the DUT:

• Targeted Device Family

• Lanes

• Lane Rate

• Application Clock Rate

• Port type

• Application Interface

• Tags supported

• Maximum payload size The following Qsys example designs are available for the Arria V GZ Hard IP for PCI Express. You can

download them from the <install_dir>/ ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_design/<dev> directory:

• pcie_de_gen1_x4_ast64.qsys

• pcie_de_gen1_x8_ast128.qsys

• pcie_de_gen2_x8_ast256.qsys

• pcie_de_gen3_x1_ast64.qsys

• pcie_de_gen3_x4_ast128.qsys

• pcie_de_gen3_x8_ast256.qsys

• pcie_de_rp_gen1_x4_ast64.qsys

• pcie_de_rp_gen1_x8_ast128.qsys

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Debug Features

Debug features allow observation and control of the Hard IP for faster debugging of system-level problems.

Related Information

Debugging on page 18-1

IP Core Verification

To ensure compliance with the PCI Express specification, Altera performs extensive verification. The simulation environment uses multiple testbenches that consist of industry-standard bus functional models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the simulation environment:

• Directed and pseudorandom stimuli are applied to test the Application Layer interface, Configuration Space, and all types and sizes of TLPs

• Error injection tests that inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and check for the proper responses

• PCI-SIG® Compliance Checklist tests that specifically test the items in the checklist

• Random tests that test a wide range of traffic patterns

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Altera provides the following two example designs that you can leverage to test your PCBs and complete compliance base board testing (CBB testing) at PCI-SIG.

Related Information

• PCI SIG Gen3 x8 Merged Design - Stratix V

• PCI SIG Gen2 x8 Merged Design - Stratix V

Compatibility Testing Environment

Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera internally tests every release with motherboards and PCI Express switches from a variety of manufac‐ turers. All PCI-SIG compliance tests are run with each IP core release.

Performance and Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device resources.

Note:

Related Information

Fitter Resources Reports

Soft calibration of the transceiver module requires additional logic. The amount of logic required depends upon the configuration.

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Recommended Speed Grades

Table 1-5: Arria V GZ Recommended Speed Grades for All Link Widths and Application Layer Clock Frequencies

Altera recommends setting the Quartus II Analysis & Synthesis Settings Optimization Technique to Speed when the Application Layer clock frequency is 250 MHz. For information about optimizing synthesis, refer to Setting Up and Running Analysis and Synthesis in Quartus II Help. For more information about how to effect the

Optimization Technique settings, refer to Area and Timing Optimization in volume 2 of the Quartus II Handbook.

1-11

Link Rate Link Width Interface

Width

x1 64 bits 62.5

x2 64 bits 125 –1, –2, –3, –4

Gen1

x4 64 bits 125 –1, –2, –3, –4

x8 64 bits 250 –1, –2, –3

x8 128 Bits 125 –1, –2, –3, –4

x1 64 bits

x2 64 bits 125 –1, –2, –3, –4

x4 64 bits 250 –1, –2, –3

Gen2

x4 128 bits 125 –1, –2, –3, –4

x8 128 bits 250 –1, –2, –3

Application Clock

Frequency (MHz)

(2)

,125 –1, –2, –3, –4

125

Recommended Speed Grades

(3)

–1, –2, –3, –4

(3)

(2) (3)

Datasheet

x8 256 bits 125 –1, –2, –3, –4

This is a power-saving mode of operation The -4 speed grade is also possible for this configuration; however, it requires significant effort by the end user to close timing.

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Steps in Creating a Design for PCI Express

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Link Rate Link Width Interface

Width

Application Clock

Frequency (MHz)

x1 64 bits 125 –1, –2, –3, –4

x2 64 bits 250 –1, –2, –3, –4

x2 128 bits 125 –1, –2, –3, –4

Gen3

x4 128 bits 250 –1, –2, –3

x4 256 bits 125 –1, –2, –3,–4

x8 256 bits 250 –1, –2, –3

Related Information

• Area and Timing Optimization

• Altera Software Installation and Licensing Manual

• Setting up and Running Analysis and Synthesis

Recommended Speed Grades

(3)

Steps in Creating a Design for PCI Express

Before you begin

Select the PCIe variant that best meets your design requirements.

• Is your design an Endpoint or Root Port?

• What Generation do you intend to implement?

• What link width do you intend to implement?

• What bandwidth does your application require?

• Does your design require CvP?

1. Select parameters for that variant.

2. Simulate using an Altera-provided example design. All of Altera's PCI Express example designs are

available under <install_dir>/ip/altera/altera_pcie/. Alternatively, create a simulation model and use your own custom or third-party BFM. The Qsys Generate menu generates simulation models. Altera supports ModelSim®-Altera for all IP. The PCIe cores support the Aldec RivieraPro, Cadence NCsim, Mentor Graphics ModelSim, and Synopsys VCS and VCS-MX simulators.

3. Compile your design using the Quartus II software. If the versions of your design and the Quartus II software you are running do not match, regenerate your PCIe design.

4. Download your design to an Altera development board or your own PCB. Click on the All Develop‐ ment Kits link below for a list of Altera's development boards.

5. Test the hardware. You can use Altera's SignalTap® II Logic Analyzer or a third-party protocol analyzer to observe behavior.

6. Substitute your Application Layer logic for the Application Layer logic in Altera's testbench. Then repeat Steps 3–6. In Altera's testbenches, the PCIe core is typically called the DUT (device under test). The Application Layer logic is typically called APPS.

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Steps in Creating a Design for PCI Express

Related Information

• Parameter Settings on page 4-1

• Getting Started with the Arria V GZ Hard IP for PCI Express on page 2-1

• All Development Kits

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Getting Started with the Arria V GZ Hard IP for

APPS altpcied_<dev>_hwtcl.v

Hard IP for PCI Express Testbench for Endpoints

Avalon-ST TX Avalon-ST RX

reset

status

Avalon-ST TX Avalon-ST RX reset status

DUT altpcie_<dev>_hip_ast_hwtcl.v

Root Port Model altpcie_tbed_<dev>_hwtcl.v

PIPE or

Serial

Interface

Root Port BFM altpcietb_bfm_rpvar_64b_x8_pipen1b

Root Port Driver and Monitor altpcietb_bfm_vc_intf

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This section provides instructions to help you quickly customize, simulate, and compile the Arria V GZ Hard IP for PCI Express IP Core. When you install the Quartus II software you also install the IP Library. This installation includes design examples for Hard IP for PCI Express under the <install_dir>/ip/altera/

altera_pcie/ directory.

After you install the Quartus II software, you can copy the design examples from the <install_dir>/ip/altera/

altera_pcie/altera_pcie/altera_pcie_hip_ast_ed/example_designs/<dev> directory. This walkthrough uses the

Gen1 ×8 Endpoint, pcie_de_gen1_x8_ast128.qsys. The following figure illustrates the top-level modules of the testbench in which the DUT, a Gen1 Endpoint, connects to a chaining DMA engine, labeled APPS in the following figure, and a Root Port model. The simulation can use the parallel PHY Interface for PCI Express (PIPE) or serial interface.

Figure 2-1: Testbench for an Endpoint

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Note:

The Quartus II release automatically creates a simulation log, altpcie_monitor_<dev>_dlhip_tlp_file_

log.log, file in your simulation directory. If you have an existing 13.1 or older design, you must

regenerate it in the current release in order to simulate. Regeneration is necessary to create the supporting monitor file the generates altpcie_monitor_<dev>_dlhip_tlp_file_log.log. Refer to Understanding Simulation Log File Generation for details.

Altera provides example designs to help you get started with the Arria V GZ Hard IP for PCI Express IP Core. You can use example designs as a starting point for your own design. The example designs include

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Qsys Design Flow

scripts to compile and simulate the Arria V GZ Hard IP for PCI Express IP Core. This example design provides a simple method to perform basic testing of the Application Layer logic that interfaces to the Hard IP for PCI Express.

For a detailed explanation of this example design, refer to the Testbench and Design Example chapter. If you choose the parameters specified in this chapter, you can run all of the tests included in Testbench and Design Example chapter.

For more information about Qsys, refer to System Design with Qsys in the Quartus II Handbook. For more information about the Qsys GUI, refer to About Qsys in Quartus II Help.

Related Information

• Understanding Simulation Log File Generation on page 2-5

• System Design with Qsys

• About Qsys

Qsys Design Flow

Copy the pcie_de_gen1_x8_ast128.qsys design example from the <install_dir>/ip/altera/altera_pcie/altera_

pcie/altera_pcie_hip_ast_ed/example_designs/<dev> to your working directory.

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The following figure illustrates this Qsys system.

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Figure 2-2: Complete Gen1 ×8 Endpoint (DUT) Connected to Example Design (APPS)

Qsys Design Flow

2-3

The example design includes the following components:

• DUT—This is Gen1 ×8 Endpoint. For your own design, you can select the data rate, number of lanes, and either Endpoint or Root Port mode.

• APPS—This Root Port BFM configures the DUT and drives read and write TLPs to test DUT functionality. An Endpoint BFM is available if your PCI Express design implements a Root Port.

• pcie_reconfig_driver_0—This Avalon-MM master drives the Transceiver Reconfiguration Controller. The pcie_reconfig_driver_0 is implemented in clear text that you can modify if your design requires different reconfiguration functions. After you generate your Qsys system, the Verilog HDL for this component is available as: <working_dir>/<variant_name>/testbench/<variant_name>_tb/simulation/

submodules/altpcie_reconfig_driver.sv.

• Transceiver Reconfiguration Controller—The Transceiver Reconfiguration Controller dynamically reconfigures analog settings to improve signal quality. For Gen1 and Gen2 data rates, the Transceiver Reconfiguration Controller must perform offset cancellation and PLL calibration. For the Gen3 data rate, the pcie_reconfig_driver_0 performs AEQ through the Transceiver Reconfiguration Controller.

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Generating the Testbench

1. On the Generate menu, select Generate Testbench System. Specify the parameters listed in the following table.

Table 2-1: Parameters to Specify on the Generation Tab in Qsys

Parameter Value

Testbench System

Create testbench Qsys system Standard, BFMs for standard Qsys interfaces

Create testbench simulation model Verilog

Allow mixed-language simulation Turn this option off

Output Directory

Testbench <working_dir>/pcie_de_gen1_x8_ast128/testbench

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2. Click the Generate button at the bottom of the Generation tab to create the testbench.

Note:

Simulating the Example Design

1. Start your simulation tool. This example uses the ModelSim® software.

2. From the ModelSim transcript window, in the testbench directory type the following commands: a. do msim_setup.tcl

b. ld_debug (This command compiles all design files and elaborates the top-level design without any

optimization.)

c. run -all

The simulation includes the following stages:

• Link training

• Configuration

• DMA reads and writes

• Root Port to Endpoint memory reads and writes

Disabling Scrambling to Interpret TLPs at the PIPE Interface

1. Go to <project_directory/<variant>/testbench/<variant>_tb/simulation/submodules/.

2. Open altpcietb_bfm_top_rp.v.

3. Locate the declaration of test_in[2:1]. Set test_in[2] = 1 and test_in[1] = 0. Changing

test_in[2] = 1 disables data scrambling on the PIPE interface.

4. Save altpcietb_bfm_top_rp.v.

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Generating Quartus II Synthesis Files

1. On the Generate menu, select Generate HDL.

2. For Create HDL design files for synthesis, select Verilog.

You can leave the default settings for all other items.

3. Click Generate to generate files for Quartus II synthesis.

4. Click Finish when the generation completes.

Understanding the Files Generated

Table 2-2: Overview of Qsys Generation Output Files

Directory Description

<testbench_dir>/<variant_name>/synthesis Includes the top-level HDL file for the Hard IP for

Generating Quartus II Synthesis Files

PCI Express and the .qip file that lists all of the necessary assignments and information required to process the IP core in the Quartus II compiler. Generally, a single .qip file is generated for each IP core.

2-5

<testbench_dir>/<variant_name>/synthesis/submodules

Includes the HDL files necessary for Quartus II synthesis.

<testbench_dir>/<variant_name>/testbench

Includes testbench subdirectories for the Aldec, Cadence, Synopsys, and Mentor simulation tools with the required libraries and simulation scripts.

<testbench_dir>/<variant_name>/testbench<cad_ vendor>

Includes the HDL source files and scripts for the simulation testbench.

For a more detailed listing of the directories and files the Quartus II software generates, refer to Files Generated for Altera IP Cores in Compiling the Design in the Qsys Design Flow.

Understanding Simulation Log File Generation

Starting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_

monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory.

Table 2-3: Sample Simulation Log File Entries

Time TLP Type Payload

(Bytes)

TLP Header

17989 RX CfgRd0 0004 04000001_0000000F_01080008 17989 RX MRd 0000 00000000_00000000_01080000 18021 RX CfgRd0 0004 04000001_0000010F_0108002C 18053 RX CfgRd0 0004 04000001_0000030F_0108003C

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Understanding Physical Placement of the PCIe IP Core

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Time TLP Type Payload

(Bytes)

18085 RX MRd 0000 00000000_00000000_0108000C

Understanding Physical Placement of the PCIe IP Core

For more information about physical placement of the PCIe blocks, refer to the links below. Contact your Altera sales representative for detailed information about channel and PLL usage.

Related Information

Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices on page 5-62

Compiling the Design in the Qsys Design Flow

To compile the Qsys design example in the Quartus II software, you must create a Quartus II project and add your Qsys files to that project.

1. Before compiling, you can optionally turn on two parameters in the testbench. The first parameter specifies pin assignments that match those for the Altera Development Kit board I/Os. The second parameter enables the Compliance Base Board (CBB) logic on the development board. In the Gen1 x8 example design, complete the following steps if you want to enable these parameters:

a. Right-click the APPS component and select Edit. b. Turn on Enable FPGA Dev kit board I/Os. c. Turn on Enable FPGA Dev kit board CBB logic. d. Click Finish. e. On the Generate menu, select Generate Testbench System and then click Generate. f. On the Generate menu, select Generate HDL and then click Generate. (You can use the same

parameters that are specified in Generating the Testbench earlier in this chapter).

2. In the Quartus II software, click the New Project Wizard icon.

3. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you

previously turned it off.)

4. On the Directory, Name, Top-Level Entity page, enter the following information:

TLP Header

5. Click Next to display the Add Files page.

6. Complete the following steps to add the Quartus II IP File ( .qip )to the project:

7. Click Next to display the Device page.

8. On the Family & Device Settings page, choose the following target device family and options:

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a. The working directory shown is correct. You do not have to change it. b. For the project name, browse to the synthesis directory that includes your Qsys project,

<working_dir>/pcie_de_gen1_x8_ast128/synthesis. Select your variant name,

pcie_de_gen1_x8_ast128.v . Then, click Open.

c. For Project Type select Empty project.

a. Click the browse button. The Select File dialog box appears. b. In the Files of type list, select IP Variation Files (*.qip *.sip). c. Click pcie_de_gen1_x8_ast128.qip and then click Open. d. On the Add Files page, click Add.

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Compiling the Design in the Qsys Design Flow

2-7

a. In the Family list, select Arria V GZ . b. In the Devices list, select Arria V GZ All. c. In the Available Devices list, select 5AGZME5K2F40C3 .

9. Click Next to close this page and display the EDA Tool Settings page.

10.From the Simulation list, select ModelSim®. From the Format list, select the HDL language you

intend to use for simulation.

11.Click Next to display the Summary page.

12.Check the Summary page to ensure that you have entered all the information correctly.

13.Click Finish to create the Quartus II project.

14.Before compiling, you must assign I/O standards to the pins of the device. Refer to Making Pin

Assignments to Assign I/O Standard to Serial Data Pins for instructions.

15.You must connect the pin_perst reset signal to the correcsponding nPERST pin of the device. Refer to the definition of pin_perst in the Reset, Status, and Link Training Signals section for more informa‐ tion.

16.Next, set the value of the test_in bus to a value that is compatible for hardware testing. In Qsys design example provided, test_in is a top-level port.

a. Comment out the test_in port in the top-level Verilog generated file. b. Add the following declaration, wire[31:0] test_in, to the same top-level Verilog file. c. Assign hip_ctrl_test_in = 32'hA8. d. Connect test_in to hip_ctrl_test_in.

Refer to the definition of test_in in the Test Signals section for more information about the bits of the

test_in bus.

17.Add the Synopsys Design Constraint (SDC) shown in the following example below to the top-level design file for your Quartus II project.

18.To compile your design using the Quartus II software, on the Processing menu, click Start Compila‐ tion. The Quartus II software then performs all the steps necessary to compile your design.

Example 2-1: Synopsys Design Constraints

create_clock -period “100 MHz” -name {refclk_pci_express}{*refclk_*} derive_pll_clocks derive_clock_uncertainty

# PHY IP reconfig controller constraints # Set reconfig_xcvr clock # Modify to match the actual clock pin name # used for this clock, and also changed to have the correct period set create_clock -period "125 MHz" -name {reconfig_xcvr_clk}{*reconfig_xcvr_clk*}

# HIP Soft reset controller SDC constraints set_false_path -to [get_registers* altpcie_rs_serdes|fifo_err_sync_r[0]] set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to[get_registers *altpcie_rs_serdes|*]

# Hard IP testin pins SDC constraints set_false_path -from [get_pins -compatibilitly_mode *hip_ctrl*]

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Notes:

1. If supported and enabled for your IP variation

2. If functional simulation models are generated

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file <your_ip>_inst.v or .vhd - Sample instantiation template

synthesis - IP synthesis files

<your_ip>.qip - Lists files for synthesis

testbench - Simulation testbench files

<testbench_hdl_files>

<simulator_vendor> - Testbench for supported simulators

<simulation_testbench_files>

<your_ip>.v or .vhd - Top-level IP variation synthesis file

simulation - IP simulation files

<your_ip>.sip - NativeLink simulation integration file

<simulator vendor> - Simulator setup scripts

<simulator_setup_scripts>

<your_ip> - IP core variation files

<your_ip>.qip or .qsys - System or IP integration file

<your_ip>_generation.rpt - IP generation report <your_ip>.bsf - Block symbol schematic file

<your_ip>.ppf - XML I/O pin information file <your_ip>.spd - Combines individual simulation startup scripts

<your_ip>.html - Contains memory map

<your_ip>.sopcinfo - Software tool-chain integration file

<your_ip>_syn.v or .vhd - Timing & resource estimation netlist

<your_ip>.debuginfo - Lists files for synthesis

<your_ip>.v, .vhd, .vo, .vho - HDL or IPFS models

<your_ip>_tb - Testbench for supported simulators

<your_ip>_tb.v or .vhd - Top-level HDL testbench file

2-8

Compiling the Design in the Qsys Design Flow

Files Generated for Altera IP Cores Figure 2-3: IP Core Generated Files

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Related Information

• Simulating the Example Design on page 3-5

• Generating the Testbench on page 2-4

• Simulating the Example Design on page 3-5

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PCB

Avalon-MM slave

Reset

Hard IP for PCI Express

Altera FPGA

PCB

Transaction Layer

Data Link Layer

PHY MAC Layer

x8 PCIe Link

(Physical Layer)

Lane 7

(Unused)

Lane 6

Lane 5

TX PLL

PHY IP Core for PCI Express

Lane 2

Lane 3

Lane 4

Lane 1

Lane 0

TX PLL

Transceiver Bank

Reconfig

to and from

Transceiver

to and from

Embedded

Controller

(Avalon-MM

slave interface)

Transceiver

Reconfiguration

Controller

Root

Port BFM

npor

Reset

APPS DUT

Chaining DMA

(User Application)

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Modifying the Example Design

To use this example design as the basis of your own design, replace the Chaining DMA Example shown in the following figure with your own Application Layer design. Then modify the Root Port BFM driver to generate the transactions needed to test your Application Layer.

Figure 2-4: Testbench for PCI Express

Modifying the Example Design

2-9

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Using the IP Catalog To Generate Your Arria V GZ Hard IP for PCI Express as a Separate Component

You can also instantiate the Arria V GZ Hard IP for PCI Express IP Core as a separate component for integration into your project.

You can use the Quartus II IP Catalog and IP Parameter Editor to select, customize, and generate files representing your custom IP variation. The IP Catalog (Tools > IP Catalog) automatically displays IP cores available for your target device. Double-click any IP core name to launch the parameter editor and generate files representing your IP variation.

For more information about the customizing and generating IP Cores refer to Specifying IP Core Parameters and Options in Introduction to Altera IP Cores. For more information about upgrading older IP cores to the current release, refer to Upgrading Outdated IP Cores in Introduction to Altera IP Cores.

Note: Your design must include the Transceiver Reconfiguration Controller IP Core and the Altera PCIe

Reconfig Driver. Refer to the figure in the Qsys Design Flow section to learn how to connect this components.

Related Information

• Qsys Design Flow on page 2-2

• Introduction to Altera IP Cores

• Managing Quartus II Projects

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Getting Started with the Configuration Space

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101 Innovation Drive, San Jose, CA 95134

Bypass Mode Qsys Example Design

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This Qsys design example demonstrates Configuration Space Bypass mode for the Arria V GZ Hard IP for PCI Express IP Core. A Root Port BFM provides stimulus to the Endpoint design. The Endpoint bypasses the standard Configuration Space to access the custom Configuration Space and memory of two functions. The Configuration Space Bypass Example Design performs the following functions:

• Accepts Configuration, Memory, and Message TLPs on the Arria V GZ Hard IP for PCI Express RX Avalon-ST interface

• Translates Type 0 Configuration Read and Configuration Write Requests to Avalon-MM read and write requests that target the Configuration Space of either Function 0 or Function 1.

• Responds to invalid Type 0 Configuration Requests with an Unsupported Request (UR) status in a Completion Message.

• Converts single dword Memory Read and Memory Write Requests to access 32-bit registers of the target function using the Avalon-MM interface.

• Maps two contiguous MBytes of memory for the two functions with the first MByte for Function 0 and the second MByte for Function 1.

• Sets up two registers for each function.

• Drops the following invalid Write Requests:

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• Memory Write Requests with a payload of more than one dword

• Messages with data

• Returns Completer Abort (CA) status in Completion message for invalid Memory Read Requests such as Memory Read Requests with a payload greater than one dword.

• Returns a Completion Status of Successful Completion for valid Configuration Requests to Function 0 and Function 1.

The following figure illustrates, the components of the Configuration Space Bypass Mode Qsys Example Design. The example design includes the following components:

• DUT: The Arria V GZ Hard IP for PCI Express. The example turns on the Enable Configuration Space Bypass parameter.

• APPS: The Configuration Space Bypass application demonstrates Configuration Space Bypass mode.

• pcie_xcvr_reconfig_0: The Transceiver Reconfiguration Controller performs offset cancellation to compensate for variations due to process, voltage, and temperature (PVT).

• pcie_reconfig_driver_0: The PCIe Reconfig Driver drives the Transceiver Reconfiguration Controller. This driver is a plain text Verilog HDL file that you can modify if necessary to meet your system requirements.

ISO 9001:2008 Registered

pcie_reconfig_driver_0

to PCIe Root Port and Host System

Configuration

Bypass Top

(cfbp_top)

APPS: Config Bypass Example (cfbp_app_example)

DUT: Hard IP for PCIe Using Configuration Bypass Mode Endpoint

Function 0

Function 1

2 MByte Memory

Reset

(rs_hip)

Configuration Space

Local Management

Interface (LMI)

alt_xcvr_reconfig_0

Function 0 Registers Function 1 Registers

3-2

Copying the Configuration Space Bypass Mode Example Design

Figure 3-1: Configuration Bypass Mode Qsys Example Design

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Copying the Configuration Space Bypass Mode Example Design

Follow these steps to copy the Configuration Space Bypass Mode Qsys Example Design to your working directory:

1. Copy the example design, pcie_cfbp_g2x8_ast256.qsys, from the installation directory: <install_dir>/ip/

altera/altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/qsys_example to your working directory.

2. Copy the Qsys wrapper file for the Configuration Space Bypass application logic, altera_pcie_cfgbp_ed_

hw.tcl, from the installation directory: <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_ cfgbp_ed/ to your working directory.

3. Rename the pcie_cfbp_g2x8_ast256.qsys top.qys. Renaming is necessary because the testbench defines

4. Start Qsys by typing qsys-edit and open top.qsys when prompted by Qsys.

The following figure shows the complete system.

top.v as the top-level wrapper. Qsys creates top.v from top.qsys when you generate the system.

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Figure 3-2: Configuration Bypass Qsys System

Generating the Qsys System

3-3

1. Note the following parameter settings for the Configuration Space Bypass Example Design:

• For the DUT, the Enable Configuration Bypass parameter is turned on under the System Settings

banner.

• The Base Address Registers specify BAR0 as 1 MByte - 20 bits of 64-bit prefetchable memory for

each function. In Configuration Space Bypass Mode, the BAR registers inside the Hard IP for PCI Express are not used. The Application Layer implements the Configuration Space for each function.

• For testbench compatibility, the Config-Bypass App Example, labeled APPs, must retain a Device ID

of 0xE001 (5734510) and a Vendor ID of 0x1172 (446610).

Generating the Qsys System

On the Qsys Generate menu, select Generate Testbench System. Specify the parameters listed in the following table.

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Generating Quartus II Synthesis Files

Table 3-1: Parameters to Specify on the Generation Tab in Qsys

Parameter Value

Create testbench Qsys system Standard, BFMs for standard Avalon interfaces

Create simulation model Verilog

Allow mixed-language simulation Turn this option off

Output Directory

Path <working_dir>/top

Testbench <working_dir>/top/testbench

1. Click Generate to generate the simulation and testbench files.

2. On the File menu, click Save.

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Generating Quartus II Synthesis Files

1. On the Generate menu, select Generate HDL.

2. For Create HDL design files for synthesis, select Verilog.

You can leave the default settings for all other items.

3. Click Generate to generate files for Quartus II synthesis.

4. Click Finish when the generation completes.

Understanding the Generated Files

Table 3-2: Qsys Generation Output Files

Directory Description

<testbench_dir>/<variant_name>/synthesis Includes the top-level HDL file for the Hard IP for

<testbench_dir>/<variant_name>/synthesis/submodules

Includes the HDL files necessary for Quartus II synthesis.

<testbench_dir>/<variant_name>/testbench/<cad_ vendor>

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Includes the HDL source files and scripts for the simulation testbench.

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Understanding Simulation Log File Generation

Starting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_

monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory.

Table 3-3: Sample Simulation Log File Entries

Understanding Simulation Log File Generation

3-5

Time TLP Type Payload

(Bytes)

17989 RX CfgRd0 0004 04000001_0000000F_01080008 17989 RX MRd 0000 00000000_00000000_01080000 18021 RX CfgRd0 0004 04000001_0000010F_0108002C 18053 RX CfgRd0 0004 04000001_0000030F_0108003C 18085 RX MRd 0000 00000000_00000000_0108000C

Simulating the Example Design

Follow these steps to simulate the Qsys system using ModelSim:

1. In a terminal window, change to the <working_dir>/top/testbench/mentor directory.

2. Start the ModelSim simulator by typing vsim.

3. To compile the simulation, type the following commands in the terminal window:

• source msim_setup.tcl (The msim_setup.tcl file defines aliases.

• ld_debug (The ld_debug command argument stops optimizations, improving visibility in the ModelSim waveforms. )

The following figure shows the design hierarchy for the Configuration Space Bypass Example Design after compilation.

TLP Header

Figure 3-3: Design Hierarchy for the Configuration Space Bypass Example Design for 256-Bit Avalon-ST Interface

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Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface

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1. To observe the simulation, on the ModelSim View menu, select wave. Then add some key interfaces to the wave window. The following four interfaces under the /top_tb/top_inst/apps/altpcierd_cfbp_top/

cfgbp_app_ctrl/genblk1 illustrate the TX and RX interfaces, the current state, and configuration.

• *RxSt*

• *TxSt*

• *Rxm*

• *_state*

• cfg_*

2. To run the simulation, type the following command: run -all

Note: By default, the simulation is serial, to simulate using the parallel PIPE interface, you can change the

default value of the serial_sim_hwtcl parameter from 1 to 0 in altera_pcie_cfgbp_ed/top/testbench/

top_tb/simulation/top_tb.v. After changing that value, you must recompile the simulation to pick up

the new value of the serial_sim_hwtcl parameter before running the simulation.

Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface

The following timing diagram illustrates a Configuration Read to Function 0 starting at time 60568 ns in the simulation.

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