Altera Arria V GZ Avalon-ST User Manual

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Arria V GZ Avalon-ST Interface for PCIe Solutions

User Guide

Last updated for Altera Complete Design Suite: 14.1

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Application

Layer

(User Logic)

Avalon-ST

Interface

PCIe Hard IP

Block

PIPE

Interface

PHY IP Core

for PCIe

(PCS/PMA)

Serial Data

Transmission

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Arria V GZ Avalon-ST Interface for PCIe Datasheet

Altera® Arria V GZ® V FPGAs include a configurable, hardened protocol stack for PCI Express compliant with PCI Express Base Specification 2.1 or 3.0. The Hard IP for PCI Express using the Avalon Streaming (Avalon-ST) interface is the most flexible variant. However, this variant requires a thorough understanding of the PCIe

Protocol.

Figure 1-1: Arria V GZ PCIe Variant with Avalon-ST Interface

Table 1-1: PCI Express Data Throughput

The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4, and 8 lanes. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and 8.0 giga-transfers per second for Gen3. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to less than 1%.

that is

PCI Express Gen1 (2.5 Gbps)

PCI Express Gen2 (5.0 Gbps)

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Link Width

×1 ×2 ×4 ×8

2 4 8 16

4 8 16 32

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Features

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Link Width

×1 ×2 ×4 ×8

PCI Express Gen3 (8.0 Gbps)

Refer to the AN 690: PCI Express DMA Reference Design for Stratix V Devices for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs, including the Arria V GZ Hard IP for PCI Express IP core.

Devices

Related Information

• PCI Express Base Specification 2.1 or 3.0

• AN 690: PCI Express DMA Reference Design for Stratix V Devices

• Creating a System with Qsys

Features

New features in the Quartus® II 14.1 software release:

• Reduced Quartus II compilation warnings by 50%. The Arria V GZ Hard IP for PCI Express supports the following features:

• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.

• Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Root Ports and Endpoints.

• Dedicated 16 KByte receive buffer.

• Optional hard reset controller for Gen2.

• Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core bitstreams to be stored separately.

• Qsys example designs demonstrating parameterization, design modules, and connectivity.

• Extended credit allocation settings to better optimize the RX buffer space based on application type.

• Support for multiple packets per cycle with the 256-bit Avalon-ST interface.

• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.

• Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions.

• Support for Gen3 PIPE simulation.

• Easy to use:

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• Flexible configuration.

• Substantial on-chip resource savings and guaranteed timing closure.

• No license requirement.

• Example designs to get started.

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Table 1-2: Feature Comparison for all Hard IP for PCI Express IP Cores

The table compares the features of the four Hard IP for PCI Express IP Cores.

Features

1-3

Feature Avalon‑ST Interface Avalon‑MM

Interface

Avalon‑MM DMA Avalon‑ST Interface with SR-

IP Core License Free Free Free Free

Native

Supported Supported Supported Supported

Endpoint

Legacy Endpoint

(1)

Supported Not Supported Not Supported Not Supported

Root port Supported Supported Not Supported Not Supported

Gen1 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 Not Supported

Gen2 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 ×4, ×8

Gen3 ×1, ×2, ×4, ×8 ×1, ×2, ×4 ×4, ×8

64-bit Applica‐

Supported Supported Not supported Not supported

×8

×4, ×8

×2, ×4, ×8

tion Layer interface

IOV

128-bit

Supported Supported Supported Supported Application Layer interface

256-bit

Supported Not Supported Supported Supported Application Layer interface

(1)

Not recommended for new designs.

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Features

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Feature Avalon‑ST Interface Avalon‑MM

Interface

Transaction Layer Packet type (TLP)

• Memory Read Request

• Memory Read RequestLocked

• Memory Write Request

• I/O Read Request

• I/O Write Request

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Message Request

• Message Request with Data Payload

• Completion Message

• Completion with Data

• Memory Read Request

• Memory Write Request

• I/O Read Request—Root Port only

• I/O Write Request—Root Port only

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Completion Message

• Completion with Data

• Memory Read Request (single dword)

• Memory Write Request (single dword)

• Completion for Locked Read without Data

Avalon‑MM DMA Avalon‑ST Interface with SR-

IOV

• Memory Read Request

• Memory Write Request

• Completion Message

• Completion with Data

• Memory Read Request

• Memory Write Request

• Configuration Read Request (from Root Port)

• Configuration Write Request (from Root Port)

• Message Request

• Completion Message

• Completion with Data

Payload size

Number of tags supported for non-posted requests

62.5 MHz clock Supported Supported Not Supported Not Supported

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128–2048 bytes 128–256 bytes 128, 256, 512 bytes 128–256 bytes

256 8 16 256

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Features

1-5

Feature Avalon‑ST Interface Avalon‑MM

Interface

Out-of-order

Not supported Supported Supported Not supported completions (transparent to the Application Layer)

Requests that

Not supported Supported Supported Supported cross 4 KByte address boundary (transparent to the Application Layer)

Polarity

Supported Supported Supported Supported Inversion of PIPE interface signals

Avalon‑MM DMA Avalon‑ST Interface with SR-

IOV

ECRC

Supported Not supported Not supported Not supported forwarding on RX and TX

Number of MSI requests

1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 (for

Physical Functions)

MSI-X Supported Supported Supported Supported

Legacy

Supported Supported Supported Supported interrupts

Expansion

Supported Not supported Not supported Not supported ROM

The Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide explains how to use this IP core and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this document only in conjunction with an understanding of the PCI Express Base Specification.

Note:

This release provides separate user guides for the different variants. The Related Information provides links to all versions.

Related Information

Datasheet

• Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide

• Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide

• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

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Release Information

Table 1-3: Hard IP for PCI Express Release Information

Item Description

Version 14.1

Release Date December 2014

Ordering Codes No ordering code is required

Product IDs There are no encrypted files for the Arria V GZ

Hard IP for PCI Express. The Product ID and

Vendor ID

Vendor ID are not required because this IP core does not require a license.

Device Family Support

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Table 1-4: Device Family Support

Device Family Support

Arria V GZ Final. The IP core is verified with final timing

models. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Other device families Refer to the Related Information below for other

device families:

Related Information

• Arria V Avalon-MM Interface for PCIe Solutions User Guide

• Arria V Avalon-ST Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide

• Arria 10 Avalon-ST Interface for PCIe Solutions User Guide

• Cyclone V Avalon-MM Interface for PCIe Solutions User Guide

• Cyclone V Avalon-ST Interface for PCIe Solutions User Guide

• IP Compiler for PCI Express User Guide

• Stratix V Avalon-MM Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface with SR-IOV for PCIe Solutions User Guide

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Altera FPGA

User Application

Logic

PCIe

Hard IP

PCIe

Hard IP

User Application

Logic

PCI Express Link

Altera FPGA

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Configurations

The Arria V GZ Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack including the following layers:

• Physical (PHY), including:

• Media Access Control (MAC)

• Data Link Layer (DL)

• Transaction Layer (TL) The Hard IP supports all memory, I/O, configuration, and message transactions. It is optimized for Altera

devices. The Application Layer interface is also optimized to achieve maximum effective throughput. You can customize the Hard IP to meet your design requirements.

Figure 1-2: PCI Express Application with a Single Root Port and Endpoint

The following figure shows a PCI Express link between two Arria V GZ FPGAs.

• Physical Media Attachment (PMA)

• Physical Coding Sublayer (PCS)

Configurations

1-7

Datasheet

Figure 1-3: PCI Express Application Using Configuration via Protocol

The Arria V GZ design below includes the following components:

• A Root Port that connects directly to a second FPGA that includes an Endpoint.

• Two Endpoints that connect to a PCIe switch.

• A host CPU that implements CvP using the PCI Express link connects through the switch. For more

information about configuration over a PCI Express link, refer to Configuration via Protocol (CvP) on page 14-1.

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PCIe Link

PCIe Hard IP

Switch

PCIe

Hard IP

User Application

Logic

PCIe Hard IP

PCIe Link

User Application

Logic

Altera FPGA Hard IP for PCI Express

Altera FPGA with Hard IP for PCI Express

Active Serial or

Active Quad

Device Configuration

Configuration via Protocol (CvP)

using the PCI Express Link

Serial or

Quad Flash

USB

Download

cable

PCIe

Hard IP

User

Application

Logic

Altera FPGA with Hard IP for PCI Express

Config Control

CVP

USB

Host CPU

PCIe

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Avalon-ST Example Designs

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Related Information

Configuration via Protocol (CvP)Implementation in Altera FPGAs User Guide

Avalon-ST Example Designs

Altera provides example designs to familiarize you with the available functionality. Each design connects the device under test (DUT) to an application programming platform (APP), labeled APPs in the figure below. Certain critical parameters of the APPs component are set to match the values of the DUT. If you change these parameters, you must change the APPs component to match. You can change the values for all other parameters of the DUT without editing the APPs component.

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Figure 1-4: Example Design Preset Parameters

Avalon-ST Example Designs

1-9

In this example design, the following parameters must be set to match the values set in the DUT:

• Targeted Device Family

• Lanes

• Lane Rate

• Application Clock Rate

• Port type

• Application Interface

• Tags supported

• Maximum payload size The following Qsys example designs are available for the Arria V GZ Hard IP for PCI Express. You can

download them from the <install_dir>/ ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_design/<dev> directory:

• pcie_de_gen1_x4_ast64.qsys

• pcie_de_gen1_x8_ast128.qsys

• pcie_de_gen2_x8_ast256.qsys

• pcie_de_gen3_x1_ast64.qsys

• pcie_de_gen3_x4_ast128.qsys

• pcie_de_gen3_x8_ast256.qsys

• pcie_de_rp_gen1_x4_ast64.qsys

• pcie_de_rp_gen1_x8_ast128.qsys

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Debug Features

Debug features allow observation and control of the Hard IP for faster debugging of system-level problems.

Related Information

Debugging on page 18-1

IP Core Verification

To ensure compliance with the PCI Express specification, Altera performs extensive verification. The simulation environment uses multiple testbenches that consist of industry-standard bus functional models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the simulation environment:

• Directed and pseudorandom stimuli are applied to test the Application Layer interface, Configuration Space, and all types and sizes of TLPs

• Error injection tests that inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and check for the proper responses

• PCI-SIG® Compliance Checklist tests that specifically test the items in the checklist

• Random tests that test a wide range of traffic patterns

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Altera provides the following two example designs that you can leverage to test your PCBs and complete compliance base board testing (CBB testing) at PCI-SIG.

Related Information

• PCI SIG Gen3 x8 Merged Design - Stratix V

• PCI SIG Gen2 x8 Merged Design - Stratix V

Compatibility Testing Environment

Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera internally tests every release with motherboards and PCI Express switches from a variety of manufac‐ turers. All PCI-SIG compliance tests are run with each IP core release.

Performance and Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device resources.

Note:

Related Information

Fitter Resources Reports

Soft calibration of the transceiver module requires additional logic. The amount of logic required depends upon the configuration.

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Recommended Speed Grades

Table 1-5: Arria V GZ Recommended Speed Grades for All Link Widths and Application Layer Clock Frequencies

Altera recommends setting the Quartus II Analysis & Synthesis Settings Optimization Technique to Speed when the Application Layer clock frequency is 250 MHz. For information about optimizing synthesis, refer to Setting Up and Running Analysis and Synthesis in Quartus II Help. For more information about how to effect the

Optimization Technique settings, refer to Area and Timing Optimization in volume 2 of the Quartus II Handbook.

1-11

Link Rate Link Width Interface

Width

x1 64 bits 62.5

x2 64 bits 125 –1, –2, –3, –4

Gen1

x4 64 bits 125 –1, –2, –3, –4

x8 64 bits 250 –1, –2, –3

x8 128 Bits 125 –1, –2, –3, –4

x1 64 bits

x2 64 bits 125 –1, –2, –3, –4

x4 64 bits 250 –1, –2, –3

Gen2

x4 128 bits 125 –1, –2, –3, –4

x8 128 bits 250 –1, –2, –3

Application Clock

Frequency (MHz)

(2)

,125 –1, –2, –3, –4

125

Recommended Speed Grades

(3)

–1, –2, –3, –4

(3)

(2) (3)

Datasheet

x8 256 bits 125 –1, –2, –3, –4

This is a power-saving mode of operation The -4 speed grade is also possible for this configuration; however, it requires significant effort by the end user to close timing.

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Steps in Creating a Design for PCI Express

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Link Rate Link Width Interface

Width

Application Clock

Frequency (MHz)

x1 64 bits 125 –1, –2, –3, –4

x2 64 bits 250 –1, –2, –3, –4

x2 128 bits 125 –1, –2, –3, –4

Gen3

x4 128 bits 250 –1, –2, –3

x4 256 bits 125 –1, –2, –3,–4

x8 256 bits 250 –1, –2, –3

Related Information

• Area and Timing Optimization

• Altera Software Installation and Licensing Manual

• Setting up and Running Analysis and Synthesis

Recommended Speed Grades

(3)

Steps in Creating a Design for PCI Express

Before you begin

Select the PCIe variant that best meets your design requirements.

• Is your design an Endpoint or Root Port?

• What Generation do you intend to implement?

• What link width do you intend to implement?

• What bandwidth does your application require?

• Does your design require CvP?

1. Select parameters for that variant.

2. Simulate using an Altera-provided example design. All of Altera's PCI Express example designs are

available under <install_dir>/ip/altera/altera_pcie/. Alternatively, create a simulation model and use your own custom or third-party BFM. The Qsys Generate menu generates simulation models. Altera supports ModelSim®-Altera for all IP. The PCIe cores support the Aldec RivieraPro, Cadence NCsim, Mentor Graphics ModelSim, and Synopsys VCS and VCS-MX simulators.

3. Compile your design using the Quartus II software. If the versions of your design and the Quartus II software you are running do not match, regenerate your PCIe design.

4. Download your design to an Altera development board or your own PCB. Click on the All Develop‐ ment Kits link below for a list of Altera's development boards.

5. Test the hardware. You can use Altera's SignalTap® II Logic Analyzer or a third-party protocol analyzer to observe behavior.

6. Substitute your Application Layer logic for the Application Layer logic in Altera's testbench. Then repeat Steps 3–6. In Altera's testbenches, the PCIe core is typically called the DUT (device under test). The Application Layer logic is typically called APPS.

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Steps in Creating a Design for PCI Express

Related Information

• Parameter Settings on page 4-1

• Getting Started with the Arria V GZ Hard IP for PCI Express on page 2-1

• All Development Kits

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Getting Started with the Arria V GZ Hard IP for

APPS altpcied_<dev>_hwtcl.v

Hard IP for PCI Express Testbench for Endpoints

Avalon-ST TX Avalon-ST RX

reset

status

Avalon-ST TX Avalon-ST RX reset status

DUT altpcie_<dev>_hip_ast_hwtcl.v

Root Port Model altpcie_tbed_<dev>_hwtcl.v

PIPE or

Serial

Interface

Root Port BFM altpcietb_bfm_rpvar_64b_x8_pipen1b

Root Port Driver and Monitor altpcietb_bfm_vc_intf

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This section provides instructions to help you quickly customize, simulate, and compile the Arria V GZ Hard IP for PCI Express IP Core. When you install the Quartus II software you also install the IP Library. This installation includes design examples for Hard IP for PCI Express under the <install_dir>/ip/altera/

altera_pcie/ directory.

After you install the Quartus II software, you can copy the design examples from the <install_dir>/ip/altera/

altera_pcie/altera_pcie/altera_pcie_hip_ast_ed/example_designs/<dev> directory. This walkthrough uses the

Gen1 ×8 Endpoint, pcie_de_gen1_x8_ast128.qsys. The following figure illustrates the top-level modules of the testbench in which the DUT, a Gen1 Endpoint, connects to a chaining DMA engine, labeled APPS in the following figure, and a Root Port model. The simulation can use the parallel PHY Interface for PCI Express (PIPE) or serial interface.

Figure 2-1: Testbench for an Endpoint

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Note:

The Quartus II release automatically creates a simulation log, altpcie_monitor_<dev>_dlhip_tlp_file_

log.log, file in your simulation directory. If you have an existing 13.1 or older design, you must

regenerate it in the current release in order to simulate. Regeneration is necessary to create the supporting monitor file the generates altpcie_monitor_<dev>_dlhip_tlp_file_log.log. Refer to Understanding Simulation Log File Generation for details.

Altera provides example designs to help you get started with the Arria V GZ Hard IP for PCI Express IP Core. You can use example designs as a starting point for your own design. The example designs include

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2-2

Qsys Design Flow

scripts to compile and simulate the Arria V GZ Hard IP for PCI Express IP Core. This example design provides a simple method to perform basic testing of the Application Layer logic that interfaces to the Hard IP for PCI Express.

For a detailed explanation of this example design, refer to the Testbench and Design Example chapter. If you choose the parameters specified in this chapter, you can run all of the tests included in Testbench and Design Example chapter.

For more information about Qsys, refer to System Design with Qsys in the Quartus II Handbook. For more information about the Qsys GUI, refer to About Qsys in Quartus II Help.

Related Information

• Understanding Simulation Log File Generation on page 2-5

• System Design with Qsys

• About Qsys

Qsys Design Flow

Copy the pcie_de_gen1_x8_ast128.qsys design example from the <install_dir>/ip/altera/altera_pcie/altera_

pcie/altera_pcie_hip_ast_ed/example_designs/<dev> to your working directory.

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The following figure illustrates this Qsys system.

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Figure 2-2: Complete Gen1 ×8 Endpoint (DUT) Connected to Example Design (APPS)

Qsys Design Flow

2-3

The example design includes the following components:

• DUT—This is Gen1 ×8 Endpoint. For your own design, you can select the data rate, number of lanes, and either Endpoint or Root Port mode.

• APPS—This Root Port BFM configures the DUT and drives read and write TLPs to test DUT functionality. An Endpoint BFM is available if your PCI Express design implements a Root Port.

• pcie_reconfig_driver_0—This Avalon-MM master drives the Transceiver Reconfiguration Controller. The pcie_reconfig_driver_0 is implemented in clear text that you can modify if your design requires different reconfiguration functions. After you generate your Qsys system, the Verilog HDL for this component is available as: <working_dir>/<variant_name>/testbench/<variant_name>_tb/simulation/

submodules/altpcie_reconfig_driver.sv.

• Transceiver Reconfiguration Controller—The Transceiver Reconfiguration Controller dynamically reconfigures analog settings to improve signal quality. For Gen1 and Gen2 data rates, the Transceiver Reconfiguration Controller must perform offset cancellation and PLL calibration. For the Gen3 data rate, the pcie_reconfig_driver_0 performs AEQ through the Transceiver Reconfiguration Controller.

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Generating the Testbench

1. On the Generate menu, select Generate Testbench System. Specify the parameters listed in the following table.

Table 2-1: Parameters to Specify on the Generation Tab in Qsys

Parameter Value

Testbench System

Create testbench Qsys system Standard, BFMs for standard Qsys interfaces

Create testbench simulation model Verilog

Allow mixed-language simulation Turn this option off

Output Directory

Testbench <working_dir>/pcie_de_gen1_x8_ast128/testbench

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2. Click the Generate button at the bottom of the Generation tab to create the testbench.

Note:

Simulating the Example Design

1. Start your simulation tool. This example uses the ModelSim® software.

2. From the ModelSim transcript window, in the testbench directory type the following commands: a. do msim_setup.tcl

b. ld_debug (This command compiles all design files and elaborates the top-level design without any

optimization.)

c. run -all

The simulation includes the following stages:

• Link training

• Configuration

• DMA reads and writes

• Root Port to Endpoint memory reads and writes

Disabling Scrambling to Interpret TLPs at the PIPE Interface

1. Go to <project_directory/<variant>/testbench/<variant>_tb/simulation/submodules/.

2. Open altpcietb_bfm_top_rp.v.

3. Locate the declaration of test_in[2:1]. Set test_in[2] = 1 and test_in[1] = 0. Changing

test_in[2] = 1 disables data scrambling on the PIPE interface.

4. Save altpcietb_bfm_top_rp.v.

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Generating Quartus II Synthesis Files

1. On the Generate menu, select Generate HDL.

2. For Create HDL design files for synthesis, select Verilog.

You can leave the default settings for all other items.

3. Click Generate to generate files for Quartus II synthesis.

4. Click Finish when the generation completes.

Understanding the Files Generated

Table 2-2: Overview of Qsys Generation Output Files

Directory Description

<testbench_dir>/<variant_name>/synthesis Includes the top-level HDL file for the Hard IP for

Generating Quartus II Synthesis Files

PCI Express and the .qip file that lists all of the necessary assignments and information required to process the IP core in the Quartus II compiler. Generally, a single .qip file is generated for each IP core.

2-5

<testbench_dir>/<variant_name>/synthesis/submodules

Includes the HDL files necessary for Quartus II synthesis.

<testbench_dir>/<variant_name>/testbench

Includes testbench subdirectories for the Aldec, Cadence, Synopsys, and Mentor simulation tools with the required libraries and simulation scripts.

<testbench_dir>/<variant_name>/testbench<cad_ vendor>

Includes the HDL source files and scripts for the simulation testbench.

For a more detailed listing of the directories and files the Quartus II software generates, refer to Files Generated for Altera IP Cores in Compiling the Design in the Qsys Design Flow.

Understanding Simulation Log File Generation

Starting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_

monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory.

Table 2-3: Sample Simulation Log File Entries

Time TLP Type Payload

(Bytes)

TLP Header

17989 RX CfgRd0 0004 04000001_0000000F_01080008 17989 RX MRd 0000 00000000_00000000_01080000 18021 RX CfgRd0 0004 04000001_0000010F_0108002C 18053 RX CfgRd0 0004 04000001_0000030F_0108003C

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Understanding Physical Placement of the PCIe IP Core

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Time TLP Type Payload

(Bytes)

18085 RX MRd 0000 00000000_00000000_0108000C

Understanding Physical Placement of the PCIe IP Core

For more information about physical placement of the PCIe blocks, refer to the links below. Contact your Altera sales representative for detailed information about channel and PLL usage.

Related Information

Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices on page 5-62

Compiling the Design in the Qsys Design Flow

To compile the Qsys design example in the Quartus II software, you must create a Quartus II project and add your Qsys files to that project.

1. Before compiling, you can optionally turn on two parameters in the testbench. The first parameter specifies pin assignments that match those for the Altera Development Kit board I/Os. The second parameter enables the Compliance Base Board (CBB) logic on the development board. In the Gen1 x8 example design, complete the following steps if you want to enable these parameters:

a. Right-click the APPS component and select Edit. b. Turn on Enable FPGA Dev kit board I/Os. c. Turn on Enable FPGA Dev kit board CBB logic. d. Click Finish. e. On the Generate menu, select Generate Testbench System and then click Generate. f. On the Generate menu, select Generate HDL and then click Generate. (You can use the same

parameters that are specified in Generating the Testbench earlier in this chapter).

2. In the Quartus II software, click the New Project Wizard icon.

3. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you

previously turned it off.)

4. On the Directory, Name, Top-Level Entity page, enter the following information:

TLP Header

5. Click Next to display the Add Files page.

6. Complete the following steps to add the Quartus II IP File ( .qip )to the project:

7. Click Next to display the Device page.

8. On the Family & Device Settings page, choose the following target device family and options:

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a. The working directory shown is correct. You do not have to change it. b. For the project name, browse to the synthesis directory that includes your Qsys project,

<working_dir>/pcie_de_gen1_x8_ast128/synthesis. Select your variant name,

pcie_de_gen1_x8_ast128.v . Then, click Open.

c. For Project Type select Empty project.

a. Click the browse button. The Select File dialog box appears. b. In the Files of type list, select IP Variation Files (*.qip *.sip). c. Click pcie_de_gen1_x8_ast128.qip and then click Open. d. On the Add Files page, click Add.

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Compiling the Design in the Qsys Design Flow

2-7

a. In the Family list, select Arria V GZ . b. In the Devices list, select Arria V GZ All. c. In the Available Devices list, select 5AGZME5K2F40C3 .

9. Click Next to close this page and display the EDA Tool Settings page.

10.From the Simulation list, select ModelSim®. From the Format list, select the HDL language you

intend to use for simulation.

11.Click Next to display the Summary page.

12.Check the Summary page to ensure that you have entered all the information correctly.

13.Click Finish to create the Quartus II project.

14.Before compiling, you must assign I/O standards to the pins of the device. Refer to Making Pin

Assignments to Assign I/O Standard to Serial Data Pins for instructions.

15.You must connect the pin_perst reset signal to the correcsponding nPERST pin of the device. Refer to the definition of pin_perst in the Reset, Status, and Link Training Signals section for more informa‐ tion.

16.Next, set the value of the test_in bus to a value that is compatible for hardware testing. In Qsys design example provided, test_in is a top-level port.

a. Comment out the test_in port in the top-level Verilog generated file. b. Add the following declaration, wire[31:0] test_in, to the same top-level Verilog file. c. Assign hip_ctrl_test_in = 32'hA8. d. Connect test_in to hip_ctrl_test_in.

Refer to the definition of test_in in the Test Signals section for more information about the bits of the

test_in bus.

17.Add the Synopsys Design Constraint (SDC) shown in the following example below to the top-level design file for your Quartus II project.

18.To compile your design using the Quartus II software, on the Processing menu, click Start Compila‐ tion. The Quartus II software then performs all the steps necessary to compile your design.

Example 2-1: Synopsys Design Constraints

create_clock -period “100 MHz” -name {refclk_pci_express}{*refclk_*} derive_pll_clocks derive_clock_uncertainty

# PHY IP reconfig controller constraints # Set reconfig_xcvr clock # Modify to match the actual clock pin name # used for this clock, and also changed to have the correct period set create_clock -period "125 MHz" -name {reconfig_xcvr_clk}{*reconfig_xcvr_clk*}

# HIP Soft reset controller SDC constraints set_false_path -to [get_registers* altpcie_rs_serdes|fifo_err_sync_r[0]] set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to[get_registers *altpcie_rs_serdes|*]

# Hard IP testin pins SDC constraints set_false_path -from [get_pins -compatibilitly_mode *hip_ctrl*]

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Notes:

1. If supported and enabled for your IP variation

2. If functional simulation models are generated

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file <your_ip>_inst.v or .vhd - Sample instantiation template

synthesis - IP synthesis files

<your_ip>.qip - Lists files for synthesis

testbench - Simulation testbench files

<testbench_hdl_files>

<simulator_vendor> - Testbench for supported simulators

<simulation_testbench_files>

<your_ip>.v or .vhd - Top-level IP variation synthesis file

simulation - IP simulation files

<your_ip>.sip - NativeLink simulation integration file

<simulator vendor> - Simulator setup scripts

<simulator_setup_scripts>

<your_ip> - IP core variation files

<your_ip>.qip or .qsys - System or IP integration file

<your_ip>_generation.rpt - IP generation report <your_ip>.bsf - Block symbol schematic file

<your_ip>.ppf - XML I/O pin information file <your_ip>.spd - Combines individual simulation startup scripts

<your_ip>.html - Contains memory map

<your_ip>.sopcinfo - Software tool-chain integration file

<your_ip>_syn.v or .vhd - Timing & resource estimation netlist

<your_ip>.debuginfo - Lists files for synthesis

<your_ip>.v, .vhd, .vo, .vho - HDL or IPFS models

<your_ip>_tb - Testbench for supported simulators

<your_ip>_tb.v or .vhd - Top-level HDL testbench file

2-8

Compiling the Design in the Qsys Design Flow

Files Generated for Altera IP Cores Figure 2-3: IP Core Generated Files

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Related Information

• Simulating the Example Design on page 3-5

• Generating the Testbench on page 2-4

• Simulating the Example Design on page 3-5

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PCB

Avalon-MM slave

Reset

Hard IP for PCI Express

Altera FPGA

PCB

Transaction Layer

Data Link Layer

PHY MAC Layer

x8 PCIe Link

(Physical Layer)

Lane 7

(Unused)

Lane 6

Lane 5

TX PLL

PHY IP Core for PCI Express

Lane 2

Lane 3

Lane 4

Lane 1

Lane 0

TX PLL

Transceiver Bank

Reconfig

to and from

Transceiver

to and from

Embedded

Controller

(Avalon-MM

slave interface)

Transceiver

Reconfiguration

Controller

Root

Port BFM

npor

Reset

APPS DUT

Chaining DMA

(User Application)

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Modifying the Example Design

To use this example design as the basis of your own design, replace the Chaining DMA Example shown in the following figure with your own Application Layer design. Then modify the Root Port BFM driver to generate the transactions needed to test your Application Layer.

Figure 2-4: Testbench for PCI Express

Modifying the Example Design

2-9

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Using the IP Catalog To Generate Your Arria V GZ Hard IP for PCI Express as a Separate Component

You can also instantiate the Arria V GZ Hard IP for PCI Express IP Core as a separate component for integration into your project.

You can use the Quartus II IP Catalog and IP Parameter Editor to select, customize, and generate files representing your custom IP variation. The IP Catalog (Tools > IP Catalog) automatically displays IP cores available for your target device. Double-click any IP core name to launch the parameter editor and generate files representing your IP variation.

For more information about the customizing and generating IP Cores refer to Specifying IP Core Parameters and Options in Introduction to Altera IP Cores. For more information about upgrading older IP cores to the current release, refer to Upgrading Outdated IP Cores in Introduction to Altera IP Cores.

Note: Your design must include the Transceiver Reconfiguration Controller IP Core and the Altera PCIe

Reconfig Driver. Refer to the figure in the Qsys Design Flow section to learn how to connect this components.

Related Information

• Qsys Design Flow on page 2-2

• Introduction to Altera IP Cores

• Managing Quartus II Projects

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Getting Started with the Configuration Space

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101 Innovation Drive, San Jose, CA 95134

Bypass Mode Qsys Example Design

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This Qsys design example demonstrates Configuration Space Bypass mode for the Arria V GZ Hard IP for PCI Express IP Core. A Root Port BFM provides stimulus to the Endpoint design. The Endpoint bypasses the standard Configuration Space to access the custom Configuration Space and memory of two functions. The Configuration Space Bypass Example Design performs the following functions:

• Accepts Configuration, Memory, and Message TLPs on the Arria V GZ Hard IP for PCI Express RX Avalon-ST interface

• Translates Type 0 Configuration Read and Configuration Write Requests to Avalon-MM read and write requests that target the Configuration Space of either Function 0 or Function 1.

• Responds to invalid Type 0 Configuration Requests with an Unsupported Request (UR) status in a Completion Message.

• Converts single dword Memory Read and Memory Write Requests to access 32-bit registers of the target function using the Avalon-MM interface.

• Maps two contiguous MBytes of memory for the two functions with the first MByte for Function 0 and the second MByte for Function 1.

• Sets up two registers for each function.

• Drops the following invalid Write Requests:

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• Memory Write Requests with a payload of more than one dword

• Messages with data

• Returns Completer Abort (CA) status in Completion message for invalid Memory Read Requests such as Memory Read Requests with a payload greater than one dword.

• Returns a Completion Status of Successful Completion for valid Configuration Requests to Function 0 and Function 1.

The following figure illustrates, the components of the Configuration Space Bypass Mode Qsys Example Design. The example design includes the following components:

• DUT: The Arria V GZ Hard IP for PCI Express. The example turns on the Enable Configuration Space Bypass parameter.

• APPS: The Configuration Space Bypass application demonstrates Configuration Space Bypass mode.

• pcie_xcvr_reconfig_0: The Transceiver Reconfiguration Controller performs offset cancellation to compensate for variations due to process, voltage, and temperature (PVT).

• pcie_reconfig_driver_0: The PCIe Reconfig Driver drives the Transceiver Reconfiguration Controller. This driver is a plain text Verilog HDL file that you can modify if necessary to meet your system requirements.

ISO 9001:2008 Registered

pcie_reconfig_driver_0

to PCIe Root Port and Host System

Configuration

Bypass Top

(cfbp_top)

APPS: Config Bypass Example (cfbp_app_example)

DUT: Hard IP for PCIe Using Configuration Bypass Mode Endpoint

Function 0

Function 1

2 MByte Memory

Reset

(rs_hip)

Configuration Space

Local Management

Interface (LMI)

alt_xcvr_reconfig_0

Function 0 Registers Function 1 Registers

3-2

Copying the Configuration Space Bypass Mode Example Design

Figure 3-1: Configuration Bypass Mode Qsys Example Design

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Copying the Configuration Space Bypass Mode Example Design

Follow these steps to copy the Configuration Space Bypass Mode Qsys Example Design to your working directory:

1. Copy the example design, pcie_cfbp_g2x8_ast256.qsys, from the installation directory: <install_dir>/ip/

altera/altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/qsys_example to your working directory.

2. Copy the Qsys wrapper file for the Configuration Space Bypass application logic, altera_pcie_cfgbp_ed_

hw.tcl, from the installation directory: <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_ cfgbp_ed/ to your working directory.

3. Rename the pcie_cfbp_g2x8_ast256.qsys top.qys. Renaming is necessary because the testbench defines

4. Start Qsys by typing qsys-edit and open top.qsys when prompted by Qsys.

The following figure shows the complete system.

top.v as the top-level wrapper. Qsys creates top.v from top.qsys when you generate the system.

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Figure 3-2: Configuration Bypass Qsys System

Generating the Qsys System

3-3

1. Note the following parameter settings for the Configuration Space Bypass Example Design:

• For the DUT, the Enable Configuration Bypass parameter is turned on under the System Settings

banner.

• The Base Address Registers specify BAR0 as 1 MByte - 20 bits of 64-bit prefetchable memory for

each function. In Configuration Space Bypass Mode, the BAR registers inside the Hard IP for PCI Express are not used. The Application Layer implements the Configuration Space for each function.

• For testbench compatibility, the Config-Bypass App Example, labeled APPs, must retain a Device ID

of 0xE001 (5734510) and a Vendor ID of 0x1172 (446610).

Generating the Qsys System

On the Qsys Generate menu, select Generate Testbench System. Specify the parameters listed in the following table.

Getting Started with the Configuration Space Bypass Mode Qsys Example Design

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Generating Quartus II Synthesis Files

Table 3-1: Parameters to Specify on the Generation Tab in Qsys

Parameter Value

Create testbench Qsys system Standard, BFMs for standard Avalon interfaces

Create simulation model Verilog

Allow mixed-language simulation Turn this option off

Output Directory

Path <working_dir>/top

Testbench <working_dir>/top/testbench

1. Click Generate to generate the simulation and testbench files.

2. On the File menu, click Save.

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Generating Quartus II Synthesis Files

1. On the Generate menu, select Generate HDL.

2. For Create HDL design files for synthesis, select Verilog.

You can leave the default settings for all other items.

3. Click Generate to generate files for Quartus II synthesis.

4. Click Finish when the generation completes.

Understanding the Generated Files

Table 3-2: Qsys Generation Output Files

Directory Description

<testbench_dir>/<variant_name>/synthesis Includes the top-level HDL file for the Hard IP for

<testbench_dir>/<variant_name>/synthesis/submodules

Includes the HDL files necessary for Quartus II synthesis.

<testbench_dir>/<variant_name>/testbench/<cad_ vendor>

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Includes the HDL source files and scripts for the simulation testbench.

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Understanding Simulation Log File Generation

Starting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_

monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory.

Table 3-3: Sample Simulation Log File Entries

Understanding Simulation Log File Generation

3-5

Time TLP Type Payload

(Bytes)

17989 RX CfgRd0 0004 04000001_0000000F_01080008 17989 RX MRd 0000 00000000_00000000_01080000 18021 RX CfgRd0 0004 04000001_0000010F_0108002C 18053 RX CfgRd0 0004 04000001_0000030F_0108003C 18085 RX MRd 0000 00000000_00000000_0108000C

Simulating the Example Design

Follow these steps to simulate the Qsys system using ModelSim:

1. In a terminal window, change to the <working_dir>/top/testbench/mentor directory.

2. Start the ModelSim simulator by typing vsim.

3. To compile the simulation, type the following commands in the terminal window:

• source msim_setup.tcl (The msim_setup.tcl file defines aliases.

• ld_debug (The ld_debug command argument stops optimizations, improving visibility in the ModelSim waveforms. )

The following figure shows the design hierarchy for the Configuration Space Bypass Example Design after compilation.

TLP Header

Figure 3-3: Design Hierarchy for the Configuration Space Bypass Example Design for 256-Bit Avalon-ST Interface

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Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface

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1. To observe the simulation, on the ModelSim View menu, select wave. Then add some key interfaces to the wave window. The following four interfaces under the /top_tb/top_inst/apps/altpcierd_cfbp_top/

cfgbp_app_ctrl/genblk1 illustrate the TX and RX interfaces, the current state, and configuration.

• *RxSt*

• *TxSt*

• *Rxm*

• *_state*

• cfg_*

2. To run the simulation, type the following command: run -all

Note: By default, the simulation is serial, to simulate using the parallel PIPE interface, you can change the

default value of the serial_sim_hwtcl parameter from 1 to 0 in altera_pcie_cfgbp_ed/top/testbench/

top_tb/simulation/top_tb.v. After changing that value, you must recompile the simulation to pick up

the new value of the serial_sim_hwtcl parameter before running the simulation.

Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface

The following timing diagram illustrates a Configuration Read to Function 0 starting at time 60568 ns in the simulation.

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RxStMask_o

RxStSop_i RxStEop_i

RxStValid_i

RxStReady_o

RxStData_i[255:0]

cfg_addr_o[31:0]

cfg_rden_o

cfg_wren_o

cfg_be_o[3:0

cfg_rddatavalid _

cfg_rddata_i[31:0]

cfg_readresponse_i[2:0]

TxStReady_i

TxStSop_o TxStEop_o

TxStValid_o

TxStEmpty_o[1:0]

TxStData_o[255:0]

rx_state[10:0]

rxcfg_state[4:0]

tx_state[1:0]

’b0000000000000000000 .

000 003 005 021 009 000

E0011172

...E00111720000000000000044A000001

0108000001120004

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Figure 3-4: Configuration Read to Function 0

Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface

3-7

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Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface

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The preceding timing diagram illustrates the following sequence of events:

1. The Application Layer indicates it is ready to receive requests by asserting RxSTReady_o. The RX Avalon-ST interface initiates a Configuration Read, asserting its RxStSop_i and RxStValid_i signals.

2. At the falling edge of RxStSop_i, the Avalon-MM master interface asserts cfg_rden_o and specifies the address on cfg_addr_o[31:0].

3. The Function 0 Avalon-MM slave interface asserts cfg_rddavalid_i and drives the data on

cfg_rddata_i[31:0].

4. On the falling edge of cfg_rddavalid_i, the TX interface asserts TxStSop_o and TxStValid_o and drives the data of TxStData_o[255:0]. This is the Completion Request to the host corresponding to its Configuration Read Request.

Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface

The following timing diagram illustrates a configuration write to Function 0 starting at time 61859 ns in the simulation.

The timing diagram illustrates the following sequence of events:

1. The Application Layer indicates it is ready to receive requests by asserting RxSTReady_o. The RX Avalon-ST interface initiates a Configuration Write, asserting its RxStSop_i and RxStValid_i signals.

2. At the falling edge of RxStSop_i, the Avalon-MM master interface asserts cfg_wren_o and specifies the data on cfg_wrdata_o[31:0]. The Master interface also assert cfg_writeresponserequest_o, to request completion status from Function 0.

3. On the falling edge of cfg_writeresponserequest_o, Function 0 asserts cfg_writeresponse-

valid_i.

4. On the falling edge of cfg_writeresponsevalid_i, the TX interface asserts TxStSop_o and

TxStValid_o and drives the completion data on TxStData_o[255:0].

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RxStMask_o

RxStSop_i RxStEop_i

RxStValid_i

RxStReady_o

RxStData_i[255:0

cfg_addr_o[31:0]

cfg_rden_o

cfg_wren_

cfg_writeresponserequest _

cfg_wrdata_o[31:0]

cfg_writeresponsevalid

cfg_writeresponse_i[2:0]

cfg_waitrequest _

cfg_be_o[3:0]

TxStReady_i

TxStSop_o TxStEop_o

TxStValid_o

TxStData_o[255:0]

rx_state[10:0]

rxavl_state[3:0]

rxcfg_state[4:0]

tx_state[1:0]

000000000000.0000000

00000060

01000004

0000000 ..800040A000001

00000000000000000000000601000004000000F440800100000F4408001

000 003 005 021 009 081 000 003

03 09 11

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Figure 3-5: Configuration Write to Function 0

Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface

3-9

Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface

The following timing diagram illustrates memory to Function 1 which occurs in the simulation starting at time 99102 ns.

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RxStMask_o

RxStSop_i RxStEop_i

RxStValid_i

RxStReady_o

TxStReady_i

TxStSop_o TxStEop_o

TxStValid_ o

rx_state[10:0]

rxavl_state[3:0]

rxcfg_state[4:0]

tx_state[1:0]

RxmAddress_0_o[19:0]

RxmFunc1Sel _o

RxmWrite_0_o

RxmWriteData_0_o[31:0]

RxmWaitRequest_0

RxmRead_0_ o

RxmReadDataValid_0 _

RxmReadData_0_i[31:0]

000 003

90030 00000

005 021 041 000 003 005 021 041 00

3 9 0 5

BABEFACE

1 3

5 6

3-10

Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface

Figure 3-6: Timing for Memory Write and Read of Function 1

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Partial Transcript for Configuration Space Bypass Simulation

The timing diagram illustrates the following sequence of events:

1. The Application Layer indicates it is ready to receive requests by asserting RxSTReady_o. The RX Avalon-ST interface initiates a Memory Write to Function 1, asserting its RxStSop_i and

RxStValid_i signals.

2. At the falling edge of RxStSop_i, RxmFunc1Sel_o is asserted and the write data is driven on RxmWrite-

Data_0_o[31:0]. The Memory Write to Function 1 completes when the data is written.

3. The Application Layer indicates it is ready to receive requests by asserting RxSTReady_o. The RX Avalon-ST interface initiates a Memory Read to Function 1, asserting its RxStSop_i and RxStValid_i signals.

4. After the falling edge of RxStSop_i, the RX Avalon-MM master interface asserts RxmRead_0_o to Function 1.

5. At the falling edge of RxmRead_0_o, Function 1 asserts RxmReadDataValid_0 and drives the data on

RxmReadData_0_i[ 31:0].

6. The host receives the completion data when TxStValid_o, TxStSop_o, and TxStEop_o are asserted.

Partial Transcript for Configuration Space Bypass Simulation

The driver performs the following transactions with status of the transactions displayed in the ModelSim simulation message window:

3-11

• Various configuration reads and writes to the Avalon-MM Arria V GZ Hard IP for PCI Express in your system after the link is initialized

• Register writes, reads and compares to both functions

• Burst memory writes, reads, and compares to both functions

The following example shows the transcript from a successful simulation run.

Example 3-1: Transcript from ModelSim Simulation of Gen1 x4 Endpoint

# INFO: 464 ns Completed initial configuration of Root Port. # 495000: INFO: top_tb.top_inst_reset_bfm.reset_deassert: Reset deasserted # INFO: 3657 ns RP LTSSM State: DETECT.ACTIVE # INFO: 4425 ns RP LTSSM State: POLLING.ACTIVE # INFO: 17257 ns RP LTSSM State: DETECT.QUIET # INFO: 20473 ns RP LTSSM State: DETECT.ACTIVE # INFO: 21193 ns RP LTSSM State: POLLING.ACTIVE # INFO: 29909 ns EP LTSSM State: DETECT.ACTIVE # INFO: 30949 ns EP LTSSM State: POLLING.ACTIVE # INFO: 33957 ns EP LTSSM State: POLLING.CONFIG # INFO: 34025 ns RP LTSSM State: DETECT.QUIET # INFO: 37241 ns RP LTSSM State: DETECT.ACTIVE # INFO: 37961 ns RP LTSSM State: POLLING.ACTIVE # INFO: 39945 ns RP LTSSM State: POLLING.CONFIG # INFO: 41033 ns RP LTSSM State: CONFIG.LINKWIDTH.START # INFO: 41445 ns EP LTSSM State: CONFIG.LINKWIDTH.START # INFO: 41765 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT # INFO: 42057 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT # INFO: 42249 ns RP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 42789 ns EP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 43033 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 43109 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 43225 ns RP LTSSM State: CONFIG.COMPLETE # INFO: 43685 ns EP LTSSM State: CONFIG.COMPLETE # INFO: 44953 ns RP LTSSM State:CONFIG.IDLE # INFO: 47941 ns EP LTSSM State: CONFIG.IDLE

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3-12

Partial Transcript for Configuration Space Bypass Simulation

# INFO: 48089 ns RP LTSSM State: L0 # INFO: 48133 ns EP LTSSM State: L0 # INFO: 48226 ns Configuring Bus 000, Device 000, Function 00 # INFO: 48226 ns RP Read Only Configuration Registers: # INFO: 48226 ns Vendor ID: 1556 # INFO: 48226 ns Device ID: 5555 # INFO: 48226 ns Revision ID: 00 # INFO: 48226 ns Class Code: 040000 # INFO: 48706 ns ECRC Check Capable: Supported # INFO: 48706 ns ECRC Generation Capable: Supported # INFO: 48738 ns RP PCI Express Slot Capability # INFO: 48738 ns Power Controller: Not Present # INFO: 48738 ns MRL Sensor: Not Present # INFO: 48738 ns Attention Indicator: Not Present # INFO: 48738 ns Power Indicator: Not Present # INFO: 48738 ns Hot-Plug Surprise: Not Supported # INFO: 48738 ns Hot-Plug Capable: Not Supported # INFO: 48738 ns Slot Power Limit Value: 0 # INFO: 48738 ns Slot Power Limit Scale: 0 # INFO: 48738 ns Physical Slot Number: 0 # INFO: 48738 ns Activity_toggle flag is set # INFO: 48802 ns RP PCI Express Link Status Register (0081): # INFO: 48802 ns RP PCI Express Max Link Speed (0002): # INFO: 48802 ns RP PCI Express Current Link Speed (0001): # INFO: 48802 ns Negotiated Link Width: x8 # INFO: 48802 ns Slot Clock Config: Local Clock Used # INFO: 48834 ns Current Link Speed: 2.5GT/s # INFO: 48889 ns RP LTSSM State: RECOVERY.RCVRLOCK # INFO: 49669 ns EP LTSSM State: RECOVERY.RCVRLOCK # INFO: 50501 ns EP LTSSM State: RECOVERY.RCVRCFG # INFO: 51209 ns RP LTSSM State: RECOVERY.RCVRCFG # INFO: 48889 ns RP LTSSM State: RECOVERY.RCVRLOCK # INFO: 53669 ns EP LTSSM State: RECOVERY.SPEED # INFO: 54721 ns RP LTSSM State: RECOVERY.RCVRLOCK # INFO: 54746 ns Wait for Link to enter L0 after negotiated to # the expected speed of EP Target Link Speed 0002): # INFO: 53337 ns RP LTSSM State: RECOVERY.SPEED # INFO: 55235 ns EP LTSSM State: RECOVERY.RCVRLOCK # INFO: 56299 ns EP LTSSM State: RECOVERY.RCVRCFG # INFO: 57163 ns RP LTSSM State: RECOVERY.RCVRCFG # INFO: 57707 ns RP LTSSM State: RECOVERY.IDLE # INFO: 57979 ns EP LTSSM State: RECOVERY.IDLE # INFO: 58035 ns RP LTSSM State: L0 # INFO: 58075 ns EP LTSSM State: L0 # INFO: 58090 ns New Link Speed: 5.0GT/s # INFO: 58106 ns RP PCI Express Link Control Register (0000): # INFO: 58106 ns Common Clock Config: Local Clock # INFO: 70602 ns Completed configuration of Endpoint BARs. # INFO: 70602 ns TASK:my_test Setup # INFO: 70602 ns TASK:my_test Write to 32bit register at # addr = 0x0 with wdata=0xBABEFACE # INFO: 70610 ns TASK:my_test Read from 32bit register at # addr 0x00000000 # INFO: 71298 ns TASK:my_test Register compare matches! # INFO: 71298 ns TASK:my_test Write to 32bit register at # 0x00000004 Actual 0x12345678 # INFO: 71306 ns TASK:my_test => 1.22 Read from 32bit register # at addr = 0x00000004 # INFO: 71994 ns TASK:my_test => 1.23 Register compare matches! # INFO 71994 ns TASK:my_test => 2.11 Fill write memory with # QWORD_INC pattern # INFO: 71994 ns TASK:my_test Memory write burst at addr=0x00 # with wdata=0x10203040 # INFO: 72002 ns TASK:my_test => 2.21 Memory Read burst # INFO: 72690 ns TASK:my_test Memory write burst at addr=0x04 # with wdata=0x10203040 # INFO: 72698 ns TASK:my_test Memory Read burst

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Getting Started with the Configuration Space Bypass Mode Qsys Example Design

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Partial Transcript for Configuration Space Bypass Simulation

# INFO: 73354 ns TASK:my_test Memory write burst at addr=0x08 # with wdata=0x10203040 # INFO: 73362 ns TASK:my_test => 2.21 Memory Read burst # INFO: 74178 ns TASK:my_test Memory write burst at addr=0x0C # with wdata=0x10203040 # INFO: 88154 ns Enumerate EP function = 0x01 # INFO: 88154 ns cfgbp_enum_config_space Setup config space # for func = 00000001 # INFO: 88154 ns Config Read # INFO: 88946 ns CfgRD at # addr =0x00000000 returns data = 0xE0011172 # INFO: 88946 ns Set Bus_Master and Memory_Space_Enable # bit in Command register00000001 # INFO: 88946 ns Read Modified WRite to config register # = 0x00000004 in func = 0x00000001 # INFO: 115370 ns TASK:my_test; 2.21 Memory Read burst # SUCCESS: Simulation stopped due to successful completion! # Break in Function ebfm_log_stop_sim at # /..//top_tb/simulation/submodules//altpcietb_bfm_log.v line 78 # INFO: 88946 ns Set Bus_Master and Memory_Space_Enable bit # in Command register00000001 # INFO: 88946 ns Read Modified WRite to config register = # 0x00000004 in func = 0x00000001 # INFO: 88946 ns Set Bus_Master and Memory_Space_Enable bit # in Command register00000001 # INFO: 88946 ns Read config reg # INFO: 89738 ns Original config read data = 00000000 # INFO: 89738 ns Config write with data = 00000006 # INFO: 91338 ns After cfg_rd_modified_wr, config_data # = 0x00000006 # INFO: 92938 ns CfgRD at BAR0 (addr =0x00000010) returns # data = 0xFFF0000C # INFO: 94530 ns CfgRD at addr =0x00000010 returns data # = 0x8000000C # INFO: 97658 ns BAR Address Assignments: # INFO: 97658 ns BAR Size Assigned Address Type # INFO: 97658 ns BAR1:0 1 MBytes 00000001 00000000 Prefetchable # INFO: 97658 ns BAR2 Disabled # INFO: 97658 ns BAR3 Disabled # INFO: 97658 ns BAR4 Disabled # INFO: 97658 ns BAR5 Disabled # INFO: 97658 ns ExpROM Disabled # INFO: 98794 ns Completed configuration of Endpoint BARs. # INFO: 98794 ns TASK:my_test Setup # INFO: 98794 ns TASK:my_test Write to 32bit register at 0x000000 # with wdata=0xBABEFACE # INFO: 98802 ns TASK:my_test 1.12 Read from 32bit register # at addr = 0x00000000 # INFO: 9490 ns TASK:my_test 1.13 Register compare matches! # INFO: 115370 ns TASK:my_test 2.21 Memory Read burst # SUCCESS: Simulation stopped due to successful completion! # Break in Function ebfm_log_stop_sim at # ./..//top_tb/simulation/submodules//altpcietb_bfm_log.v # line 78

3-13

Getting Started with the Configuration Space Bypass Mode Qsys Example Design

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Parameter Settings

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System Settings

Table 4-1: System Settings for PCI Express

Parameter Value Description

Number of Lanes ×1, ×2, ×4, ×8 Specifies the maximum number of lanes supported.

Lane Rate Gen1 (2.5 Gbps)

Gen2 (2.5/5.0 Gbps)

Gen3 (2.5/5.0/8.0

Gbps)

Port type Native Endpoint

Root Port

Legacy Endpoint

Specifies the maximum data rate at which the link can operate.

Specifies the port type. Altera recommends Native Endpoint for all new Endpoint designs. Select Legacy Endpoint only when you require I/O transaction support for compatibility. The Legacy Endpoint is not available for the Avalon-MM Arria V GZ Hard IP for PCI Express.

The Endpoint stores parameters in the Type 0 Configuration Space. The Root Port stores parameters in the Type 1 Configu‐ ration Space.

PCI Express Base Specification

2.1

3.0

Select either the 2.1 or 3.0 specification.

version

Application Interface

Avalon-ST 64-bit

Avalon-ST 128-bit

Specifies the width of the Avalon-ST interface. By doubling the interface width allows you to run your Application Layer at half the frequency.

Avalon-ST 256-bit

ISO 9001:2008 Registered

4-2

System Settings

Parameter Value Description

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RX Buffer credit allocation performance for received requests

Minimum

Low

Balanced

High

Maximum

Determines the allocation of posted header credits, posted data credits, non-posted header credits, completion header credits, and completion data credits in the 16 KByte RX buffer. The 5 settings allow you to adjust the credit allocation to optimize your system. The credit allocation for the selected setting displays in the message pane.

Refer to the Throughput Optimization chapter for more information about optimizing performance. The Flow Control chapter explains how the RX credit allocation and the

Maximum payload RX Buffer credit allocation and the Maximum payload size that you choose affect the allocation of flow control credits. You can set the Maximum payload size parameter on the Device tab.

The Message window dynamically updates the number of credits for Posted, Non-Posted Headers and Data, and Completion Headers and Data as you change this selection.

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Parameter Value Description

• Minimum—configures the minimum PCIe specification

allowed for non-posted and posted request credits, leaving most of the RX Buffer space for received completion header and data. Select this option for variations where application logic generates many read requests and only infrequently receives single requests from the PCIe link.

• Low—configures a slightly larger amount of RX Buffer

space for non-posted and posted request credits, but still dedicates most of the space for received completion header and data. Select this option for variations where application logic generates many read requests and infrequently receives small bursts of requests from the PCIe link. This option is recommended for typical endpoint applications where most of the PCIe traffic is generated by a DMA engine that is located in the endpoint application layer logic.

• Balanced—configures approximately half the RX Buffer

space to received requests and the other half of the RX Buffer space to received completions. Select this option for variations where the received requests and received completions are roughly equal.

• High—configures most of the RX Buffer space for received

requests and allocates a slightly larger than minimum amount of space for received completions. Select this option where most of the PCIe requests are generated by the other end of the PCIe link and the local application layer logic only infrequently generates a small burst of read requests. This option is recommended for typical root port applications where most of the PCIe traffic is generated by DMA engines located in the endpoints.

• Maximum—configures the minimum PCIe specification

allowed amount of completion space, leaving most of the RX Buffer space for received requests. Select this option when most of the PCIe requests are generated by the other end of the PCIe link and the local application layer logic never or only infrequently generates single read requests. This option is recommended for control and status endpoint applications that don't generate any PCIe requests of their own and only are the target of write and read requests from the root complex.

System Settings

4-3

Parameter Settings

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4-4

System Settings

Parameter Value Description

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Reference clock frequency

Use 62.5 MHz application clock

Use deprecated RX Avalon-ST data byte enable port (rx_st_be)

100 MHz 125 MHz

The PCI Express Base Specification 3.0 requires a 100 MHz ±300 ppm reference clock. The 125 MHz reference clock is provided as a convenience for systems that include a 125 MHz clock source. For more information about Gen3 operation, refer to 4.3.8 Refclk Specifications for 8.0 GT/sin the specification.

For Gen3, Altera recommends using a common reference clock (0 ppm) because when using separate reference clocks (non 0 ppm), the PCS occasionally must insert SKP symbols, potentially causes the PCIe link to go to recovery. Arria V GZ PCIe Hard IP in Gen1 or Gen2 modes are not affected by this issue. Systems using the common reference clock (0 ppm) are not affected by this issue. The primary repercussion of this is a slight decrease in bandwidth. On Gen3 x8 systems, this bandwidth impact is negligible. If non 0 ppm mode is required, so that separate reference clocks are being used, please contact Altera for further information and guidance.

On/Off This mode is only available only for Gen1 ×1.

On/Off This parameter is only available for the Avalon-ST Arria V GZ

Hard IP for PCI Express.

Enable byte parity ports on Avalon-ST interface

Enable multiple packets per cycle

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On/Off When On, the RX and TX datapaths are parity protected.

Parity is odd. This parameter is only available for the Avalon-ST Arria V GZ

Hard IP for PCI Express.

On/Off When On, the 256-bit Avalon-ST interface supports the

transmission of TLPs starting at any 128-bit address boundary, allowing support for multiple packets in a single cycle. To support multiple packets per cycle, the Avalon-ST interface includes 2 start of packet and end of packet signals for the 256-bit Avalon-ST interfaces. This feature is only supported for Gen3 ×8.

For more information refer to Tradeoffs to Consider when

Enabling Multiple Packets per Cycle on page 5-17 and Multiple Packets per Cycle on the Avalon-ST TX 256-Bit Interface on page 5-32.

Parameter Settings

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Base Address Register (BAR) and Expansion ROM Settings

Parameter Value Description

4-5

Enable configu‐ ration via PCI Express (CvP)

Enable credit consumed selection port tx_ cons_cred_sel

Enable Configu‐ ration bypass (CfgBP)

Enable Hard IP Reconfiguration

On/Off When On, the Quartus II software places the Endpoint in the

location required for configuration via protocol (CvP). For more information about CvP, click the Configuration via Protocol (CvP) link below. CvP is not supported for Gen3 variants.

On/Off When you turn on this option, the core includes the tx_cons_

cred_sel port. This parameter does not apply to the Avalon-

MM interface.

On/Off When On, the Arria V GZ Hard IP for PCI Express bypasses

the Transaction Layer Configuration Space registers included as part of the Hard IP, allowing you to substitute a custom Configuration Space implemented in soft logic.

This parameter is not available for the Avalon-MM IP Cores.

On/Off When On, you can use the Hard IP reconfiguration bus to

dynamically reconfigure Hard IP read-only registers. For more information refer to Hard IP Reconfiguration Interface. This parameter is not available for the Avalon-MM IP Cores.

Enable Hard IP completion tag checking

On/Off

When enabled, the Hard IP can use 32 or 64 tags for completions and validates completion tags. When disabled, the Hard IP can use up to 256 tags. The Application Layer logic must validate completion tags.

Enable Hard IP reset pulse at power-up when using the soft reset controller

On/Off

When On, the soft reset controller generates a pulse at power up to reset the Hard IP. This pulse ensures that the Hard IP is reset after programming the device, regardless of the behavior of the dedicated PCI Express reset pin, perstn. This option is available for Gen2 and Gen3 designs that use a soft reset controller.

Related Information

• Throughput Optimization on page 12-1

• Configuration via Protocol (CvP) on page 14-1

• PCI Express Base Specification 2.1 or 3.0

Base Address Register (BAR) and Expansion ROM Settings

The type and size of BARs available depend on port type.

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Base Address Register (BAR) and Expansion ROM Settings

Table 4-2: BAR Registers

Parameter Value Description

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Type Disabled

64-bit prefetchable memory 32-bit non-prefetchable memory 32-bit prefetchable memory I/O address space

If you select 64-bit prefetchable memory, 2 contiguous BARs are combined to form a 64-bit prefetchable BAR; you must set the higher numbered BAR to Disabled. A non-prefetchable 64-bit BAR is not supported because in a typical system, the Root Port Type 1 Configuration Space sets the maximum non-prefetchable memory window to 32 bits. The BARs can also be configured as separate 32-bit memories.

Defining memory as prefetchable allows contiguous data to be fetched ahead. Prefetching memory is advantageous when the requestor may require more data from the same region than was originally requested. If you specify that a memory is prefetch‐ able, it must have the following 2 attributes:

• Reads do not have side effects such as changing the value of the data read

• Write merging is allowed

The 32-bit prefetchable memory and I/O address

space BARs are only available for the Legacy Endpoint.

Size

Expansion ROM

16 Bytes–8 EBytes Supports the following memory sizes:

• 128 bytes–2 GBytes or 8 EBytes: Endpoint and Root Port variants

• 6 bytes–4 KBytes: Legacy Endpoint variants

Disabled–16 MBytes Specifies the size of the optional ROM.

The expansion ROM is only available for the Avalon-ST interface.

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Base and Limit Registers for Root Ports

Table 4-3: Base and Limit Registers

The following table describes the Base and Limit registers which are available in the Type 1 Configuration Space for Root Ports. These registers are used for TLP routing and specify the address ranges assigned to components that are downstream of the Root Port or bridge.

Parameter Value Description

4-7

Input/ Output

16-bit I/O addressing

Disabled

Specifies the address widths for the IO base and IO

limit registers.

32-bit I/O addressing

Prefetchable memory

16-bit memory addressing

Disabled

Specifies the address widths for the Prefetchable

Memory Base register and Prefetchable Memory Limit register.

32-bit memory addressing

Related Information

PCI to PCI Bridge Architecture Specification

Device Identification Registers

Table 4-4: Device ID Registers

The following table lists the default values of the read-only Device ID registers. You can use the parameter editor to change the values of these registers. Refer to Type 0 Configuration Space Registers for the layout of the Device Identification registers.

Vendor ID 16 bits 0x00000000 Sets the read-only value of the Vendor ID register. This

Device ID 16 bits 0x00000001 Sets the read-only value of the Device ID register. This

Revision ID 8 bits 0x00000001 Sets the read-only value of the Revision ID register.

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parameter cannot be set to 0xFFFF, per the PCI Express Specification.

Address offset: 0x000.

Address offset: 0x008.

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4-8

PCI Express and PCI Capabilities Parameters

Class code 24 bits 0x00000000 Sets the read-only value of the Class Code register.

Address offset: 0x008.

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Subsystem Vendor ID

16 bits 0x00000000 Sets the read-only value of the Subsystem Vendor ID

register in the PCI Type 0 Configuration Space. This parameter cannot be set to 0xFFFF per the PCI Express Base Specification. This value is assigned by PCI-SIG to the device manufacturer. This register is only valid in the Type 0 (Endpoint) Configuration Space.

Address offset: 0x02C.

Subsystem Device ID

16 bits 0x00000000 Sets the read-only value of the Subsystem Device ID

At run time, you can change the values of these registers using the optional reconfiguration block signals.

Related Information

• Hard IP Reconfiguration on page 15-1

• PCI Express Base Specification 2.1 or 3.0

PCI Express and PCI Capabilities Parameters

This group of parameters defines various capability properties of the IP core. Some of these parameters are stored in the PCI Configuration Space - PCI Compatible Configuration Space. The byte offset indicates the parameter address.

Device Capabilities

Table 4-5: Capabilities Registers

Parameter Possible Values Default Value Description

Maximum payload size

128 bytes 256 bytes

512 bytes 1024 bytes 2048 bytes

128 bytes Specifies the maximum payload size supported. This

parameter sets the read-only value of the max payload size supported field of the Device Capabilities register (0x084[2:0]). Address: 0x084.

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Parameter Possible Values Default Value Description

Device Capabilities

4-9

Number of Tags supported

Completion timeout range

32 64

ABCD

BCD ABC

B A

None

32 Indicates the number of tags supported for non-posted

requests transmitted by the Application Layer. This parameter sets the values in the Device Control register (0x088) of the PCI Express capability structure described in Table 9–9 on page 9–5.

The Transaction Layer tracks all outstanding completions for non-posted requests made by the Application Layer. This parameter configures the Transaction Layer for the maximum number of Tags supported to track. The Application Layer must set the tag values in all non-posted PCI Express headers to be less than this value. Values greater than 32 also set the extended tag field supported bit in the Configuration Space Device Capabilities register. The Application Layer can only use tag numbers greater than 31 if configuration software sets the Extended Tag Field Enable bit of the Device Control register. This bit is available to the Application Layer on the tl_cfg_ctl output signal as cfg_devcsr[8].

ABCD Indicates device function support for the optional

completion timeout programmability mechanism. This mechanism allows system software to modify the completion timeout value. This field is applicable only to Root Ports and Endpoints that issue requests on their own behalf. Completion timeouts are specified and enabled in the Device Control 2 register (0x0A8) of the PCI Express Capability Structure Version. For all other functions this field is reserved and must be hardwired to 0x0000b. Four time value ranges are defined:

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• Range A: 50 us to 10 ms

• Range B: 10 ms to 250 ms

• Range C: 250 ms to 4 s

• Range D: 4 s to 64 s Bits are set to show timeout value ranges supported. The

function must implement a timeout value in the range 50 s to 50 ms. The following values specify the range:

• None—Completion timeout programming is not supported

• 0001 Range A

• 0010 Range B

• 0011 Ranges A and B

• 0110 Ranges B and C

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4-10

Error Reporting

Parameter Possible Values Default Value Description

• 0111 Ranges A, B, and C

• 1110 Ranges B, C and D

• 1111 Ranges A, B, C, and D

All other values are reserved. Altera recommends that the completion timeout mechanism expire in no less than 10 ms.

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Implement completion timeout disable

On/Off On For Endpoints using PCI Express version 2.1 or 3.0, this

option must be On. The timeout range is selectable. When On, the core supports the completion timeout disable mechanism via the PCI Express Device

Control Register 2. The Application Layer logic must

implement the actual completion timeout mechanism for the required ranges.

Error Reporting

Table 4-6: Error Reporting

Parameter Value Default Value Description

Advanced error reporting (AER)

Enable ECRC checking

On/Off Off When On, enables the Advanced Error Reporting (AER)

capability.

On/Off Off When On, enables ECRC checking. Sets the read-only

value of the ECRC check capable bit in the Advanced

Error Capabilities and Control Register. This

parameter requires you to enable the AER capability.

Enable ECRC generation

Enable ECRC forwarding on the Avalon-ST interface

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On/Off Off

When On, enables ECRC generation capability. Sets the read-only value of the ECRC generation capable bit in the Advanced Error Capabilities and Control

AER capability.

On/Off Off When On, enables ECRC forwarding to the Application

Layer. On the Avalon-ST RX path, the incoming TLP contains the ECRC dword

(1)

and the TD bit is set if an ECRC exists. On the transmit the TLP from the Applica‐ tion Layer must contain the ECRC dword and have the

TD bit set.

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Parameter Value Default Value Description

Link Capabilities

4-11

Track RX completion buffer

On/Off Off When On, the core includes the rxfx_cplbuf_ovf

output status signal to track the RX posted completion buffer overflow status.

overflow on the AvalonST interface

Note:

1. Throughout this user guide, the terms word, dword and qword have the same meaning that they have

in the PCI Express Base Specification. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

Related Information

PCI Express Base Specification Revision 2.1 or 3.0

Link Capabilities

Table 4-7: Link Capabilities

Parameter Value Description

Link port number

0x01 Sets the read-only value of the port number field in the Link

Capabilities register.

Data link layer active reporting

Surprise down reporting

Slot clock configuration

On/Off

Turn On this parameter for a downstream port, if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable downstream port (as indicated by the Hot Plug Capable field of the Slot

Capabilities register), this parameter must be turned On.

For upstream ports and components that do not support this optional capability, turn Off this option. This parameter is only supported for the Arria V GZ Hard IP for PCI Express in Root Port mode.

On/Off

When this option is On, a downstream port supports the optional capability of detecting and reporting the surprise down error condition. This parameter is only supported for the Arria V GZ Hard IP for PCI Express in Root Port mode.

On/Off When On, indicates that the Endpoint or Root Port uses the

same physical reference clock that the system provides on the connector. When Off, the IP core uses an independent clock regardless of the presence of a reference clock on the connector.

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MSI and MSI-X Capabilities

Table 4-8: MSI and MSI-X Capabilities

Parameter Value Description

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MSI messages requested

1, 2, 4, 8, 16, 32 Specifies the number of messages the Application Layer can

request. Sets the value of the Multiple Message Capable field of the Message Control register, 0x050[31:16].

MSI-X Capabilities

Implement MSI-X On/Off When On, enables the MSI-X functionality.

Bit Range

Table size [10:0] System software reads this field to determine the MSI-X Table

size <n>, which is encoded as <n–1>. For example, a returned value of 2047 indicates a table size of 2048. This field is readonly. Legal range is 0–2047 (211).

Address offset: 0x068[26:16]

Table Offset [31:0] Points to the base of the MSI-X Table. The lower 3 bits of the

table BAR indicator (BIR) are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only.

Table BAR Indicator

[2:0] Specifies which one of a function’s BARs, located beginning at

0x10 in Configuration Space, is used to map the MSI-X table into memory space. This field is read-only. Legal range is 0–5.

Pending Bit Array (PBA) Offset

PBA BAR Indicator

Related Information

PCI Express Base Specification Revision 2.1 or 3.0

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[31:0] Used as an offset from the address contained in one of the

function’s Base Address registers to point to the base of the MSI-X PBA. The lower 3 bits of the PBA BIR are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only.

[2:0] Specifies the function Base Address registers, located

beginning at 0x10 in Configuration Space, that maps the MSIX PBA into memory space. This field is read-only. Legal range is 0–5.

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31 19 1 8 17 16 1 5 14

6 5

Physical Slot Number

No Command Completed Support

Electromechanical Interlock Present

Slot Power Limit Scale Slot Power Limit Value

Hot-Plug Capable Hot-Plug Surprise

Power Indicator Present

Attention Indicator Present

MRL Sensor Present

Power Controller Present

Attention Button Present

04 3 2 1

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Slot Capabilities

Table 4-9: Slot Capabilities

Parameter Value Description

Use Slot register On/Off The slot capability is required for Root Ports if a slot is implemented

Slot Capabilities

on the port. Slot status is recorded in the PCI Express Capabili-

ties register. This parameter is only supported in Root Port mode.

Defines the characteristics of the slot. You turn on this option by selecting Enable slot capability. The various bits are defined as follows:

4-13

Slot power scale

0–3

Specifies the scale used for the Slot power limit. The following coefficients are defined:

• 0 = 1.0x

• 1 = 0.1x

• 2 = 0.01x

• 3 = 0.001x The default value prior to hardware and firmware initialization is

b’00. Writes to this register also cause the port to send the Set_

Slot_Power_Limit Message.

Refer to Section 6.9 of the PCI Express Base Specification Revision for more information.

Slot power limit

0–255

In combination with the Slot power scale value, specifies the upper limit in watts on power supplied by the slot. Refer to Section 7.8.9 of the PCI Express Base Specification for more information.

Slot number

Related Information

0-8191

Specifies the slot number.

PCI Express Base Specification Revision 2.1 or 3.0

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Power Management

Table 4-10: Power Management Parameters

Parameter Value Description

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Endpoint L0s acceptable latency

Endpoint L1 acceptable latency

Maximum of 64 ns Maximum of 128 ns Maximum of 256 ns Maximum of 512 ns Maximum of 1 us Maximum of 2 us Maximum of 4 us No limit

Maximum of 1 us Maximum of 2 us Maximum of 4 us Maximum of 8 us Maximum of 16 us Maximum of 32 us No limit

This design parameter specifies the maximum acceptable latency that the device can tolerate to exit the L0s state for any links between the device and the root complex. It sets the read-only value of the Endpoint L0s acceptable latency field of the Device Capabilities Register (0x084).

This Endpoint does not support the L0s or L1 states. However, in a switched system there may be links connected to switches that have L0s and L1 enabled. This parameter is set to allow system configuration software to read the acceptable latencies for all devices in the system and the exit latencies for each link to determine which links can enable Active State Power Management (ASPM). This setting is disabled for Root Ports.

The default value of this parameter is 64 ns. This is the safest setting for most designs.

This value indicates the acceptable latency that an Endpoint can withstand in the transition from the L1 to L0 state. It is an indirect measure of the Endpoint’s internal buffering. It sets the read-only value of the Endpoint L1 acceptable latency field of the Device Capabilities Register.

This Endpoint does not support the L0s or L1 states. However, a switched system may include links connected to switches that have L0s and L1 enabled. This parameter is set to allow system configuration software to read the acceptable latencies for all devices in the system and the exit latencies for each link to determine which links can enable Active State Power Management (ASPM). This setting is disabled for Root Ports.

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The default value of this parameter is 1 µs. This is the safest setting for most designs.

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Vendor Specific Extended Capability (VSEC)

Table 4-11: VSEC

Parameter Value Description

Vendor Specific Extended Capability (VSEC)

4-15

User ID register from the Vendor Sepcific Extended

Custom value

Sets the read-only value of the 16-bit User ID register from the Vendor Specific Extended Capability. This parameter is only valid for Endpoints.

Capability

PHY Characteristics

Table 4-12: PHY Characteristics

Parameter Value Description

Gen2 transmit deemphasis

Use ATX PLL On/Off When enabled, the Hard IP for PCI Express uses the ATX PLL

3.5dB 6dB

Specifies the transmit de-emphasis for Gen2. Altera recommends the following settings:

• 3.5dB: Short PCB traces

• 6.0dB: Long PCB traces.

instead of the CMU PLL Using the ATX PLL instead of the CMU PLL reduces the number of transceiver channels that are necessary for Gen1 and Gen2 variants. This option requires the use of the soft reset controller and does not support the CvP flow. For more information about channel placement, refer to Serial Data Signals on page 5-60.

Enable Common Clock Configura‐ tion (for lower latency)

Parameter Settings

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On/Off When you turn this option on, the Application Layer and

Transaction Layer use a common clock. Using a common clock reduces datapath latency because synchronizers are not necessary.

This parameter is only available for the Avalon-ST interface.

Altera Corporation

2014.12.15

rx_st_data[63:0], [127:0] rx_st_sop rx_st_eop rx_st_empty[1:0] rx_st_ready rx_st_valid rx_st_err rx_st_mask rx_st_bar[7:0] rx_st_be[7:0] rx_bar_dec_func_num[2:0]

Hard IP for PCI Express, Avalon-ST Interface

Test

RX Port

tx_st_data[63:0], [127:0] tx_st_sop tx_st_eop tx_st_ready tx_st_valid tx_st_empty[1:0] tx_st_err

tx_cred_datafccp[11:0] tx_cred_datafcnp[11:0] tx_cred_datafcp[11:0] tx_cred_fchipons[5:0] tx_cred_fcinfinite[5:0] tx_cred_hdrfccp[7:0] tx_cred_hdrfcnp[7:0] tx_cred_hdrfcp[7:0] ko_cpl_spc_header[7:0] ko_cpl_spc_data[11:0]

Clocks

Reset

Power

Managementt

TX Port

Transaction Layer

Configuration

ECC Error

Completion

Interface

LMI

txdata0[7:0]

txdatak0

txdetectrx0

txelecidle0

txcompl0

rxpolarity0

powerdown0[1:0]

tx_deemph

rxdata0[7:0]

rxdatak0

rxvalid0

phystatus0

eidleinferset0[[2:0]

rxelecidle0

rxstatus0[2:0]

sim_ltssmstate[4:0]

sim_pipe_rate[1:0]

sim_pipe_pclk_in

txmargin0[2:0]

txswing0

8-bit PIPE

test_in[31:0]

simu_mode_pipe

lane_act[3:0]

testin_zero

tl_cfg_add[6:0]

tl_cfg_ctl[31:0]

tl_cfg_ctl_wr

tl_cfg_sts[122:0]

tl_cfg_sts_wr

tl_hpg_ctrler[4:0]

lmi_dout[31:0]

lmi_rden lmi_wren

lmi_ack

lmi_addr[14:0]

lmi_din[31:0]

reconfig_fromxcvr[(<n>70-1):0]

reconfig_toxcvr[(<n>46-1):0]

Transceiver

Reconfiguration

for internal PHY

x number of lanes

tx_out0

rx_in0

Serial IF to PIPE

Avalon-ST

Component

Specific

Component

Specific

Credit

derr_cor_ext_rcv0 derr_rpl derr_cor_ext_rpl0

Interrupts (Root Port)

int_status[3:0] aer_msi_num[4:0] pex_msi_num[4:0] serr_out

cpl_err[6:0] cpl_pending cpl_err_func[2:0]

Interrupt (Endpoint)

app_msi_req app_msi_ack app_msi_tc[2:0] app_msi_num[4:0] app_msi_func[2:0] app_int_sts_vec[7:0]

pme_to_cr pme_to_sr

pm_event

pm_event_func[2:0]

pm_data[9:0]

pm_auxpwr

refclk pld_clk coreclkout

npor reset_status pin_perstn

sedes_pll_locked pld_core_ready pld_clk_inuse dlup dlup_exit ev128ns ev1us hotrst_exit l2_exit current_speed[1:0] ltssm[4:0]

Lock Status

PIPE

Interface

for Simulation

and Hardware

Debug Using dl_ltssm[4:0] in SignalTap

Hard IP Reconfiguration (Optional)

hip_reconfig_clk

hip_reconfig_rst_n

hip_reconfig_address[9:0]

hip_reconfig_read

hip_reconfig_readdata[15:0]

hip_reconfig_write

hip_reconfig_writedata[15:0]

hip_reconfig_byte_en[1:0]

ser_shift_load

interface_sel

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Interfaces and Signal Descriptions

UG-01127_avst

Figure 5-1: Avalon-ST Hard IP for PCI Express Top-Level Signals

Send Feedback

ISO 9001:2008 Registered

5-2

Avalon‑ST RX Interface

The following table describes the signals that comprise the Avalon-ST RX Datapath. The RX data signal can be 64, 128, or 256 bits.

Table 5-1: 64-, 128-, or 256‑Bit Avalon-ST RX Datapath

Signal Direction Description

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rx_st_data[<n>-1:0]

Output Receive data bus. Refer to figures following this table for the

mapping of the Transaction Layer’s TLP information to rx_st_

data and examples of the timing of this interface. Note that the

position of the first payload dword depends on whether the TLP address is qword aligned. The mapping of message TLPs is the same as the mapping of TLPs with 4-dword headers. When using a 64-bit Avalon-ST bus, the width of rx_st_data is 64. When using a 128-bit Avalon-ST bus, the width of rx_st_data is 128. When using a 256-bit Avalon-ST bus, the width of rx_st_data is 256 bits.

rx_st_sop[<n>-1:0]

Output Indicates that this is the first cycle of the TLP when rx_st_valid

is asserted. When using a 256-bit Avalon-ST bus the following correspondences apply:

When you turn on Enable multiple packets per cycle,

• bit 0 indicates that a TLP begins in rx_st_data[127:0]

• bit 1 indicates that a TLP begins in rx_st_data[255:128] In single packet per cycle mode, this signal is a single bit which

indicates that a TLP begins in this cycle.

rx_st_eop[<n>-1:0] Output Indicates that this is the last cycle of the TLP when rx_st_valid

is asserted.

rx_st_empty[1:0]

Altera Corporation

When using a 256-bit Avalon-ST bus the following correspond‐ ences apply:

When you turn on Enable multiple packets per cycle,

• bit 0 indicates that a TLP ends in rx_st_data[127:0]

• bit 1 indicates that a TLP ends in rx_st_data[255:128] In single packet per cycle mode, this signal is a single bit which

indicates that a TLP ends in this cycle.

Output Indicates the number of empty qwords in rx_st_data. Not used

when rx_st_data is 64 bits. Valid only when rx_st_eop is asserted in 128-bit and 256-bit modes.

Interfaces and Signal Descriptions

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2014.12.15

Avalon‑ST RX Interface

Signal Direction Description

For 128-bit data, only bit 0 applies; this bit indicates whether the upper qword contains data. For 256-bit data single packet per cycle mode, both bits are used to indicate whether 0-3 upper qwords contain data, resulting in the following encodings for the 128-and 256-bit interfaces:

• 128-Bit interface:

• rx_st_empty = 0, rx_st_data[127:0]contains valid data

• rx_st_empty = 1, rx_st_data[63:0] contains valid data

• 256-bit interface: single packet per cycle mode

• rx_st_empt y = 0, rx_st_data[255:0] contains valid data

• rx_st_empty = 1, rx_st_data[191:0] contains valid data

• rx_st_empty = 2, rx_st_data[127:0] contains valid data

• rx_st_empty = 3, rx_st_data[63:0] contains valid data

• For 256-bit data, when you turn on Enable multi ple packets per cycle, the following correspondences apply:

5-3

rx_st_ready

• bit 1 applies to the eop occurring in rx_st_data[255:128]

• bit 0 applies to the eop occurring in rx_st_data[127:0]

• When the TLP ends in the lower 128 bits, the following equations apply:

• rx_st_eop[0]=1 & rx_st_empty[0]=0, rx_st_

data[127:0] contains valid data

• rx_st_eop[0]=1 & rx_st_empty[0]=1, rx_st_

data[63:0] contains valid data, rx_st_data[127:64] is

empty

• When TLP ends in the upper 128bits, the following equations apply:

• rx_st_ eop[1]=1 & rx_st_empty[1]=0, rx_st_

data[255:128] contains valid data

• rx_st_eop[1]=1 & rx_st_empty[1]=1, rx_st_

data[191:128] contains valid data, rx_st_ data[255:192] is empty

Input Indicates that the Application Layer is ready to accept data. The

Application Layer deasserts this signal to throttle the data stream. If rx_st_ready is asserted by the Application Layer on cycle

<n> , then <n + > readyLatency > is a ready cycle, during which the Transaction Layer may assert valid and transfer data.

Interfaces and Signal Descriptions

Send Feedback

The RX interface supports a readyLatency of 2 cycles.

Altera Corporation

5-4

Avalon‑ST RX Component Specific Signals

Signal Direction Description

rx_st_valid Output Clocks rx_st_data into the Application Layer. Deasserts within

2 clocks of rx_st_ready deassertion and reasserts within 2 clocks of rx_st_ready assertion if more data is available to send.

For 256-bit data, when you turn on Enable multiple packets per cycle, bit 0 applies to the entire bus rx_st_data[255:0]. Bit 1 is not used.

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rx_st_err[<n>-1:0]

Output Indicates that there is an uncorrectable error correction coding

(ECC) error in the internal RX buffer. Active when ECC is enabled. ECC is automatically enabled by the Quartus II assembler. ECC corrects single-bit errors and detects double-bit errors on a per byte basis.

When an uncorrectable ECC error is detected, rx_st_err is asserted for at least 1 cycle while rx_st_valid is asserted.

For 256-bit data, when you turn on Enable multiple packets per cycle, bit 0 applies to the entire bus rx_st_data[255:0]. Bit 1 is not used.

Altera recommends resetting the Arria V GZ Hard IP for PCI Express when an uncorrectable double-bit ECC error is detected.

Related Information

Avalon Interface Specifications.

Avalon‑ST RX Component Specific Signals

Table 5-2: Avalon-ST RX Component Specific Signals

rx_st_mask Input

Altera Corporation

Signal Direction Description

The Application Layer asserts this signal to tell the Hard IP to stop sending non-posted requests. This signal can be asserted at any time. The total number of non-posted requests that can be transferred to the Application Layer after rx_st_mask is asserted is not more than 10.

Interfaces and Signal Descriptions

Send Feedback

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2014.12.15

rx_st_bar[7:0] Output The decoded BAR bits for the TLP. Valid for MRd, MWr, IOWR, and

Avalon‑ST RX Component Specific Signals

Signal Direction Description

IORD TLPs. Ignored for the completion or message TLPs. Valid

during the cycle in which rx_st_sop is asserted. Refer to 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-

Dword Header TLPs with Non-Qword Addresses and 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Qword Aligned Addresses for the timing of this signal

for 64- and 128-bit data, respectively. The following encodings are defined for Endpoints:

• Bit 0: BAR 0

• Bit 1: BAR 1

• Bit 2: Bar 2

• Bit 3: Bar 3

• Bit 4: Bar 4

• Bit 5: Bar 5

• Bit 6: Expansion ROM

• Bit 7: Reserved

5-5

The following encodings are defined for Root Ports:

• Bit 0: BAR 0

• Bit 1: BAR 1

• Bit 2: Primary Bus number

• Bit 3: Secondary Bus number

• Bit 4: Secondary Bus number to Subordinate Bus number window

• Bit 5: I/O window

• Bit 6: Non-Prefetchable window

• Bit 7: Prefetchable window

Interfaces and Signal Descriptions

Send Feedback

Altera Corporation

5-6

Avalon‑ST RX Component Specific Signals

Signal Direction Description

rx_st_be[<n>-1:0] Output Byte enables corresponding to the rx_st_data. The byte enable

signals only apply to PCI Express Memory Write and I/O Write TLP payload fields. When using 64-bit Avalon-ST bus, the width of rx_st_be is 8 bits. When using 128-bit Avalon-ST bus, the width of rx_st_be is 16 bits. This signal is optional. You can derive the same information by decoding the FBE and LBE fields in the TLP header. The byte enable bits correspond to data bytes as follows:

• rx_st_data[127:120] = rx_st_be[15]

• rx_st_data[119:112] = rx_st_be[14]

• rx_st_data[111:104] = rx_st_be[13]

• rx_st_data[95:88] = rx_st_be[12]

• rx_st_data[87:80] = rx_st_be[11]

• rx_st_data[79:72] = rx_st_be[10]

• rx_st_data[71:64] = rx_st_be[9]

• rx_st_data[7:0] = rx_st_be[8]

• rx_st_data[63:56] = rx_st_be[7]

• rx_st_data[55:48] = rx_st_be[6]

• rx_st_data[47:40] = rx_st_be[5]

• rx_st_data[39:32] = rx_st_be[4]

• rx_st_data[31:24] = rx_st_be[3]

• rx_st_data[23:16] = rx_st_be[2]

• rx_st_data[15:8] = rx_st_be[1]

• rx_st_data[7:0] = rx_st_be[0]

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rx_st_parity[<n>-1:0]

rxfc_cplbuf_ovf] Output

For more information about the Avalon-ST protocol, refer to the Avalon Interface Specifications.

Related Information

Avalon Interface Specifications.

Altera Corporation

Output

This signal is deprecated.

The IP core generates byte parity when you turn on Enable byte parity ports on Avalon-ST interface on the System Settings tab of the parameter editor. Each bit represents odd parity of the associated byte of the rx_st_datarx_st_data bus. For example, bit[0] corresponds to rx_st_data[7:0] rx_st_data[7:0], bit[1] corresponds to rx_st_data[15:8].

When asserted indicates that the RX buffer has overflowed.

Interfaces and Signal Descriptions

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. . .

0x0

0x8

0x10

0x18

Header Addr = 0x4

64 bits

PCB Memory

Valid Data

UG-01127_avst

2014.12.15

Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface

To facilitate the interface to 64-bit memories, the Arria V GZ Hard IP for PCI Express aligns data to the qword or 64 bits by default. Consequently, if the header presents an address that is not qword aligned, the Hard IP block shifts the data within the qword to achieve the correct alignment.

Qword alignment applies to all types of request TLPs with data, including the following TLPs:

• Memory writes

• Configuration writes

• I/O writes The alignment of the request TLP depends on bit 2 of the request address. For completion TLPs with data,

alignment depends on bit 2 of the lower address field. This bit is always 0 (aligned to qword boundary) for completion with data TLPs that are for configuration read or I/O read requests.

Figure 5-2: Qword Alignment

The following figure shows how an address that is not qword aligned, 0x4, is stored in memory. The byte enables only qualify data that is being written. This means that the byte enables are undefined for 0x0– 0x3. This example corresponds to 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Non-Qword Aligned Address.

5-7

The following table shows the byte ordering for header and data packets.

Table 5-3: Mapping Avalon-ST Packets to PCI Express TLPs

Packet TLP

Header0 pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3

Header1 pcie_hdr _byte4, pcie_hdr _byte5, pcie_hdr byte6, pcie_hdr _byte7

Header2 pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11

Header3 pcie_hdr _byte12, pcie_hdr _byte13, header_byte14, pcie_hdr _byte15

Data0 pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0

Interfaces and Signal Descriptions

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Altera Corporation

pld_clk

rx_st_data[63:32]

rx_st_data[31:0]

rx_st_sop

rx_st_eop

rx_st_be[7:4]

rx_st_be[3:0]

Header1 Data0 Data2

Header0 Header2 Data1

F F

5-8

Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface

Packet TLP

Data1 pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4

Data2 pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8

Data<n> pcie_data_byte<4n+3>, pcie_data_byte<4n+2>, pcie_data_byte<4n+1>, pcie_data_

byte<n>

The following figure illustrates the mapping of Avalon-ST RX packets to PCI Express TLPs for a three dword header with non-qword aligned addresses with a 64-bit bus. In this example, the byte address is unaligned and ends with 0x4, causing the first data to correspond to rx_st_data[63:32] .

Note: The Avalon-ST protocol, as defined in Avalon Interface Specifications, is big endian, while the Hard

IP for PCI Express packs symbols into words in little endian format. Consequently, you cannot use the standard data format adapters available in Qsys.

Figure 5-3: 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Non-Qword Aligned Address

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Altera Corporation

The following figure illustrates the mapping of Avalon-ST RX packets to PCI Express TLPs for a three dword header with qword aligned addresses. Note that the byte enables indicate the first byte of data is not valid and the last dword of data has a single valid byte.

Interfaces and Signal Descriptions

Send Feedback

clk

rx_st_data[63:32]

rx_st_data[31:0]

rx_st_sop

rx_st_eop rx_st_be[7:4] rx_st_be[3:0]

Header 1 Data1 Data3 Header 0 Header2 Data0 Data2

F 1

pld_clk

rx_st_data[63:32]

rx_st_data[31:0]

rx_st_sop

rx_st_eop

rx_st_be[7:4]

rx_st_be[3:0]

header1 header3 data1

header0 header2 data0

UG-01127_avst

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Figure 5-4: 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Qword Aligned Address

Figure 5-5: 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-Dword Header TLPs with Qword Aligned Addresses

Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface

In the following figure, rx_st_be[7:4] corresponds to rx_st_data[63:32]. rx_st_be[3:0] corresponds to rx_st_data[31:0].

The following figure shows the mapping of Avalon-ST RX packets to PCI Express TLPs for TLPs for a four dword header with qword aligned addresses with a 64-bit bus.

5-9

Interfaces and Signal Descriptions

Send Feedback

Altera Corporation

pld_clk

rx_st_data[63:32]

rx_st_data[31:0]

rx_st_sop

rx_st_eop

rx_st_bardec[7:0]

rx_st_be[7:4]

rx_st_be[3:0]

header1 header3 data0 data2

header0 header2 data1

C F

pld_clk

rx_st_data[63:0]

rx_st_sop

rx_st_eop

rx_st_ready

rx_st_valid

000.010

CCCC0002CCCC0001 CC

5-10

Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface

Figure 5-6: 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-Dword Header TLPs with NonQword Addresses

The following figure shows the mapping of Avalon-ST RX packet to PCI Express TLPs for TLPs for a four dword header with non-qword addresses with a 64-bit bus. Note that the address of the first dword is 0x4. The address of the first enabled byte is 0xC. This example shows one valid word in the first dword, as indicated by the rx_st_be signal. rx_st_be[7:4] corresponds to rx_st_data[63:32]. rx_st_be[3:0] corresponds to rx_st_data[31:0].

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Figure 5-7: 64-Bit Application Layer Backpressures Transaction Layer

The following figure illustrates the timing of the RX interface when the Application Layer backpressures the Arria V GZ Hard IP for PCI Express by deasserting rx _st_ready. The rx_st_valid signal deasserts within three cycles after rx_st_ready is deasserted. In this example, rx_st_valid is deasserted in the next cycle. rx_st_data is held until the Application Layer is able to accept it.

Altera Corporation

Interfaces and Signal Descriptions

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pld_clk

rx_st_data[63:0]

rx_st_sop

rx_st_eop

rx_st_ready

rx_st_valid

C. C. C. C. CCCC0089002... C. C. C. C. C. C. C.

C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C C

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Figure 5-8: 4-Bit Avalon-ST Interface Back-to-Back Transmission

Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface

5-11

The following figure illustrates back-to-back transmission on the 64-bit Avalon-ST RX interface with no idle cycles between the assertion of rx_st_eop and rx_st_sop.

Related Information

• Transaction Layer Packet (TLP) Header Formats on page 19-1

• Avalon Interface Specifications

Interfaces and Signal Descriptions

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Altera Corporation

pld_clk

rx_st_valid

rx_st_data[127:96]

rx_st_data[95:64]

rx_st_data[63:32]

rx_st_data[31:0]

rx_st_bardec[7:0]

rx_st_sop

rx_st_eop

rx_st_empty

data3

header2 data2

header1 data1 data<n>

header0 data0 data<n-1>

5-12

Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface

Figure 5-9: 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Qword Aligned Addresses

The following figure shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs for TLPs with a three dword header and qword aligned addresses. The assertion of rx_st_empty in a rx_st_eop cycle, indicates valid data on the lower 64 bits of rx_st _data.

UG-01127_avst

2014.12.15

Altera Corporation

Interfaces and Signal Descriptions

Send Feedback

rx_st_valid

rx_st_data[127:96]

rx_st_data[95:64] rx_st_data[63:32]

rx_st_data[31:0]

rx_st_sop

rx_st_eop

rx_st_empty

Data0

Data 4

Header 2

Data 3 Header 1 Data 2 Data (n) Header 0 Data 1 Data (n-1)

pld_clk

rx_st_valid

rx_st_data[127:96]

rx_st_data[95:64] rx_st_data[63:32]

rx_st_data[31:0]

rx_st_sop

rx_st_eop

rx_st_empty

Header 3 Data 2 Header 2 Data 1

Data n

Header 1 Data 0

Data n-1

Header 0

Data n-2

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Figure 5-10: 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with nonQword Aligned Addresses

Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface

5-13

The following figure shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs for TLPs with a 3 dword header and non-qword aligned addresses. In this case, bits[127:96] represent Data0 because address[2] in the TLP header is set. The assertion of rx_st_empty in a rx_st_eop cycle indicates valid data on the lower 64 bits of rx_st_data.

Figure 5-11: 128-Bit Avalon-ST rx_st_data Cycle Definition for 4-Dword Header TLPs with non-Qword Aligned Addresses

The following figure shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs for a four dword header with non-qword aligned addresses. In this example, rx_st_empty is low because the data is valid for all 128 bits in the rx_st_eop cycle.

Interfaces and Signal Descriptions

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Altera Corporation

pld_clk

rx_st_valid

rx_st_data[127:96]

rx_st_data[95:64] rx_st_data[63:32]

rx_st_data[31:0]

rx_st_sop

rx_st_eop

rx_st_empty

Header3 Data3 Data n Header 2 Data 2 Data n-1 Header 1 Data 1 Data n-2 Header 0 Data 0 Data n-3

pld_clk

rx_st_data[127:0]

rx_st_sop

rx_st_eop

rx_st_empty

rx_st_ready

rx_st_valid

4562 . . . c19a . . . 0217b . . . 134c . . . 8945 . . .3458ce. . . 2457ce. . .000a7896c000bc34...

5-14

Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface

Figure 5-12: 128-Bit Avalon-ST rx_st_data Cycle Definition for 4-Dword Header TLPs with Qword Aligned Addresses

The following figure shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs for a four dword header with qword aligned addresses. In this example, rx_st_empty is low because data is valid for all 128-bits in the rx_st_eop cycle.

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Figure 5-13: 128-Bit Application Layer Backpressures Hard IP Transaction Layer for RX Transactions

The following figure illustrates the timing of the RX interface when the Application Layer backpressures the Hard IP by deasserting rx_st_ready. The rx_st_valid signal deasserts within three cycles after

rx_st_ready is deasserted. In this example, rx_st_valid is deasserted in the next cycle. rx_st_data is

held until the Application Layer is able to accept it.

The following figure illustrates back-to-back transmission on the 128-bit Avalon-ST RX interface with no idle cycles between the assertion of rx_st_eop and rx_st_sop.

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Interfaces and Signal Descriptions

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pld_clk

rx_st_data[127:0]

rx_st_sop

rx_st_eop

rx_st_empty

rx_st_ready

rx_st_valid

rx_st_err

BB ... BB ... BB ... BB ... BB ... BB ... BB ... BB ... BB ... BB ... BB ... BB ... ...BB

pld_clk

rx_st_data[127:0]

rx_st_sop

rx_st_eop

rx_st_empty

rx_st_ready

rx_st_valid

0000090 1C0020000F0000000100004 450AC89000012FE0D10004

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Figure 5-14: 128-Bit Avalon-ST Interface Back-to-Back Transmission

Single Packet Per Cycle

5-15

The following figure illustrates back-to-back transmission on the 128-bit Avalon-ST RX interface with no idle cycles between the assertion of rx_st_eop and rx_st_sop.

Figure 5-15: 128-Bit Packet Examples of rx_st_empty and Single-Cycle Packet

The following figure illustrates a two-cycle packet with valid data in the lower qword (rx_st_data[63:0]) and a one-cycle packet where the rx_st_sop and rx_st_eop occur in the same cycle.

For a complete description of the TLP packet header formats, refer to Appendix A, Transaction Layer Packet (TLP) Header Formats.

Interfaces and Signal Descriptions

Single Packet Per Cycle

In single packer per cycle mode, all received TLPs start at the lower 128-bit boundary on a 256-bit Avalon-ST interface. Turn on Enable Multiple Packets per Cycle on the System Settings tab of the parameter editor to change multiple packets per cycle.

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255

4DW header, Aligned data

4DW header, Unaligned data

3DW header, Aligned data

3DW header, Unaligned data

pld_clk

rx_st_data[255:0]

rx_st_sop

rx_st_eop

rx_st_empty[1:0]

rx_st_ready

rx_st_valid

XX..BE ...

1 0 2

XXXXXXXXXXXXXXXX. . . 4592001487DF08876210...

5-16

Data Alignment and Timing for 256‑Bit Avalon‑ST RX Interface

Single packer per cycle mode requires simpler Application Layer packet decode logic on the TX and RX paths because packets always start in the lower 128-bits of the Avalon-ST interface. However, the Applica‐ tion Layer must still track Completion Credits to avoid RX buffer overflow. To track Completion Credits, use the following signals to monitor the completion space available and to ensure enough space is available before transmitting Non-Posted requests.

• ko_cpl_spc_header

• ko_cpl_spc_data

Data Alignment and Timing for 256‑Bit Avalon‑ST RX Interface

Figure 5-16: Location of Headers and Data for Avalon-ST 256-Bit Interface

The following figure shows the location of headers and data for the 256-bit Avalon-ST packets. This layout of data applies to both the TX and RX buses.

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Figure 5-17: 256-Bit Avalon-ST RX Packets Use of rx_st_empty and Single-Cycle Packets

The following figure illustrates two single-cycle 256-bit packets. The first packet has two empty qword,

rx_st_data[191:0] is valid. The second packet has two empty dwords; rx_st_data[127:0] is valid.

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Tradeoffs to Consider when Enabling Multiple Packets per Cycle

A comparison of the largest and smallest packet sizes illustrates this point. Large packets using the full 256 bits achieve the following throughput:

256/256*8 = 8 GBytes/sec

The smallest PCIe packet, such as a 3-dword memory read, uses 96 bits of the 256-bits bus and achieve the following throughput:

96/256*8 = 3 GBytes/sec

If you enable mMultiple Packets Per Cycle, when a TLP ends in the upper 128 bits of the Avalon-ST bus, a new TLP can start in the lower 128 bits Consequently, the bandwidth of small packets doubles:

96*2/256*8 = 3 GBytes/sec

This mode adds complexity to the Application Layer user decode logic. However, it could result in higher throughput.

5-17

Figure 5-18: 256-Bit Avalon-ST RX Interface with Multiple Packets Per Cycle

The following figure illustrates this mode for a 256-bit Avalon-ST RX interface. In this figure

rx_st_eop[0] and rx_st_sop[1] are asserted in the same cycle.

Interfaces and Signal Descriptions

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rx_st_sop[0]

rx_st_eop[0]

rx_st_sop[1]

rx_st_eop[1]

rx_st_data[255:0]

rx_st_be[31:0]

rx_st_bardec1[7:0]

rx_st_bardec2[7:0]

rx_st_empty[1:0]

rx_st_err

rx_st_mask

rx_st_ready

rx_st_valid

.. 12... 12... 12... 12... 12... 12... 12... 12... 00... 12... 12... 12... 12... 12... 12... 12... 003458

FF...

FFFFFFFF

5-18

Avalon-ST TX Interface

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Avalon-ST TX Interface

The following table describes the signals that comprise the Avalon-ST TX Datapath. The TX data signal can be 64, 128, or 256 bits.

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Interfaces and Signal Descriptions

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Table 5-4: 64-, 128-, or 256‑Bit Avalon-ST TX Datapath

Signal Direction Description

Avalon-ST TX Interface

5-19

tx_st_data[<n>-1:0]

tx_st_sop[<n>-1:0]

Input Data for transmission. Transmit data bus. Refer to the following

sections on data alignment for the 64-, 128-, and 256-bit interfaces for the mapping of TLP packets to tx_st_data and examples of the timing of this interface. When using a 64-bit Avalon-ST bus, the width of tx_st_d ata is 64. When using a 128-bit Avalon-ST bus, the width of tx_st_data is 128 bits. When using a 256-bit Avalon-ST bus, the width of tx_st_data is 256 bits. The Application Layer must provide a properly formatted TLP on the TX interface. The mapping of message TLPs is the same as the mapping of Transaction Layer TLPs with 4 dword headers. The number of data cycles must be correct for the length and address fields in the header. Issuing a packet with an incorrect number of data cycles results in the TX interface hanging and becoming unable to accept further requests.

<n> = 64, 128, or 256.

Input Indicates first cycle of a TLP when asserted together with tx_st_

valid. <n> = 1 or 2.

When using a 256-bit Avalon-ST bus with Multiple packets per cycle, bit 0 indicates that a TLP begins in tx_st_data[127:0], bit 1

indicates that a TLP begins in tx_st_data[255:128].

tx_st_eop[<n>-1:0]

Input Indicates last cycle of a TLP when asserted together with tx_st_

valid. <n> = 1 or 2.

When using a 256-bit Avalon-ST bus with Multiple packets per cycle, bit 0 indicates that a TLP ends with tx_st_data[127:0], bit 1

indicates that a TLP ends with tx_st_data[255:128].

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5-20

Avalon-ST TX Interface

Signal Direction Description

tx_st_ready Output Indicates that the Transaction Layer is ready to accept data for

transmission. The core deasserts this signal to throttle the data stream. tx_st_ready may be asserted during reset. The Applica‐ tion Layer should wait at least 2 clock cycles after the reset is released before issuing packets on the Avalon-ST TX interface. The reset_status signal can also be used to monitor when the IP core has come out of reset.

If tx_st_ready is asserted by the Transaction Layer on cycle <n> , then <n + readyLatency> is a ready cycle, during which the Application Layer may assert valid and transfer data.

When tx_st_ready, tx_st_valid and tx_st_data are registered (the typical case), Altera recommends a readyLa-

tency of 2 cycles to facilitate timing closure; however, a readyLatency of 1 cycle is possible. If no other delays are added

to the read-valid latency, the resulting delay corresponds to a

readyLatency of 2.

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tx_st_valid

tx_st_empty[1:0]

Input Clocks tx_st_data to the core when tx_st_ready is also

asserted. Between tx_st_sop and tx_st_eop, tx_st_valid must not be deasserted in the middle of a TLP except in response to

tx_st_ready deassertion. When tx_st_ready deasserts, this

signal must deassert within 1 or 2 clock cycles. When tx_st_

ready reasserts, and tx_st_data is in mid-TLP, this signal must

reassert within 2 cycles. The figure entitled64-Bit Transaction Layer Backpressures the Application Layer illustrates the timing of

this signal. For 256-bit data, when you turn on Enable multiple packets per

cycle, the bit 0 applies to the entire bus tx_st_data[255:0]. Bit 1 is not used.

To facilitate timing closure, Altera recommends that you register both the tx_st_ready and tx_st_valid signals. If no other delays are added to the ready-valid latency, the resulting delay corresponds to a readyLatency of 2.

Input Indicates the number of qwords that are empty during cycles that

contain the end of a packet. When asserted, the empty dwords are in the high-order bits. Valid only when tx_st_eop is asserted.

Not used when tx_st_data is 64 bits. For 128-bit data, only bit 0 applies and indicates whether the upper qword contains data. For 256-bit data, both bits are used to indicate the number of upper

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Interfaces and Signal Descriptions

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Avalon-ST TX Interface

Signal Direction Description

words that contain data, resulting in the following encodings for the 128-and 256-bit interfaces:

128-Bit interface:tx_st_empty = 0, tx_st_data[127:0]contains valid datatx_st_empty = 1, tx_st_data[63:0] contains valid data

256-bit interface:tx_st_empty = 0, tx_st_data[255:0] contains valid datatx_ st_empty = 1, tx_st_data[191:0] contains valid datatx_st_empty = 2, tx_st_data[127:0] contains valid datatx_st_empty = 3, tx_st_data[63:0] contains valid data

For 256-bit data, when you turn on Enable multiple packets per cycle, the following correspondences apply:

• bit 1 applies to the eop occurring in rx_st_data[255:128]

• bit 0 applies to the eop occurring in rx_st_data[127:0] When the TLP ends in the lower 128bits, the following equations

apply:

5-21

• tx_st_eop[0]=1 & tx_st_empty[0]=0, tx_st_

data[127:0] contains valid data

• tx_st_eop[0]=1 & tx_st_empty[0]=1, tx_st_data[63:0] contains valid data, tx_st_data[127:64] is empty

When TLP ends in the upper 128bits, the following equations apply:

• tx_st_eop[1]=1 & tx_st_empty[1]=0, tx_st_

data[255:128] contains valid data

• tx_st_eop[1]=1 & tx_st_empty[1]=1, tx_st_

data[191:128] contains valid data, tx_st_data[255:192] is

empty

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Avalon-ST TX Interface

Signal Direction Description

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tx_st_err

tx_st_parity[<n>-1:0]

Input Indicates an error on transmitted TLP. This signal is used to

nullify a packet. It should only be applied to posted and completion TLPs with payload. To nullify a packet, assert this signal for 1 cycle after the SOP and before the EOP. When a packet is nullified, the following packet should not be transmitted until the next clock cycle. tx_st_err is not available for packets that are 1 or 2 cycles long.

For 256-bit data, when you turn on Enable multiple packets per cycle, bit 0 applies to the entire bus tx_st_data[255:0]. Bit 1 is not used.

Refer to the figure entitled 128-Bit Avalon-ST tx_st_data Cycle

Definition for 3-Dword Header TLP with non-Qword Aligned Address for a timing diagram that illustrates the use of the error

signal. Note that it must be asserted while the valid signal is asserted.

Output Byte parity is generated when you turn on Enable byte parity

ports on Avalon ST interface on the System Settings tab of the parameter editor.Each bit represents odd parity of the associated byte of the tx_st_data bus. For example, bit[0] corresponds to

tx_st_data[7:0], bit[1] corresponds to tx_st_data[15:8],

and so on.

tx_cred_ datafccp[11:0]

tx_cred_ datafcnp[11:0]

tx_cred_datafcp[11:0]

<n> = 8, 16, or 32.

Component Specific Signals

Output Data credit limit for the received FC completions. Each credit is

16 bytes.

Output Data credit limit for the non-posted requests. Each credit is 16

bytes.

Output Data credit limit for the FC posted writes. Each credit is 16 bytes.

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Interfaces and Signal Descriptions

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Avalon-ST TX Interface

Signal Direction Description

5-23

tx_cred_ fchipcons[5:0]

Output Asserted for 1 cycle each time the Hard IP consumes a credit.

These credits are from messages that the Hard IP for PCIe generates for the following reasons:

• To respond to memory read requests

• To send error messages

This signal is not asserted when an Application Layer credit is consumed. The Application Layer must keep track of its own consumed credits. To calculate the total credits consumed, the Application Layer must add its own credits consumed to those consumed by the Hard IP for PCIe. The credit signals are valid after dlup (data link up) is asserted.

The 6 bits of this vector correspond to the following 6 types of credit types:

• [5]: posted headers

• [4]: posted data

• [3]: non-posted header

• [2]: non-posted data

• [1]: completion header

• [0]: completion data

tx_cred_fc_ infinite[5:0]

tx_cred_hdrfccp[7:0]

tx_cred_hdrfcnp[7:0]

tx_cred_hdrfcp[7:0]

During a single cycle, the IP core can consume either a single header credit or both a header and a data credit.

Output When asserted, indicates that the corresponding credit type has

infinite credits available and does not need to calculate credit limits. The 6 bits of this vector correspond to the following 6 types of credit types:

• [5]: posted headers

• [4]: posted data

• [3]: non-posted header

• [2]: non-posted data

• [1]: completion header

• [0]: completion data

Output Header credit limit for the FC completions. Each credit is 20

bytes.

Output Header limit for the non-posted requests. Each credit is 20 bytes.

Output Header credit limit for the FC posted writes. Each credit is 20

bytes.

Interfaces and Signal Descriptions

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5-24

Avalon-ST Packets to PCI Express TLPs

Signal Direction Description

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ko_cpl_spc_ header[7:0]

ko_cpl_spc_data[11:0]

Related Information

Output The Application Layer can use this signal to build circuitry to

• Data Alignment and Timing for the 64-Bit Avalon-ST TX Interface on page 5-25

• Data Alignment and Timing for the 128-Bit Avalon-ST TX Interface on page 5-27

• Data Alignment and Timing for the 256-Bit Avalon-ST TX Interface on page 5-30

Avalon-ST Packets to PCI Express TLPs

The following figures illustrate the mappings between Avalon-ST packets and PCI Express TLPs. These mappings apply to all types of TLPs, including posted, non-posted, and completion TLPs. Message TLPs use the mappings shown for four dword headers. TLP data is always address-aligned on the Avalon-ST interface whether or not the lower dwords of the header contains a valid address, as may be the case with TLP type (message request with data payload).

prevent RX buffer overflow for completion headers. Endpoints must advertise infinite space for completion headers; however, RX buffer space is finite. ko_cpl_spc_header is a static signal that indicates the total number of completion headers that can be stored in the RX buffer.

prevent RX buffer overflow for completion data. Endpoints must advertise infinite space for completion data; however, RX buffer space is finite. ko_cpl_spc_data is a static signal that reflects the total number of 16 byte completion data units that can be stored in the completion RX buffer.

For additional information about TLP packet headers, refer to Appendix A, Transaction Layer Packet (TLP) Header Formats and Section 2.2.1 Common Packet Header Fields in the PCI Express Base Specifica‐ tion .

Related Information

PCI Express Base Specification Revision 2.1 or 3.0

Altera Corporation

Interfaces and Signal Descriptions

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pld_clk

tx_st_data[63:32]

tx_st_data[31:0]

tx_st_sop

tx_st_eop

Header1 Data0 Data2

Header0 Header2 Data1

pld_clk

tx_st_data[63:32]

tx_st_data[31:0]

tx_st_sop

tx_st_eop

Header1 Header3 Data1

Header0 Header2 Data0

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Data Alignment and Timing for the 64‑Bit Avalon‑ST TX Interface

Figure 5-19:

The following figure illustrates the mapping between Avalon-ST TX packets and PCI Express TLPs for three dword header TLPs with non-qword aligned addresses on a 64-bit bus.

Figure 5-20: 64-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with Non-Qword Aligned Address

This figure illustrates the storage of non-qword aligned data.) Non-qword aligned address occur when

address[2] is set. When address[2] is set, tx_st_data[63:32]contains Data0 and tx_st_data[31:0]

contains dword header2. In this figure, the headers are formed by the following bytes:

5-25

H0 ={pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3} H1 = {pcie_hdr_byte4, pcie_hdr _byte5, header pcie_hdr byte6, pcie_hdr _byte7} H2 = {pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11} Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0} Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4} Data2 = {pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8}

The following figure illustrates the mapping between Avalon-ST TX packets and PCI Express TLPs for a four dword header with qword aligned addresses on a 64-bit bus

Figure 5-21: 64-Bit Avalon-ST tx_st_data Cycle Definition for 4-Dword TLP with Qword Aligned Address

In this figure, the headers are formed by the following bytes.

Interfaces and Signal Descriptions

H0 = {pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3} H1 = {pcie_hdr _byte4, pcie_hdr _byte5, pcie_hdr byte6, pcie_hdr _byte7} H2 = {pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11} H3 = pcie_hdr _byte12, pcie_hdr _byte13, header_byte14, pcie_hdr _byte15}, 4 dword header only

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pld_clk

tx_st_data[63:32]

tx_st_data[31:0]

tx_st_sop

tx_st_eop

Header 1 Header3 Data0 Data2 Header 0 Header2 Data1

coreclkout

tx_st_sop

tx_st_eop

tx_st_ready

tx_st_valid

tx_st_err

tx_st_data[63:0] . . . . . . . . . .

readyLatency

00. . 00 ... BB... BB ... BBBB0306BBB0305 BB... BB.. BB ... BB ... BB ... BB ... BB... .

5-26

Data Alignment and Timing for the 64‑Bit Avalon‑ST TX Interface

Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0} Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4}

Figure 5-22: 64-Bit Avalon-ST tx_st_data Cycle Definition for TLP 4-Dword Header with Non-Qword Aligned Address

Figure 5-23: 64-Bit Transaction Layer Backpressures the Application Layer

The following figure illustrates the timing of the TX interface when the Arria V GZ Hard IP for PCI Express pauses transmission by the Application Layer by deasserting tx_st_ready. Because the readyLa-

tency is two cycles, the Application Layer deasserts tx_st_valid after two cycles and holds tx_st_data

until two cycles after tx_st_ready is asserted.

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Interfaces and Signal Descriptions

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coreclkout

tx_st_sop

tx_st_eop

tx_st_ready

tx_st_valid

tx_st_err

tx_st_data[63:0] 01 ... 00 ... BB ... BB ... BB ... BB ... B ... ... BB ... 01 ... 00 ... CC ... CC ... CC ... CC ... CC ... CC ...

Data3 Header2 Data 2 Header1 Data1 Data(n) Header0 Data0 Data(n-1)

pld_clk

tx_st_valid

tx_st_data[127:96]

tx_st_data[95:64] tx_st_data[63:32]

tx_st_data[31:0]

tx_st_sop

tx_st_eop

tx_st_empty

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Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface

Figure 5-24: 64-Bit Back-to-Back Transmission on the TX Interface

The following figure illustrates back-to-back transmission of 64-bit packets with no idle cycles between the assertion of tx_st_eop and tx_st_sop.

Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface

5-27

Figure 5-25: 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with Qword Aligned Address

The following figure shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs for a three dword header with qword aligned addresses. Assertion of tx_st_empty in an rx_st_eop cycle indicates valid data in the lower 64 bits of tx_st_data.

Interfaces and Signal Descriptions

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pld_clk

tx_st_valid

tx_st_data[127:96]

tx_st_data[95:64] tx_st_data[63:32]

tx_st_data[31:0]

tx_st_sop

tx_st_err

tx_st_eop

tx_st_empty

Data0 Data 4

Header 2

Data 3 Header 1 Data 2 Data (n) Header 0 Data 1 Data (n-1)

pld_clk

tx_st_data[127:96]

tx_st_data[95:64] tx_st_data[63:32]

tx_st_data[31:0]

tx_st_sop

tx_st_eop

tx_st_empty

Header 3 Data 3 Header 2 Data 2 Header 1 Data 1 Header 0 Data 0 Data 4

5-28

Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface

Figure 5-26: 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with non-Qword Aligned Address

The following figure shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs for a 3 dword header with non-qword aligned addresses. It also shows tx_st_err assertion.

Figure 5-27: 128-Bit Avalon-ST tx_st_data Cycle Definition for 4-Dword Header TLP with Qword Aligned Address

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Figure 5-28: 128-Bit Avalon-ST tx_st_data Cycle Definition for 4-Dword Header TLP with non-Qword Aligned Address

The following figure shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs for a four dword header TLP with non-qword aligned addresses. In this example, tx_st_empty is low because the data ends in the upper 64 bits of tx_st_data.

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Header 3 Data 2 Header 2 Data 1

Data n

Header 1 Data 0

Data n-1

Header 0

Data n-2

pld_clk

tx_st_valid

tx_st_data[127:96]

tx_st_data[95:64] tx_st_data[63:32]

tx_st_data[31:0]

tx_st_sop

tx_st_eop

tx_st_empty

pld_clk

tx_st_data[127:0]

tx_st_sop

tx_st_eop

tx_st_empty

tx_st_ready

tx_st_valid

tx_st_err

.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Figure 5-29: 128-Bit Back-to-Back Transmission on the Avalon-ST TX Interface

Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface

5-29

The following figure illustrates back-to-back transmission of 128-bit packets with idle dead cycles between the assertion of tx_st_eop and tx_st_sop.

Interfaces and Signal Descriptions

Figure 5-30: 128-Bit Hard IP Backpressures the Application Layer for TX Transactions

The following figure illustrates the timing of the TX interface when the Arria V GZ Hard IP for PCI Express pauses the Application Layer by deasserting tx_st_ready. Because the readyLatency is two cycles, the Application Layer deasserts tx_st_valid after two cycles and holds tx_st_data until two cycles after tx_st_ready is reasserted

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pld_clk

tx_st_data[127:0]

tx_st_sop

tx_st_eop

tx_st_empty

tx_st_ready

tx_st_valid

tx_st_err

000 CC... CC... CC... CC... CC... CC... CC... CC... CC... CC... CC...

5-30

Data Alignment and Timing for the 256‑Bit Avalon‑ST TX Interface

Refer to Figure 8–16 on page 8–15 layout of headers and data for the 256-bit Avalon-ST packets with qword aligned and qword unaligned addresses.

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Single Packet Per Cycle

Single packet per cycle mode requires simpler Application Layer packet decode logic on the TX and RX paths because packets always start in the lower 128-bits of the Avalon-ST interface. Although this mode simplifies the Application Layer logic, failure to use the full 256-bit Avalon-ST may slightly reduce the throughput of a design.

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01 10

clk

tx_st_data[63:0]

Aligned Data Unaligned Data

tx_st_data[127:64]

tx_st_data[191:128]

tx_st_data[255:192]

tx_st_sop

tx_st_eop

tx_st_empty[1:0]

Header 1 Header 0

XXXXXXXX Header 2

XXXXXXXX Data 0

XXXXXXXXX XXXXXXXX

Header 1 Header 0

Data 0 Header 2

XXXXXXXXX XXXXXXXX

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Figure 5-31: 256-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with Qword Addresses

Single Packet Per Cycle

5-31

The following figure illustrates the layout of header and data for a three dword header on a 256-bit bus with aligned and unaligned data.

Single Packet Per Cycle

The following figure illustrates the layout of header and data for a three dword header on a 256-bit bus with aligned and unaligned data.

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01 10

clk

tx_st_data[63:0]

Aligned Data Unaligned Data

tx_st_data[127:64]

tx_st_data[191:128]

tx_st_data[255:192]

tx_st_sop

tx_st_eop

tx_st_empty[1:0]

Header 1 Header 0

XXXXXXXX Header 2

XXXXXXXX Data 0

XXXXXXXXX XXXXXXXX

Header 1 Header 0

Data 0 Header 2

XXXXXXXXX XXXXXXXX

tx_st_sop[0]

tx_st_eop[0]

tx_st_sop[1]

tx_st_eop[1]

tx_st_ready

tx_st_valid

tx_st_data[255:0] 12 ... 12... 12... 12... 12... 12... 12... 12... 00... 5A... 5A... 5A... 5A... 5A... 5A... 5A... 5A...

tx_st_empty[1:0]

5-32

Multiple Packets per Cycle on the Avalon-ST TX 256-Bit Interface

Figure 5-32: 256-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with Qword Addresses

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Multiple Packets per Cycle on the Avalon-ST TX 256-Bit Interface

If you enable Multiple Packets Per Cycle under the Systems Settings heading, a TLP can start on a 128-bit boundary. This mode supports multiple start of packet and end of packet signals in a single cycle when the Avalon-ST interface is 256 bits wide. The following figure illustrates this mode for a 256-bit Avalon-ST TX interface. In this figure tx_st_eop[0] and tx_st_sop[1] are asserted in the same cycle. Using this mode increases the complexity of the Application Layer logic but results in higher throughput, depending on the TX traffic. Refer to Tradeoffs to Consider when Enabling Multiple Packets per Cycle for an example of the bandwidth when Multiple Packets Per Cycle is enabled and disabled.

Figure 5-33: 256-Bit Avalon-ST TX Interface with Multiple Packets Per Cycle

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Related Information

Tradeoffs to Consider when Enabling Multiple Packets per Cycle on page 5-17

Root Port Mode Configuration Requests

If your Application Layer implements ECRC forwarding, it should not apply ECRC forwarding to Configuration Type 0 packets that it issues on the Avalon-ST interface. There should be no ECRC appended to the TLP, and the TD bit in the TLP header should be set to 0. These packets are processed internally by the Hard IP block and are not transmitted on the PCI Express link.

To ensure proper operation when sending Configuration Type 0 transactions in Root Port mode, the application should wait for the Configuration Type 0 transaction to be transferred to the Hard IP for PCI Express Configuration Space before issuing another packet on the Avalon-ST TX port. You can do this by waiting for the core to respond with a completion on the Avalon-ST RX port before issuing the next Configuration Type 0 transaction.

Clock Signals

Table 5-5: Clock Signals

Root Port Mode Configuration Requests

5-33

Signal Direction Description

refclk

pld_clk

coreclkout

Input Reference clock for the IP core. It must have the frequency

specified under the System Settings heading in the parameter editor. This is a dedicated free running input clock to the dedicated REFCLK pin.

If your design meets the following criteria:

• Enables CvP

• Includes an additional transceiver PHY connected to the same Transceiver Reconfiguration Controller

then you must connect refclk to the mgmt_clk_clk signal of the Transceiver Reconfiguration Controller and the additional transceiver PHY. In addition, if your design includes more than one Transceiver Reconfiguration Controller on the same side of the FPGA, they all must share the mgmt_clk_clk signal.

Input Clocks the Application Layer. You can drive this clock with

coreclkout_hip. If you drive pld_clk with another clock

source, it must be equal to or faster than coreclkout_hip.

Output This is a fixed frequency clock used by the Data Link and

Transaction Layers. To meet PCI Express link bandwidth constraints, this clock has minimum frequency requirements as listed in Application Layer Clock Frequency for All Combination

of Link Width, Data Rate and Application Layer Interface Width in the Reset and Clocks chapter .

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Reset, Status, and Link Training Signals

Related Information

Clocks on page 7-5

Reset, Status, and Link Training Signals

Refer to Reset and Clocks for more information about the reset sequence and a block diagram of the reset logic.

Table 5-6: Reset Signals

Signal Direction Description

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npor

reset_status

pin_perst

Input Active low reset signal. In the Altera hardware example designs,

npor is the OR of pin_perst and local_rstn coming from the

software Application Layer. If you do not drive a soft reset signal from the Application Layer, this signal must be derived from

pin_perst. You cannot disable this signal. Resets the entire IP

Core and transceiver. Asynchronous. In systems that use the hard reset controller, this signal is edge,

not level sensitive; consequently, you cannot use a low value on this signal to hold custom logic in reset. For more information about the hard and soft reset controllers, refer to Reset.

Output Active high reset status signal. When asserted, this signal

indicates that the Hard IP clock is in reset. The reset_status signal is synchronous to the pld_clk clock and is deasserted only when the npor is deasserted and the Hard IP for PCI Express is not in reset (reset_status_hip = 0). You should use reset_

status to drive the reset of your application. This reset is used

for the Hard IP for PCI Express IP Core with the Avalon-ST interface.

Input Active low reset from the PCIe reset pin of the device. pin_perst

resets the datapath and control registers. Configuration via Protocol (CvP) requires this signal. For more information about CvP refer to Configuration via Protocol (CvP).

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Arria V GZ V devices can have up to 4 instances of the Hard IP for PCI Express. Each instance has its own pin_perst signal. You

must connect the pin_perst of each Hard IP instance to the corresponding nPERST pin of the device. These pins have the

following locations:

• NPERSTL0: bottom left Hard IP and CvP blocks

• NPERSTL1: top left Hard IP block

• NPERSTR0: bottom right Hard IP block

• NPERSTR1: top right Hard IP block

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npor

IO_POF_Load

PCIe_LinkTraining_Enumeration

dl_ltssm[4:0]

detect

detect.active polling.active

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Reset, Status, and Link Training Signals

Signal Direction Description

For example, if you are using the Hard IP instance in the bottom left corner of the device, you must connect pin_perst to

NPERSL0.

For maximum use of the Arria V GZ V device, Altera recommends that you use the bottom left Hard IP first. This is the only location that supports CvP over a PCIe link. If your design does not require CvP, you may select other Hard IP blocks.

Refer to the appropriate device pinout for correct pin assignment for more detailed information about these pins. The PCI Express Card Electromechanical Specification 2.0 specifies this pin requires 3.3 V. You can drive this 3.3V signal to the nPERST* even if the V

VCCPGM

of the bank is not 3.3V if the following 2

conditions are met:

• The input signal meets the VIH and VIL specification for LVTTL.

• The input signal meets the overshoot specification for 100°C operation as defined in the device handbook.

5-35

Figure 5-34: Reset and Link Training Timing Relationships

The following figure illustrates the timing relationship between npor and the LTSSM L0 state.

Note:

To meet the 100 ms system configuration time, you must use the fast passive parallel configuration scheme with CvP and a 32-bit data width (FPP x32) or use the CvP in autonomous mode.

Table 5-7: Status and Link Training Signals

Signal Direction Description

serdes_pll_locked

Output When asserted, indicates that the PLL that generates the

coreclkout_hip clock signal is locked. In pipe simulation mode

this signal is always asserted.

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Reset, Status, and Link Training Signals

Signal Direction Description

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pld_core_ready

pld_clk_inuse

dlup

dlup_exit

Input When asserted, indicates that the Application Layer is ready for

operation and is providing a stable clock to the pld_clk input. If the coreclkout_hip Hard IP output clock is sourcing the pld_

clk Hard IP input, this input can be connected to the serdes_ pll_locked output.

Output When asserted, indicates that the Hard IP Transaction Layer is

using the pld_clk as its clock and is ready for operation with the Application Layer. For reliable operation, hold the Application Layer in reset until pld_clk_inuse is asserted.

Output When asserted, indicates that the Hard IP block is in the Data

Link Control and Management State Machine (DLCMSM) DL_ Up state.

Output This signal is asserted low for one pld_clk cycle when the IP

core exits the DLCMSM DL_Up state, indicating that the Data Link Layer has lost communication with the other end of the PCIe link and left the Up state. When this pulse is asserted, the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles.

ev128ns

ev1us

hotrst_exit

Output Asserted every 128 ns to create a time base aligned activity.

Output Asserted every 1µs to create a time base aligned activity.

Output Hot reset exit. This signal is asserted for 1 clock cycle when the

LTSSM exits the hot reset state. This signal should cause the Application Layer to be reset. This signal is active low. When this pulse is asserted, the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles.

l2_exit

Output L2 exit. This signal is active low and otherwise remains high. It is

asserted for one cycle (changing value from 1 to 0 and back to 1) after the LTSSM transitions from l2.idle to detect. When this pulse is asserted, the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles.

lane_act[3:0] Output Lane Active Mode: This signal indicates the number of lanes that

configured during link training. The following encodings are defined:

• 4’b0001: 1 lane

• 4’b0010: 2 lanes

• 4’b0100: 4 lanes

• 4’b1000: 8 lanes

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Reset, Status, and Link Training Signals

Signal Direction Description

5-37

currentspeed[1:0]

ltssmstate[4:0]

Output Indicates the current speed of the PCIe link. The following

encodings are defined:

• 2b’00: Undefined

• 2b’01: Gen1

• 2b’10: Gen2

• 2b’11: Gen3

Output LTSSM state: The LTSSM state machine encoding defines the

following states:

• 00000: Detect.Quiet

• 00001: Detect.Active

• 00010: Polling.Active

• 00011: Polling.Compliance

• 00100: Polling.Configuration

• 00101: Polling.Speed

• 00110: config.Linkwidthstart

• 00111: Config.Linkaccept

• 01000: Config.Lanenumaccept

• 01001: Config.Lanenumwait

• 01010: Config.Complete

• 01011: Config.Idle

• 01100: Recovery.Rcvlock

• 01101: Recovery.Rcvconfig

• 01110: Recovery.Idle

• 01111: L0

• 10000: Disable

• 10001: Loopback.Entry

• 10010: Loopback.Active

• 10011: Loopback.Exit

• 10100: Hot.Reset

• 10101: LOs

• 11001: L2.transmit.Wake

• 11010: Speed.Recovery

• 11011: Recovery.Equalization, Phase 0

• 11100: Recovery.Equalization, Phase 1

• 11101: Recovery.Equalization, Phase 2

• 11110: recovery.Equalization, Phase 3

Related Information

• PCI Express Card Electromechanical Specification 2.0

• Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide

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5-38

ECRC Forwarding

On the Avalon-ST interface, the ECRC field follows the same alignment rules as payload data. For packets with payload, the ECRC is appended to the data as an extra dword of payload. For packets without payload, the ECRC field follows the address alignment as if it were a one dword payload. The position of the ECRC data for data depends on the address alignment. For packets with no payload data, the ECRC position corresponds to the position of Data0.

Error Signals

The following table describes the ECC error signals. These signals are all valid for one clock cycle. They are synchronous to coreclkout_hip.

ECC for the RX and retry buffers is implemented with MRAM. These error signals are flags. If a specific location of MRAM has errors, as long as that data is in the ECC decoder, the flag indicates the error.

When a correctable ECC error occurs, the Arria V GZ Hard IP for PCI Express recovers without any loss of information. No Application Layer intervention is required. In the case of uncorrectable ECC error, Altera recommends that you reset the core.

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The Avalon-ST rx_st_err indicates an uncorrectable error in the RX buffer. This signal is described in 64-, 128-, or 256-Bit Avalon-ST RX Datapath in the Avalon-ST RX Interface description.

Table 5-8: Error Signals

Signal I/O Description

derr_cor_ext_rcv0 Output Indicates a corrected error in the RX buffer. This signal is for

debug only. It is not valid until the RX buffer is filled with data. This is a pulse, not a level, signal. Internally, the pulse is generated with the 500 MHz clock. A pulse extender extends the signal so that the FPGA fabric running at 250 MHz can capture it. Because the error was corrected by the IP core, no Application Layer intervention is required.

derr_rpl Output Indicates an uncorrectable error in the retry buffer. This signal is

for debug only.

derr_cor_ext_rpl0 Output Indicates a corrected ECC error in the retry buffer. This signal is

(1)

for debug only. Because the error was corrected by the IP core,

(1)

rxfc_cplbuf_ovf

no Application Layer intervention is required.

Output The optional status signal is available when you turn on Track

Receive Completion Buffer Overflow in the parameter editor. Because the RX buffer completion space advertises infinite credits for Endpoints, you can use this status bit as an additional check to complement the soft logic that tracks space in the completion buffer.

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Signal I/O Description

Notes:

1. Debug signals are not rigorously verified and should only be used to observe behavior. Debug signals

should not be used to drive logic custom logic.

Related Information

Avalon-ST RX Interface on page 5-2

Interrupts for Endpoints

Refer to Interrupts for detailed information about all interrupt mechanisms.

Table 5-9: Interrupt Signals for Endpoints

Signal Direction Description

Interrupts for Endpoints

5-39

app_msi_req

app_msi_ack

app_msi_tc[2:0]

app_msi_num[4:0]

app_int_sts

Input Application Layer MSI request. Assertion causes an MSI posted

write TLP to be generated based on the MSI configuration register values and the app_msi_tc and app_msi_num input ports.

Output Application Layer MSI acknowledge. This signal acknowledges

the Application Layer's request for an MSI interrupt.

Input Application Layer MSI traffic class. This signal indicates the

traffic class used to send the MSI (unlike INTX interrupts, any traffic class can be used to send MSIs).

Input MSI number of the Application Layer. This signal provides the

low order message data bits to be sent in the message data field of MSI messages requested by app_msi_req. Only bits that are enabled by the MSI Message Control register apply.

Input Controls legacy interrupts. Assertion of app_int_sts causes an

Assert_INTA message TLP to be generated and sent upstream. Deassertion of app_int_sts causes a Deassert_INTA message TLP to be generated and sent upstream.

app_int_ack

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Output This signal is the acknowledge for app_int_sts. It is asserted for

at least one cycle either when either of the following events occur:

• The Assert_INTA message TLP has been transmitted in response to the assertion of the app_int_sts.

• The Deassert_INTA message TLP has been transmitted in response to the deassertion of the app_int_sts signal.

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5-40

Interrupts for Root Ports

Table 5-10: Interrupt Signals for Root Ports

Signal Direction Description

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int_status[3:0]

Output These signals drive legacy interrupts to the Application Layer as

follows:

• int_status[0]: interrupt signal A

• int_status[1]: interrupt signal B

• int_status[2]: interrupt signal C

• int_status[3]: interrupt signal D

serr_out

Output System Error: This signal only applies to Root Port designs that

report each system error detected, assuming the proper enabling bits are asserted in the Root Control and Device Control registers. If enabled, serr_out is asserted for a single clock cycle when a system error occurs. System errors are described in the PCI Express Base Specification 2.1 or 3.0 in the Root Control register.

Related Information

PCI Express Base Specification 2.1 or 3.0

Completion Side Band Signals

The following table describes the signals that comprise the completion side band signals for the AvalonST interface. The Arria V GZ Hard IP for PCI Express provides a completion error interface that the Application Layer can use to report errors, such as programming model errors. When the Application Layer detects an error, it can assert the appropriate cpl_err bit to indicate what kind of error to log. If separate requests result in two errors, both are logged. The Hard IP sets the appropriate status bits for the errors in the Configuration Space, and automatically sends error messages in accordance with the PCI Express Base Specification. Note that the Application Layer is responsible for sending the completion with the appropriate completion status value for non-posted requests. Refer to Error Handling for information on errors that are automatically detected and handled by the Hard IP.

For a description of the completion rules, the completion header format, and completion status field values, refer to Section 2.2.9 of the PCI Express Base Specification.

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Table 5-11: Completion Signals for the Avalon-ST Interface

Completion Side Band Signals

5-41

Signal Directi

cpl_err[6:0]

Description

Input Completion error. This signal reports completion errors to the

Configuration Space. When an error occurs, the appropriate signal is asserted for one cycle.

• cpl_err[0]: Completion timeout error with recovery. This signal should be asserted when a master-like interface has performed a non-posted request that never receives a corresponding completion transaction after the 50 ms timeout period when the error is correctable. The Hard IP automatically generates an advisory error message that is sent to the Root Complex.

• cpl_err[1]: Completion timeout error without recovery. This signal should be asserted when a master-like interface has performed a non-posted request that never receives a corresponding completion transaction after the 50 ms time-out period when the error is not correctable. The Hard IP automati‐ cally generates a non-advisory error message that is sent to the Root Complex.

• cpl_err[2]: Completer abort error. The Application Layer asserts this signal to respond to a non-posted request with a Completer Abort (CA) completion. The Application Layer generates and sends a completion packet with Completer Abort (CA) status to the requestor and then asserts this error signal to the Hard IP. The Hard IP automatically sets the error status bits in the Configura‐ tion Space register and sends error messages in accordance with the PCI Express Base Specification.

• cpl_err[3]: Unexpected completion error. This signal must be asserted when an Application Layer master block detects an unexpected completion transaction. Many cases of unexpected completions are detected and reported internally by the Transac‐ tion Layer. For a list of these cases, refer to Transaction Layer Errors.

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Completion Side Band Signals

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Signal Directi

Description

• cpl_err[4]: Unsupported Request (UR) error for posted TLP. The Application Layer asserts this signal to treat a posted request as an Unsupported Request. The Hard IP automatically sets the error status bits in the Configuration Space register and sends error messages in accordance with the PCI Express Base Specifica‐ tion. Many cases of Unsupported Requests are detected and reported internally by the Transaction Layer. For a list of these cases, refer to Transaction Layer Errors.

• cpl_err[5]: Unsupported Request error for non-posted TLP. The Application Layer asserts this signal to respond to a non-posted request with an Request (UR) completion. In this case, the Application Layer sends a completion packet with the Unsupported Request status back to the requestor, and asserts this error signal. The Hard IP automatically sets the error status bits in the Configuration Space Register and sends error messages in accordance with the PCI Express Base Specification. Many cases of Unsupported Requests are detected and reported internally by the Transaction Layer. For a list of these cases, refer to Transaction Layer Errors.

• cpl_err[6]: Log header. If header logging is required, this bit must be set in the every cycle in which any of cpl_err[2], cpl_

err[3], cpl_err[4], or cpl_err[5]is set. The Application Layer

presents the header to the Hard IP by writing the following values to the following 4 registers using LMI before asserting cpl_

err[6]:. The Application Layer presents the header to the Hard IP

by writing the following values to the following 4 registers using LMI before asserting cpl_err[6]:

cpl_pending

Related Information

• Transaction Layer Errors on page 9-3

• PCI Express Base Specification Rev. 2.1 or 3.0

Altera Corporation

• lmi_addr: 12'h81C, lmi_din: err_desc_func0[127:96]

• lmi_addr: 12'h820, lmi_din: err_desc_func0[95:64]

• lmi_addr: 12'h824, lmi_din: err_desc_func0[63:32]

• lmi_addr: 12'h828, lmi_din: err_desc_func0[31:0]

Input Completion pending. The Application Layer must assert this signal

when a master block is waiting for completion, for example, when a Non-Posted Request is pending. The state of this input is reflected by the Transactions Pending bit of the Device Status Register as defined in Section 7.8.5 of the PCI Express Base Specification.

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Parity Signals

You enable parity checking by selecting Enable byte parity ports on the Avalon-ST interface under the System Settings heading of the parameter editor. Parity is odd. This option is not available for the

Avalon-MM Arria V GZ Hard IP for PCI Express. Parity protection provides some data protection in systems that do not use ECRC checking.

On the RX datapath, parity is computed on the incoming TLP prior to the LCRC check in the Data Link Layer. Up to 32 parity bits are propagated to the Application Layer along with the RX Avalon-ST data. The RX datapath also propagates up to 32 parity bits to the Transaction Layer for Configuration TLPs. On the TX datapath, parity generated in the Application Layer is checked in Transaction Layer and the Data Link Layer.

The following table lists the signals that indicate parity errors. When an error is detected, parity error signals are asserted for one cycle.

Table 5-12: Parity Signals

Signal Name Direction Description

Parity Signals

5-43

tx_par_err[1:0]

rx_par_err

Output When asserted for a single cycle, indicates a parity error during

TX TLP transmission. These errors are logged in the VSEC register. The following encodings are defined:

• 2’b10: A parity error was detected by the TX Transaction Layer. The TLP is nullified and logged as an uncorrectable internal error in the VSEC registers. For more information, refer to Uncorrectable Internal Error Status Register.

• 2’b01: Some time later, the parity error is detected by the TX Data Link Layer which drives 2’b01 to indicate the error. Altera recommends resetting the Arria V GZ Hard IP for PCI Express when this error is detected. Contact Altera if resetting becomes unworkable.

Note that not all simulation models assert the Transaction Layer error bit in conjunction with the Data Link Layer error bit.

Output When asserted for a single cycle, indicates that a parity error was

detected in a TLP at the input of the RX buffer. This error is logged as an uncorrectable internal error in the VSEC registers. For more information, refer to Uncorrectable Internal Error Status Register. If this error occurs, you must reset the Hard IP if this error occurs because parity errors can leave the Hard IP in an unknown state.

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Configuration Space

128 32-bit registers

(4 KBytes)

LMI

lmi_dout lmi_ack

lmi_addr

lmi_din

lmi_rden

lmi_wren

pld_clk

Hard IP for PCIe

5-44

LMI Signals

Signal Name Direction Description

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cfg_par_err

Output When asserted for a single cycle, indicates that a parity error was

Output Indicates that a parity error in a TLP routed to the internal

LMI Signals

LMI interface is used to write log error descriptor information in the TLP header log registers. The LMI access to other registers is intended for debugging, not normal operation.

Figure 5-35: Local Management Interface

detected in a TLP that was routed to internal Configuration Space or to the Configuration Space Shadow Extension Bus. This error is logged as an uncorrectable internal error in the VSEC registers. For more information, refer to Uncorrectable Internal Error Status Register. If this error occurs, you must reset the core because parity errors can put the Hard IP in an unknown state.

Configuration Space or to the Configuration Space Shadow Extension Bus. This error is also logged in the Vendor Specific Extended Capability internal error register. You must reset the Hard IP if this event occurs.

Altera Corporation

The LMI interface is synchronized to pld_clk and runs at frequencies up to 250 MHz. The LMI address is the same as the Configuration Space address. The read and write data are always 32 bits. The LMI interface provides the same access to Configuration Space registers as Configuration TLP requests. Register bits have the same attributes, (read only, read/write, and so on) for accesses from the LMI interface and from Configuration TLP requests.

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pld_clk

lmi_rden lmi_addr[11:0] lmi_dout[31:0]

lmi_ack

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Note: You can also use the Configuration Space signals to read Configuration Space registers. For more

When a LMI write has a timing conflict with configuration TLP access, the configuration TLP accesses have higher priority. LMI writes are held and executed when configuration TLP accesses are no longer pending. An acknowledge signal is sent back to the Application Layer when the execution is complete.

All LMI reads are also held and executed when no configuration TLP requests are pending. The LMI interface supports two operations: local read and local write. The timing for these operations complies with the Avalon-MM protocol described in the Avalon Interface Specifications. LMI reads can be issued at any time to obtain the contents of any Configuration Space register. LMI write operations are not recommended for use during normal operation. The Configuration Space registers are written by requests received from the PCI Express link and there may be unintended consequences of conflicting updates from the link and the LMI interface. LMI Write operations are provided for AER header logging, and debugging purposes only.

• In Root Port mode, do not access the Configuration Space using TLPs and the LMI bus simultane‐ ously.

Table 5-13: LMI Interface

Signal Direction Description

information, refer to Transaction Layer Configuration Space Signals.

LMI Signals

5-45

lmi_dout[31:0]

lmi_rden

lmi_wren

lmi_ack

lmi_addr[11:0]

lmi_din[31:0]

Figure 5-36: LMI Read

Output Data outputs.

Input Read enable input.

Input Write enable input.

Output Write execution done/read data valid.

Input Address inputs, [1:0] not used.

Input Data inputs.

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pld_clk

lmi_wren

lmi_din[31:0]

lmi_addr[11:0]

lmi_ack

5-46

Transaction Layer Configuration Space Signals

Figure 5-37: LMI Write

Only writeable configuration bits are overwritten by this operation. Read-only bits are not affected. LMI write operations are not recommended for use during normal operation with the exception of AER header logging.

Related Information

Avalon Interface Specifications

Transaction Layer Configuration Space Signals

Table 5-14: Configuration Space Signals

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These signals are not available if Configuration Space Bypass mode is enabled.

Signal Direction Description

tl_cfg_add[3:0]

0utput Address of the register that has been updated. This signal is an

index indicating which Configuration Space register information is being driven onto tl_cfg_ctl. The indexing is defined in

Multiplexed Configuration Register Information Available on tl_ cfg_ctl. The index increments on every pld_clk cycle.

tl_cfg_ctl[31:0]

0utput The tl_cfg_ctl signal is multiplexed and contains the contents

of the Configuration Space registers. The indexing is defined in

Multiplexed Configuration Register Information Available on tl_ cfg_ctl.

tl_cfg_sts[52:0]

0utput Configuration status bits. This information updates every pld_

clk cycle. The following table provides detailed descriptions of

the status bits.

Input The hpg_ctrler signals are only available in Root Port mode and

when the Slot capability register is enabled. Refer to the Slot

hpg_ctrler[4:0]

register and Slot capability register parameters in Table 6–9 on page 6–10. For Endpoint variations the hpg_ctrler input should be hardwired to 0s. The bits have the following meanings:

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Transaction Layer Configuration Space Signals

Signal Direction Description

Input • [0]: Attention button pressed. This signal should be asserted

when the attention button is pressed. If no attention button exists for the slot, this bit should be hardwired to 0, and the

Attention Button Present bit (bit[0]) in the Slot capability

Input • [1]: Presence detect. This signal should be asserted when a

presence detect circuit detects a presence detect change in the slot.

Input • [2]: Manually-operated retention latch (MRL) sensor

changed. This signal should be asserted when an MRL sensor indicates that the MRL is Open. If an MRL Sensor does not exist for the slot, this bit should be hardwired to 0, and the

MRL Sensor Present bit (bit[2]) in the Slot capability register

parameter is set to 0.

Input • [3]: Power fault detected. This signal should be asserted when

the power controller detects a power fault for this slot. If this slot has no power controller, this bit should be hardwired to 0, and the Power Controller Present bit (bit[1]) in the Slot capability register parameter is set to 0.

5-47

Input • [4]: Power controller status. This signal is used to set the

command completed bit of the Slot Status register. Power controller status is equal to the power controller control signal. If this slot has no power controller, this bit should be hardwired to 0 and the Power Controller Present bit (bit[1]) in the Slot capability register is set to 0.

Table 5-15: Mapping Between tl_cfg_sts and Configuration Space Registers

tl_cfg_sts Configuration Space Register Description

[52:49] Device Status Register[3:0] Records the following errors:

• Bit 3: unsupported request detected

• Bit 2: fatal error detected

• Bit 1: non-fatal error detected

• Bit 0: correctable error detected

[48] Slot Status Register[8] Data Link Layer state changed

[47]

Slot Status Register[4] Command completed. (The hot plug

controller completed a command.)

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5-48

Transaction Layer Configuration Space Signals

tl_cfg_sts Configuration Space Register Description

[46:31] Link Status Register[15:0] Records the following link status informa‐

tion:

• Bit 15: link autonomous bandwidth status

• Bit 14: link bandwidth management status

• Bit 13: Data Link Layer link active

• Bit 12: Slot clock configuration

• Bit 11: Link Training

• Bit 10: Undefined

• Bits[9:4]: Negotiated Link Width

• Bits[3:0] Link Speed

UG-01127_avst

2014.12.15

[30]

Link Status 2 Register[0] Current de-emphasis level.

[29:25] Status Register[15:11] Records the following 5 primary command

status errors:

• Bit 15: detected parity error

• Bit 14: signaled system error

• Bit 13: received master abort

• Bit 12: received target abort

• Bit 11: signalled target abort

[24] Secondary Status Register[8] Master data parity error

[23:6] Root Status Register[17:0] Records the following PME status informa‐

tion:

• Bit 17: PME pending

• Bit 16: PME status

• Bits[15:0]: PME request ID[15:0]

[5:1] Secondary Status Register[15:11] Records the following 5 secondary command

status errors:

[0] Secondary Status Register[8] Master Data Parity Error

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• Bit 15: detected parity error

• Bit 14: received system error

• Bit 13: received master abort

• Bit 12: received target abort

• Bit 11: signalled target abort

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