Altera Arria V GX Starter Board User Manual

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Arria V GX Starter Board Reference Manual

Arria V GX Starter Board

Reference Manual

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© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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9001:2008

Registered

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Arria V GX FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

I/O and Transceiver Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

MAX V CPLD 5M2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

Flash Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

JTAG Chain Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

PCI Express Link Width DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Image Load Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Image Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Off-Board Clock Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

General LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

HSMC LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

PCI Express LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

HSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

SDI Video Output/Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

HDMI Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

Synchronous SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

iv Contents

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–49

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–52

CE EMI Conformity Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–52

Additional Information

Board Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

This document describes the hardware features of the Arria® V GX starter board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Arria V GX starter board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Arria V GX FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V GX designs.

1. Overview

One high-speed mezzanine card (HSMC) connector is available to add additional functionality via a variety of HSMCs available from Altera

and various partners.

f To see a list of the latest HSMCs available or to download a copy of the HSMC

specification, refer to the Development Board Daughtercards page of the Altera website.

Design advancements and innovations, such as the PCI Express hard IP, partial reconfiguration, and hard memory controller implementation ensure that designs implemented in the Arria V GXs operate faster, with lower power, and have a faster time to market than previous FPGA families.

f For more information on the following topics, refer to the respective documents:

■ Arria V device family, refer to the Arria V Device Handbook.

■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

The starter board features the following major component blocks:

■ One Arria V GX 5AGXFB3H4F35C4N FPGA in a 1152-pin FineLine BGA (FBGA)

package

■ 362,000 LEs

■ 136,880 adaptive logic modules (ALMs)

■ 17,260 Kbit on-die block memory

■ 24 high-speed transceivers

■ 12 fractional phase locked loops (PLLs)

■ 2,090 18x19 multipliers

■ 544 general purpose input/output

■ 1.1-V core voltage

■ MAX

■ MAX II EPM570F100C5N CPLD in a 100-pin FBGA package

V 5M2210ZF256C4N CPLD in a 256-pin FBGA package

■ FPGA configuration circuitry

■ MAX V CPLD 5M2210ZF256C4N System Controller and flash fast passive

parallel (FPP) configuration

■ On-board USB-Blaster

■ Clocking circuitry

■ Programmable clock generator for FPGA reference clock input

■ 125-MHz LVDS oscillator for FPGA reference clock input

■ 148.5/148.35-MHz LVDS VCXO for FPGA reference clock input

■ 50-MHz single-ended oscillator for FPGA and CPLD clock input

■ 100-MHz single-ended oscillator for CPLD configuration clock input

■ SMA input (LVPECL)

■ Memory

■ Two 128-Mbyte (MB) DDR3 SDRAM with a total of 32-bit data bus

■ 2-MB SSRAM

■ Two 128-MB synchronous flash

II for use with the Quartus® II Programmer

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ General user I/O

■ LEDs and displays

■ Four user LEDs

■ One two-line character LCD display

■ Three configuration select LED

■ One configuration done LED

■ Four on-board USB-Blaster II status LEDs

■ Two HSMC interface transmit/receive LED (TX/RX)

■ Four PCI Express LEDs

■ Five Ethernet LEDs

■ One serial digital interface (SDI) carrier detect LED

■ Push buttons

■ One CPU reset push button

■ One configuration reset push button

■ Three general user push buttons

■ DIP switches

■ Four MAX V CPLD System Controller control switches

■ Three JTAG chain control switches

■ Three PCI Express link width switches

■ Four general user switches

■ Power supply

■ 19-V (laptop) DC input

■ PCI Express edge connector power

■ Mechanical

■ PCI card standard size (6.600" x 4.199")

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

1–4 Chapter 1: Overview

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Arria V GX starter board.

Figure 1–1. Arria V GX Starter Board Block Diagram

LVDS/Single-Ended

Type-B

USB 2.0

Embedded

USB-Blaster II

REFCLK SMA

Trigger SMA

Out

Gigabit Ethernet

PHY

SDI

TX/RX

JTAG Chain

x1 LVPECL

XCVR x1

Programmable

Oscillator

50 M, 125 M

Port A

x80

CLKIN x3

5AGXFB3H4F35C4N

XCVR x8

CLKOUT x3

XVCR x8

x8 Edge

256-MB

DDR3

x32

ADDR x27

CONFIG x16

5M2210ZF256C4N

DATA x32

x4 XVCR

x1 XCVR

x11

x10

x32

SSRAM

2-MB

HDMI

XCVR

SMA Out & In

2x16 LCD

Push buttons

LEDs

128-MB

Flash

x16x16

128-MB

Flash

Handling the Board

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Introduction

1 A complete set of schematics, a physical layout database, and GERBER files for the

f For information about powering up the board and installing the demonstration

2. Board Components

This chapter introduces the major components on the Arria V GX starter board.

Figure 2–1 illustrates the component locations and Table 2–1 provides a brief

description of all component features of the board.

development board reside in the Arria V GX starter kit documents directory.

software, refer to the Arria V GX Starter Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Arria V GX FPGA” on page 2–5

■ “MAX V CPLD 5M2210 System Controller” on page 2–7

■ “FPGA Configuration” on page 2–12

■ “Clock Circuitry” on page 2–20

■ “General User Input/Output” on page 2–23

■ “Components and Interfaces” on page 2–27

■ “Memory” on page 2–39

■ “Power Supply” on page 2–48

■ “Statement of China-RoHS Compliance” on page 2–52

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–2 Chapter 2: Board Components

Clock Input SMA Connector (J7, J8)

Max V Reset

Push Button (S3)

General User Push Buttons

(PB1, PB2)

Flash x32

Memory

(U12, U13)

Board Settings

DIP Switch

(SW4)

PCI Express

Edge Connector (J1)

DDR3 x32 (U10,U11)

DC Input Jack (J4)

Character LCD (J16)

CPU Reset

Push Button (S4)

Powe r Switch (SW1)

User DIP

Switch (SW2)

User LEDs (D20-D23)

MAX V CPLD

EPM2210 System

Controller (U15)

Clock Output

SMA Connector

(J12)

HSMC Port A (J13)

Configuration Done,

Load, and Error

LEDs (D10-D12)

Program Load,

Program Select

Push Buttons

(S1, S2)

Program Select

LEDs (D24-D26)

Transceiver RX

SMA Connector

(J2, J3)

Transceiver TX

SMA Connector

(J4, J5)

USB Type-B

Connector (J14)

HDMI Video

Port (J10)

SDI Video Port

(J11, J12)

Gigabit Ethernet

Port (J19)

JTAG Chain Header (J9)

Fan Power

Header (J18)

SSRAM x36

Memory

(U14)

PCI Express

Mode DIP Switch

(SW1)

Arria V GX FPGA (U1)

Board Overview

This section provides an overview of the Arria V GX starter board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features.

Figure 2–1. Overview of the Arria V GX Starter Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Arria V GX Starter Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U1 FPGA Arria V GX, 5AGXFB3H4F35C4N, 1152-pin FBGA.

U15 CPLD MAX V CPLD, 5M2210ZF256C4N , 256-pin FBGA.

Configuration, Status, and Setup Elements

J9 JTAG chain header

D6, D7 JTAG LEDs

Provides access to the JTAG chain and disables the on-board USB-Blaster II when using an external USB-Blaster cable.

Indicate transmit or receive activity of the JTAG chain. The TX and RX LEDs would flicker if the link is in use and active.

SW2 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Arria V GX Starter Board Components (Part 2 of 3)

Board Reference Type Description

J14 On-Board USB-Blaster II

USB interface for programming and debugging the FPGA through embedded USB-Blaster II JTAG via a type-B USB cable.

Controls the MAX V CPLD 5M2210 System Controller functions such

SW4 Board settings DIP switch

as clock enable, SMA clock input control, and which image to load from flash memory at power-up.

prsnt

SW1 PCI Express DIP switch

S2 Image select push button

S1 Load image push button

Controls the PCI Express lane width by connecting together on the PCI Express edge connector.

Toggles the configuration LEDs which selects the program image that loads from flash memory to the FPGA.

Load image from flash memory to the FGPA based on the configuration LED setting.

pins

Indicate transmit or receive activity of the System Console USB

D8, D9 System Console LEDs

interface. The TX and RX LEDs would flicker if the link is in use and active.

D12 Configuration done LED Illuminates when the FPGA is configured.

D11 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.

D10 Error LED Illuminates when the FPGA configuration from flash memory fails.

D30 Power LED Illuminates when 5.0-V power is present.

Illuminates to show the LED sequence that determines which flash

D24, D25, D26 Configuration LEDs

memory image loads to the FPGA when you press the

PGM_SEL

push

button.

D2, D3, D4, D5, D33

Ethernet LEDs Shows the connection speed as well as transmit or receive activity.

D13, D14 HSMC port A LEDs You can configure these LEDs to indicate transmit or receive activity.

D15 HSMC port A present LED Illuminates when a daughtercard is plugged into the HSMC port A.

D16, D17, D18, D19

PCI Express link LEDs

You can configure these LEDs to indicate the PCI Express link width (x1, x4, x8) and Gen2 link.

Clock Circuitry

Programmable oscillator with default frequencies of 125 MHz,

U4 Quad-output oscillator

409.6 MHz, 156.25 MHz, and 100 MHz. The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

148.500-MHz voltage controlled crystal oscillator for serial digital

X1 148.5-MHz oscillator

interface (SDI) video. This oscillator is programmable to any frequency between 20–810 MHz using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

X3 100-MHz oscillator

100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System Controller.

X2 125-MHz oscillator 125.000 MHz crystal oscillator for Gigabit Ethernet.

J7, J8 Clock input SMAs

Drive LVPECL-compatible clock inputs into the clock multiplexer buffer (U5).

J6 Clock output SMA Drive out 2.5-V CMOS clock output from the FPGA.

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Arria V GX Starter Board Components (Part 3 of 3)

Board Reference Type Description

General User Input/Output

D20–D23 User LEDs Four user LEDs. Illuminates when driven low.

SW3 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.

S4 CPU reset push button Press to reset the FPGA logic.

S3 MAX V reset push button Press to reset the MAX V CPLD 5M2210 System Controller.

S5, S6, S7 General user push buttons Three user push buttons. Driven low when pressed.

Memory Devices

U10, U11 DDR3 x32 memory

U14 SSRAM x36 memory

256-Mbyte DDR3 SDRAM with a 32-bit data bus. The 32-bit data bus consists of two x16 devices with a single address or command bus.

2-Mbyte standard synchronous RAM with a 32-bit data bus and 4-bit parity.

Two 128-Mbyte synchronous flash devices with 16-bit data buses for

U12, U13 Flash x32 memory

non-volatile memory. The board supports two flash devices of 16-bit interface each, which combine to allow for 256-Mbyte synchronous flash with a 32-bit data bus.

Communication Ports

J1 PCI Express edge connector

J13 HSMC port A

J19 Gigabit Ethernet connector

Video and Display Ports

J16 Character LCD

J10 HDMI video port

J11, J12 SDI video port

Power Supply

J1 PCI Express edge connector

J17 DC input jack

SW5 Power switch

Gold-plated edge fingers connector for up to ×8 signaling in Gen1 or Gen2 mode.

Provides eight transceiver channels and 84 CMOS or 17 LVDS channels per the HSMC specification.

RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.

Connector that interfaces to a provided 16 character × 2 line LCD module along with two standoffs.

A 19-pin HDMI connector that provides a HDMI video output of up to 1080i.

Two 75-Ω sub-miniature version B (SMB) connectors that provide a full-duplex SDI interface through a LMH0303 cable driver and LMH0384 cable equalizer.

Interfaces to a PCI Express root port such as an appropriate PC motherboard.

Accepts a 14–20-V DC power supply. This input jack is not to be used while the board is plugged into a PCI Express slot.

Switch to power on or off the board when power is supplied from the DC input jack.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

Bank 3A

Total I/O in Each Bank

Bank Number

Bank 3B32

Bank 3C32

Bank 3D32

Bank 4D32

Bank 4C32

Bank 8A

Bank 8B

Bank 8C

Bank 8D

Bank 7D

Bank 7C

Bank 4B32

Bank 4A32

Bank 7B

Bank 7A3231

Transceiver Block

5AGXFB3H4F35

Featured Device: Arria V GX FPGA

The Arria V GX starter board features a Arria V GX 5AGXFB3H4F35C4N device (U1) in a 1152-pin FBGA package.

f For more information about Arria V device family, refer to the Arria V Device

Handbook.

Tab le 2– 2 describes the features of the Arria V GX 5AGXFB3H4F35C4N device.

Table 2–2. Arria V GX Features

ALMs

Equivalent

LEs

M10K RAM

Blocks

Total RAM

(Kbits)

18-bit × 19-bit

Multipliers

PLLs Transceivers Package Type

136,880 362,000 1,726 17,260 2,090 12 24 1152-pin FBGA

Tab le 2– 3 lists the Arria V GX component reference and manufacturing information.

Table 2–3. Arria V GX Component Reference and Manufacturing Information

Board Reference Description Manufacturer

FPGA, Arria V GX F1152, 362K LEs, leadfree

Corporation 5AGXFB3H4F35C4N www.altera.com

Altera

Manufacturing

Part Number

Manufacturer

Website

I/O and Transceiver Resources

Figure 2–2 illustrates the bank organization and I/O count for the Arria V GX

5AGXFB3H4F35C4N device in the 1152-pin FBGA package.

Figure 2–2. Arria V GX Device I/O Bank Diagram

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–6 Chapter 2: Board Components

Featured Device: Arria V GX FPGA

Figure 2–3 illustrates the transceiver channels on the left and right side of the

Arria V GX 5AGXFB3H4F35C4N device in the 1152-pin FBGA package.

Figure 2–3. Arria V GX Device Transceiver Bank Diagram

CH 5

CH 4

CH 3

GXB_L1 GXB_R1

GXB_L0

CH 2

CH 1

CH 0

5AGXFB3H4F35

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

Channels Per Bank

Transceiver Bank

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

GXB_R0

Tab le 2 –4 lists the Arria V GX device I/O and transceiver pin count and usage by

function on the board.

Table 2–4. Arria V GX Device I/O and Transceiver Pin Count

Function I/O Standard I/O Count Special Pins

DDR3 1.5-V SSTL 70 One differential x4 DQS pin

Flash, SSRAM, and MAX V FSM bus 2.5-V CMOS 87 —

MAX V CPLD 5M2210 System Controller 2.5-V CMOS 10 —

PCI Express x8 2.5-V CMOS + XCVR 42 One reference clock

HSMA port A 2.5-V CMOS + LVDS + XCVR 116

Eight XCVR, 17 LVDS, six clock inputs/outputs, I

Gigabit Ethernet 2.5-V CMOS + LVDS 20 One LVDS

On-Board USB-Blaster II 2.5-V CMOS 20 —

SDI video 2.5-V CMOS 15 One reference clock

HDMI video 2.5-V CMOS 14 One reference clock

Push buttons 2.5-V CMOS 4 One DEV_CLRn

DIP switches 2.5-V CMOS 4 —

Character LCD 2.5-V CMOS 11 —

LEDs 2.5-V CMOS 7 —

Clock or Oscillators 2.5-V CMOS + LVDS + PCML 21 11 reference clock

Total I/O Used: 441

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–7

Information

On-Board

USB-Blaster II

Si571

Controller

Si5538

Controller

SLD-HUB

PFL

FSM BUS

MAX V CPLD System Controller

Power

Measurement

Results

Virtual-JTAG

FPGA

LTC2418 Controller

Flash

Decoder

Encoder

GPIO

JTAG Control

Flash

SSRAM

Control

Si571

Programmable

Oscillator

Si5338

Programmable

Oscillator

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Fan control (shared with the FPGA)

■ Control registers for clocks

■ Control and status registers for remote system update

Figure 2–4 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Figure 2–4. MAX V CPLD 5M2210 System Controller Block Diagram

Tab le 2 –5 lists the I/O signals present on the MAX V CPLD 5M2210 System

Controller. The signal names and functions are relative to the MAX V device (U15).

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 6)

Board

Reference (U15)

A15

A13

J12

November 2013 Altera Corporation Arria V GX Starter Board

Schematic Signal Name I/O Standard Description

5M2210_JTAG_TMS

CLK125_EN

CLK50_EN

CLK_CONFIG

CLK_ENABLE

CLK_SEL

CLKIN_50_MAXV

Reference Manual

2.5-V MAX V JTAG TMS

2.5-V 125 MHz oscillator enable

2.5-V 50 MHz oscillator enable

2.5-V 100 MHz configuration clock input

2.5-V DIP switch for clock oscillator enable

2.5-V DIP switch for clock select—SMA or oscillator

2.5-V 50 MHz clock input

2–8 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 2 of 6)

Board

Reference (U15)

D10

T13

T15

R14

N12

Schematic Signal Name I/O Standard Description

CLOCK_SCL

CLOCK_SDA

CPU_RESETN

EXTRA_SIG0

EXTRA_SIG1

EXTRA_SIG2

FACTORY_LOAD

FACTORY_REQUEST

FACTORY_STATUS

FAN_FORCE_ON

FLASH_ADVN

FLASH_CEN0

FLASH_CEN1

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN0

FLASH_RDYBSYN1

FLASH_RESETN

FLASH_WEN

FPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D1

FPGA_CONFIG_D2

FPGA_CONFIG_D3

FPGA_CONFIG_D4

FPGA_CONFIG_D5

FPGA_CONFIG_D6

FPGA_CONFIG_D7

FPGA_CONFIG_D8

FPGA_CONFIG_D9

FPGA_CONFIG_D10

FPGA_CONFIG_D11

FPGA_CONFIG_D12

FPGA_CONFIG_D13

FPGA_CONFIG_D14

FPGA_CONFIG_D15

FPGA_CVP_CONFDONE

FPGA_DCLK

2.5-V Programmable oscillator I2C clock

2.5-V Programmable oscillator I2C data

2.5-V FPGA reset push button

2.5-V USB-Blaster II interface. Reserved for future use.

2.5-V DIP switch to load factory or user design at power-up

2.5-V

On-Board USB-Blaster II request to send FACTORY command

2.5-V On-Board USB-Blaster II FACTORY command status

2.5-V DIP switch to on or off the fan

2.5-V FSM bus flash memory address valid

2.5-V FSM bus flash memory chip enable 0

2.5-V FSM bus flash memory chip enable 1

2.5-V FSM bus flash memory clock

2.5-V FSM bus flash memory output enable

2.5-V FSM bus flash memory ready 0

2.5-V FSM bus flash memory ready 1

2.5-V FSM bus flash memory reset

2.5-V FSM bus flash memory write enable

2.5-V FPGA configuration done LED

2.5-V FPGA configuration data

2.5-V FPGA configuration via protocol done LED

2.5-V FPGA configuration clock

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 6)

Board

Reference (U15)

E14

C14

C15

E13

E12

D15

F14

D16

F13

E15

E16

F15

G14

F16

G13

G15

G12

G16

H14

H15

H13

H16

J13

J14

J15

K16

K13

K15

K14

L16

Schematic Signal Name I/O Standard Description

FPGA_NCONFIG

FPGA_NSTATUS

FPGA_PR_DONE

FPGA_PR_ERROR

FPGA_PR_READY

FPGA_PR_REQUEST

FSM_A0

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

2.5-V FPGA configuration active

2.5-V FPGA configuration ready

2.5-V FPGA partial reconfiguration done

2.5-V FPGA partial reconfiguration error

2.5-V FPGA partial reconfiguration ready

2.5-V FPGA partial reconfiguration request

2.5-V FSM address bus

2.5-V FSM data bus

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–10 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 6)

Board

Reference (U15)

L11

L15

L12

M16

L13

M15

L14

N16

M13

N15

N14

P15

P14

D13

D14

F11

J16

F12

K12

M14

N13

P11

P12

Schematic Signal Name I/O Standard Description

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

FSM_D16

FSM_D17

FSM_D18

FSM_D19

FSM_D20

FSM_D21

FSM_D22

FSM_D23

FSM_D24

FSM_D25

FSM_D26

FSM_D27

FSM_D28

FSM_D29

FSM_D30

FSM_D31

HSMA_PRSNTN

INT_TSD_SDA

INT_TSD_SCL

LTC3880_SDA_2.5V

LTC3880_SCL_2.5V

LTC3880_ALERT_N_2.5V

LTC3880_GPIO0_N_2.5V

JTAG_5M2210_TDI

JTAG_5M2210_TDO

JTAG_TCK

M570_CLOCK

M570_PCIE_JTAG_EN

2.5-V FSM data bus

2.5-V HSMC port A present

2.5-V Internal TSD I2C bus

2.5-V 1.1-V VCC core power supply to PMBus

2.5-V MAX V CPLD on-board JTAG chain data in

2.5-V MAX V CPLD on-board JTAG chain data out

2.5-V JTAG chain clock

2.5-V

25-MHz clock to on-board USB-Blaster II for sending FACTORY command

Low signal to disable the on-board USB-Blaster II when PCI Express is the master to the JTAG chain

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–11

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 5 of 6)

Board

Reference (U15)

P10

R11

T12

N11

T11

R10

M10

N10

E11

B10

C10

C12

D12

B14

C13

B16

B13

D11

R12

Schematic Signal Name I/O Standard Description

MAX5_BEN0

MAX5_BEN1

MAX5_BEN2

MAX5_BEN3

MAX5_CLK

MAX5_CSN

MAX5_OEN

MAX5_WEN

MAX_CONF_DONEN

MAX_ERROR

MAX_LOAD

MAX_RESETN

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

OVERTEMP

PCIE_JTAG_EN

PGM_CONFIG

PGM_LED0

PGM_LED1

PGM_LED2

PGM_SEL

SDI_RX_BYPASS

SDI_RX_EN

SDI_TX_EN

SECURITY_MODE

SENSE_CS0N

SENSE_SCK

SENSE_SDI

SENSE_SDO

SI571_EN

USB_CFG0

USB_CFG1

USB_CFG2

USB_CFG3

USB_CFG4

USB_CFG5

2.5-V FSM bus MAX V byte enable 0

2.5-V FSM bus MAX V byte enable 1

2.5-V FSM bus MAX V byte enable 2

2.5-V FSM bus MAX V byte enable 3

2.5-V FSM bus MAX V clock

2.5-V FSM bus MAX V chip select

2.5-V FSM bus MAX V output enable

2.5-V FSM bus MAX V write enable

2.5-V On-board USB-Blaster II configuration done LED

2.5-V FPGA configuration error LED

2.5-V FPGA configuration active LED

2.5-V MAX V reset push button

2.5-V FPGA mode select 0

2.5-V FPGA mode select 1

2.5-V FPGA mode select 2

2.5-V FPGA mode select 3

2.5-V FPGA mode select 4

2.5-V Temperature monitor fan enable

2.5-V DIP switch to enable the PCI Express JTAG master

2.5-V Load the flash memory image identified by the PGM LEDs

2.5-V Flash memory PGM select indicator 0

2.5-V Flash memory PGM select indicator 1

2.5-V Flash memory PGM select indicator 2

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

2.5-V SDI equalization bypass

2.5-V SDI receive enable

2.5-V SDI transmit enable

2.5-V Reserved for future use

2.5-V Power monitor chip select

2.5-V Power monitor SPI clock

2.5-V Power monitor SPI data in

2.5-V Power monitor SPI data out

2.5-V Si571 programmable VCXO enable

2.5-V Reserved for future use

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–12 Chapter 2: Board Components

FPGA Configuration

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 6 of 6)

Board

Reference (U15)

T10

Schematic Signal Name I/O Standard Description

USB_CFG6

USB_CFG7

USB_CFG8

USB_CFG9

USB_CFG10

USB_CFG11

USB_CLK

2.5-V Reserved for future use

2.5-V On-board USB-Blaster II clock

Tab le 2 –6 lists the MAX V CPLD 5M2210 System Controller component reference and

manufacturing information.

Table 2–6. MAX II CPLD 5M2210 System Controller Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U15

IC - MAX V CPLD 2210 LES, 256 FBGA 1.8 V VCCINT

Corporation 5M2210ZF256C4N www.altera.com

Altera

Manufacturing

Part Number

Manufacturer

FPGA Configuration

Website

This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System Controller device programming methods supported by the Arria V GX starter board.

The Arria V GX starter board supports the following three configuration methods:

■ Embedded USB-Blaster is the default method for configuring the FPGA at any

time using the Quartus II Programmer in JTAG mode with the supplied USB cable.

■ External USB-Blaster for configuring the FPGA using an external USB-Blaster that

connects to the JTAG programming header.

■ Flash memory download for configuring the FPGA using stored images from the

flash memory on either power-up or pressing the

FPGA Programming over Embedded USB-Blaster

This configuration method implements a USB Type-B connector (J14), a USB 2.0 PHY device (U23), and an Altera MAX II CPLD EPM570F100C5N (U21) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB port on the board and a USB port of a PC running the Quartus II software.

The embedded USB-Blaster in the MAX II CPLD EPM570F100C5N normally masters the JTAG chain. To prevent contention between the JTAG masters, the embedded USB-Blaster is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG connector.

PGM_CONFIG

push button (S1).

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–13

Cypress

On-Board

USB-Blaster II

GPIO

TCK

Arria V GX

FPGA

Analog Switch

MAX V

System

Controller

HSMC Port A

GPIO

TMS

GPIO

TDO

GPIO

TDI

JTAG Master

GPIO

DISABLE

ENABLE

JTAG Slave

Installed

HSMC

Card

TCK

TMS

TDI

TDO

TCK

2.5 V

TMS

TDI

TDO

TCK

TMS

TDI

TDO

JTAG Slave

Analog

Switch

ALWAYS

ENABLED

(in chain)

DIP Switch

10-pin

JTAG Header

Flash

Memory

PCI Express

Edge

Connector

JTAG Master

PCI Express

Motherboard

TCK

TMS

TDI

TDO

Level

Shifter

2.5 V

FPGA Configuration

Figure 2–5 illustrates the JTAG chain.

Figure 2–5. JTAG Chain

The JTAG DIP switch (SW2) controls the jumpers shown in Figure 2–5. To connect a device or interface in the chain, their corresponding switch must be in the OFF position. Slide all the switches in the ON position to only have the FPGA in the chain.

1 The MAX V CPLD 5M2210 System Controller must be in the chain to use some of the

GUI interfaces.

Flash Memory Programming

Flash memory programming is possible through a variety of methods.

The default method is to use the factory design—Board Update Portal. This design is an embedded webserver, which serves the Board Update Portal web page. The web page allows you to select new FPGA designs including hardware, software, or both in an industry-standard S-Record File (.flash) and write the design to the user hardware page (page 1) of the flash memory over the network.

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–14 Chapter 2: Board Components

FPGA Configuration

The secondary method is to use the pre-built parallel flash loader (PFL) design included in the development kit. The development board implements the Altera PFL megafunction for flash memory programming. The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash memory device. This pre-built design contains the PFL megafunction that allows you to write either page 0, page 1, or other areas of flash memory over the USB interface using the Quartus II software. This method is used to restore the development board to its factory default settings.

Other methods to program the flash memory can be used as well, including the

Nios

II processor.

f For more information on the Nios II processor, refer to the Nios II Processor page of

the Altera website.

FPGA Programming from Flash Memory

On either power-up or by pressing the program configuration push button,

PGM_CONFIG

FPGA from the flash memory. The PFL megafunction reads 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 16-bit data is then written to the dedicated configuration pins in the FPGA during configuration.

(S1), the MAX V CPLD 5M2210 System Controller's PFL configures the

Pressing the based on which

Tab le 2 –7 defines the design that loads when you press the

Table 2–7. PGM_LED Settings

PGM_LED0 PGM_LED1 PGM_LED2 Design

ON OFF OFF Factory

OFF ON OFF User design 1

OFF OFF ON User design 2

Note to Tab le 2–7:

(1) ON indicates a setting of ’0’ while OFF indicates a setting of ’1’.

PGM_CONFIG

PGM_LED[2:0]

push button (S1) loads the FPGA with a hardware page

LED (D11, D12, D13) illuminates.

PGM_CONFIG

(1)

push button.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

MAX V CPLD

5M2210 System Controller

Arria V FPGA

FPGA_DATA [7:0]

FPGA_DCLK

FLASH_A [26:1]

FLASH_D [31:0]

DATA [7:0]

DCLK

nSTATUS

nCONFIG

CONF_DONE

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

MSEL[4:0] also

connects to MAX V CPLD

Note: At any one time, install either the pull-up or pull-down resistor. Refer to the datasheet for valid MSEL settings to avoid undesired FPGA behavior.

2.5 V

10 kΩ

nCE

CFI Flash

FLASH_CEn0 FLASH_CEn1

FLASH_OEn

FLASH_WEn

FLASH_A [26:1]

FLASH_D [15:0]

FLASH_CEn0

FLASH_OEn

FLASH_WEn

FLASH_WPn

FLASH_ADVn

FPGA_nCONFIG

FPGA_CONF_DONE

FLASH_RYBSYn0

FLASH_RYBSYn0 FLASH_RYBSYn1

FPGA_nSTATUS

2.5 V

10 kΩ

FLASH_ADVn

CONF_DONE_LED

2.5 V

FLASH_CLK

FLASH_RSTn

FLASH_RESETn

FPP Mode

Flash Interface

56.2 Ω

100 Ω56.2 Ω

56.2 Ω

50 MHz

100 MHz

2.5 V

ERROR

CONF_DONE

LOAD

CFI Flash

FLASH_A [26:1]

FLASH_D [31:16]

FLASH_CEn1

FLASH_OEn

FLASH_WEn

FLASH_WPn

FLASH_ADVn

FLASH_RYBSYn1

FLASH_CLK

FLASH_RESETn

Reserved

FACTORY_LOAD

CLK_ENABLE

CLK_SEL

MAX_RESETn

PGM_CONFIG

PGM_SEL

PGM_LED0

PGM_LED1

PGM_LED2

DIP Switch

10 kΩ

2.5 V

DNI (0 Ω)

0 Ω

Chapter 2: Board Components 2–15

FPGA Configuration

Figure 2–6 shows the PFL configuration.

Figure 2–6. PFL Configuration

f For information about the flash memory map storage, refer to the Arria V GX Starter

Kit User Guide.

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–16 Chapter 2: Board Components

Status Elements

FPGA Programming over External USB-Blaster

The JTAG programming header provides another method for configuring the FPGA using an external USB-Blaster device with the Quartus II Programmer running on a PC. The external USB-Blaster connects to the board through the JTAG header (J9).

f For more information on the following topics, refer to the respective documents:

■ Board Update Portal and PFL design, refer to the Arria V GX Starter Kit User Guide.

■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.

Status Elements

The development board includes status LEDs. This section describes the status elements.

Tab le 2 –8 lists the LED board references, names, and functional descriptions.

Table 2–8. Board-Specific LEDs (Part 1 of 2)

Board

Reference

D30

D12

D11

D10

D24

D25

D26

D6, D7

D8, D9

D33

Schematic Signal

Name

Power

MAX_CONF_DONEn

MAX_LOAD

MAX_ERROR

PGM_LED[0]

PGM_LED[1]

PGM_LED[2]

JTAG_RX, JTAG_TX

SC_RX, SC_TX

ENET_LED_TX

ENET_LED_RX

ENET_LED_LINK10

ENET_LED_LINK100

ENET_LED_LINK1000

I/O

Standard

5.0-V Blue LED. Illuminates when 5.0 V power is active.

2.5-V

Green LED. Illuminates when the FPGA is successfully configured. Driven by the MAX V CPLD 5M2210 System Controller.

Green LED. Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA. Driven by the MAX V CPLD 5M2210 System Controller.

Red LED. Illuminates when the MAX V CPLD 5M2210 System Controller fails to configure the FPGA. Driven by the MAX V CPLD 5M2210 System Controller.

Green LEDs. Illuminates to indicate which hardware page loads from flash memory when you press the

Green LEDs. Illuminates to indicate USB-Blaster II receive and transmit activities.

Green LED. Illuminates to indicate Ethernet PHY transmit activity. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet PHY receive activity. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 10 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Description

PGM_SEL

push button.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–17

Setup Elements

Table 2–8. Board-Specific LEDs (Part 2 of 2)

Board

Reference

Schematic Signal

Name

SDI_RX_CDn

I/O

Standard

3.3-V

Description

Green LED. Illuminates to indicate that input signal is detected at the SDI RX port. Driven by the SDI cable equalizer.

Green LED. Illuminates when HSMC port A has a board or cable

D15

HSMA_PRSNTn

3.3-V

plugged-in such that pin 160 becomes grounded. Driven by the add-in card.

Tab le 2 –9 lists the board-specific LEDs component references and manufacturing

information.

Table 2–9. Board-Specific LEDs Component References and Manufacturing Information

Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website

D1 – D9,

D11 – D15,

Green LEDs Lumex Inc. SML-LXT0805GW-TR www.lumex.com

D24 – D26, D33

D10 Red LED Lumex Inc. SML-LXT0805IW-TR www.lumex.com

D30 Blue LED Lumex Inc. SML-LX0805USBC-TR www.lumex.com

Setup Elements

The starter board includes several different kinds of setup elements. This section describes the following setup elements:

■ Board settings DIP switch

■ JTAG settings DIP switch

■ PCI Express control DIP switch

■ CPU reset push button

■ MAX V reset push button

■ Image load push button

■ Image select push button

Tab le 2 –1 0 lists the switch and push button component references and manufacturing

information.

Table 2–10. Switch and Push Button Component References and Manufacturing Information

Board

Reference

Description Manufacturer

SW1, SW2, SW4 Four-position DIP switch

C&K Components/ ITT Industries

Manufacturer

Part Number

TDA04H0SB1 www.ittcannon.com

S1–S4 Push button Panasonic EVQPAC07K www.panasonic.com

Website

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–18 Chapter 2: Board Components

Setup Elements

Board Settings DIP Switch

The board settings DIP switch (SW4) controls various features specific to the board and the MAX V CPLD 5M2210 System Controller logic design. Table 2–11 lists the switch controls and descriptions.

Table 2–11. Board Settings DIP Switch Controls

Switch Schematic Signal Name Description Default

CLK_SEL

CLK_EN

FACTORY_LOAD

SECURITY

ON: Select SMA input clock

OFF: Select programmable oscillator clock

ON: Disable On-board oscillator

OFF: Enable On-board oscillator

ON: Load the user design from flash at power up.

OFF: Load the factory design from flash for Arria V at power up.

Reserved for future use. OFF

OFF

JTAG Chain Control DIP Switch

The JTAG chain control DIP switch (SW2) either remove or include devices in the active JTAG chain. The Arria V GX is always in the JTAG chain. Table 2–12 lists the switch controls and its descriptions.

Table 2–12. JTAG Chain Control Switch

Switch Schematic Signal Name Description Default

5M2210_JTAG_EN

HSMA_JTAG_EN

PCIE_JTAG_EN

ON : Bypass MAX V CPLD 5M2210 System Controller

OFF : MAX V CPLD 5M2210 System Controller in-chain

ON : Bypass HSMA

OFF : HSMA in-chain

ON : Bypass PCI Express edge connector

OFF : PCI Express edge connector in-chain

Not used ON

OFF

PCI Express Link Width DIP Switch

The PCI Express link width DIP switch (SW1) enable or disable different link width configurations. Table 2–13 lists the switch controls and descriptions.

Table 2–13. PCI Express Link Width DIP Switch Controls (Part 1 of 2)

Switch Schematic Signal Name Description Default

PCIE_PRSNT2n_x1

PCIE_PRSNT2n_x4

ON : Enable x1 presence detect

OFF : Disable x1 presence detect

ON : Enable x4 presence detect

OFF : Disable x4 presence detect

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–19

Setup Elements

Table 2–13. PCI Express Link Width DIP Switch Controls (Part 2 of 2)

Switch Schematic Signal Name Description Default

PCIE_PRSNT2n_x8

FAN_FORCE_ON

ON : Enable x8 presence detect

OFF : Disable x8 presence detect

ON : Enable fan

OFF : Disable fan

OFF

CPU Reset Push Button

The CPU reset push button, pin and is an open-drain I/O from the MAX V CPLD System Controller. This push button is the default reset for both the FPGA and CPLD logic. The MAX V CPLD 5M2210 System Controller also drives this push button during power-on-reset (POR).

MAX V Reset Push Button

The MAX V reset push button, 5M2210 System Controller. This push button is the default reset for the CPLD logic.

Image Load Push Button

The image load push button, 5M2210 System Controller. This input forces a FPGA reconfiguration from the flash memory. The location in the flash memory is based on the settings of which is controlled by the image select push button,

PGM_LED0, PGM_LED1

FPGA designs.

, or

Image Select Push Button

The program select push button, Controller. This push button toggles the location in the flash memory is used to configure the FPGA. Refer to Tabl e 2– 7 for the

PGM_LED[2:0]

sequence definitions.

CPU_RESETn

MAX_RESETn

PGM_CONFIG

PGM_LED2

(S4), is an input to the Arria V GX

(S3), is an input to the MAX V CPLD

(S1), is an input to the MAX V CPLD

PGM_SEL

on the three pages in flash memory reserved for

PGM_SEL

(S2), is an input to the MAX V CPLD System

PGM_LED[2:0]

. Valid settings include

sequence that selects which

DEV_CLRn

PGM_LED[2:0]

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2–20 Chapter 2: Board Components

SMA

Bank Top

CH0 125 MHz

CH1 409.6 MHz

CH2 156.25 MHz

CH3 100 MHz

Si5338

x4 LVDS Output

Bank Bottom

Bank L1

Bank R1

2 Unused Channels

HSMC x8

HDMI x3

SMA x1 SDI x1

PCIe x8

Enet

DDR3 x32 UniOHY, User I/O

User I/O, HSMC VIO, Enet, HDMI

Bank R0

IDT5T9306

Clock Fan-Out

x4 LVDS

NB6L11SMNG

Clock Fan-Out

x2 LVDS

100 MHz

CH0

Si5338

CH2

Si5338

Si511

125.0 MHz LVDS Fixed Oscillator

Si510 SE

50 MHz Fixed

Oscillator

Si510 SE

50 MHz Fixed

Oscillator

SL18860DC Clock Fan-Out x4 SE 50 MHz

MAX V CPLD

System Controller

Arria V FPGA

FA-128

24.0 MB-W

24 MHz XTAL

CY7C68013A

USB

Microcontroller

MAX II CPLD

Embedded

USB-Blaster

10/100/1000

Base-T

Ethernet PHY

88E1111

SG-310DF

25.0 M-B3 25 MHz

Fixed Oscillator

Bank

Si571

LVDS VCXO

148.5 MHz and

148.35 MHz

Tr igger Out

SMA

LVPECL

Clock input

Clock Circuitry

This section describes the board's clock inputs and outputs.

On-Board Oscillators

The starter board includes programmable oscillators with a frequency of 100-MHz, 125-MHz, 156.25-MHz, and 409.60-MHz.

Figure 2–7 shows the default frequencies of all external clocks going to the Arria V GX

starter board.

Figure 2–7. Arria V GX Starter Board Clocks

Table 2–14. On-Board Oscillators

Source Schematic Signal Name Frequency I/O Standard

Tab le 2 –1 4 lists the oscillators, its I/O standard, and voltages required for the starter

board.

CLKIN_50_TOP

CLKIN_50_BOT

CLKIN_50_MAXV

CLLK_CONFIG

50.000 MHz 2.5V CMOS

100.000 MHz 2.5V CMOS — Fast FPGA configuration

Arria V GX Pin

Number

A16

AP29

—

Application

Nios II and MAX V

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–21

Clock Circuitry

Table 2–14. On-Board Oscillators

Source Schematic Signal Name Frequency I/O Standard

REFCLK2_QL1_P

REFCLK2_QL1_N

CLKINBOT_125_P

CLKINBOT_125_N

CLKINTOP_125_P

125.000 MHz

LVDS

(fanout buffer)

CLKINTOP_125_N

REFCLK2_QR1_P

REFCLK2_QR1_N

CLK_125_P

CLK_125_N

CLK_148_P

CLK_148_N

Si5338A_CLK0_125_P

Si5338A_CLK0_125_N

REFCLK1_QL0_P

REFCLK1_QL0_N

REFCLK1_QR0_P

REFCLK1_QR0_N

Si5338A_CLK3_100_P

Si5338A_CLK3_100_N

CLKINTOP_100_P

CLKINTOP_100_N

CLKINBOT_100_P

CLKINBOT_100_N

125.000 MHz LVDS

148.500 MHz LVDS

125.000 MHz

LVDS

(fanout buffer)

409.600 MHz LVDS

156.250 MHz LVDS

100.000 MHz

LVDS

(fanout buffer)

LVDS

100.000 MHz

LVDS

Arria V GX Pin

Number

U26

U27

AP32

AP31

AH17

AG17

R26

R27

—

W26

W27

—

A19

A20

AH18

AG18

Application

Left transceiver bank

Bottom edge

Top edge

HSMC port A

10/100/1000 Ethernet

HD-SDI video

LVDS fanout buffer

SMA

HSMC port A

LVDS fanout buffer

Top edge—DDR3

Bottom edge

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2–22 Chapter 2: Board Components

Clock Circuitry

Off-Board Clock Input/Output

The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.

Tab le 2 –1 5 lists the clock inputs for the starter board.

Table 2–15. Off-Board Clock Inputs

Source

SMA

Samtec HSMC

PCI Express Edge

Schematic Signal

Name

CLKIN_SMA_P

CLKIN_SMA_N

HSMA_CLK_IN0

HSMA_CLK_IN_P1

HSMA_CLK_IN_N1

HSMA_CLK_IN_P2

HSMA_CLK_IN_N2

REFCLK3_QR1_P

REFCLK3_QR1_N

PCIE_REFCLK_P

PCIE_REFCLK_N

Tab le 2 –1 6 lists the clock outputs for the starter board.

Table 2–16. Off-Board Clock Outputs

Source

Samtec HSMC

SMA

Schematic Signal

Name

HSMA_CLK_OUT0

HSMA_CLK_OUT_P1

HSMA_CLK_OUT_N1

HSMA_CLK_OUT_P2

HSMA_CLK_OUT_N2

CLKOUT_SMA

I/O Standard

LVPECL —

2.5-V AL5

LVDS/2.5-V AN3

LVDS/LVTTL AP2

LVDS/LVTTL C1

LVDS/LVTTL C2

LVDS R9

HCSL R8

LVDS AA27

HCSL AA28

I/O Standard

2.5V CMOS AL6 FPGA CMOS output (or GPIO)

LVDS/2.5V CMOS AD8

LVDS/2.5V CMOS AC8

LVDS/2.5V CMOS L9

LVDS/2.5V CMOS M8

2.5V CMOS C3 FPGA CMOS output (or GPIO)

Arria V GX

Pin Number

Arria V GX

Pin Number

Description

Input to LVDS fan-out buffer (drives one REFCLK)

Single-ended input from the installed HSMC cable or board.

LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs.

LVDS input from the installed HSMC cable or board.

LVDS input from the PCI Express edge connector.

Description

LVDS output. Can also support 2x CMOS outputs.

Tab le 2 –1 7 lists the crystal oscillators component references and manufacturing

information.

Table 2–17. Crystal Oscillator Component References and Manufacturing Information

Board

Reference

Programmable LVDS

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

quad-clock 125M, 409.6M,

156.25M, 100M defaults

148.50 MHz LVDS voltage controlled crystal oscillator

Description Manufacturer

Silicon Labs Si5338A-A01343-GM www.silabs.com

Silicon Labs 571FDB000159DG www.silabs.com

Manufacturer

Part Number

Manufacturer Website

Chapter 2: Board Components 2–23

General User Input/Output

Table 2–17. Crystal Oscillator Component References and Manufacturing Information

Board

Reference

100 MHz crystal oscillator, ±50 ppm, CMOS, 2.5 V

50 MHz crystal oscillator, ±50 ppm, CMOS, 2.5 V

125 MHz crystal oscillator, ±50 ppm, LVDS, 2.5 V

Description Manufacturer

General User Input/Output

This section describes the user I/O interface to the FPGA, including the push buttons, DIP switches, LEDs, and character LCD.

User-Defined Push Buttons

The starter board includes three user-defined push buttons. For information on the system and safe reset push buttons, refer to “Setup Elements” on page 2–17.

Board references S5, S6, and S7 are push buttons that allow you to interact with the Arria V GX. When you press and hold down the switch, the device pin is set to logic 0; when you release the switch, the device pin is set to logic 1. There are no board-specific functions for these general user push buttons.

Manufacturer

Part Number

Silicon Labs 510GBA100M000BAGx www.silabs.com

Silicon Labs 510GBA50M0000BAGx www.silabs.com

Silicon Labs 511FBA125M000BAGx www.silabs.com

Manufacturer Website

Tab le 2 –1 8 lists the user-defined push button schematic signal names and their

corresponding Arria V GX device pin numbers.

Table 2–18. User-Defined Push Button Schematic Signal Names and Functions

Board Reference

Schematic Signal

Name

USER_PB0

USER_PB1

USER_PB2

Arria V GX Pin

Number

A14 2.5-V

B15 2.5-V

B14 2.5-V

I/O Standard Description

User-defined push buttonsS6

Tab le 2 –1 9 lists the user-defined push button component reference and the

manufacturing information.

Table 2–19. User-Defined Push Button Component Reference and Manufacturing Information

Board Reference Description Manufacturer

S5 to S7 Push button Dawning Precision Co. TS-A02SA-2-S100 www.dawning2.com.tw

Manufacturer

Part Number

Manufacturer Website

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2–24 Chapter 2: Board Components

General User Input/Output

User-Defined DIP Switch

Board reference SW3 is a four-pin DIP switch. This switch is user-defined and provides additional FPGA input control. There are no board-specific functions for this switch.

Tab le 2 –2 0 lists the user-defined DIP switch schematic signal names and their

corresponding Arria V GX pin numbers.

Table 2–20. User-Defined DIP Switch Schematic Signal Names and Functions

Board Reference

(SW3)

Schematic

Signal Name

USER_DIPSW0

USER_DIPSW1

USER_DIPSW2

USER_DIPSW3

Arria V GX

Pin Number

D15 2.5-V

D14 2.5-V

D13 2.5-V

E15 2.5-V

I/O Standard Description

User-defined DIP switch that connects to the FPGA. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected.

Tab le 2 –2 1 lists the user-defined DIP switch component reference and the

manufacturing information.

Table 2–21. User-Defined DIP Switch Component Reference and Manufacturing Information

Board

Reference

SW3 Four-position DIP switch

Description Manufacturer

C&K Components/ ITT

Industries

Manufacturer

Part Number

TDA04H0SB1 www.ittcannon.com

User-Defined LEDs

The starter board includes general and HSMC user-defined LEDs. This section describes all user-defined LEDs. For information on board specific or status LEDs, refer to “Status Elements” on page 2–16.

Manufacturer Website

General LEDs

Board references D20 through D23 are four user-defined LEDs. The status and debugging signals are driven to the LEDs from the designs loaded into the Arria V GX. There are no board-specific functions for these LEDs.

Tab le 2 –2 2 lists the general LED schematic signal names and their corresponding

Arria V GX pin numbers.

Table 2–22. General LED Schematic Signal Names and Functions

Board Reference

D20

D21

D22

D23

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Schematic

Signal Name

USER_LED0

USER_LED1

USER_LED2

USER_LED3

Arria V GX

Pin Number

C16 2.5-V

C14 2.5-V

C13 2.5-V

D16 2.5-V

I/O Standard Description

User-defined LEDs. Driving a logic 0 on the I/O port turns the LED ON. Driving a logic 1 on the I/O port turns the LED OFF.

Chapter 2: Board Components 2–25

General User Input/Output

Tab le 2 –2 3 lists the general LED component reference and the manufacturing

information.

Table 2–23. General LED Component Reference and Manufacturing Information

Board Reference Device Description Manufacturer

D20 to D23 Green LEDs Lumex Inc. SML-LXT0805GW-TR www.lumex.com

Manufacturer

Part Number

Manufacturer Website

HSMC LEDs

Each HSMC port has two LEDs located nearby. There are no board-specific functions for the HSMC LEDs. The LEDs are labeled TX and RX, and are intended to display data flow to and from the connected HSMC daughtercards. The LEDs are driven by the Arria V GX.

Tab le 2 –2 4 lists the HSMC LED schematic signal names and their corresponding

Arria V GX pin numbers.

Table 2–24. HSMC LED Schematic Signal Names and Functions

Board Reference

D13

D14

Schematic

Signal Name

HSMA_RX_LED

HSMA_TX_LED

Tab le 2 –2 5 lists the HSMC LED component reference and the manufacturing

information.

Arria V GX

Pin Number

D8 2.5-V

D9 2.5-V

I/O Standard Description

User-defined LEDs. Labeled RX for HSMC port A.

User-defined LEDs. Labeled TX for HSMC port A.

Table 2–25. HSMC LED Component Reference and Manufacturing Information

Board Reference Description Manufacturer

D13, D14 Green LEDs Lumex Inc. SML-LXT0805GW-TR www.lumex.com

Manufacturer

Part Number

Manufacturer Website

PCI Express LEDs

Board references D16 through D19 are four PCI Express LEDs for link width indication. There are no board-specific functions for the PCI Express LEDs. You can configure the LEDs to display the functions as listed in Table 2–26. The LEDs are driven by the Arria V GX.

Tab le 2 –2 6 lists the PCI Express LED schematic signal names and their corresponding

Arria V GX GX pin numbers.

Table 2–26. PCI Express LED Schematic Signal Names and Functions

Board

Reference

D16

D17

Schematic

Signal Name

PCIE_LED_X1

PCIE_LED_X4

Arria V GX

Pin Number

G17 2.5-V

G16 2.5-V

I/O Standard Description

Green LED. Configure this LED to display the PCI Express link width x1.

Green LED. Configure this LED to display the PCI Express link width x4.

November 2013 Altera Corporation Arria V GX Starter Board

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2–26 Chapter 2: Board Components

General User Input/Output

Table 2–26. PCI Express LED Schematic Signal Names and Functions

Board

Reference

D18

D19

Schematic

Signal Name

PCIE_LED_X8

PCIE_LED_G2

Arria V GX

Pin Number

G15 2.5-V

F17 2.5-V

I/O Standard Description

Green LED. Configure this LED to display the PCI Express link width x8.

Green LED. Configure this LED to display the PCI Express Gen2 link.

Tab le 2 –2 5 lists the PCI Express LED component reference and the manufacturing

information.

Table 2–27. PCI Express LED Component Reference and Manufacturing Information

Board Reference Description Manufacturer

D16 to D19 Yellow LEDs Lumex Inc. SML-LXT0805YW-TR www.lumex.com

Manufacturer

Part Number

Manufacturer Website

Character LCD

The starter board includes a single 14-pin 0.1" pitch dual-row header that interfaces to a 16 character × 2 line Lumex character LCD display. The character LCD has a 14-pin receptacle that mounts directly to the board's 14-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging or other purposes.

Tab le 2 –2 8 summarizes the character LCD pin assignments. The signal names and

directions are relative to the Arria V GX.

Table 2–28. Character LCD Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J16)

Schematic Signal Name

LCD_DATA0

LCD_DATA1

LCD_DATA2

LCD_DATA3

LCD_DATA4

LCD_DATA5

LCD_DATA6

LCD_DATA7

LCD_D_Cn

LCD_WEn

LCD_CSn

Arria V GX

Pin Number

C19 2.5-V LCD data bus

D19 2.5-V LCD data bus

D18 2.5-V LCD data bus

D17 2.5-V LCD data bus

E17 2.5-V LCD data bus

G19 2.5-V LCD data bus

E18 2.5-V LCD data bus

F19 2.5-V LCD data bus

B18 2.5-V LCD data or command select

C17 2.5-V LCD write enable

B17 2.5-V LCD chip select

I/O Standard Description

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Chapter 2: Board Components 2–27

Components and Interfaces

Tab le 2 –2 9 lists the LCD pin definitions, and is an excerpt from Lumex data sheet.

Table 2–29. LCD Pin Definitions and Functions

Number

Symbol

Level

—

—GND (0 V)

Power supply

— For LCD drive

4RS H/L

H: Data input

L: Instruction input

5R/W H/L

H: Data read (module to MPU)

L: Data write (MPU to module)

6 E H, H to L Enable

7–14 DB0–DB7 H/L Data bus—software selectable 4-bit or 8-bit mode

f For more information such as timing, character maps, interface guidelines, and other

related documentation, visit www.lumex.com.

Tab le 2 –3 0 lists the LCD component references and the manufacturing information.

Table 2–30. LCD Component References and Manufacturing Information

Board

Reference

J16

2×7 pin, 100 mil, vertical header Samtec TSM-107-07-G-D www.samtec.com

2×16 character display, 5×8 dot matrix Lumex Inc. LCM-S01602DSR/C www.lumex.com

Description Manufacturer

Function

Manufacturer

Part Number

5 V

Manufacturer

Website

Components and Interfaces

This section describes the starter board's communication ports and interface cards relative to the Arria V GX. The development board supports the following communication ports:

■ PCI Express

■ 10/100/1000 Ethernet

■ HSMC

■ SDI video output/input

■ HDMI video output

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2–28 Chapter 2: Board Components

MAX

= 1.15 V

CROSS MAX

= 550 mV

CROSS MIN

= 250 mV

MIN

= –0.30 V

REFCLK –

REFCLK +

Components and Interfaces

PCI Express

The Arria V GX starter board is designed to fit entirely into a PC motherboard with a ×8 PCI Express slot that can accommodate a full height long form factor add-in card. This interface uses the Arria V GX's PCI Express hard IP block, saving logic resources for the user logic application.

f For more information on using the PCI Express hard IP block, refer to the PCI Express

Compiler User Guide.

The PCI Express edge connector has a connection speed of 2.5 Gbps/lane for a maximum of 20 Gbps full-duplex (Gen1) or 5.0 Gbps/lane for a maximum of 40 Gbps full-duplex (Gen2).

The power for the board can be sourced entirely from the PCI Express edge connector when installed into a PC motherboard. Although the board can also be powered by a laptop power supply for use on a lab bench, it is not recommended to power from both supplies at the same time. Ideal diode power sharing devices have been designed into this board to prevent damages or back-current from one supply to the other.

The

PCIE_REFCLK_P/N

motherboard on to this board through the edge connector. This signal connects directly to a Arria V GX terminated on the motherboard and therefore, no on-board termination is required. This clock can have spread-spectrum properties that change its period between

9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL).

signal is a 100 MHz differential input that is driven from the PC

REFCLK

input pin pair using DC coupling. This clock is

Figure 2–8 shows the PCI Express reference clock levels.

Figure 2–8. PCI Express Reference Clock Levels

The JTAG and SMB are optional signals in the PCI Express specification. Both types of signals are wired to the Arria V GX but are not required for normal operation. The PCI Express control DIP switch allows the presence detect grounding to be altered to enable a ×1, ×4, or ×8 width edge connector. The PCI Express control DIP switch does not support auto-negotiation.

The PCI express edge connector has a presence detect feature to allow the motherboard to determine if a card is installed. A DIP switch provides an option to connect the

PRSNT1n

pin to any of the three

PRSNT2n

pins found within the ×8 connector definition. This is to address issues on some PC systems that would base the link width capability on the presence detect pins versus a query operation.

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Chapter 2: Board Components 2–29

Components and Interfaces

Tab le 2 –3 1 summarizes the PCI Express pin assignments. The signal names and

directions are relative to the Arria V GX.

Table 2–31. PCI Express Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J1)

A11

B17

B31

B48

A13

A14

B14

B15

B19

B20

B23

B24

B27

B28

B33

B34

B37

B38

B41

B42

B45

B46

A16

A17

A21

A22

A25

A26

A29

Schematic Signal Name

PCIE_JTAG_TCK

PCIE_JTAG_TDI

PCIE_JTAG_TDO

PCIE_JTAG_TMS

PCIE_PERSTN

PCIE_PRSNT1N

PCIE_PRSNT2N_X1

PCIE_PRSNT2N_X4

PCIE_PRSNT2N_X8

PCIE_REFCLK_P

PCIE_REFCLK_N

PCIE_RX_P0

PCIE_RX_N0

PCIE_RX_P1

PCIE_RX_N1

PCIE_RX_P2

PCIE_RX_N2

PCIE_RX_P3

PCIE_RX_N3

PCIE_RX_P4

PCIE_RX_N4

PCIE_RX_P5

PCIE_RX_N5

PCIE_RX_P6

PCIE_RX_N6

PCIE_RX_P7

PCIE_RX_N7

PCIE_SMBCLK

PCIE_SMBDAT

PCIE_TX_CP0

PCIE_TX_CN0

PCIE_TX_CP1

PCIE_TX_CN1

PCIE_TX_CP2

PCIE_TX_CN2

PCIE_TX_CP3

Arria V GX

Pin Number

I/O Standard Description

— LVTTL JTAG chain clock

— LVTTL JTAG chain data in

— LVTTL JTAG chain data out

— LVTTL JTAG chain mode select

B2 LVTTL Reset

— LVTTL Link width DIP switch

AA27 HCSL Motherboard reference clock

AA28 HCSL Motherboard reference clock

AK34 1.5-V PCML Receive bus

AK33 1.5-V PCML Receive bus

AH34 1.5-V PCML Receive bus

AH33 1.5-V PCML Receive bus

AF34 1.5-V PCML Receive bus

AF33 1.5-V PCML Receive bus

AD34 1.5-V PCML Receive bus

AD33 1.5-V PCML Receive bus

Y34 1.5-V PCML Receive bus

Y33 1.5-V PCML Receive bus

V34 1.5-V PCML Receive bus

V33 1.5-V PCML Receive bus

T34 1.5-V PCML Receive bus

T33 1.5-V PCML Receive bus

P34 1.5-V PCML Receive bus

P33 1.5-V PCML Receive bus

F16 2.5-V SMB clock

F14 2.5-V SMB data

AJ32 1.5-V PCML Transmit bus

AJ31 1.5-V PCML Transmit bus

AG32 1.5-V PCML Transmit bus

AG31 1.5-V PCML Transmit bus

AE32 1.5-V PCML Transmit bus

AE31 1.5-V PCML Transmit bus

AC32 1.5-V PCML Transmit bus

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2–30 Chapter 2: Board Components

10/100/1000 Mbps

Ethernet MAC

Marvell 88E1111

PHY

Device

Transformer

RJ45

RGMII Interface

TXD[3:0]

RXD[3:0]

CAT 5 UTP:

- 10BASE-T

- 100BASE-TX

- 1000BASE-T

Components and Interfaces

Table 2–31. PCI Express Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J1)

A30

A35

A36

A39

A40

A43

A44

A47

A48

B11

10/100/1000 Ethernet

Schematic Signal Name

PCIE_TX_CN3

PCIE_TX_CP4

PCIE_TX_CN4

PCIE_TX_CP5

PCIE_TX_CN5

PCIE_TX_CP6

PCIE_TX_CN6

PCIE_TX_CP7

PCIE_TX_CN7

PCIE_WAKEN

Arria V GX

Pin Number

I/O Standard Description

AC31 1.5-V PCML Transmit bus

W32 1.5-V PCML Transmit bus

W31 1.5-V PCML Transmit bus

U32 1.5-V PCML Transmit bus

U31 1.5-V PCML Transmit bus

R32 1.5-V PCML Transmit bus

R31 1.5-V PCML Transmit bus

N32 1.5-V PCML Transmit bus

N31 1.5-V PCML Transmit bus

E14 2.5-V Wake signal

The starter board supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The PHY-to-MAC interface employs a RGMII interface to the Arria V GX. The MAC function must be provided in the FPGA for typical networking applications.

The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. The PHY interfaces to a Wurth Elektronik model RJ45 with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Figure 2–9 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111

PHY.

Figure 2–9. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY

Tab le 2 –3 2 lists the Ethernet PHY interface pin assignments.

Table 2–32. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference (U20)

Schematic Signal Name

ENET_INTN

ENET_MDC

ENET_MDIO

ENET_RESETN

ENET_RX_CLK

Arria V GX

Pin Number

I/O Standard Description

AG11 2.5-V CMOS Management bus interrupt

AJ11 2.5-V CMOS Management bus data clock

AH11 2.5-V CMOS Management bus data

AL11 2.5-V CMOS Device reset

AL4 2.5-V CMOS RGMII receive clock

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–31

Components and Interfaces

Table 2–32. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board

Reference (U20)

Schematic Signal Name

ENET_RX_D0

ENET_RX_D1

ENET_RX_D2

ENET_RX_D3

ENET_RX_DV

ENET_RX_P

ENET_RX_N

ENET_TX_D0

ENET_TX_D1

ENET_TX_D2

ENET_TX_D3

ENET_TX_EN

ENET_GTX_CLK

ENET_TX_P

ENET_TX_N

Arria V GX

Pin Number

AF11 2.5-V CMOS RGMII receive data

AF13 2.5-V CMOS RGMII receive data

AE12 2.5-V CMOS RGMII receive data

AE13 2.5-V CMOS RGMII receive data

AB13 2.5-V CMOS RGMII receive data valid

AP14 LVDS SGMII receive channel

AN14 LVDS SGMII receive channel

AC11 2.5-V CMOS RGMII transmit data

AC12 2.5-V CMOS RGMII transmit data

AC13 2.5-V CMOS RGMII transmit data

AB11 2.5-V CMOS RGMII transmit data

AB12 2.5-V CMOS RGMII transmit enable

AD12 2.5-V CMOS RGMII transmit clock

AP13 LVDS SGMII transmit channel

AN12 LVDS SGMII transmit channel

I/O Standard Description

Tab le 2 –3 3 lists the Ethernet PHY interface component reference and manufacturing

information.

Table 2–33. Ethernet PHY Component Reference and Manufacturing Information

Board

Reference

U20 Ethernet PHY BASE-T device

J19 RJ-45 connector,10/100/1000 Mbps Wurth Elektronik 7499111001A www.we-online.com

Description Manufacturer

Marvell Semiconductor

Manufacturing

Part Number

88E1111-B2-CAA1C000 www.marvell.com

Manufacturer

Website

HSMC

The starter board contains a HSMC interface (Port A). This physical interface provides eight channels of 6.5536 Gbps-capable transceivers. The HSMC interface also supports a full SPI4.2 interface (17 LVDS channels), three input and output clocks, as well as JTAG and SMB signals. The LVDS channels can be used for CMOS signaling or LVDS.

1 The HSMC is an Altera-developed open specification, which allows you to expand

the functionality of the development board through the addition of daughtercards (HSMCs).

f For more information about the HSMC specification such as signaling standards,

signal integrity, compatible connectors, and mechanical information, refer to the High

Speed Mezzanine Card (HSMC) Specification manual.

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–32 Chapter 2: Board Components

Components and Interfaces

The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins, and 13 ground pins. The ground pins are located between the two rows of signal and power pins, acting both as a shield and a reference. The HSMC host connector is based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board connectors from Samtec. There are three banks in this connector. Bank 1 has every third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have all the pins populated as done in the QSH/QTH series.

Figure 2–10 shows the bank arrangement of signals with respect to the Samtec

connector's three banks.

Figure 2–10. HSMC Signal and Bank Diagram

Bank 3

Powe r

D(79.40)

-or-

LVDS

CLKIN2, CLKOUT2

Bank 2

Powe r

D(39:0)

-or-

D[3:0] + LVDS

CLKIN1, CLKOUT1

Bank 1

8 TX Channels CDR

8 RX Channels CDR

JTAG

SMB

CLKIN0, CLKOUT0

The HSMC interface has programmable bidirectional I/O pins that can be used as 2.5V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to, LVDS, mini-LVDS, and RSDS with up to 17 full-duplex channels.

1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and

single-ended I/O standards are only guaranteed to function when mixed according to either the generic single-ended pin-out or generic differential pin-out.

Tab le 2 –3 4 lists the HSMC port A interface pin assignments, signal names, and

functions.

Table 2–34. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference (J13)

Schematic Signal Name

HSMA_TX_P7

HSMA_RX_P7

HSMA_TX_N7

HSMA_RX_N7

HSMA_TX_P6

HSMA_RX_P6

HSMA_TX_N6

Arria V GX

Pin Number

I/O Standard Description

AA3 1.5-V PCML Transceiver TX bit 7

AB1 1.5-V PCML Transceiver RX bit 7

AA4 1.5-V PCML Transceiver TX bit 7n

AB2 1.5-V PCML Transceiver RX bit 7n

W3 1.5-V PCML Transceiver TX bit 6

Y1 1.5-V PCML Transceiver RX bit 6

W4 1.5-V PCML Transceiver TX bit 6n

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–33

Components and Interfaces

Table 2–34. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference (J13)

Schematic Signal Name

HSMA_RX_N6

HSMA_TX_P5

HSMA_RX_P5

HSMA_TX_N5

HSMA_RX_N5

HSMA_TX_P4

HSMA_RX_P4

HSMA_TX_N4

HSMA_RX_N4

HSMA_TX_P3

HSMA_RX_P3

HSMA_TX_N3

HSMA_RX_N3

HSMA_TX_P2

HSMA_RX_P2

HSMA_TX_N2

HSMA_RX_N2

HSMA_TX_P1

HSMA_RX_P1

HSMA_TX_N1

HSMA_RX_N1

HSMA_TX_P0

HSMA_RX_P0

HSMA_TX_N0

HSMA_RX_N0

HSMA_SDA

HSMA_SCL

JTAG_TCK

HSMA_JTAG_TMS

HSMA_JTAG_TDO

JTAG_FPGA_TDO_RETIMER

HSMA_CLK_OUT0

HSMA_CLK_IN0

HSMA_D0

HSMA_D1

HSMA_D2

HSMA_D3

HSMA_TX_D_P0

HSMA_RX_D_P0

Arria V GX

Pin Number

I/O Standard Description

Y2 1.5-V PCML Transceiver RX bit 6n

U3 1.5-V PCML Transceiver TX bit 5

V1 1.5-V PCML Transceiver RX bit 5

U4 1.5-V PCML Transceiver TX bit 5n

V2 1.5-V PCML Transceiver RX bit 5n

R3 1.5-V PCML Transceiver TX bit 4

T1 1.5-V PCML Transceiver RX bit 4

R4 1.5-V PCML Transceiver TX bit 4n

T2 1.5-V PCML Transceiver RX bit 4n

N3 1.5-V PCML Transceiver TX bit 3

P1 1.5-V PCML Transceiver RX bit 3

N4 1.5-V PCML Transceiver TX bit 3n

P2 1.5-V PCML Transceiver RX bit 3n

L3 1.5-V PCML Transceiver TX bit 2

M1 1.5-V PCML Transceiver RX bit 2

L4 1.5-V PCML Transceiver TX bit 2n

M2 1.5-V PCML Transceiver RX bit 2n

J3 1.5-V PCML Transceiver TX bit 1

K1 1.5-V PCML Transceiver RX bit 1

J4 1.5-V PCML Transceiver TX bit 1n

K2 1.5-V PCML Transceiver RX bit 1n

G3 1.5-V PCML Transceiver TX bit 0

H1 1.5-V PCML Transceiver RX bit 0

G4 1.5-V PCML Transceiver TX bit 0n

H2 1.5-V PCML Transceiver RX bit 0n

AK8 2.5-V CMOS Management serial data

AJ8 2.5-V CMOS Management serial clock

AN32 2.5-V CMOS JTAG clock signal

— 2.5-V CMOS JTAG mode select signal

— 2.5-V CMOS JTAG data output

— 2.5-V CMOS JTAG data input

AL6 2.5-V CMOS Dedicated CMOS clock out

AL5 2.5-V CMOS Dedicated CMOS clock in

AJ10 2.5-V CMOS Dedicated CMOS I/O bit 0

AH10 2.5-V CMOS Dedicated CMOS I/O bit 1

AH9 2.5-V CMOS Dedicated CMOS I/O bit 2

AH8 2.5-V CMOS Dedicated CMOS I/O bit 3

AM10 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4

AP11 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–34 Chapter 2: Board Components

Components and Interfaces

Table 2–34. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference (J13)

101

102

103

104

107

Schematic Signal Name

HSMA_TX_D_N0

HSMA_RX_D_N0

HSMA_TX_D_P1

HSMA_RX_D_P1

HSMA_TX_D_N1

HSMA_RX_D_N1

HSMA_TX_D_P2

HSMA_RX_D_P2

HSMA_TX_D_N2

HSMA_RX_D_N2

HSMA_TX_D_P3

HSMA_RX_D_P3

HSMA_TX_D_N3

HSMA_RX_D_N3

HSMA_TX_D_P4

HSMA_RX_D_P4

HSMA_TX_D_N4

HSMA_RX_D_N4

HSMA_TX_D_P5

HSMA_RX_D_P5

HSMA_TX_D_N5

HSMA_RX_D_N5

HSMA_TX_D_P6

HSMA_RX_D_P6

HSMA_TX_D_N6

HSMA_RX_D_N6

HSMA_TX_D_P7

HSMA_RX_D_P7

HSMA_TX_D_N7

HSMA_RX_D_N7

HSMA_CLK_OUT_P1

HSMA_CLK_IN_P1

HSMA_CLK_OUT_N1

HSMA_CLK_IN_N1

HSMA_TX_D_P8

HSMA_RX_D_P8

HSMA_TX_D_N8

HSMA_RX_D_N8

HSMA_TX_D_P9

Arria V GX

Pin Number

I/O Standard Description

AL10 LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6

AP10 LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7

AL9 LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8

AN8 LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9

AK9 LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10

AN9 LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11

AF10 LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12

AM8 LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13

AE10 LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14

AL8 LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15

AE9 LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16

AN11 LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17

AD9 LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18

AM11 LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19

AJ6 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20

AL12 LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21

AH6 LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22

AK12 LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23

AC6 LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24

AM13 LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25

AC7 LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26

AL13 LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27

AM4 LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28

AH12 LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29

AM3 LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30

AG12 LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31

AE6 LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32

AJ13 LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33

AD6 LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34

AH13 LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35

AD8 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36

AN3 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37

AC8 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38

AP2 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 39

G9 LVDS or 2.5-V LVDS TX bit 8 or CMOS bit 40

A13 LVDS or 2.5-V LVDS RX bit 8 or CMOS bit 41

H9 LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42

B12 LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43

J6 LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–35

Components and Interfaces

Table 2–34. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board

Reference (J13)

108

109

110

113

114

115

116

119

120

121

122

125

126

127

128

131

132

133

134

137

138

139

140

143

144

145

146

149

150

151

152

155

156

157

158

160

Schematic Signal Name

HSMA_RX_D_P9

HSMA_TX_D_N9

HSMA_RX_D_N9

HSMA_TX_D_P10

HSMA_RX_D_P10

HSMA_TX_D_N10

HSMA_RX_D_N10

HSMA_TX_D_P11

HSMA_RX_D_P11

HSMA_TX_D_N11

HSMA_RX_D_N11

HSMA_TX_D_P12

HSMA_RX_D_P12

HSMA_TX_D_N12

HSMA_RX_D_N12

HSMA_TX_D_P13

HSMA_RX_D_P13

HSMA_TX_D_N13

HSMA_RX_D_N13

HSMA_TX_D_P14

HSMA_RX_D_P14

HSMA_TX_D_N14

HSMA_RX_D_N14

HSMA_TX_D_P15

HSMA_RX_D_P15

HSMA_TX_D_N15

HSMA_RX_D_N15

HSMA_TX_D_P16

HSMA_RX_D_P16

HSMA_TX_D_N16

HSMA_RX_D_N16

HSMA_CLK_OUT_P2

HSMA_CLK_IN_P2

HSMA_CLK_OUT_N2

HSMA_CLK_IN_N2

HSMA_PRSNTn

Arria V GX

Pin Number

I/O Standard Description

A11 LVDS or 2.5-V LVDS RX bit 9 or CMOS bit 45

K6 LVDS or 2.5-V LVDS TX bit 9n or CMOS bit 46

B11 LVDS or 2.5-V LVDS RX bit 9n or CMOS bit 47

G8 LVDS or 2.5-V LVDS TX bit 10 or CMOS bit 48

E11 LVDS or 2.5-V LVDS RX bit 10 or CMOS bit 49

G7 LVDS or 2.5-V LVDS TX bit 10n or CMOS bit 50

F11 LVDS or 2.5-V LVDS RX bit 10n or CMOS bit 51

G6 LVDS or 2.5-V LVDS TX bit 11 or CMOS bit 52

F10 LVDS or 2.5-V LVDS RX bit 11 or CMOS bit 53

H6 LVDS or 2.5-V LVDS TX bit 11n or CMOS bit 54

G10 LVDS or 2.5-V LVDS RX bit 11n or CMOS bit 55

E1 LVDS or 2.5-V LVDS TX bit 12 or CMOS bit 56

C11 LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57

F1 LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58

D11 LVDS or 2.5-V LVDS RX bit 12n or CMOS bit 59

E5 LVDS or 2.5-V LVDS TX bit 13 or CMOS bit 60

A10 LVDS or 2.5-V LVDS RX bit 13 or CMOS bit 61

F6 LVDS or 2.5-V LVDS TX bit 13n or CMOS bit 62

B9 LVDS or 2.5-V LVDS RX bit 13n or CMOS bit 63

E8 LVDS or 2.5-V LVDS TX bit 14 or CMOS bit 64

C8 LVDS or 2.5-V LVDS RX bit 14 or CMOS bit 65

F7 LVDS or 2.5-V LVDS TX bit 14n or CMOS bit 66

D7 LVDS or 2.5-V LVDS RX bit 14n or CMOS bit 67

E9 LVDS or 2.5-V LVDS TX bit 15 or CMOS bit 68

A7 LVDS or 2.5-V LVDS RX bit 15 or CMOS bit 69

F8 LVDS or 2.5-V LVDS TX bit 15n or CMOS bit 70

A6 LVDS or 2.5-V LVDS RX bit 15n or CMOS bit 71

A8 LVDS or 2.5-V LVDS TX bit 16 or CMOS bit 72

B6 LVDS or 2.5-V LVDS RX bit 16 or CMOS bit 73

B8 LVDS or 2.5-V LVDS TX bit 16n or CMOS bit 74

C7 LVDS or 2.5-V LVDS RX bit 16n or CMOS bit 75

L9 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 76

C1 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77

M8 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78

C2 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79

J8 2.5-V CMOS HSMC port A presence detect

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–36 Chapter 2: Board Components

Components and Interfaces

Tab le 2 –3 5 lists the HSMC connector component reference and manufacturing

information.

Table 2–35. HSMC Connector Component Reference and Manufacturing Information

Board Reference Description Manufacturer

J13

HSMC, custom version of QSH-DP family high-speed socket.

Samtec ASP-122953-01 www.samtec.com

SDI Video Output/Input

The SDI video port consists of a LMH0303 cable driver and a LMH0384 cable equalizer. The PHY devices from National Semiconductor interface to single-ended 75-Ω SMB connectors.

The cable driver supports operation at 270 Mbit standard definition (SD), 1.5 Gbit high definition (HD), and 2.97 Gbit dual-link HD modes. Control signals are allowed for SD and HD modes selections, as well as device enable. The device can be clocked by the 148.5 MHz voltage-controlled crystal oscillator (VCXO) and matched to incoming signals within 50 ppm using the UP and DN voltage control lines to the VCXO.

Tab le 2 –3 6 lists the supported output standards for the SD and HD input.

Table 2–36. Supported Output Standards for SD and HD Input

SD_HD Input Supported Output Standards Rise TIme

0 SMPTE 424M, SMPTE 292M Faster

1 SMPTE 259M Slower

Manufacturing

Part Number

Manufacturer

Website

f For more information about the application circuit of the cable driver, refer to the

cable driver data sheet in www.national.com.

Tab le 2 –3 7 summarizes the SDI video output interface pin assignments, signal names,

and functions.

Table 2–37. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (U18)

SDI_TX_P

SDI_TX_N

SDI_TX_EN

SDI_SDA

SDI_SCL

SDI_TX_SD_HDN

SDI_FAULT

Schematic

Signal Name

Arria V GX

Pin Number

L32 1.5-V PCML SDI video output P

L31 1.5-V PCML SDI video output N

AC24 2.5-V Device enable

AJ28 2.5-V Cable driver I2C bus

AH28 2.5-V Cable driver I2C bus

AC25 2.5-V High-definition select

AJ29 2.5-V Data transmission fault

I/O Standard Description

The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and 2.97 Gbit dual-link HD modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute signal interface.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–37

BYPASS

MUTE

REF

1.0 μF

75 Ω

37.4 Ω

1.0 μF

SDI

SDO

MUTE

REF

BYPASS

AEC+

AEC–

75 Ω

MUTE

Coaxial Cable

SDI Adaptive

Cable Equalizer

To FPGA

5.6 nH

Components and Interfaces

Tab le 2 –3 8 lists the cable equalizer lengths.

Table 2–38. SDI Cable Equalizer Lengths

Data Rate (Mbps) Cable Type Maximum Cable Length (m)

270

1485 140

Belden 1694A

400

2970 120

Figure 2–11 is an excerpt from the LMH0384 cable equalizer data sheet that shows the

SDI cable equalizer. On this starter board, the output is a single-ended output, with the negative channel driving a load local to the board.

Figure 2–11. SDI Cable Equalizer

Tab le 2 –3 9 summarizes the SDI video input interface pin assignments, signal names,

and functions.

Table 2–39. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (U19)

November 2013 Altera Corporation Arria V GX Starter Board

SDI_RX_BYPASS

SDI_RX_EN

SDI_RX_P

SDI_RX_N

Schematic

Signal Name

Arria V GX

Pin Number

I/O Standard Description

AD24 2.5-V Equalizer bypass enable

AD23 2.5-V Device enable

M34 1.5-V PCML SDI video input P

M33 1.5-V PCML SDI video input N

Reference Manual

2–38 Chapter 2: Board Components

Components and Interfaces

Tab le 2 –4 0 lists the SDI connector component reference and manufacturing

information.

Table 2–40. SDI Connector Component Reference and Manufacturing Information

Board

Reference

U18

U19

Description Manufacturer

3-Gbps HD/SD SDI cable driver with cable detect

3-Gbps HD/SD SDI adaptive cable equalizer

National Semiconductor LMH0303SQx www.national.com

National Semiconductor LMH0384SQ www.national.com

Manufacturing

Part Number

HDMI Video Output

This starter board supports HDMI video (output only) using Arria V transceiver through the TMDS level shifter. This device is compliant with HDMI v1.3. The 2.7 Gbps operation supports television resolutions from 720p up to 1080p at 12-bit color depth and computer graphics outputs at up to UXGA, or 1600x1200.

f For more information about the HDMI video IP, visit www.bitec-dsp.com.

Tab le 2 –4 1 summarizes the HDMI video output TMDS level shifter pin assignments,

signal names, and functions.

Table 2–41. HDMI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions

Board Reference

(U16)

HDMI_FPGA_HPD

HDMI_FPGA_OE_N

HDMI_FPGA_SCL_DDC

HDMI_FPGA_SDA_DDC

HDMI_TX_P0

HDMI_TX_N0

HDMI_TX_P1

HDMI_TX_N1

HDMI_TX_P2

HDMI_TX_N2

HDMI_TX_CLK_P

HDMI_TX_CLK_N

Schematic

Signal Name

Arria V GX

Pin Number

AF8 2.5-V HDMI connector hot-plug detect

AC9 2.5-V Video output data or clock enable

AE11 2.5-V Management bus clock

AD11 2.5-V Management bus data

AJ3 1.5-V PCML Video output data

AJ4 1.5-V PCML Video output data

AG3 1.5-V PCML Video output data

AG4 1.5-V PCML Video output data

AE3 1.5-V PCML Video output data

AE4 1.5-V PCML Video output data

AC3 1.5-V PCML Video output clock

AC4 1.5-V PCML Video output clock

I/O Standard Description

Manufacturer

Website

Tab le 2 –4 0 lists the HDMI video output component reference and manufacturing

information.

Table 2–42. HDMI Video Output Component Reference and Manufacturing Information

Board

Reference

J10 19-pin HDMI connector Samtec HDMI-19-01-F-SM www.samtec.com

U16 TMDS level shifter ST Microelectronics STHDLS101T www.st.com

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

Chapter 2: Board Components 2–39

Memory

This section describes the starter board’s memory interface support and also their signal names, types, and connectivity relative to the Arria V GX. The starter board has the following memory interfaces:

■ DDR3 SDRAM

■ Synchronous SRAM

■ Synchronous flash

f For more information about the memory interfaces, refer to the following documents:

■ Timing Analysis section in volume 4 of the External Memory Interface Handbook.

■ DDR, DDR2, and DDR3 SDRAM Design Tutorials section in volume 6 of the

External Memory Interface Handbook.

DDR3 SDRAM

The starter board supports a 8Mx32x8 bank DDR3 SDRAM interface for very high-speed sequential memory access. The 32-bit data bus consists of two x16 devices with a single address or command bus. This interface connects to the vertical I/O banks on the top edge of the FPGA.

This DDR3 SDRAM has two interface options. The first option is a x32 interface using a hard memory controller. The second option is a x32 interface using a soft memory controller.

With a hard memory controller, this interface runs at the target frequency of 533 MHz for a maximum theoretical bandwidth of 33.31 Gbps. With a soft memory controller, this interface runs at the target frequency of 667 MHz for a maximum theoretical bandwidth of 41.66 Gbps. Though a soft memory controller runs at higher data rate than a hard memory controller, the hard memory controller operates at a much higher efficiency. The maximum frequency for the Micron device is 667 MHz with a CAS latency of 9.

Tab le 2 –4 3 lists the DDR3 pin assignments, signal names, and functions. The signal

names and types are relative to the Arria V GX in terms of I/O setting and direction.

Table 2–43. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board Reference

DDR3 x16 (U11)

Schematic

Signal Name

DDR3_A0

DDR3_A1

DDR3_A2

DDR3_A3

DDR3_A4

DDR3_A5

DDR3_A6

Arria V GX

Pin Number

D26 1.5-V SSTL Class I Address bus

E27 1.5-V SSTL Class I Address bus

A27 1.5-V SSTL Class I Address bus

B27 1.5-V SSTL Class I Address bus

G26 1.5-V SSTL Class I Address bus

H26 1.5-V SSTL Class I Address bus

K27 1.5-V SSTL Class I Address bus

I/O Standard Description

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–40 Chapter 2: Board Components

Memory

Table 2–43. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board Reference

Schematic

Signal Name

DDR3_A7

DDR3_A8

DDR3_A9

DDR3_A10

DDR3_A11

DDR3_A12

DDR3_A13

DDR3_BA0

DDR3_BA1

DDR3_BA2

DDR3_CASN

DDR3_CKE

DDR3_CLK_P

DDR3_CLK_N

DDR3_CSN

DDR3_DM0

DDR3_DM1

DDR3_DQ0

DDR3_DQ1

DDR3_DQ2

DDR3_DQ3

DDR3_DQ4

DDR3_DQ5

DDR3_DQ6

DDR3_DQ7

DDR3_DQ8

DDR3_DQ9

DDR3_DQ10

DDR3_DQ11

DDR3_DQ12

DDR3_DQ13

DDR3_DQ14

DDR3_DQ15

DDR3_DQS_P0

DDR3_DQS_N0

Arria V GX

Pin Number

I/O Standard Description

L27 1.5-V SSTL Class I Address bus

D27 1.5-V SSTL Class I Address bus

C28 1.5-V SSTL Class I Address bus

C29 1.5-V SSTL Class I Address bus

D28 1.5-V SSTL Class I Address bus

G27 1.5-V SSTL Class I Address bus

G28 1.5-V SSTL Class I Address bus

A29 1.5-V SSTL Class I Bank address bus

A28 1.5-V SSTL Class I Bank address bus

B29 1.5-V SSTL Class I Bank address bus

F28 1.5-V SSTL Class I Row address select

K29 1.5-V SSTL Class I Column address select

E26

F26

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential output clock

D30 1.5-V SSTL Class I Chip select

M25 1.5-V SSTL Class I Write mask byte lane

M23 1.5-V SSTL Class I Write mask byte lane

G24 1.5-V SSTL Class I Data bus byte lane 0

H24 1.5-V SSTL Class I Data bus byte lane 0

M24 1.5-V SSTL Class I Data bus byte lane 0

A26 1.5-V SSTL Class I Data bus byte lane 0

A25 1.5-V SSTL Class I Data bus byte lane 0

C25 1.5-V SSTL Class I Data bus byte lane 0

B26 1.5-V SSTL Class I Data bus byte lane 0

C26 1.5-V SSTL Class I Data bus byte lane 0

H23 1.5-V SSTL Class I Data bus byte lane 1

J23 1.5-V SSTL Class I Data bus byte lane 1

K24 1.5-V SSTL Class I Data bus byte lane 1

B24 1.5-V SSTL Class I Data bus byte lane 1

C23 1.5-V SSTL Class I Data bus byte lane 1

D23 1.5-V SSTL Class I Data bus byte lane 1

D24 1.5-V SSTL Class I Data bus byte lane 1

E24 1.5-V SSTL Class I Data bus byte lane 1

F25

G25

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 0

Data strobe N byte lane 0

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Chapter 2: Board Components 2–41

Memory

Table 2–43. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board Reference

DDR3 x16 (U10)

Schematic

Signal Name

DDR3_DQS_P1

DDR3_DQS_N1

DDR3_ODT

DDR3_RASN

DDR3_RESETN

DDR3_WEN

DDR3_ZQ01

DDR3_A0

DDR3_A1

DDR3_A2

DDR3_A3

DDR3_A4

DDR3_A5

DDR3_A6

DDR3_A7

DDR3_A8

DDR3_A9

DDR3_A10

DDR3_A11

DDR3_A12

DDR3_A13

DDR3_BA0

DDR3_BA1

DDR3_BA2

DDR3_CASN

DDR3_CKE

DDR3_CLK_N

DDR3_CLK_P

DDR3_CSN

DDR3_DM2

DDR3_DM3

DDR3_DQ16

DDR3_DQ17

DDR3_DQ18

DDR3_DQ19

DDR3_DQ20

Arria V GX

Pin Number

F23

G23

I/O Standard Description

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 1

Data strobe N byte lane 1

H27 1.5-V SSTL Class I On-die termination enable

B30 1.5-V SSTL Class I Row address select

K25 1.5-V SSTL Class I Reset

F29 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

D26 1.5-V SSTL Class I Address bus

E27 1.5-V SSTL Class I Address bus

A27 1.5-V SSTL Class I Address bus

B27 1.5-V SSTL Class I Address bus

G26 1.5-V SSTL Class I Address bus

H26 1.5-V SSTL Class I Address bus

K27 1.5-V SSTL Class I Address bus

L27 1.5-V SSTL Class I Address bus

D27 1.5-V SSTL Class I Address bus

C28 1.5-V SSTL Class I Address bus

C29 1.5-V SSTL Class I Address bus

D28 1.5-V SSTL Class I Address bus

G27 1.5-V SSTL Class I Address bus

G28 1.5-V SSTL Class I Address bus

A29 1.5-V SSTL Class I Bank address bus

A28 1.5-V SSTL Class I Bank address bus

B29 1.5-V SSTL Class I Bank address bus

F28 1.5-V SSTL Class I Row address select

K29 1.5-V SSTL Class I Column address select

F26 1.5-V SSTL Class I Differential output clock

E26 1.5-V SSTL Class I Differential output clock

D30 1.5-V SSTL Class I Chip select

M22 1.5-V SSTL Class I Write mask byte lane

K21 1.5-V SSTL Class I Write mask byte lane

D21 1.5-V SSTL Class I Data bus byte lane 2

E21 1.5-V SSTL Class I Data bus byte lane 2

M21 1.5-V SSTL Class I Data bus byte lane 2

C22 1.5-V SSTL Class I Data bus byte lane 2

D22 1.5-V SSTL Class I Data bus byte lane 2

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–42 Chapter 2: Board Components

Memory

Table 2–43. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board Reference

Schematic

Signal Name

DDR3_DQ21

DDR3_DQ22

DDR3_DQ23

DDR3_DQ24

DDR3_DQ25

DDR3_DQ26

DDR3_DQ27

DDR3_DQ28

DDR3_DQ29

DDR3_DQ30

DDR3_DQ31

DDR3_DQS_P2

DDR3_DQS_N2

DDR3_DQS_P3

DDR3_DQS_N3

DDR3_ODT

DDR3_RASN

DDR3_RESETN

DDR3_WEN

DDR3_ZQ2

Arria V GX

Pin Number

G21 1.5-V SSTL Class I Data bus byte lane 2

A23 1.5-V SSTL Class I Data bus byte lane 2

B23 1.5-V SSTL Class I Data bus byte lane 2

K20 1.5-V SSTL Class I Data bus byte lane 3

L20 1.5-V SSTL Class I Data bus byte lane 3

M20 1.5-V SSTL Class I Data bus byte lane 3

A22 1.5-V SSTL Class I Data bus byte lane 3

B21 1.5-V SSTL Class I Data bus byte lane 3

B20 1.5-V SSTL Class I Data bus byte lane 3

F20 1.5-V SSTL Class I Data bus byte lane 3

G20 1.5-V SSTL Class I Data bus byte lane 3

F22

G22

D20

E20

H27 1.5-V SSTL Class I On-die termination enable

B30 1.5-V SSTL Class I Row address select

K25 1.5-V SSTL Class I Reset

F29 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

I/O Standard Description

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 2

Data strobe N byte lane 2

Data strobe P byte lane 3

Data strobe N byte lane 3

Tab le 2 –4 4 lists the DDR3 component reference and manufacturing information.

Table 2–44. DDR3 Component Reference and Manufacturing Information

Board

Reference

U10, U11 8M×16×8, 1 Gb, DDR3 memory Micron MT41J64M16JT-15E www.micron.com

Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

Synchronous SRAM

The starter board supports a 18-Mb standard synchronous SRAM intended to be used by NIOS II systems for instruction and data storage with low-latency random access capability. The device has a 512K x 36-bits interface (32-bits data and 4-bits parity). This device is part of the shared FSM bus that connects to the flash memory, SRAM, and MAX V CPLD 5M2210 System Controller.

The device speed is 200 MHz single-data-rate. There is no minimum speed for this device. The theoretical bandwidth of this 32-bit interface is 6.4 Gbps for continuous bursts. The read latency for any address is two clocks while the write latency is one clock.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–43

Memory

Tab le 2 –4 5 lists the SSRAM pin assignments, signal names, and functions.

Table 2–45. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference (U14)

A10

B10

P10

P11

R10

R11

B11

C10

J10

J11

K10

K11

L10

L11

M10

M11

D10

D11

E10

E11

F10

Signal Name

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

FSM_D12

Schematic

Arria V GX

Pin Number

I/O Standard Description

AN23 2.5-V Address bus

AN24 2.5-V Address bus

AM23 2.5-V Address bus

AL23 2.5-V Address bus

AL24 2.5-V Address bus

AK24 2.5-V Address bus

AK23 2.5-V Address bus

AJ23 2.5-V Address bus

AJ25 2.5-V Address bus

AH23 2.5-V Address bus

AH24 2.5-V Address bus

AH25 2.5-V Address bus

AG23 2.5-V Address bus

AG24 2.5-V Address bus

AF23 2.5-V Address bus

AF25 2.5-V Address bus

AE25 2.5-V Address bus

AE24 2.5-V Address bus

AE23 2.5-V Address bus

AP20 2.5-V Address bus

AN21 2.5-V Address bus

AN20 2.5-V Address bus

AM20 2.5-V Address bus

AM22 2.5-V Address bus

AD27 2.5-V Data bus

AD26 2.5-V Data bus

AE26 2.5-V Data bus

AE28 2.5-V Data bus

AF29 2.5-V Data bus

AF28 2.5-V Data bus

AF26 2.5-V Data bus

AG29 2.5-V Data bus

AG26 2.5-V Data bus

AH29 2.5-V Data bus

AG27 2.5-V Data bus

AH27 2.5-V Data bus

AH26 2.5-V Data bus

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–44 Chapter 2: Board Components

Memory

Table 2–45. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Board

Reference (U14)

F11

G10

G11

N11

C11

H11

Schematic

Signal Name

FSM_D13

FSM_D14

FSM_D15

FSM_D16

FSM_D17

FSM_D18

FSM_D19

FSM_D20

FSM_D21

FSM_D22

FSM_D23

FSM_D24

FSM_D25

FSM_D26

FSM_D27

FSM_D28

FSM_D29

FSM_D30

FSM_D31

SRAM_ADSCN

SRAM_ADSPN

SRAM_ADVN

SRAM_BWEN

SRAM_BWN0

SRAM_BWN1

SRAM_BWN2

SRAM_BWN3

SRAM_CEN

SRAM_CLK

SRAM_DQP0

SRAM_DQP1

SRAM_DQP2

SRAM_DQP3

SRAM_GWN

SRAM_MODE

SRAM_OEN

SRAM_ZZ

Arria V GX

Pin Number

I/O Standard Description

AJ26 2.5-V Data bus

AK27 2.5-V Data bus

AK26 2.5-V Data bus

AL27 2.5-V Data bus

AL28 2.5-V Data bus

AL29 2.5-V Data bus

AL31 2.5-V Data bus

AM31 2.5-V Data bus

AM29 2.5-V Data bus

AM28 2.5-V Data bus

AL26 2.5-V Data bus

AL25 2.5-V Data bus

AM26 2.5-V Data bus

AM25 2.5-V Data bus

AN26 2.5-V Data bus

AP28 2.5-V Data bus

AP27 2.5-V Data bus

AP26 2.5-V Data bus

AP25 2.5-V Data bus

AP19 2.5-V Address status controller

AF19 2.5-V Address status processor

AE19 2.5-V Address valid

AP17 2.5-V Byte write enable

AM17 2.5-V Byte lane 0 write enable

AM19 2.5-V Byte lane 1 write enable

AN17 2.5-V Byte lane 2 write enable

AN18 2.5-V Byte lane 3 write enable

AL19 2.5-V Chip enable

AL18 2.5-V Clock

AF20 2.5-V Data bus parity byte lane 0

AE20 2.5-V Data bus parity byte lane 1

AE22 2.5-V Data bus parity byte lane 2

AE21 2.5-V Data bus parity byte lane 3

AF22 2.5-V Global write enable

AG21 2.5-V Burst sequence selection

AL17 2.5-V Output enable

AD21 2.5-V Power sleep mode

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–45

Memory

Tab le 2 –4 4 lists the SRAM component reference and manufacturing information.

Table 2–46. SRAM Component Reference and Manufacturing Information

Board

Reference

U14

Description Manufacturer

Standard synchronous pipelined SCD, 512K × 36 bit, 200 MHz

Integrated Silicon Solution, Inc.

Manufacturing

Part Number

IS61VPS51236A-

Flash

The starter board supports two 1-Gb CFI-compatible synchronous flash device for non-volatile storage of FPGA configuration data, board information, test application data, and user code space. This device is part of the shared FSM bus that connects to the flash memory, SSRAM, and MAX V CPLD 5M2210 System Controller.

This 16-bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps per device. The write performance is 270 µs for a single word buffer while the erase time is 800 ms for a 128 K array block.

Tab le 2 –4 7 lists the flash pin assignments, signal names, and functions. The signal

names and types are relative to the Arria V GX in terms of I/O setting and direction.

Table 2–47. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference

Schematic Signal Name

Arria V GX

Pin Number

I/O Standard Description

200B3

Manufacturer

Website

www.issi.com

Flash A (U12)

FLASH_ADVN

FLASH_CEN0

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN0

FLASH_RESETN

FLASH_WEN

FLASH_WPN

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

AJ20 2.5-V Address valid

AK21 2.5-V Chip enable

AJ22 2.5-V Clock

AL22 2.5-V Output enable

AH20 2.5-V Ready

AH22 2.5-V Reset

AH21 2.5-V Write enable

— 2.5-V Write protect

AN23 2.5-V Address bus

AN24 2.5-V Address bus

AM23 2.5-V Address bus

AL23 2.5-V Address bus

AL24 2.5-V Address bus

AK24 2.5-V Address bus

AK23 2.5-V Address bus

AJ23 2.5-V Address bus

AJ25 2.5-V Address bus

AH23 2.5-V Address bus

AH24 2.5-V Address bus

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–46 Chapter 2: Board Components

Memory

Table 2–47. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

Schematic Signal Name

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_A26

FSM_A27

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

Arria V GX

Pin Number

I/O Standard Description

AH25 2.5-V Address bus

AG23 2.5-V Address bus

AG24 2.5-V Address bus

AF23 2.5-V Address bus

AF25 2.5-V Address bus

AE25 2.5-V Address bus

AE24 2.5-V Address bus

AE23 2.5-V Address bus

AP20 2.5-V Address bus

AN21 2.5-V Address bus

AN20 2.5-V Address bus

AM20 2.5-V Address bus

AM22 2.5-V Address bus

AL20 2.5-V Address bus

AD20 2.5-V Address bus

AD27 2.5-V Data bus

AD26 2.5-V Data bus

AE26 2.5-V Data bus

AE28 2.5-V Data bus

AF29 2.5-V Data bus

AF28 2.5-V Data bus

AF26 2.5-V Data bus

AG29 2.5-V Data bus

AG26 2.5-V Data bus

AH29 2.5-V Data bus

AG27 2.5-V Data bus

AH27 2.5-V Data bus

AH26 2.5-V Data bus

AJ26 2.5-V Data bus

AK27 2.5-V Data bus

AK26 2.5-V Data bus

Flash B (U13)

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

FLASH_ADVN

FLASH_CEN1

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN1

FLASH_RESETN

AJ20 2.5-V Address valid

AK20 2.5-V Chip enable

AJ22 2.5-V Clock

AL22 2.5-V Output enable

AG20 2.5-V Ready

AH22 2.5-V Reset

Chapter 2: Board Components 2–47

Memory

Table 2–47. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference

Schematic Signal Name

FLASH_WEN

FLASH_WPN

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_A26

FSM_A27

FSM_D16

FSM_D17

FSM_D18

FSM_D19

FSM_D20

FSM_D21

FSM_D22

FSM_D23

FSM_D24

FSM_D25

FSM_D26

Arria V GX

Pin Number

I/O Standard Description

AH21 2.5-V Write enable

— 2.5-V Write protect

AN23 2.5-V Address bus

AN24 2.5-V Address bus

AM23 2.5-V Address bus

AL23 2.5-V Address bus

AL24 2.5-V Address bus

AK24 2.5-V Address bus

AK23 2.5-V Address bus

AJ23 2.5-V Address bus

AJ25 2.5-V Address bus

AH23 2.5-V Address bus

AH24 2.5-V Address bus

AH25 2.5-V Address bus

AG23 2.5-V Address bus

AG24 2.5-V Address bus

AF23 2.5-V Address bus

AF25 2.5-V Address bus

AE25 2.5-V Address bus

AE24 2.5-V Address bus

AE23 2.5-V Address bus

AP20 2.5-V Address bus

AN21 2.5-V Address bus

AN20 2.5-V Address bus

AM20 2.5-V Address bus

AM22 2.5-V Address bus

AL20 2.5-V Address bus

AD20 2.5-V Address bus

AL27 2.5-V Data bus

AL28 2.5-V Data bus

AL29 2.5-V Data bus

AL31 2.5-V Data bus

AM31 2.5-V Data bus

AM29 2.5-V Data bus

AM28 2.5-V Data bus

AL26 2.5-V Data bus

AL25 2.5-V Data bus

AM26 2.5-V Data bus

AM25 2.5-V Data bus

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–48 Chapter 2: Board Components

Power Supply

Table 2–47. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board

Reference

Schematic Signal Name

FSM_D27

FSM_D28

FSM_D29

FSM_D30

FSM_D31

Arria V GX

Pin Number

AN26 2.5-V Data bus

AP28 2.5-V Data bus

AP27 2.5-V Data bus

AP26 2.5-V Data bus

AP25 2.5-V Data bus

I/O Standard Description

Tab le 2 –4 8 lists the flash component reference and manufacturing information.

Table 2–48. Flash Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U12, U13 1-Gb synchronous flash Numonyx PC28F00AP30BF www.numonyx.com

Manufacturing

Part Number

Manufacturer

Power Supply

You can power up the starter board either from a laptop-style DC power input or from the PCI Express edge connector. The input voltage must be in the range of 14 V to 20 V. The DC voltage is then stepped down to various power rails used by the board components and installed into the HSMC connectors.

Website

Tab le 2 –4 9 outlines the allowable power inputs.

Table 2–49. Power Inputs

Power Source Voltage (V) Current (A) Maximum Wattage (W)

Laptop-style DC input 19.0 6.5 120

25-W PCI Express edge connector

75-W PCI Express edge connector

3.3 3.0 9

12.0 2.1 16

3.3 3.0 9

12.0 5.5 66

An on-board multi-channel analog-to-digital converter (ADC) measures the current for several specific board rails.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

LEGEND

Arria V Power

Board Main Power Rails

LTC3605

2.5 V Switcher (5.0 A) +/- 5%

LTC3855

3.3 V (5A) and 12 V (7A)

Dual Switcher

(5.0 A)

+/- 5%

LTC3880 Channel 2

2.5 V Switcher (7.0 A) +/- 5%

LTC3633 Channel 2

1.5 V Switcher (3.0 A) +/- 5%

LTC3633 Channel 1

1.15 V Low Noise Switcher (2.0 A)

+/- 30 mV

LTC3880 Channel 1

1.1 V Low Noise

Switcher (14.0 A)

+/- 30 mV

LTC3025-1

1.8 V LDO (500 mA)

+/- 5%

LTC3025-1

1.5 V LDO (500 mA)

+/- 5%

LTC3025-1

1.0 V LDO (500 mA)

+/- 5%

LTC3009

5.0 V LDO (20 mA)

+/- 5%

LTC3009

5.37 V LDO (20 mA)

+/- 5%

TPS51100DGQ

0.75 V LDO (3.0 A) +/- 5%

14 V - 20 V

DC INPUT

12 V

3.3 V

2.9 A

12 V

5.6 A

2.5 V

2.4 A

1.8 V

201 mA

1.0 V

250 mA

2.5 V

5.2 A

1.5 V

1.5 A

1.5 V

283 mA

1.1 V

11.6 A

1.15 V

1.3 A

5.37 V

0.3 mA

5.0 V

8.8 mA

12 V

3.3 V

12 V

Filter

Ethernet PHY

SSRAM

Flash

MAX V VCCIO

MAX II VCCIO

Oscillators

Clock Generators and Buffers

Flash

MAX V VCCint

MAX II VCCint

Ethernet PHY

Filter

VCCH_GXB VCCD_FPLL

VCCBAT

0.75 V

308 mA

SDRAM

Address or

Command Lines

Termination

VCCAUX VCCA_GXB VCCA_FPLL

VCCIO

VCCPD

VCCPGM

VCCIO

SDRAM x2

VCCT_GXB

VCCL_GXB

VCCR_GXB

VCC Core

VCCP CoreFilter

Fan

LTC4352

HSMC

MAX II VCCIO

USB-Blaster II PHY VCC

SDI Cable Driver/Equalizer

HDMI Level Shifter

PCI Express JTAG Level Shifter

HDMI DCC Level Shifter

SPI Level Shifter DDR3 VTT LDO

LCD

PCI Express x8

Gold Finger

Power Monitor

Chapter 2: Board Components 2–49

Power Supply

Power Distribution System

Figure 2–12 shows the power distribution system on the development board.

Regulator inefficiencies and sharing are reflected in the currents shown, which are conservative absolute maximum levels.

1 If the sourcing current is higher than the rated current of the switching regulator, refer

to www.linear.com for technical support.

Figure 2–12. Power Distribution System

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–50 Chapter 2: Board Components

SCK

SPI Bus

DSI

DSO

CSn

8 Ch.

Power Supply Load #0-7

SENSE

5M2210

Arria V

FPGA

To User PC

JTAG Chain

Feedback

14-pin

2x16

Character

LCD

E RW RS D(0:7)

Supply

#0-7

EPM570

USB PHY

Embedded

USB-Blaster II

Power Supply

Power Measurement

There are 8 power supply rails that have on-board current sense capabilities using 24-bit differential ADC devices. Precision sense resistors split the ADC devices and rails from the primary supply plane for the ADC to measure current. A SPI bus connects these ADC devices to the MAX V CPLD 5M2210 System Controller.

Figure 2–13 shows the block diagram for the power measurement circuitry.

Figure 2–13. Power Measurement Circuit

Tab le 2 –5 0 lists the targeted rails. The schematic signal name column specifies the

name of the rail being measured while the device pin column specifies the devices attached to the rail. If no subnet is named, the power is the total output power for that voltage.

Table 2–50. Power Measurement Rails (Part 1 of 2)

Channel Schematic Signal Name Voltage (V) Device Pin Description

0 A5_VCCINT 1.1 VCC FPGA core and periphery power

1.1 VCCL_GXB XCVR analog clock network

1 A5_VCCL_VCCR_VCCT_GXB

1.1 VCCR_GXB XCVR analog receive

1.1 VCCT_GXB XCVR analog transmit

VCCIO_8A,

2 A5_VCCIO_1.5V 1.5

VCCIO_8B,

VCCIO bank 8 (DDR3)

VCCIO_8C

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–51

Power Supply

Table 2–50. Power Measurement Rails (Part 2 of 2)

Channel Schematic Signal Name Voltage (V) Device Pin Description

2.5 VCCPD I/O pre-drivers

2.5 VCCPGM Configuration I/O

VCCIO_3A, VCCIO_3B, VCCIO_3C, VCCIO_3D,

3 A5_VCCIO_VCCPD_VCCPGM

2.5

VCCIO_4A, VCCIO_4B, VCCIO_4C,

VCC I/O banks 3, 4, 7 and 8D VCCIO_4D, VCCIO_7A, VCCIO_7B, VCCIO_7C, VCCIO_7D, VCCIO_8D

4 A5_VCCAUX_VCCA_FPLL

2.5 VCCA_FPLL PLL analog power

2.5 VCC_AUX Auxiliary

5 A5_VCCA_GXB 2.5 VCCA_GXB XCVR transmit driver, receiver, CDR

6 A5_VCCH_GXB 1.5 VCCH_GXB XCVR block level transmit buffers

7 A5_VCCD_FPLL_VCCBAT

1.5 VCCD_FPLL PLL digital power

1.5 VCCBAT Battery power

Tab le 2 –5 1 lists the power measurement ADC component reference and

manufacturing information.

Table 2–51. Power Measurement ADC Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

U40 8-channel differential 24-bit ADC Linear Technology LTC2418CGN#PBF www.linear.com

Manufacturer

Website

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–52 Chapter 2: Board Components

Statement of China-RoHS Compliance

Tab le 2 –5 2 lists hazardous substances included with the kit.

(Hg)

(1), (2)

Polybrominated biphenyls (PBB)

Polybrominated diphenyl Ethers

(PBDE)

Table 2–52. Table of Hazardous Substances’ Name and Concentration Notes

Part Name

Arria V GX starter board X* 0 0 0 0 0

12 V power supply 0 0 0 0 0 0

Type A-B USB cable 0 0 0 0 0 0

User guide 0 0 0 0 0 0

Notes to Table 2–52:

(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the

SJ/T11363-2006 standard.

(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant

threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.

Lead

(Pb)

Cadmium

(Cd)

Hexavalent

Chromium

(Cr6+)

Mercury

CE EMI Conformity Caution

This development kit is delivered conforming to relevant standards mandated by Directive 2004/108/EC. Because of the nature of programmable logic devices it is possible for the user to modify the kit in such a way as to generate electromagnetic interference (EMI) that exceeds the limits established for this equipment. Any EMI caused as the result of modifications to the delivered material is the responsibility of the user.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

This chapter provides additional information about the document and Altera.

Board Revision History

The following table lists the versions of all releases of the Arria V GX starter board.

Version Release Date Description

Production silicon October 2012 Production device.

Engineering silicon (ES) July 2012 Initial release.

Document Revision History

The following table lists the revision history for this document.

Additional Information

Date Version Changes

November 2013 1.3

February 2013 1.2

October 2012 1.1

July 2012 1.0 Initial release.

■ Updated the PCI Express link width DIP switch (SW1) default settings in Table 2–13.

■ Updated information for DDR3.

■ Added CE EMI Conformity Caution section.

■ New board revision—changed to production silicon 5AGXFB3H4F35C4N.

■ Added

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the following table.

Contact

Technical support Website www.altera.com/support

Technical training

Product literature Website www.altera.com/literature

Nontechnical support (general) Email nacomp@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

(1)

(software licensing) Email authorization@altera.com

ENET_GTX_CLK

pin information in Table 2–32.

Contact Method Address

Website www.altera.com/training

Email custrain@altera.com

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

Info–2 Additional Information

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

italic type

Initial Capital Letters

“Subheading Title”

Courier type

r An angled arrow instructs you to press the Enter key.

1., 2., 3., and a., b., c., and so on

■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.

1 The hand points to information that requires special attention. h The question mark directs you to a software help system with related information. f The feet direct you to another document or website with related information. m The multimedia icon directs you to a related multimedia presentation.

Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

Indicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

Indicate keyboard keys and menu names. For example, the Delete key and the Options menu.

Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example,

tdi

, and

input

. The suffix n denotes an active-low signal. For example,

data1

resetn

Indicates command line commands and anything that must be typed exactly as it appears. For example,

c:\qdesigns\tutorial\chiptrip.gdf

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword

TRI

example,

SUBDESIGN

), and logic function names (for

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Altera Arria V GX Starter Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

Introduction

2. Board Components

Board Overview

Featured Device: Arria V GX FPGA

I/O and Transceiver Resources

MAX V CPLD 5M2210 System Controller

FPGA Configuration

FPGA Programming over Embedded USB-Blaster

Flash Memory Programming

FPGA Programming from Flash Memory

Status Elements

FPGA Programming over External USB-Blaster

Setup Elements

Board Settings DIP Switch

JTAG Chain Control DIP Switch

PCI Express Link Width DIP Switch

CPU Reset Push Button

MAX V Reset Push Button

Image Load Push Button

Image Select Push Button

Clock Circuitry

On-Board Oscillators

Off-Board Clock Input/Output

General User Input/Output

User-Defined Push Buttons

User-Defined DIP Switch

User-Defined LEDs

General LEDs

HSMC LEDs

PCI Express LEDs

Character LCD

Components and Interfaces

PCI Express

10/100/1000 Ethernet

HSMC

SDI Video Output/Input

HDMI Video Output

Memory

DDR3 SDRAM

Synchronous SRAM

Flash

Power Supply

Power Distribution System

Power Measurement

Statement of China-RoHS Compliance

CE EMI Conformity Caution

Board Revision History

Document Revision History

Additional Information

How to Contact Altera

Typographic Conventions