Altera Arria V GX Starter Board User Manual

Arria V GX Starter Board Reference Manual

Arria V GX Starter Board

Reference Manual

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© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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9001:2008

Registered

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

The Arria V GX starter board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Arria V GX FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V GX designs.

1. Overview

One high-speed mezzanine card (HSMC) connector is available to add additional functionality via a variety of HSMCs available from Altera

®

and various partners.

f To see a list of the latest HSMCs available or to download a copy of the HSMC

specification, refer to the Development Board Daughtercards page of the Altera website.

Design advancements and innovations, such as the PCI Express hard IP, partial reconfiguration, and hard memory controller implementation ensure that designs implemented in the Arria V GXs operate faster, with lower power, and have a faster time to market than previous FPGA families.

f For more information on the following topics, refer to the respective documents:

■ Arria V device family, refer to the Arria V Device Handbook.

■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

The starter board features the following major component blocks:

■ One Arria V GX 5AGXFB3H4F35C4N FPGA in a 1152-pin FineLine BGA (FBGA)

package

■ 362,000 LEs

■ 136,880 adaptive logic modules (ALMs)

■ 17,260 Kbit on-die block memory

■ 24 high-speed transceivers

■ 12 fractional phase locked loops (PLLs)

■ 2,090 18x19 multipliers

■ 544 general purpose input/output

■ 1.1-V core voltage

■ MAX

■ MAX II EPM570F100C5N CPLD in a 100-pin FBGA package

®

V 5M2210ZF256C4N CPLD in a 256-pin FBGA package

■ FPGA configuration circuitry

■ MAX V CPLD 5M2210ZF256C4N System Controller and flash fast passive

parallel (FPP) configuration

■ On-board USB-Blaster

■ Clocking circuitry

■ Programmable clock generator for FPGA reference clock input

■ 125-MHz LVDS oscillator for FPGA reference clock input

■ 148.5/148.35-MHz LVDS VCXO for FPGA reference clock input

■ 50-MHz single-ended oscillator for FPGA and CPLD clock input

■ 100-MHz single-ended oscillator for CPLD configuration clock input

■ SMA input (LVPECL)

■ Memory

■ Two 128-Mbyte (MB) DDR3 SDRAM with a total of 32-bit data bus

■ 2-MB SSRAM

■ Two 128-MB synchronous flash

TM

II for use with the Quartus® II Programmer

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ General user I/O

■ LEDs and displays

■ Four user LEDs

■ One two-line character LCD display

■ Three configuration select LED

■ One configuration done LED

■ Four on-board USB-Blaster II status LEDs

■ Two HSMC interface transmit/receive LED (TX/RX)

■ Four PCI Express LEDs

■ Five Ethernet LEDs

■ One serial digital interface (SDI) carrier detect LED

■ Push buttons

■ One CPU reset push button

■ One configuration reset push button

■ Three general user push buttons

■ DIP switches

■ Four MAX V CPLD System Controller control switches

■ Three JTAG chain control switches

■ Three PCI Express link width switches

■ Four general user switches

■ Power supply

■ 19-V (laptop) DC input

■ PCI Express edge connector power

■ Mechanical

■ PCI card standard size (6.600" x 4.199")

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

1–4 Chapter 1: Overview

x

6

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Arria V GX starter board.

Figure 1–1. Arria V GX Starter Board Block Diagram

LVDS/Single-Ended

Type-B

USB 2.0

Embedded

USB-Blaster II

REFCLK SMA

In

Trigger SMA

Out

Gigabit Ethernet

PHY

SDI

TX/RX

JTAG Chain

x1 LVPECL

XCVR x1

x1

XCVR x1

Programmable

Oscillator

50 M, 125 M

Port A

x80

CLKIN x3

5AGXFB3H4F35C4N

XCVR x8

CLKOUT x3

x4

XVCR x8

x8 Edge

256-MB

DDR3

x32

ADDR x27

CONFIG x16

5M2210ZF256C4N

DATA x32

x4 XVCR

x1 XCVR

x11

x3

x4

x10

x32

SSRAM

2-MB

HDMI

TX

XCVR

SMA Out & In

2x16 LCD

Push buttons

LEDs

128-MB

Flash

x16x16

128-MB

Flash

Handling the Board

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Introduction

1 A complete set of schematics, a physical layout database, and GERBER files for the

f For information about powering up the board and installing the demonstration

2. Board Components

This chapter introduces the major components on the Arria V GX starter board.

Figure 2–1 illustrates the component locations and Table 2–1 provides a brief

description of all component features of the board.

development board reside in the Arria V GX starter kit documents directory.

software, refer to the Arria V GX Starter Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Arria V GX FPGA” on page 2–5

■ “MAX V CPLD 5M2210 System Controller” on page 2–7

■ “FPGA Configuration” on page 2–12

■ “Clock Circuitry” on page 2–20

■ “General User Input/Output” on page 2–23

■ “Components and Interfaces” on page 2–27

■ “Memory” on page 2–39

■ “Power Supply” on page 2–48

■ “Statement of China-RoHS Compliance” on page 2–52

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–2 Chapter 2: Board Components

Clock Input SMA Connector (J7, J8)

Max V Reset

Push Button (S3)

General User Push Buttons

(PB1, PB2)

Flash x32

Memory

(U12, U13)

Board Settings

DIP Switch

(SW4)

PCI Express

Edge Connector (J1)

DDR3 x32 (U10,U11)

DC Input Jack (J4)

Character LCD (J16)

CPU Reset

Push Button (S4)

Powe r Switch (SW1)

User DIP

Switch (SW2)

User LEDs (D20-D23)

MAX V CPLD

EPM2210 System

Controller (U15)

Clock Output

SMA Connector

(J12)

HSMC Port A (J13)

Configuration Done,

Load, and Error

LEDs (D10-D12)

Program Load,

Program Select

Push Buttons

(S1, S2)

Program Select

LEDs (D24-D26)

Transceiver RX

SMA Connector

(J2, J3)

Transceiver TX

SMA Connector

(J4, J5)

USB Type-B

Connector (J14)

HDMI Video

Port (J10)

SDI Video Port

(J11, J12)

Gigabit Ethernet

Port (J19)

JTAG Chain Header (J9)

Fan Power

Header (J18)

SSRAM x36

Memory

(U14)

PCI Express

Mode DIP Switch

(SW1)

Arria V GX FPGA (U1)

Board Overview

This section provides an overview of the Arria V GX starter board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features.

Figure 2–1. Overview of the Arria V GX Starter Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Arria V GX Starter Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U1 FPGA Arria V GX, 5AGXFB3H4F35C4N, 1152-pin FBGA.

U15 CPLD MAX V CPLD, 5M2210ZF256C4N , 256-pin FBGA.

Configuration, Status, and Setup Elements

J9 JTAG chain header

D6, D7 JTAG LEDs

Provides access to the JTAG chain and disables the on-board USB-Blaster II when using an external USB-Blaster cable.

Indicate transmit or receive activity of the JTAG chain. The TX and RX LEDs would flicker if the link is in use and active.

SW2 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Arria V GX Starter Board Components (Part 2 of 3)

Board Reference Type Description

J14 On-Board USB-Blaster II

USB interface for programming and debugging the FPGA through embedded USB-Blaster II JTAG via a type-B USB cable.

Controls the MAX V CPLD 5M2210 System Controller functions such

SW4 Board settings DIP switch

as clock enable, SMA clock input control, and which image to load from flash memory at power-up.

prsnt

SW1 PCI Express DIP switch

S2 Image select push button

S1 Load image push button

Controls the PCI Express lane width by connecting together on the PCI Express edge connector.

Toggles the configuration LEDs which selects the program image that loads from flash memory to the FPGA.

Load image from flash memory to the FGPA based on the configuration LED setting.

pins

Indicate transmit or receive activity of the System Console USB

D8, D9 System Console LEDs

interface. The TX and RX LEDs would flicker if the link is in use and active.

D12 Configuration done LED Illuminates when the FPGA is configured.

D11 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.

D10 Error LED Illuminates when the FPGA configuration from flash memory fails.

D30 Power LED Illuminates when 5.0-V power is present.

Illuminates to show the LED sequence that determines which flash

D24, D25, D26 Configuration LEDs

memory image loads to the FPGA when you press the

PGM_SEL

push

button.

D2, D3, D4, D5, D33

Ethernet LEDs Shows the connection speed as well as transmit or receive activity.

D13, D14 HSMC port A LEDs You can configure these LEDs to indicate transmit or receive activity.

D15 HSMC port A present LED Illuminates when a daughtercard is plugged into the HSMC port A.

D16, D17, D18, D19

PCI Express link LEDs

You can configure these LEDs to indicate the PCI Express link width (x1, x4, x8) and Gen2 link.

Clock Circuitry

Programmable oscillator with default frequencies of 125 MHz,

U4 Quad-output oscillator

409.6 MHz, 156.25 MHz, and 100 MHz. The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

148.500-MHz voltage controlled crystal oscillator for serial digital

X1 148.5-MHz oscillator

interface (SDI) video. This oscillator is programmable to any frequency between 20–810 MHz using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

X3 100-MHz oscillator

100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System Controller.

X2 125-MHz oscillator 125.000 MHz crystal oscillator for Gigabit Ethernet.

J7, J8 Clock input SMAs

Drive LVPECL-compatible clock inputs into the clock multiplexer buffer (U5).

J6 Clock output SMA Drive out 2.5-V CMOS clock output from the FPGA.

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Arria V GX Starter Board Components (Part 3 of 3)

Board Reference Type Description

General User Input/Output

D20–D23 User LEDs Four user LEDs. Illuminates when driven low.

SW3 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.

S4 CPU reset push button Press to reset the FPGA logic.

S3 MAX V reset push button Press to reset the MAX V CPLD 5M2210 System Controller.

S5, S6, S7 General user push buttons Three user push buttons. Driven low when pressed.

Memory Devices

U10, U11 DDR3 x32 memory

U14 SSRAM x36 memory

256-Mbyte DDR3 SDRAM with a 32-bit data bus. The 32-bit data bus consists of two x16 devices with a single address or command bus.

2-Mbyte standard synchronous RAM with a 32-bit data bus and 4-bit parity.

Two 128-Mbyte synchronous flash devices with 16-bit data buses for

U12, U13 Flash x32 memory

non-volatile memory. The board supports two flash devices of 16-bit interface each, which combine to allow for 256-Mbyte synchronous flash with a 32-bit data bus.

Communication Ports

J1 PCI Express edge connector

J13 HSMC port A

J19 Gigabit Ethernet connector

Video and Display Ports

J16 Character LCD

J10 HDMI video port

J11, J12 SDI video port

Power Supply

J1 PCI Express edge connector

J17 DC input jack

SW5 Power switch

Gold-plated edge fingers connector for up to ×8 signaling in Gen1 or Gen2 mode.

Provides eight transceiver channels and 84 CMOS or 17 LVDS channels per the HSMC specification.

RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.

Connector that interfaces to a provided 16 character × 2 line LCD module along with two standoffs.

A 19-pin HDMI connector that provides a HDMI video output of up to 1080i.

Two 75-Ω sub-miniature version B (SMB) connectors that provide a full-duplex SDI interface through a LMH0303 cable driver and LMH0384 cable equalizer.

Interfaces to a PCI Express root port such as an appropriate PC motherboard.

Accepts a 14–20-V DC power supply. This input jack is not to be used while the board is plugged into a PCI Express slot.

Switch to power on or off the board when power is supplied from the DC input jack.

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

Bank 3A

Total I/O in Each Bank

Bank Number

48

Bank 3B32

Bank 3C32

Bank 3D32

Bank 4D32

Bank 4C32

Bank 8A

Bank 8B

Bank 8C

Bank 8D

Bank 7D

Bank 7C

48

32

Bank 4B32

Bank 4A32

Bank 7B

Bank 7A3231

Transceiver Block

5AGXFB3H4F35

Featured Device: Arria V GX FPGA

The Arria V GX starter board features a Arria V GX 5AGXFB3H4F35C4N device (U1) in a 1152-pin FBGA package.

f For more information about Arria V device family, refer to the Arria V Device

Handbook.

Tab le 2– 2 describes the features of the Arria V GX 5AGXFB3H4F35C4N device.

Table 2–2. Arria V GX Features

ALMs

Equivalent

LEs

M10K RAM

Blocks

Total RAM

(Kbits)

18-bit × 19-bit

Multipliers

PLLs Transceivers Package Type

136,880 362,000 1,726 17,260 2,090 12 24 1152-pin FBGA

Tab le 2– 3 lists the Arria V GX component reference and manufacturing information.

Table 2–3. Arria V GX Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U1

FPGA, Arria V GX F1152, 362K LEs, leadfree

Corporation 5AGXFB3H4F35C4N www.altera.com

Altera

Manufacturing

Part Number

Manufacturer

Website

I/O and Transceiver Resources

Figure 2–2 illustrates the bank organization and I/O count for the Arria V GX

5AGXFB3H4F35C4N device in the 1152-pin FBGA package.

Figure 2–2. Arria V GX Device I/O Bank Diagram

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–6 Chapter 2: Board Components

Featured Device: Arria V GX FPGA

Figure 2–3 illustrates the transceiver channels on the left and right side of the

Arria V GX 5AGXFB3H4F35C4N device in the 1152-pin FBGA package.

Figure 2–3. Arria V GX Device Transceiver Bank Diagram

CH 5

CH 4

CH 3

GXB_L1 GXB_R1

GXB_L0

CH 2

CH 1

CH 0

5AGXFB3H4F35

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

Channels Per Bank

Transceiver Bank

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

GXB_R0

Tab le 2 –4 lists the Arria V GX device I/O and transceiver pin count and usage by

function on the board.

Table 2–4. Arria V GX Device I/O and Transceiver Pin Count

Function I/O Standard I/O Count Special Pins

DDR3 1.5-V SSTL 70 One differential x4 DQS pin

Flash, SSRAM, and MAX V FSM bus 2.5-V CMOS 87 —

MAX V CPLD 5M2210 System Controller 2.5-V CMOS 10 —

PCI Express x8 2.5-V CMOS + XCVR 42 One reference clock

HSMA port A 2.5-V CMOS + LVDS + XCVR 116

Eight XCVR, 17 LVDS, six clock inputs/outputs, I

2

C

Gigabit Ethernet 2.5-V CMOS + LVDS 20 One LVDS

On-Board USB-Blaster II 2.5-V CMOS 20 —

SDI video 2.5-V CMOS 15 One reference clock

HDMI video 2.5-V CMOS 14 One reference clock

Push buttons 2.5-V CMOS 4 One DEV_CLRn

DIP switches 2.5-V CMOS 4 —

Character LCD 2.5-V CMOS 11 —

LEDs 2.5-V CMOS 7 —

Clock or Oscillators 2.5-V CMOS + LVDS + PCML 21 11 reference clock

Total I/O Used: 441

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–7

Information

Register

On-Board

USB-Blaster II

Si571

Controller

Si5538

Controller

SLD-HUB

PFL

FSM BUS

MAX V CPLD System Controller

Power

Measurement

Results

Virtual-JTAG

PC

FPGA

LTC2418 Controller

Flash

Decoder

Encoder

GPIO

JTAG Control

Flash

SSRAM

Control

Register

Si571

Programmable

Oscillator

Si5338

Programmable

Oscillator

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Fan control (shared with the FPGA)

■ Control registers for clocks

■ Control and status registers for remote system update

Figure 2–4 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Figure 2–4. MAX V CPLD 5M2210 System Controller Block Diagram

Tab le 2 –5 lists the I/O signals present on the MAX V CPLD 5M2210 System

Controller. The signal names and functions are relative to the MAX V device (U15).

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 6)

Board

Reference (U15)

N4

B9

E9

J5

A15

A13

J12

November 2013 Altera Corporation Arria V GX Starter Board

Schematic Signal Name I/O Standard Description

5M2210_JTAG_TMS

CLK125_EN

CLK50_EN

CLK_CONFIG

CLK_ENABLE

CLK_SEL

CLKIN_50_MAXV

Reference Manual

2.5-V MAX V JTAG TMS

2.5-V 125 MHz oscillator enable

2.5-V 50 MHz oscillator enable

2.5-V 100 MHz configuration clock input

2.5-V DIP switch for clock oscillator enable

2.5-V DIP switch for clock select—SMA or oscillator

2.5-V 50 MHz clock input

2–8 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 2 of 6)

Board

Reference (U15)

C9

D9

D10

M1

T13

T15

A2

R14

N12

C8

N7

R5

M7

R6

M6

T5

R7

P7

N6

K1

D3

C2

C3

E3

D2

E4

D1

E5

F3

E1

F4

F2

F1

F6

G2

G3

N3

J3

Schematic Signal Name I/O Standard Description

CLOCK_SCL

CLOCK_SDA

CPU_RESETN

EXTRA_SIG0

EXTRA_SIG1

EXTRA_SIG2

FACTORY_LOAD

FACTORY_REQUEST

FACTORY_STATUS

FAN_FORCE_ON

FLASH_ADVN

FLASH_CEN0

FLASH_CEN1

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN0

FLASH_RDYBSYN1

FLASH_RESETN

FLASH_WEN

FPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D1

FPGA_CONFIG_D2

FPGA_CONFIG_D3

FPGA_CONFIG_D4

FPGA_CONFIG_D5

FPGA_CONFIG_D6

FPGA_CONFIG_D7

FPGA_CONFIG_D8

FPGA_CONFIG_D9

FPGA_CONFIG_D10

FPGA_CONFIG_D11

FPGA_CONFIG_D12

FPGA_CONFIG_D13

FPGA_CONFIG_D14

FPGA_CONFIG_D15

FPGA_CVP_CONFDONE

FPGA_DCLK

2.5-V Programmable oscillator I2C clock

2.5-V Programmable oscillator I2C data

2.5-V FPGA reset push button

2.5-V USB-Blaster II interface. Reserved for future use.

2.5-V DIP switch to load factory or user design at power-up

2.5-V

On-Board USB-Blaster II request to send FACTORY command

2.5-V On-Board USB-Blaster II FACTORY command status

2.5-V DIP switch to on or off the fan

2.5-V FSM bus flash memory address valid

2.5-V FSM bus flash memory chip enable 0

2.5-V FSM bus flash memory chip enable 1

2.5-V FSM bus flash memory clock

2.5-V FSM bus flash memory output enable

2.5-V FSM bus flash memory ready 0

2.5-V FSM bus flash memory ready 1

2.5-V FSM bus flash memory reset

2.5-V FSM bus flash memory write enable

2.5-V FPGA configuration done LED

2.5-V FPGA configuration data

2.5-V FPGA configuration via protocol done LED

2.5-V FPGA configuration clock

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 6)

Board

Reference (U15)

N1

J4

H1

P2

E2

F5

E14

C14

C15

E13

E12

D15

F14

D16

F13

E15

E16

F15

G14

F16

G13

G15

G12

G16

H14

H15

H13

H16

J13

R3

P5

T2

J14

J15

K16

K13

K15

K14

L16

Schematic Signal Name I/O Standard Description

FPGA_NCONFIG

FPGA_NSTATUS

FPGA_PR_DONE

FPGA_PR_ERROR

FPGA_PR_READY

FPGA_PR_REQUEST

FSM_A0

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

2.5-V FPGA configuration active

2.5-V FPGA configuration ready

2.5-V FPGA partial reconfiguration done

2.5-V FPGA partial reconfiguration error

2.5-V FPGA partial reconfiguration ready

2.5-V FPGA partial reconfiguration request

2.5-V FSM address bus

2.5-V FSM data bus

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

2–10 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 6)

Board

Reference (U15)

L11

L15

L12

M16

L13

M15

L14

N16

M13

N15

N14

P15

P14

D13

D14

F11

J16

F12

K12

M14

N13

R1

P4

N5

P6

B8

D6

E6

C4

B4

B1

C5

L6

M5

P3

P11

P12

Schematic Signal Name I/O Standard Description

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

FSM_D16

FSM_D17

FSM_D18

FSM_D19

FSM_D20

FSM_D21

FSM_D22

FSM_D23

FSM_D24

FSM_D25

FSM_D26

FSM_D27

FSM_D28

FSM_D29

FSM_D30

FSM_D31

HSMA_PRSNTN

INT_TSD_SDA

INT_TSD_SCL

LTC3880_SDA_2.5V

LTC3880_SCL_2.5V

LTC3880_ALERT_N_2.5V

LTC3880_GPIO0_N_2.5V

JTAG_5M2210_TDI

JTAG_5M2210_TDO

JTAG_TCK

M570_CLOCK

M570_PCIE_JTAG_EN

2.5-V FSM data bus

2.5-V HSMC port A present

2.5-V Internal TSD I2C bus

2.5-V 1.1-V VCC core power supply to PMBus

2.5-V MAX V CPLD on-board JTAG chain data in

2.5-V MAX V CPLD on-board JTAG chain data out

2.5-V JTAG chain clock

2.5-V

25-MHz clock to on-board USB-Blaster II for sending FACTORY command

Low signal to disable the on-board USB-Blaster II when PCI Express is the master to the JTAG chain

Arria V GX Starter Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–11

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 5 of 6)

Board

Reference (U15)

P10

R11

T12

N11

T11

R10

M10

N10

E11

A4

A6

M9

B10

B3

C10

C12

C6

B7

C7

D12

B14

C13

B16

B13

D5

E8

D11

R12

E7

A5

D7

B6

D4

R4

T4

P8

T7

N8

R8

Schematic Signal Name I/O Standard Description

MAX5_BEN0

MAX5_BEN1

MAX5_BEN2

MAX5_BEN3

MAX5_CLK

MAX5_CSN

MAX5_OEN

MAX5_WEN

MAX_CONF_DONEN

MAX_ERROR

MAX_LOAD

MAX_RESETN

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

OVERTEMP

PCIE_JTAG_EN

PGM_CONFIG

PGM_LED0

PGM_LED1

PGM_LED2

PGM_SEL

SDI_RX_BYPASS

SDI_RX_EN

SDI_TX_EN

SECURITY_MODE

SENSE_CS0N

SENSE_SCK

SENSE_SDI

SENSE_SDO

SI571_EN

USB_CFG0

USB_CFG1

USB_CFG2

USB_CFG3

USB_CFG4

USB_CFG5

2.5-V FSM bus MAX V byte enable 0

2.5-V FSM bus MAX V byte enable 1

2.5-V FSM bus MAX V byte enable 2

2.5-V FSM bus MAX V byte enable 3

2.5-V FSM bus MAX V clock

2.5-V FSM bus MAX V chip select

2.5-V FSM bus MAX V output enable

2.5-V FSM bus MAX V write enable

2.5-V On-board USB-Blaster II configuration done LED

2.5-V FPGA configuration error LED

2.5-V FPGA configuration active LED

2.5-V MAX V reset push button

2.5-V FPGA mode select 0

2.5-V FPGA mode select 1

2.5-V FPGA mode select 2

2.5-V FPGA mode select 3

2.5-V FPGA mode select 4

2.5-V Temperature monitor fan enable

2.5-V DIP switch to enable the PCI Express JTAG master

2.5-V Load the flash memory image identified by the PGM LEDs

2.5-V Flash memory PGM select indicator 0

2.5-V Flash memory PGM select indicator 1

2.5-V Flash memory PGM select indicator 2

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

2.5-V SDI equalization bypass

2.5-V SDI receive enable

2.5-V SDI transmit enable

2.5-V Reserved for future use

2.5-V Power monitor chip select

2.5-V Power monitor SPI clock

2.5-V Power monitor SPI data in

2.5-V Power monitor SPI data out

2.5-V Si571 programmable VCXO enable

2.5-V Reserved for future use

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

Altera Arria V GX Starter Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

Introduction

2. Board Components

Board Overview

Featured Device: Arria V GX FPGA

I/O and Transceiver Resources

MAX V CPLD 5M2210 System Controller