Altera Arria V GT FPGA Development Board User Manual

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Arria V GT FPGA Development Board Reference Manual

Arria V GT FPGA Development Board

Reference Manual

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© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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9001:2008

Registered

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Dual FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

FPGA 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

FPGA 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

Chapter 2. Board Components

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Arria V GT FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

MAX II CPLD EPM2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming over On-Board USB-Blaster II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

JTAG Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

PCI Express Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

MAX II Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Configuration Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Image Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Off-Board Clock Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

SDI Video Output/Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

HSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

SFP+ Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45

FMC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

Bull's Eye Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–52

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–54

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

iv ContentsContents

DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–54

DDR3A for FPGA 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–54

DDR3B/C for FPGA 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–59

QDRII+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–64

Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–67

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–68

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–69

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–70

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–72

Chapter 3. Board Components Reference

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

This document describes the hardware features of the Arria® V GT FPGA development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Arria V GT FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Arria V GT FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V GT FPGA designs.

1. Overview

Two high-speed mezzanine card (HSMC) connectors are available to add additional functionality via a variety of HSMCs available from Altera

and various partners.

f To see a list of the latest HSMCs available or to download a copy of the HSMC

specification, refer to the Development Board Daughtercards page of the Altera website.

Design advancements and innovations, such as the PCI Express hard IP implementation and programmable power technology ensure that designs implemented in the Arria V GT FPGAs operate faster, with lower power, and have a faster time to market than previous FPGA families.

f For more information on the following topics, refer to the respective documents:

■ Arria V device family, refer to the Arria V Device Handbook.

■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

The development board features the following major component blocks:

■ Two Arria V GT FPGA 5AGTFD7K3F40I3N in the 1517-pin FineLine BGA (FBGA)

package

■ 504K LEs

■ 190,240 adaptive logic modules (ALMs)

■ 24,140 Kbit (Kb) M10K on-die memory

■ 2,906 Kb MLAB memory

■ 36 transceivers

■ 16 phase locked loops (PLLs)

■ 2,312 18x18 multipliers

■ 1.15-V core voltage

■ MAX

■ FPGA configuration circuitry

II CPLD EPM2210GF324 System Controller in the 324-pin FBGA package

■ MAX

II CPLD EPM570GM100 and flash fast passive parallel (FPP)

configuration

■ On-board USB-Blaster

II for use with the Quartus® II Programmer

■ Clocking circuitry

■ Nine on-board oscillators

■ One 50-MHz oscillator

■ Two 125-MHz oscillators

■ Clock buffer with six outputs sourced by SMA or programmable oscillator

with a default frequency of 100-MHz

■ One programmable oscillator with a default frequency of 148.5-MHz

■ Four programmable oscillators with four outputs each of various default

frequencies

■ Clock buffer with two outputs sourced by one of the above four

programmable oscillators with one output to the FPGA reference clock and Bull's Eye

■ SMA connectors for external LVPECL clock input

■ Power supply

■ 14-V – 20-V DC input

■ PCI Express edge connector power

■ 12-V PCI Express ATX supply

SMA

■ On-board power measurement circuitry

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ Mechanical

■ PCI Express long form factor (4.376” x 10.45”)

■ PCI Express chassis or bench-top operation

Dual FPGA

The development board includes two Arria V GT FPGAs that connect to other components on the board to provide a better transceiver and bandwidth design solution.

FPGA 1

The first FPGA device (FPGA 1) connects to the following components:

■ Communication ports

■ One PCI Express x8 edge connector

■ One universal HSMC expansion port (port A)

■ One USB 2.0 connector

■ One gigabit Ethernet port

■ Chip-to-Chip (C2C) bridge with 29 LVDS inputs and 29 LVDS outputs, and x8

transceivers

■ Two small form factor pluggable plus (SFP+) channels

■ One SMA 10 Gbps transceiver channel

■ Three Bull’s Eye 10 Gbps transceiver channels

■ Memory

■ 1152-Mbyte (MB) DDR3 SDRAM with a 72-bit data bus

■ 72-Mbit (Mb) QDRII+ SRAM

■ 1-Gbit (Gb) synchronous flash with a 16-bit data bus

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

1–4 Chapter 1: Overview

Board Component Blocks

■ General user I/O

■ LEDs and displays

■ Eight dual color user LEDs

■ Two-line character LCD display

■ Three configuration select LEDs

■ One configuration done LED

■ Two HSMC interface transmit/receive (TX/RX) LEDs

■ Three PCI Express LEDs

■ Five Ethernet LEDs

■ Push buttons

■ One CPU reset push button

■ One Max II CPLD EPM2210 System Controller configuration reset

push button

■ One load image push button (to program the FPGA from flash memory)

■ One image select push button (select an image to load from flash memory)

■ Three general user push buttons

■ Eight user control DIP switches

FPGA 2

The second FPGA device (FPGA 2) connects to the following components:

■ Communication ports

■ One universal HSMC expansion port (port B)

■ One FMC port

■ C2C bridge with 29 LVDS inputs and 29 LVDS outputs, and x8 transceivers

■ One serial digital interface (SDI) channel

■ One SMA 10 Gbps transceiver channel

■ One Bull's Eye 6 Gbps transceiver channel

■ One Bull’s Eye 10 Gbps transceiver channel

■ Memory

■ 1024-MB DDR3 SDRAM with a 64-bit data bus (soft controller)

■ 512-MB DDR3 SDRAM with a 32-bit data bus (hard IP controller)

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 1: Overview 1–5

Port B

Port A

1152-MB

DDR3

2x16 LCD

Push buttons

8 bi-color LEDs

CPLD

1-Gb Flash

FMC

x8 Edge

SMAs

10G

Gigabit Ethernet

PHY (RGMII)

On-Board

USB-Blaster II

and

USB Interface

Mini-USB

2.0

XCVR x1

Bull’s Eye

10G

XCVR x3

SDI

TX/RX

XCVR x1

Bull’s Eye

10G

Bull’s Eye

XCVR x1

SMAs

10G

XCVR x1

SFP+

XCVR x2

x16

x72

DDR3

(x64)

x32 Hard IP

(x64 Soft IP)

72-Mb

QDRII+

x36

x11

ADDR x16

XCVR x8 Chip-to Chip

LVDS x29 Chip-to Chip + 1 Clock Input

XVCR x8

XVCR x10

x80

CLKIN x3

CLKOUT x3

XCVR x4

x80

CLKIN x3

CLKOUT x3

XCVR x8

JTAG Chain

USB Interface x19

Programmable

Oscillators + 50 M, 100 M

Programmable

Oscillators + 50 M, 100 M

5AGTFD7K3F40

FPGA 1

5AGTFD7K3F40

FPGA 2

x16

Push Buttons

DIP Switches

8 bi-color LEDs

x16

Development Board Block Diagram

■ General user I/O

■ LEDs and displays

■ Eight dual color user LEDs

■ Two HSMC interface transmit/receive (TX/RX) LEDs

■ Push buttons

■ One CPU reset push button

■ Three general user push buttons

■ Eight user control DIP switches

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Arria V GT FPGA development board.

Figure 1–1. Arria V GT FPGA Development Board Block Diagram

Handling the Board

When handling the board, it is important to observe the following static discharge precaution:

December 2014 Altera Corporation Arria V GT FPGA Development Board

anti-static handling precautions when touching the board.

c Without proper anti-static handling, the board can be damaged. Therefore, use

Reference Manual

1–6 Chapter 1: Overview

Handling the Board

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Introduction

1 A complete set of schematics, a physical layout database, and GERBER files for the

f For information about powering up the board and installing the demonstration

2. Board Components

This chapter introduces the major components on the Arria V GT FPGA development board. Figure 2–1 illustrates the component locations and Tab le 2– 1 provides a brief description of all component features of the board.

development board reside in the Arria V GT FPGA development kit documents directory.

software, refer to the Arria V GT FPGA Development Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Arria V GT FPGA” on page 2–6

■ “MAX II CPLD EPM2210 System Controller” on page 2–8

■ “Configuration, Status, and Setup Elements” on page 2–14

■ “Clock Circuitry” on page 2–22

■ “General User Input/Output” on page 2–27

■ “Components and Interfaces” on page 2–33

■ “Memory” on page 2–54

■ “Power Supply” on page 2–68

■ “Statement of China-RoHS Compliance” on page 2–72

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–2 Chapter 2: Board Components

Arria V FPGA

(U16)

Arria V FPGA (U13)

FMC Bank B Voltage Select (J11)

FMC VCCPD

B4 Select (J5)

FMC Bank B Power Source Select (J28)

MAX II CPLD

EPM2210 System

Controller (U2)

PCI

Express Edge

Connector

(J14)

JTAG Connector

(J1)

Embedded

USB-Blaster

Circuitry (J7)

Gigabit Ethernet

Port (J8)

SFP+ Port (J10)

SFP+ Port (J15)

[Available in

Arria V GT

Development

Board Only]

DC Input Jack (J6)

Character LCD (J29)

Board Power Switch (SW1)

ATX Power Connector (J4)

FMC Connector (J9)

CPU Reset

Push

Button (S4)

DDR3A

(U7, U11, U18,

U21, U28)

DDR3C

(U19, U22)

DDR3B (U6, U12)

Tx/Rx

Transceivers

(J19-J22)

Tx/Rx

Transceivers

(J12, J13, J24, J25)

Fan Power

(J23)

Fan Power

(J14)

SDI Video

Por t

(J26, J27)

Bullseye

SMA

Connector

(J16)

Clock Input

SMA Connector (J10, J11)

Configuration LEDs (D12-D17)

Configuration Push Buttons

(S1-S3)

Flash

Memory (U4)

User LEDs (D18-D25)

User Push

Buttons (S5-S7)

User LEDs (D26-D33)

User Push Buttons (S9-S11)

CPU Reset

Push Button (S8)

User DIP Switch (SW3)

User DIP

Switch (SW2)

HSMC

Port A (J2)

HSMC

Port B (J3)

Board Overview

This section provides an overview of the Arria V GT FPGA development board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the available components.

Figure 2–1. Overview of the Arria V GT FPGA Development Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Arria V GT FPGA Development Board Components (Part 1 of 4)

Board Reference Type Description

Featured Devices

U13, U16 FPGA Two Arria V GT FPGA, 5AGTFD7K3F40I3N, 1517-pin FBGA.

U2 CPLD MAX II CPLD, EPM2210GF324, 324-pin BGA.

Configuration, Status, and Setup Elements

J1 JTAG connector

J7 On-Board USB-Blaster II Mini-USB 2.0 connector for programming and debugging the FPGA.

SW5 Board settings DIP switch

SW6 JTAG chain DIP switch

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Disables the on-board USB-Blaster II (for use with external USB-Blasters).

Controls the MAX as clock enable, SMA clock input control, and which image to load from flash memory at power-up. This switch is located on the bottom of the board.

II CPLD EPM2210 System Controller functions such

Enables and disables devices in the JTAG chain. This switch is located on the bottom of the board.

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Arria V GT FPGA Development Board Components (Part 2 of 4)

Board Reference Type Description

SW7 PCI Express DIP switch

Controls the PCI Express lane width by connecting together on the PCI Express edge connector. This switch is located on

prsnt

pins

the bottom of the board.

SW8

SW4

FPGA 1 mode select DIP switch

FPGA 2 mode select DIP switch

S2 Image select push button

Program configuration push button

Sets the Arria V MSEL[4,2,1] pins. This switch is located on the bottom of the board.

Toggles the configuration LEDs which selects the program image that loads from flash memory to the FPGA.

Configures the FPGA from flash memory image based on the program LEDs.

D1 Power LED Illuminates when 5.0-V power is present.

Indicate the transmit or receive activity of the JTAG chain. The Tx and

D2, D3 JTAG Tx/Rx LEDs

Rx LEDs blink when the link is in use and active. The LEDs are off when not in use and on when in use or idle.

D4, D5 HSMC port A LEDs You can configure these LEDs to indicate transmit or receive activity.

D6 HSMC port A present LED Illuminates when a daughtercard is plugged into the HSMC port A.

D7, D8 HSMC port B LEDs You can configure these LEDs to indicate transmit or receive activity.

D9 HSMC port B present LED Illuminates when a daughtercard is plugged into the HSMC port B.

Indicate the transmit or receive activity of the System Console USB

D10, D11 System Console Tx/Rx LEDs

interface. The Tx and Rx LEDs blink when the link is in use and active. The LEDs are off when not in use and on when in use or idle.

Illuminates to show the LED sequence that determines which flash

D12, D13, D14 Configuration LEDs

memory image loads to the FPGA when you press the

PGM1_SEL

push

button.

D15 Error LED Illuminates when the FPGA configuration from flash memory fails.

D16 Configuration done LED Illuminates when the FPGA is configured.

D17 Load LED

D36, D37, D38, D39, D40

Ethernet LEDs Shows the connection speed as well as transmit or receive activity.

D42, D43, D44 PCI Express link LEDs

Illuminates when the MAX II CPLD EPM2210 System Controller is actively configuring the FPGA.

You can configure these LEDs to display the PCI Express link width (x1, x4, x8).

Clock Circuitry

Programmable oscillator with default frequencies of CLK0=125 MHz,

C address

U48

Si5338 programmable oscillator

CLK1=100 MHz, CLK2=625 MHz, CLK3=125 MHz at I 71 HEX. The frequency is programmable using the clock GUI with the default MAX II CPLD EPM2210 System Controller design programmed into the MAX II EPM2210.

Programmable oscillator with default frequencies of CLK0=625 MHz,

C address

U53

Si5338 programmable oscillator

CLK1=156.25 MHz, CLK2=125 MHz, CLK3=125 MHz at I 70 HEX. The frequency is programmable using the clock GUI with the default MAX II CPLD EPM2210 System Controller design programmed into the MAX II EPM2210.

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Arria V GT FPGA Development Board Components (Part 3 of 4)

Board Reference Type Description

Programmable oscillator with default frequencies of CLK0=125 MHz,

C address

U52

Si5338 programmable oscillator

CLK1=100 MHz, CLK2=156.25 MHz, CLK3=125 MHz at I 73 HEX. The frequency is programmable using the clock GUI with the default MAX II CPLD EPM2210 System Controller design programmed into the MAX II EPM2210.

Programmable oscillator with default frequencies of CLK0=625 MHz,

C address

U34

Si5338 programmable oscillator

CLK1=100 MHz, CLK2=625 MHz, CLK3=125 MHz at I 72 HEX. The frequency is programmable using the clock GUI with the default MAX II CPLD EPM2210 System Controller design programmed into the MAX II EPM2210.

X1 125 MHz oscillator 125.000 MHz crystal oscillator for general purpose logic to FPGA 1.

X4 125 MHz oscillator 125.000 MHz crystal oscillator for general purpose logic to FPGA 2.

Programmable oscillator for SDI or REFCLK0RP/N with default

Si571 programmable Oscillator (148.5 MHz default)

frequencies at I using the clock GUI with the default MAX II EPM2210 System

C address 55 HEX. The frequency is programmable

Controller design programmed into the MAX II EPM2210.

Programmable oscillator with a default frequency of 100.00 MHz. The

X7, or J17 and J18 to U56 buffer

Programmable oscillator (100 MHz default)

frequency is programmable using the clock GUI with the default MAX II CPLD EPM2210 System Controller design programmed into the MAX II EPM2210. Multiplex with

CLKIN_SMA_P/N

based on

CLK_SEL

switch value.

X6 to U51 1:3 zero delay clock

50 MHz oscillator

buffer

J17, J18 Clock input SMAs

50.000 MHz crystal oscillator for general purpose logic. Three outputs connect to the FPGA 1, FPGA 2, and MAX II devices.

Drive LVPECL-compatible clock inputs into the clock multiplexer buffer (U56).

General User Input/Output

SW2 FPGA 1 user DIP switch Octal user DIP switches. When the switch is ON, a logic 0 is selected.

SW3 FPGA 2 user DIP switch Octal user DIP switches. When the switch is ON, a logic 0 is selected.

S1 MAX II reset push button Resets the MAX II CPLD EPM2210 System Controller.

S4 FPGA 1 CPU reset push button Resets the FPGA 1 logic.

S8 FPGA 2 CPU reset push button Resets the FPGA 2 logic.

S5–S7

S9–S11

FPGA 1 general user push buttons

FPGA 2 general user push buttons

Three user push buttons. Driven low when pressed.

D18–D25 FPGA 1 user LEDs Eight bi-color user LEDs. Illuminates when driven low.

D26–D33 FPGA 2 user LEDs Eight bi-color user LEDs. Illuminates when driven low.

D35 FPGA 1 LED LED indicator for FPGA 1.

D32 FPGA 2 LED LED indicator for FPGA 2.

Memory Devices

U4 Flash x16 memory

Synchronous burst mode flash device that provides a 16-bit 125-MB non-volatile memory port.

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

Board Overview

Table 2–1. Arria V GT FPGA Development Board Components (Part 4 of 4)

Board Reference Type Description

U8 QDRII+ memory

U7, U11, U18, U21, U28

DDR3A memory

9-MB QDRII+ SRAM with a 36-bit data bus. The device has a separate 36-bit read and 36-bit write port with DDR signalling at up to 400 MHz.

DDR3 SDRAM interface on FPGA 1. This 1152-MB DDR3 x72-bit data bus consists of four x16 devices and one x8 device with a single address or command bus.

DDR3 SDRAM interface on FPGA 2. There are two interface options:

■ Option 1: 512-MB interface with a 32-bit data bus. This DDR3

U6, U12, U19, U22

DDR3B/C memory

x32-bit data bus consists of two x16 devices with a single shared address.

■ Option 2: 1024-MB interface with a 64-bit data bus. This DDR3

x64-bit data bus consists of four x16 devices with a single shared address.

Communication Ports

J30 PCI Express edge connector

J2 HSMC port A

J3 HSMC port B

J7 Mini-USB type-AB connector

Gold-plated edge fingers connector for up to ×8 signaling in Gen1 and x4 Gen2 modes.

Provides four transceiver channels and 80 CMOS or 17 LVDS channels per the HSMC specification.

USB interface for programming the FPGA through on-board USB-Blaster II JTAG via a type-AB Mini-USB cable.

RJ-45 connector which provides a 10/100/1000 Ethernet connection

J8 Gigabit Ethernet

via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.

Display Ports

J29 Character LCD connector

Connector which interfaces to the provided 16 character × 2 line LCD module along with two standoffs at MTH7 and MTH8.

Power Supply

J6 DC input jack

Accepts a 19-V DC power supply. Do not use this input jack while the board is plugged into a PCI Express slot.

J4 ATX power connector PCI Express auxiliary power source option.

J30 PCI Express edge connector

SW1 Power switch

Interfaces to a PCI Express root port such as an appropriate PC motherboard.

Switch to power on or off the board when power is supplied from the DC input jack.

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–6 Chapter 2: Board Components

Featured Device: Arria V GT FPGA

The Arria V GT FPGA development board features two Arria V GT FPGA 5AGTFD7K3F40I3N device (U13 and U16) in a 1517-pin FBGA package.

f For more information about Arria V device family, refer to the Arria V Device

Handbook.

Tab le 2– 2 describes the features of the Arria V GT FPGA 5AGTFD7K3F40I3N device.

Table 2–2. Arria V GT FPGA Features

ALMs

Equivalent

LEs

M10K RAM

Blocks

Total RAM

Kbits

18-bit × 18-bit

Multipliers

PLLs Transceivers Package Type

190,240 504,000 24,140 27,046 2,312 16 36 1517-pin FBGA

I/O Resources

Figure 2–2 illustrates the bank organization and I/O count for the Arria V GT FPGA

5AGTFD7K3F40I3N device in the 1517-pin FBGA package.

Figure 2–2. Arria V GT FPGA Device I/O Bank Diagrams

2.5 V

Chip-to-Chip

LCD

USER

1.5 V

DDR3 x72

USB

ENET

PCIe SFP+

HSMA

SFP+

USER

QDRII+

Flash/MAX

2.5 V

1.8 V

AW1

HSMA

Bank 4A48

Bank 4B48

Bank 4C32

Bank 4D48

Bank 3D48

Bank 3C48

Bank 3B32

Bank 3A48

C2C

PCIe

SMA

HSMA

(6G)

GXB_R XCVRs

5AGTFD7K3F40I3N

Device 1

GXB_L XCVRs

SFP+

SMA

(6G)

SMA

(10G)

SMA

(10G)

SFP+

Bank 7A4848

Bank 7B

Bank 7C

Bank 7D

Bank 8D

Bank 8C

Bank 8B

Bank 8A

DDR3 x72

Chip-to-Chip

LCD

1.5 V

2.5 V

Bank 8A

Bank 8B

Bank 8C

Bank 8D

Bank 7D

Bank 7C

Bank 7B

Bank 7A

SMA

(10G)

5AGTFD7K3F40I3N

FMC

Device 2

SMA (6G)

GXB_L XCVRs

GXB_R

XCVRs

SMA

(10G)

SDI

C2C

HSMB

Bank 3A 48

Bank 3B 32

Bank 3C 48

Bank 3D 48

Bank 4D 48

Bank 4C 32

Bank 4B 48

Bank 4A 48

2.5 V

HSMB

SDI

USER

2.5 V

FMC

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–7

Featured Device: Arria V GT FPGA

Tab le 2– 3 lists the Arria V GT FPGA 1 pin count and usage by function on the

development board. Clocks are listed under special pins as it uses dedicated I/O pins.

Table 2–3. Arria V GT FPGA 1 Pin Count and Usage

Function I/O Standard I/O Count Special Pins

DDR3 ×72 interface 1.5-V SSTL 125 1 differential ×9 differential DQS

QDRII+ ×36 interface 1.8-V HSTL 103 1 differential ×36 differential DQS

MAX II System Controller 1.8-V CMOS 8 —

Flash 1.8-V CMOS 49 —

PCI Express 2.5-V CMOS 10 1 reference clock

HSMC port A 2.5-V CMOS + LVDS 84 1 reference clock

Gigabit Ethernet 2.5-V CMOS + LVDS 16 —

On-Board USB-Blaster II 1.5-V/2.5-V CMOS 19 —

SFP+ 2.5-V CMOS 16 2 reference clocks

Chip-to-chip bridge 2.5-V 120 2 reference clocks

Buttons 2.5-V CMOS 3 —

Switches 2.5-V CMOS 4 —

LCD 2.5-V CMOS 11 —

LEDs 2.5-V CMOS 16 —

Clocks or Oscillators 1.8-V CMOS + LVDS 10 5 differential clocks, 1 single-ended

Total I/O Used:

625

Transceivers

SMA or Bull’s Eye — 16 —

HSMC port A — 32 —

PCI Express — 32 —

Chip-to-chip bridge — 32 —

SFP+ — 8 —

Total Transceiver Used:

120

Tab le 2– 4 lists the Arria V GT FPGA 2 pin count and usage by function on the

development board. Clocks are listed under special pins as it uses dedicated I/O pins.

Table 2–4. Arria V GT FPGA 2 Pin Count and Usage (Part 1 of 2)

Function I/O Standard I/O Count Special Pins

DDR3 ×64 device 1.5-V SSTL 156 1 differential ×9 differential DQS

HSMC port B 2.5-V CMOS + LVDS 84 1 reference clock

FMC 2.5-V 178 1 reference clock

SDI 2.5-V CMOS 8 1 reference clock

Chip-to-chip bridge 2.5-V 120 1 reference clock

Buttons 2.5-V CMOS 4 —

Switches 2.5-V CMOS 8 —

LEDs 2.5-V CMOS 16 —

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–8 Chapter 2: Board Components

Information

Embedded

Blaster

MAX II CPLD

Power

Calculations

SLD-HUB

PFL

Power

Measurement

Results

Virtual-JTAG

Arria V

FPGA

LTC2418

Controller

Flash

Decoder

Encoder

GPIO

JTAG Control

Control

MAX II CPLD EPM2210 System Controller

Table 2–4. Arria V GT FPGA 2 Pin Count and Usage (Part 2 of 2)

Function I/O Standard I/O Count Special Pins

Clocks or Oscillators 1.8-V CMOS + LVDS 10 5 differential clocks, 1 single-ended

Total I/O Used:

584

Transceivers

SMAs or Bull's Eye — 12 —

HSMC port B — 16 —

FMC — 40 —

Chip-to-chip bridge — 32 —

Total Transceivers:

116

MAX II CPLD EPM2210 System Controller

The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power consumption monitoring

■ Virtual JTAG interface for PC-based GUI

■ Control registers for clocks

■ Control registers for remote system update

Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality

and external circuit connections as a block diagram.

Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX II CPLD EPM2210 System Controller

Tab le 2– 5 lists the I/O signals present on the MAX II CPLD EPM2210 System

Controller. The signal names and functions are relative to the MAX

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 1 of 5)

Schematic Signal Name

CLK125A_EN

CLK125B_EN

CLK50_EN

CLK_CONFIG

CLK_ENABLE

CLK_SEL

CLKIN_MAX_50

CLOCK_SCL

CLOCK_SDA

CPU1_RESETN

CPU2_RESETN

DEVICE1_LED

DEVICE2_LED

EXTRA_SIG0

EXTRA_SIG1

EXTRA_SIG2

FACTORY_USER1

FACTORY_USER2

FACTORY_REQUEST

FACTORY_STATUS

FLASH_ACCESSN

FLASH_ADVN

FLASH_CEN

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FM_A0

FM_A1

FM_A2

FM_A3

FM_A4

FM_A5

FM_A6

FM_A7

MAX II CPLD

Pin Number

I/O Standard Description

B13 2.5-V 125 MHz oscillator enable

D7 2.5-V 125 MHz oscillator enable

D11 2.5-V 50 MHz oscillator enable

K6 2.5-V 100 MHz configuration clock input

B5 2.5-V DIP switch for clock oscillator enable

E7 2.5-V DIP switch for clock select—SMA or oscillator

K13 2.5-V 50 MHz clock input

C14 2.5-V Programmable oscillator I2C clock

L4 2.5-V Programmable oscillator I2C data

B8 2.5-V FPGA 1 reset push button

E6 2.5-V FPGA 2 reset push button

D13 2.5-V FPGA 1 configuration done LED

C15 2.5-V FPGA 2 configuration done LED

B10 2.5-V Reserved for future use.

F16 1.8-V Reserved for future use.

J16 1.8-V Reserved for future use.

A5 2.5-V Load factory or user design at power-up

C4 2.5-V Load factory or user design at power-up

B9 2.5-V On-Board USB-Blaster II request to send FACTORY command

F10 2.5-V On-Board USB-Blaster II FACTORY command status

B12 1.8-V FM bus flash memory access indication

G15 1.8-V FM bus flash memory address valid

E16 1.8-V FM bus flash memory chip enable

E17 1.8-V FM bus flash memory clock

F14 1.8-V FM bus flash memory output enable

D18 1.8-V FM bus flash memory ready

F13 1.8-V FM bus flash memory reset

D17 1.8-V FM bus flash memory write enable

T17 1.8-V FM bus address

R15 1.8-V FM bus address

T16 1.8-V FM bus address

F15 1.8-V FM bus address

R16 1.8-V FM bus address

P15 1.8-V FM bus address

R17 1.8-V FM bus address

P14 1.8-V FM bus address

II device (U2).

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–10 Chapter 2: Board Components

MAX II CPLD EPM2210 System Controller

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 5)

Schematic Signal Name

FM_A8

FM_A9

FM_A10

FM_A11

FM_A12

FM_A13

FM_A14

FM_A15

FM_A16

FM_A17

FM_A18

FM_A19

FM_A20

FM_A21

FM_A22

FM_A23

FM_A24

FM_A25

FM_A26

FM_D0

FM_D1

FM_D2

FM_D3

FM_D4

FM_D5

FM_D6

FM_D7

FM_D8

FM_D9

FM_D10

FM_D11

FM_D12

FM_D13

FM_D14

FM_D15

FMC_C2M_PG

FMC_M2C_PG

FMC_PRSNT

FMC_SCL

MAX II CPLD

Pin Number

I/O Standard Description

R18 1.8-V FM bus address

N15 1.8-V FM bus address

P16 1.8-V FM bus address

N14 1.8-V FM bus address

P18 1.8-V FM bus address

M15 1.8-V FM bus address

N16 1.8-V FM bus address

P17 1.8-V FM bus address

N13 1.8-V FM bus address

M14 1.8-V FM bus address

N17 1.8-V FM bus address

M13 1.8-V FM bus address

N18 1.8-V FM bus address

M12 1.8-V FM bus address

M16 1.8-V FM bus address

K14 1.8-V FM bus address

K18 1.8-V FM bus address

K15 1.8-V FM bus address

H17 1.8-V FM bus address

L16 1.8-V FM data bus

M18 1.8-V FM data bus

L14 1.8-V FM data bus

L17 1.8-V FM data bus

L13 1.8-V FM data bus

L18 1.8-V FM data bus

M17 1.8-V FM data bus

L15 1.8-V FM data bus

K16 1.8-V FM data bus

K17 1.8-V FM data bus

D15 1.8-V FM data bus

C17 1.8-V FM data bus

E15 1.8-V FM data bus

C16 1.8-V FM data bus

D16 1.8-V FM data bus

E14 1.8-V FM data bus

P6 2.5-V FMC card to module power good

T4 2.5-V FMC module to card power good

U3 2.5-V FMC module present

R5 2.5-V FMC module clock

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–11

MAX II CPLD EPM2210 System Controller

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 5)

Schematic Signal Name

FMC_SDA

FPGA1_CEN

FPGA1_CEON

FPGA1_CONF_DONE

FPGA1_CONFIG_D0

FPGA1_CONFIG_D1

FPGA1_CONFIG_D2

FPGA1_CONFIG_D3

FPGA1_CONFIG_D4

FPGA1_CONFIG_D5

FPGA1_CONFIG_D6

FPGA1_CONFIG_D7

FPGA1_CONFIG_D8

FPGA1_CONFIG_D9

FPGA1_CONFIG_D10

FPGA1_CONFIG_D11

FPGA1_CONFIG_D12

FPGA1_CONFIG_D13

FPGA1_CONFIG_D14

FPGA1_CONFIG_D15

FPGA1_CVP_CONFDONE

FPGA1_MSEL0

FPGA1_MSEL1

FPGA1_MSEL2

FPGA1_MSEL3

FPGA1_MSEL4

FPGA1_NCONFIG

FPGA1_NSTATUS

FPGA1_PR_DONE

FPGA1_PR_ERROR

FPGA1_PR_READY

FPGA1_PR_REQUEST

FPGA2_CEN

FPGA2_CEON

FPGA2_CONF_DONE

FPGA2_CVP_CONFDONE

FPGA2_MSEL0

FPGA2_MSEL1

FPGA2_MSEL2

MAX II CPLD

Pin Number

I/O Standard Description

V2 2.5-V FMC module data

L1 2.5-V FPGA 1 chip enable

F11 2.5-V FPGA 1 chip output enable

M4 2.5-V FPGA 1 configuration done

D1 2.5-V FPGA configuration data

D3 2.5-V FPGA configuration data

E2 2.5-V FPGA configuration data

D4 2.5-V FPGA configuration data

E1 2.5-V FPGA configuration data

E3 2.5-V FPGA configuration data

F3 2.5-V FPGA configuration data

E4 2.5-V FPGA configuration data

F2 2.5-V FPGA configuration data

E5 2.5-V FPGA configuration data

F1 2.5-V FPGA configuration data

F4 2.5-V FPGA configuration data

G3 2.5-V FPGA configuration data

F5 2.5-V FPGA configuration data

G2 2.5-V FPGA configuration data

F6 2.5-V FPGA configuration data

M1 2.5-V FPGA 1 configuration via protocol done

F8 2.5-V FPGA 1 mode select 0

A6 2.5-V FPGA 1 mode select 1

E8 2.5-V FPGA 1 mode select 2

B7 2.5-V FPGA 1 mode select 3

D8 2.5-V FPGA 1 mode select 4

M5 2.5-V FPGA 1 configuration active

N1 2.5-V FPGA 1 configuration ready

K4 2.5-V FPGA 1 partial reconfiguration done

L5 2.5-V FPGA 1 partial reconfiguration error

L6 2.5-V FPGA 1 partial reconfiguration ready

L2 2.5-V FPGA 1 partial reconfiguration request

K5 2.5-V FPGA 2 chip enable

C11 2.5-V FPGA 2 chip output enable

M3 2.5-V FPGA 2 configuration done

B18 2.5-V FPGA 2 configuration via protocol done

U5 2.5-V FPGA 2 mode select 0

R7 2.5-V FPGA 2 mode select 1

V5 2.5-V FPGA 2 mode select 2

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–12 Chapter 2: Board Components

MAX II CPLD EPM2210 System Controller

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 5)

Schematic Signal Name

FPGA2_MSEL3

FPGA2_MSEL4

FPGA2_NCONFIG

FPGA2_NSTATUS

FPGA2_PR_DONE

FPGA2_PR_ERROR

FPGA2_PR_READY

FPGA2_PR_REQUEST

FPGA_DCLK

HSMA_PRSNTN

HSMB_PRSNTN

INIT_DONE1

INIT_DONE2

JTAG_EPM2210_TDI

JTAG_BLASTER_TDI

JTAG_TCK

JTAG_TMS

M570_CLOCK

M570_PCIE_JTAG_EN

MAX_BEN0

MAX_BEN1

MAX_BEN2

MAX_BEN3

MAX_CLK

MAX_CSN

MAX_OEN

MAX_WEN

MAX_CONF_DONE1

MAX_CTL0

MAX_CTL1

MAX_CTL2

MAX_ERROR1

MAX_LOAD1

MAX_RESETN

OVERTEMP1

OVERTEMP2

PGM1_CONFIG

MAX II CPLD

Pin Number

I/O Standard Description

T7 2.5-V FPGA 2 mode select 3

U6 2.5-V FPGA 2 mode select 4

M2 2.5-V FPGA 2 configuration active

M6 2.5-V FPGA 2 configuration ready

B16 2.5-V FPGA 2 partial reconfiguration done

D14 2.5-V FPGA 2 partial reconfiguration error

A17 2.5-V FPGA 2 partial reconfiguration ready

E13 2.5-V FPGA 2 partial reconfiguration request

N2 2.5-V FPGA configuration clock

A14 2.5-V HSMC port A present

E11 2.5-V HSMC port B present

T6 2.5-V FPGA initialization done

V4 2.5-V FPGA initialization done

M7 2.5-V MAX II CPLD on-board JTAG chain data in

N6 2.5-V MAX II CPLD on-board JTAG chain data out

R4 2.5-V JTAG chain clock

P5 2.5-V JTAG mode select

A10 1.8-V

D9 1.8-V

25-MHz clock to the on-board USB-Blaster II for sending FACTORY command

Low signal to disable the on-board USB-Blaster II when the PCI Express acts as a master to the JTAG chain.

B11 2.5-V FM bus MAX II byte enable 0

C10 2.5-V FM bus MAX II byte enable 1

A11 2.5-V FM bus MAX II byte enable 2

C9 2.5-V FM bus MAX II byte enable 3

J18 1.8-V FM bus MAX II clock

J17 1.8-V FM bus MAX II chip select

J15 1.8-V FM bus MAX II output enable

J14 1.8-V FM bus MAX II write enable

B3 2.5-V FPGA configuration done LED

E10 2.5-V FPGA 1 to MAX II option

A12 2.5-V FPGA 1 to MAX II option

D10 2.5-V FPGA 1 to MAX II option

C7 2.5-V FPGA 1 configuration error LED

B6 2.5-V FPGA 1 configuration active LED

E18 1.8-V MAX II reset push button

B14 2.5-V FPGA 1 fan RPM control

C12 2.5-V FPGA 2 fan RPM control

B4 2.5-V Load the flash memory image identified by the PGM LEDs

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–13

MAX II CPLD EPM2210 System Controller

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 5 of 5)

Schematic Signal Name

PGM1_LED0

PGM1_LED1

PGM1_LED2

PGM1_SEL

PHASE0

SDI_A_RX_BYPASS

SDI_A_RX_EN

SDI_A_TX_EN

SENSE_CS0N

SENSE_CS1N

SENSE_SCK

SENSE_SDI

SENSE_SDO

SI570_EN

SI571_EN

USB_CFG0

USB_CFG1

USB_CFG2

USB_CFG3

USB_CFG4

USB_CFG5

USB_CFG6

USB_CFG7

USB_CFG8

USB_CFG9

USB_CFG10

USB_CFG11

USB_CLK

VCCINT_SCL

VCCINT_SDA

MAX II CPLD

Pin Number

I/O Standard Description

A4 2.5-V Flash memory PGM select indicator 0

F7 2.5-V Flash memory PGM select indicator 1

C5 2.5-V Flash memory PGM select indicator 2

D6 2.5-V Toggles the

PGM_LED[0:2]

P8 2.5-V LTM4601 phase control

A8 2.5-V SDI equalization bypass

E9 2.5-V SDI receive enable

F9 2.5-V SDI transmit enable

F12 2.5-V Power monitor chip select

B15 2.5-V Power monitor chip select

E12 2.5-V Power monitor SPI clock

A15 2.5-V Power monitor SPI data in

D12 2.5-V Power monitor SPI data out

A13 2.5-V Si570 programmable oscillator enable

C13 2.5-V Si571 programmable VCXO enable

H14 1.8-V On-board USB-Blaster II data

H13 1.8-V On-board USB-Blaster II data

G13 1.8-V On-board USB-Blaster II data

F17 1.8-V On-board USB-Blaster II data

G12 1.8-V On-board USB-Blaster II data

F18 1.8-V On-board USB-Blaster II data

H16 1.8-V On-board USB-Blaster II data

G16 1.8-V On-board USB-Blaster II data

H15 1.8-V On-board USB-Blaster II data

G17 1.8-V On-board USB-Blaster II data

G14 1.8-V On-board USB-Blaster II data

G18 1.8-V On-board USB-Blaster II data

J6 2.5-V On-board USB-Blaster II clock

R3 2.5-V LTC3880 serial clock

R2 2.5-V LTC3880 serial data

LED sequence

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2–14 Chapter 2: Board Components

Configuration, Status, and Setup Elements

This section describes the board's configuration, status, and setup elements.

Configuration

This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System Controller device programming methods supported by the Arria V GT FPGA development board.

The Arria V GT FPGA development board supports the following three configuration methods:

■ On-board USB-Blaster II is the default method for configuring the FPGA at any

time using the Quartus II Programmer in JTAG mode with the supplied USB cable.

■ External USB-Blaster for configuring the FPGA using an external USB-Blaster that

connects to the JTAG programming header (J1).

■ Flash memory download for configuring the FPGA using stored images from the

flash memory on either power-up or pressing the program configuration push button,

PGM1_CONFIG

(S3).

FPGA Programming over On-Board USB-Blaster II

This configuration method implements a USB Type-AB connector (J7), a FTDI USB 2.0 PHY device (U5), and an Altera MAX II CPLD (U2) to allow the FPGA configuration using a USB cable that connects directly between the USB port on the board and a USB port of a PC running the Quartus II software.

The on-board USB-Blaster II in the MAX II CPLD EPM570GM100 normally masters the JTAG chain. To prevent contention between the JTAG masters, the on-board USB-Blaster II is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG connector.

If the USB-Blaster II is detected but no hardware is found in the chain, try reducing the clock frequency of the JTAG chain using these commands:

■ To check the current setting:

■ To set a new setting (example clock frequency = 16 M):

<cable-no> JtagClock 16M

The USB-Blaster II needs to be 16 M or slower in this case. Only 6 M, 16 M, and 24 M clock frequency options are available. Insert a value of 1 for the the only JTAG cable you attach to the board.

1 Installing daughtercards such as HSMC or FMC can affect performance and requires a

lower speed.

jtagconfig --getparam <cable-no> JtagClock

jtagconfig --setparam

<cable-no>

if this is

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Chapter 2: Board Components 2–15

Configuration, Status, and Setup Elements

Figure 2–4 illustrates the JTAG chain.

Figure 2–4. JTAG Chain

10-pin

DISABLE

JTAG Header

GPIO

Cypress

On-Board

USB-Blaster

JTAG Master

GPIO

ENABLE

TCK

TMS

TDO

TDI

Analog Switch

2.5V

TCK

TMS TDI

TDO

JTAG Slave

TCK

TMS

TDI

TDO

JTAG Slave

TCK

TMS

TDI

TDO

JTAG Slave

TCK

TMS

TDI

TDO

JTAG Slave

Arria V

(FPGA 2)

HSMC Por t A

HSMC Por t B

Arria V

(FPGA 1)

ALWAYS

ENABLED

(in-chain)

ALWAYS

ENABLED

(in-chain)

Installed

HSMC

Card

Installed

HSMC

Card

DIP switch

ENABLE

Analog Switch

TCK

TMS

TDI

TDO

JTAG Slave

TCK

TMS

TDI TDO

JTAG Slave

FMC Port

MAX II CPLD

System

Controller

Installed

FMC Card

ALWAYS

ENABLED

(in-chain)

Each jumper shown in Figure 2–4 is located in the JTAG chain DIP switch (SW6) on the back of the board. To connect a device or interface in the chain, you must set the corresponding switch from the JTAG chain DIP switch (SW6). The interface in the JTAG chain depends on the switch settings but the FPGAs and MAX II devices are always in the JTAG chain.

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2–16 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Flash Memory Programming

Flash memory programming is possible through a variety of methods.

The default method is to use the factory design—Board Update Portal (BUP). This design is an embedded webserver, which serves the BUP web page. The web page allows you to select new FPGA designs including hardware, software, or both in an industry-standard S-Record File (.flash) and write the design to the user hardware page (page 1) of the flash memory over the network.

The secondary method is to use the pre-built parallel flash loader (PFL) design included in the development kit. The development board implements the Altera PFL megafunction for flash memory programming. The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash memory device. This pre-built design contains the PFL megafunction that allows you to write either page 0, page 1, or other areas of flash memory over the USB interface using the Quartus II software. This method is used to restore the development board to its factory default settings.

Other methods to program the flash memory can be used as well, including the

Nios

II processor.

f For more information on the Nios II processor, refer to the Nios II Processor page of

the Altera website.

FPGA Programming from Flash Memory

On either power-up or by pressing the program configuration push button,

PGM1_CONFIG

FPGA from the flash memory when the megafunction reads 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 8-bit data is then written to the FPGA's dedicated configuration pins during configuration.

(S3), the MAX II CPLD EPM2210 System Controller's PFL configures the

PGM1_LED[2:0]

are ON. The PFL

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Chapter 2: Board Components 2–17

MAX II CPLD

EPM2210 System Controller

Arria V FPGA

FPGA_DATA [7:0]

FPGA_DCLK

FLASH_A [26:1]

FLASH_D [15:0]

DATA [7:0]

DCLK

INIT_DONE

nSTATUS

nCONFIG

CONF_DONE

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

MSEL[4:0] also

goes to MAX II CPLD

2.5 V

10 kΩ

nCE

CFI

Flash

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_A [26:0]

FLASH_D [15:0]

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_WPn

FLASH_ADVn

FPGA_nCONFIG

FPGA_CONF_DONE

FLASH_RYBSYn

FPGA_nSTATUS

FPGA_INIT_DONE

1.8 V

10 kΩ

FLASH_ADVn

CONF_DONE_LED

2.5 V

FLASH_CLK

FLASH_RSTn

FLASH_RESETn

PS Port

Flash Interface

56.2 Ω

100 Ω56.2 Ω

56.2 Ω

50 MHz

100 MHz

2.5 V

MAX_ERROR1

MAX_CONF_DONE1

MAX_LOAD1

FACTORY2

FACTORY1

CLK_ENABLE

CLK_SEL

MAX_RESETn

PGM1_CONFIG

PGM1_SEL

PGM1_LED0

PGM1_LED1

PGM1_LED2

DIP Switch

1 kΩ

Configuration, Status, and Setup Elements

Figure 2–5 shows the PFL configuration.

Figure 2–5. PFL Configuration

December 2014 Altera Corporation Arria V GT FPGA Development Board

f For information on the flash memory map storage, refer to the Arria V GT FPGA

Development Kit User Guide.

There are two pages reserved for the FPGA configuration data. The factory hardware page—page 0—loads upon power-up when the '1'. Otherwise, the user hardware page 1 loads. Pressing the (S3) loads the FPGA with a hardware page based on which D13, D14) illuminates.

Factory1

DIP switch (SW5.3) is set to

PGM1_CONFIG

PGM1_LED[2:0]

push button

LED (D12,

Reference Manual

2–18 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Tab le 2– 6 defines the hardware page that loads when you press the

PGM1_CONFIG

button (S3).

Table 2–6. PGM1_LED Settings

PGM1_LED0 PGM1_LED1 PGM1_LED2 Design

ON OFF OFF Factory hardware

OFF ON OFF User design 1

OFF OFF ON User design 2

FPGA Programming over External USB-Blaster

The JTAG programming header provides another method for configuring the FPGA using an external USB-Blaster device with the Quartus II Programmer running on a PC. The external USB-Blaster connects to the board through the JTAG connector (J5). Both FPGAs and the MAX II devices are always in the JTAG chain.

f For more information on the following topics, refer to the respective documents:

■ Board Update Portal and PFL design, refer to the Arria V GT FPGA Development Kit

User Guide.

■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.

push

Status Elements

The development board includes status LEDs. This section describes the status elements.

Tab le 2– 7 lists the LED board references, names, and functional descriptions.

Table 2–7. Board-Specific LEDs (Part 1 of 2)

Board

Reference

D1 Power — 5.0-V Blue LED. Illuminates when 5.0 V power is active.

D16 MAX_CONF_DONE1 — 2.5-V

D17 MAX_LOAD1 — 2.5-V

D15 MAX_ERROR1 — 2.5-V

D12, D13,

D14

Schematic Signal

Name

PGM1_LED[2:0] — 2.5-V

Arria V GT FPGA

Pin Number

I/O

Standard

Description

Green LED. Illuminates when the MAX II CPLD EPM2210 System Controller is successfully configured. Driven by the MAX II CPLD EPM2210 System Controller.

Green LED. Illuminates when the MAX II CPLD EPM2210 System Controller is actively configuring the FPGA. Driven by the MAX II CPLD EPM2210 System Controller wire-OR'd with the on-board USB-Blaster II CPLD.

Red LED. Illuminates when the MAX II CPLD EPM2210 System Controller fails to configure the FPGA. Driven by the MAX II CPLD EPM2210 System Controller.

Green LEDs. Illuminates to indicate which hardware page loads from flash memory when you press the

PGM1_SEL

board.

push button or when you power-on the

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Chapter 2: Board Components 2–19

Configuration, Status, and Setup Elements

Table 2–7. Board-Specific LEDs (Part 2 of 2)

Board

Reference

Schematic Signal

Name

Arria V GT FPGA

Pin Number

D34 DEVICE1_LED — 2.5-V

D35 DEVICE2_LED — 2.5-V

D36 ENET_LED_TX — 2.5-V

D37 ENET_LED_RX — 2.5-V

D40 ENET_LED_LINK10 — 2.5-V

D38 ENET_LED_LINK100 — 2.5-V

D39 ENET_LED_LINK1000 AN17 2.5-V

D4 HSMA_RX_LED AT15 2.5-V

D5 HSMA_TX_LED AH14 2.5-V

D6 HSMA_PRSNTn AW15 3.3-V

D7 HSMB_RX_LED AG26 2.5-V

D8 HSMB_TX_LED AM28 2.5-V

D9 HSMB_PRSNTn AT24 3.3-V

D44 PCIE_LED_X1 AC18 2.5-V

D43 PCIE_LED_X4 AD17 2.5-V

D42 PCIE_LED_X8 AT16 2.5-V

I/O

Standard

Description

Green LED. Illuminates when FPGA 1 is successfully configured. Driven by the MAX II CPLD EPM2210 System Controller.

Green LED. Illuminates when FPGA 2 is successfully configured. Driven by the MAX II CPLD EPM2210 System Controller.

Green LED. Illuminates to indicate Ethernet PHY transmit activity. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet PHY receive activity. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 10 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate HSMA port A receive data activity.

Green LED. Illuminates to indicate HSMA port A transmit data activity.

Green LED. Illuminates when HSMC port A has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card.

Green LED. Illuminates to indicate HSMA port B receive data activity.

Green LED. Illuminates to indicate HSMA port B transmit data activity.

Green LED. Illuminates when HSMC port B has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card.

Yellow LED. Configure this LED to display the PCI Express link width x1.

Yellow LED. Configure this LED to display the PCI Express link width x4.

Yellow LED. Configure this LED to display the PCI Express link width x8.

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Configuration, Status, and Setup Elements

Setup Elements

The development board includes several different kinds of setup elements. This section describes the following setup elements:

■ Board settings DIP switch

■ JTAG chain header switch

■ PCI Express control DIP switch

■ CPU reset push button

■ MAX II reset push button

■ Configuration push button

■ Image select push button

f For more information about the default settings of the DIP switches, refer to the

Arria V GT FPGA Development Kit User Guide.

Board Settings DIP Switch

The board settings DIP switch (SW5) controls various features specific to the board and the MAX switch controls and descriptions.

II CPLD EPM2210 System Controller logic design. Tab le 2– 8 lists the

Table 2–8. Board Settings DIP Switch Controls

Switch

Schematic

Signal Name

CLK_SEL

CLK_ENABLE

FACTORY_USER1

FACTORY_USER2

Description

ON : 100 MHz clock select

OFF : SMA input clock select

ON : Enable on-board oscillators

OFF : Disable on-board oscillators

ON : Load the factory design from flash for Arria V FPGA 1 at power up

OFF : Load the user design from flash at power up

Unused

JTAG Settings DIP Switch

The JTAG settings DIP switch (SW6) either remove or include devices in the active JTAG chain. However, the Arria V GT FPGAs and MAX Controller are always in the JTAG chain. Tab le 2 –9 lists the switch controls and its descriptions.

Table 2–9. JTAG Chain Header Switch Controls (Part 1 of 2)

Switch Schematic Signal Name Description

HSMA_JTAG_EN

HSMB_JTAG_EN

ON : Bypass HSMA

OFF : HSMA in-chain

ON : Bypass HSMB

OFF : HSMB in-chain

II CPLD EPM2210 System

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Chapter 2: Board Components 2–21

Configuration, Status, and Setup Elements

Table 2–9. JTAG Chain Header Switch Controls (Part 2 of 2)

Switch Schematic Signal Name Description

FMC_JTAG_EN

ON : Bypass FMC connector

OFF : FMC connector in-chain

Unused

PCI Express Control DIP Switch

The PCI Express control DIP switch (SW7) is provided to enable or disable different configurations. Table 2–10 lists the switch controls and descriptions.

Table 2–10. PCI Express Control DIP Switch Controls

Switch Schematic Signal Name Description

PCIE_PRSNT2n_x1

PCIE_PRSNT2n_x4

PCIE_PRSNT2n_x8

ON : Enable x1 presence detect

OFF : Disable x1 presence detect

ON : Enable x4 presence detect

OFF : Disable x4 presence detect

ON : Enable x8 presence detect

OFF : Disable x8 presence detect

Unused

CPU Reset Push Button

Each Arria V GT FPGA has a CPU reset push button,

CPU2_RESETn

FPGA

(S8) for FPGA 2. Both these push buttons are inputs to the Arria V GT

DEV_CLRn

pin and are open-drain I/Os from the MAX II CPLD System Controller. The push button is the default reset for both the FPGA and CPLD logic. The MAX II System Controller also drives these push button during POR.

1 You must enable the

function to work. Otherwise, the enable the signal in the Quartus II software, and then pull high on the board, every register within the FPGA resets to a low signal.

MAX II Reset Push Button

The MAX II reset push button, Controller. This push button is the default reset for the CPLD logic.

Configuration Push Button

The configuration push button, EPM2210 System Controller. The push button forces a reconfiguration of the FPGA from flash memory. The location in the flash memory is based on the settings of the

PGM1_LED[2:0]

Valid settings include memory reserved for FPGA designs.

, which is controlled by the image select push button,

CPU_RESETn

signal within the Quartus II software for this reset

CPU_RESETn

MAX_RESETn

PGM1_CONFIG

PGM1_LED0, PGM1_LED1

CPU1_RESETn

(S4) for FPGA 1 and

acts as a regular I/O pin. When you

, is an input to the MAX II CPLD System

(S3), is an input to the MAX II CPLD

, or

PGM1_LED2

PGM1_SEL

on the three pages in flash

(S2).

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2–22 Chapter 2: Board Components

Clock Circuitry

Image Select Push Button

The program select push button, System Controller. The push button toggles the which location in the flash memory is used to configure the FPGA. Refer to Table 2–6 for the

PGM1_LED[2:0]

sequence definitions.

PGM1_SEL

(S2), is an input to the MAX II CPLD

PGM1_LED[2:0]

sequence that selects

Clock Circuitry

This section describes the board's clock inputs and outputs.

On-Board Oscillators

The development board includes fixed and programmable oscillators with a frequency of 50-MHz, 100-MHz, 125-MHz, 148.5-MHz, 156.25-MHz, and 625-MHz.

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Chapter 2: Board Components 2–23

Clock Circuitry

Figure 2–6 shows the default frequencies of all external clocks going to the Arria V GT

FPGA development board.

Figure 2–6. Arria V GT FPGA Development Board Clocks

U51

REFCLK INPUT

50 MHz

SMA

Buffer

50 MHz

U56

SMA

Buffe

Si570

100 MHz

Default

U53

Si5388

CLK3

CLK2

CLK1

CLK0

125 MHz

156.25 MHz

625 MHz

100 MHz

Default

REFCLK1A_Q L0_P/N

PCIE_REF_CLK_P /N

REFCLK3_A_Q L1_P/N

REFCLK2_A_Q L1_P/N

REFCLK4_A_Q L2_P/N

100 MHz

(PCIe )

(SFP +)

50 MHz

125 MHz

CLKIN_MAX_50

100 MHz

U16

QL0

QL1

QL2

BO TA_P/N [1] N

KINBOTA_P/N[0] L

CLKI

CLK6

CLK7

B3 B4

B8 B7

50 MHz

CLKINA_50

CLK5

125 MHz

CLKA_125_P/N

CLK0

QR0

QR1

QR2

REFCLK0_A_Q R0_P/N

C2C)

(

REFCLK2_A_Q R1_P/N

(C2C , HSMA )

REFCLK4_A_Q R2_P/N

HSMA)

(

125 MHz

625 MHz

100 MHz

125 MHz

CLK3

CLK2

CLK1

CLK0

U48

Si5388

Clock Buffer

1:2

156.25 MHz

J16U25

Bullseye

Connector

CLK17

CLK19CLKINTOPA_P/N[0]

125 MHz

CLKINTOPA_P/N[1]

100 MHz

125 MHz

_50 B N

100 MHz

U13

QL0

QL1

QL2

B_125_P/

LK C

CLK

CLK6

CLK

B3 B4

B8 B7

50 MHz

100 MHz

U34

Si5388

CLK3

CLK2

CLK1

CLK0

125 MHz

625 MHz

100 MHz

625 MHz

REFCLK1_B_Q L0_P/N

REFCLK0_B_Q L0_P/N (C2C )

REFCLK2_B_Q L1_P/N (C2C )

REFCLK4_B_Q L2_P/N (C2C )

[ N

_P/

INB OTB

CLKINBOTB_P/N[1]

CLK

CLK7

CLK11

QR0

QR1

QR2

LK15 C

CLK

] 1

/N[0] P _

125 MHz

/N[ P _

U53

SDI (148.5 M/148.35 M)

Si571

148.5 MHz Default

EFCLK0_B_QR 0_P/N

(HSMB, SDI)

REFCLK1_B_Q R0_P/N (HSMB, SDI)

REFCLK2_B_Q R1_P/N

(FMC )

REFCLK3_B_Q R2_P/N (FMC )

125 MHz

156.25 MHz

100 MHz

125 MHz

U52

CLK3

CLK2

Si5388

CLK1

CLK0

KINTOPB

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2–24 Chapter 2: Board Components

Clock Circuitry

Tab le 2 –11 lists the oscillators, its I/O standard, and voltages required for the

development board.

Table 2–11. On-Board Oscillators

Source

X6 to U51 1:3 clock buffer

X7 to U56 1:6 clock buffer

U53

U48

Schematic Signal

Name

CLKIN_MAX_50

CLKINA_50

CLKINB_50

CLK_CONFIG

REFCLK1_A_QL0_P

REFCLK1_A_QL0_N

CLKINBOTA_P0

CLKINBOTA_N0

CLKINTOPA_P0

CLKINTOPA_N0

CLKINBOTB_P0

CLKINBOTB_N0

CLKINTOPB_P0

CLKINTOPB_N0

CLKA_125_P

CLKA_125_N

CLKB_125_P

CLKB_125_N

REFCLK0_QR0_P

REFCLK0_QL2_N

REFCLK4_A_QL2_P

REFCLK4_A_QL2_N

REFCLK3_A_BUF_P

REFCLK3_A_BUF_N

REFCLK2_A_QL1_P

REFCLK2_A_QL1_N

CLKINBOTA_P1

CLKINBOTA_N1

REFCLK4_A_QR2_P

REFCLK4_A_QR2_N

REFCLK2_A_QR1_P

REFCLK2_A_QR1_N

REFCLK0_A_QR0_P

REFCLK0_A_QR0_N

CLKINTOPA_P1

CLKINTOPA_N1

Arria V GT

Frequency I/O Standard

FPGA Pin

Application

Number

1.8-V —

50.000 MHz

1.8-V AF21

Nios II and MAX II CPLD

1.8-V AP34

100.000 MHz 2.5-V CMOS — Fast FPGA configuration

100.000 MHz

125.000 MHz

148.500 MHz

625.000 MHz

156.250 MHz

125.000 MHz

100.000 MHz

625.000 MHz

125.000 MHz

LVDS

(fanout buffer)

LVDS AP34

LVDS AN34

LVDS AD20

LVDS AC21

LVDS —

LVDS W 31

LVDS W 32

LVDS —

LVDS U31

LVDS U32

LVDS AL20

LVDS AK20

LVDS T9

LVDS T8

LVDS AB9

LVDS AB8

LVDS AF 8

LVDS AF 7

LVDS A2 2

LVDS A2 1

AE31

AE32

AD20

AC21

C20

D20

AK7

AJ7

C34

D34

PCI Express host/dual-XTL

Bottom edge FPGA 1 – QDRII+

Top edge FPGA 1 – DDR3

Bottom edge FPGA 2

Top edge FPGA 2 – DDR3

Fixed clock at 125 MHz for FPGA 1 bank 3A

Fixed clock at 125 MHz for FPGA 1 bank 3D

HD-SDI video

SFP+

SFP+, Bull's Eye connector,

1:2 clock to REFCLK3 on FPGA 1,

Bottom edge FPGA 1 – memory

HSMC port A, C2C

C2C

Top edge FPGA 1 – memory

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Chapter 2: Board Components 2–25

Clock Circuitry

Table 2–11. On-Board Oscillators

U34

U52

Source

Schematic Signal

Name

REFCLK4_B_QL2_P

REFCLK4_B_QL2_N

REFCLK2_B_QL1_P

REFCLK2_B_QL1_N

REFCLK0_B_QL0_P

REFCLK0_B_QL0_N

CLKINBOTB_P1

CLKINBOTB_N1

REFCLK3_B_QR2_P

REFCLK3_B_QR2_N

REFCLK2_B_QR1_P

REFCLK2_B_QR1_N

REFCLK1_B_QR0_P

REFCLK1_B_QR0_N

CLKINTOPB_P1

CLKINTOPB_N1

Frequency I/O Standard

625.000 MHz

100.000 MHz

625.000 MHz

125.000 MHz

100.000 MHz

156.250 MHz

125.000 MHz

LVDS U31

LVDS U32

LVDS AC31

LVDS AC32

LVDS AG32

LVDS AG33

LVDS AL20

LVDS AK20

LVDS T9

LVDS T8

LVDS Y 9

LVDS Y 8

LVDS A D9

LVDS A D8

LVDS H6

LVDS J 6

Arria V GT

FPGA Pin

Number

Application

C2C

Bottom edge FPGA 2 – memory

FMC

HSMC port B, SDI

Top edge FPGA 2

Off-Board Clock Input/Output

The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.

Tab le 2 –1 2 lists the clock inputs for the development board.

Table 2–12. Off-Board Clock Inputs

Source

SMA

HSMC

Schematic Signal

Name

CLKIN_SMA_P

CLKIN_SMA_N

HSMA_CLK_IN0

HSMA_CLK_IN_P1

HSMA_CLK_IN_N1

HSMA_CLK_IN_P2

HSMA_CLK_IN_N2

HSMB_CLK_IN0

HSMB_CLK_IN_P1

HSMB_CLK_IN_N1

Arria V GT

I/O Standard

LVPECL — Input to LVDS fan-out buffer (drives one REFCLK,

LVP ECL —

2.5-V AT7

LVDS/2.5-V AW 4

LVDS/LVTTL AV4

LVDS/LVTTL AR6

LVDS/LVTTL AP6

2.5-V AR6

LVDS/LVTTL AM33

LVDS/LVTTL AL33

FPGA Pin

Number

Description

one clock on the top edge and one on the bottom edge of each FPGA)

Single-ended input from the installed HSMC cable or board.

LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs.

Single-ended input from the installed HSMC cable or board.

LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs.

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Clock Circuitry

Table 2–12. Off-Board Clock Inputs

Source

HSMC

PCI Express Edge

Schematic Signal

Name

HSMB_CLK_IN_P2

HSMB_CLK_IN_N2

PCIE_REFCLK_P

PCIE_REFCLK_N

FMC_REFCLK_P0

FMC_REFCLK_P1

FMC_REFCLK_N0

FMC

FMC_REFCLK_N1

FMC_CLK_M2C_P0

FMC_CLK_M2C_P1

FMC_CLK_M2C_N0

Tab le 2 –1 3 lists the clock outputs for the development board.

Table 2–13. Off-Board Clock Outputs

Source

HSMC

Schematic Signal

Name

HSMA_CLK_OUT0

HSMA_CLK_OUT_P1

HSMA_CLK_OUT_N1

HSMA_CLK_OUT_P2

HSMA_CLK_OUT_N2

HSMB_CLK_OUT0

HSMB_CLK_OUT_P1

HSMB_CLK_OUT_N1

HSMB_CLK_OUT_P2

HSMB_CLK_OUT_N2

Arria V GT

I/O Standard

FPGA Pin

Description

Number

LVDS/LVTTL AU32

LVDS/LVTTL AT32

LVDS/LVTTL AG32

HCSL AG33

LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs.

LVDS input from the PCI Express edge connector.

LVDS AB9

LVDS V 9

LVDS AB8

LVDS input from the FMC board (drives two REFCLKs on FPGA 2)

LVDS V 8

LVDS AV 19

LVDS A F2 1

LVDS AU 19

LVDS input from the FMC board.

LVDS AE21

Arria V GT

I/O Standard

FPGA Pin

Description

Number

2.5V CMOS AL14 FPGA CMOS output (or GPIO)

LVDS/2.5V CMOS AU13

LVDS/2.5V CMOS AT13

LVDS/2.5V CMOS AM7

LVDS/2.5V CMOS AL7

LVDS output. Can also support 2x CMOS outputs.

2.5V CMOS AJ33 FPGA CMOS output (or GPIO)

LVDS/2.5V CMOS AM33

LVDS/2.5V CMOS AL34

LVDS/2.5V CMOS AU32

LVDS/2.5V CMOS AD26

LVDS output. Can also support 2x CMOS outputs.

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Chapter 2: Board Components 2–27

General User Input/Output

This section describes the user I/O interface to the FPGA, including the push buttons, DIP switches, status LEDs, character LCD, and SDI video output/input port.

User-Defined Push Buttons

The development board includes three user-defined push buttons for each FPGA device. For information on the system and safe reset push buttons, refer to “Setup

Elements” on page 2–20.

Board references S5, S6, and S7 are push buttons that allow you to interact with the Arria V GT FPGA 1 while S9, S10, and S11 are for use with the Arria V GT FPGA 2. When you press and hold down the button, the device pin is set to logic 0; when you release the button, the device pin is set to logic 1. There are no board-specific functions for these general user push buttons.

Tab le 2 –1 4 lists the user-defined push button schematic signal names and their

corresponding Arria V GT FPGA device pin numbers.

Table 2–14. User-Defined Push Button Schematic Signal Names and Functions

Board Reference

S11

S10

User-Defined DIP Switches

Schematic Signal

Name

USER1_PB0

USER1_PB1

USER1_PB2

USER2_PB0

USER2_PB1

USER2_PB2

Arria V GT FPGA Pin

Number

U16.T19 2.5-V

U16.R19 2.5-V

U16.F18 2.5-V

U13.D6 2.5-V

U13.C6 2.5-V

U13.K7 2.5-V

I/O Standard Description

User-defined push buttons for FPGA 1.

User-defined push buttons for FPGA 2.

Board references SW2 and SW3 are two sets of eight-pin DIP switches. There are no board-specific functions for these switches. Each of the Arria V GT FPGA have a set of user-defined DIP switch. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected.

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General User Input/Output

Tab le 2 –1 5 lists the user-defined DIP switch schematic signal names and their

corresponding Arria V GT FPGA pin numbers.

Table 2–15. User-defined DIP Switch Schematic Signal Names and Functions

Board Reference

SW2.1

SW2.2

SW2.3

SW2.4

SW2.5

SW2.6

SW2.7

SW2.8

SW3.1

SW3.2

SW3.3

SW3.4

SW3.5

SW3.6

SW3.7

SW3.8

Schematic

Signal Name

USER1_DIPSW0

USER1_DIPSW1

USER1_DIPSW2

USER1_DIPSW3

USER1_DIPSW4

USER1_DIPSW5

USER1_DIPSW6

USER1_DIPSW7

USER2_DIPSW0

USER2_DIPSW1

USER2_DIPSW2

USER2_DIPSW3

USER2_DIPSW4

USER2_DIPSW5

USER2_DIPSW6

USER2_DIPSW7

Arria V GT FPGA

Pin Number

P18 2.5-V

N18 2.5-V

C16 2.5-V

B16 2.5-V

G17 2.5-V

F17 2.5-V

D17 2.5-V

C17 2.5-V

C8 2.5-V

D8 2.5-V

E7 2.5-V

E6 2.5-V

G8 2.5-V

F8 2.5-V

D15 2.5-V

G11 2.5-V

I/O Standard Description

User-defined DIP switch that connects to FPGA 1.

User-defined DIP switch that connects to FPGA 2.

User-Defined LEDs

The development board includes general and user-defined LEDs. This section describes all user-defined LEDs. For information on board specific or status LEDs, refer to “Status Elements” on page 2–18.

General User-Defined LEDs

Board references D18 through D25 and D26 through D33 are two sets of eight pairs user-defined LEDs. Each of the Arria V GT FPGA have a set of user-defined LEDs. The LEDs illuminate when a logic 0 is driven, and turns off when a logic 1 is driven. There are no board-specific functions for these LEDs.

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Chapter 2: Board Components 2–29

General User Input/Output

Tab le 2 –1 6 lists the user-defined LED schematic signal names and their corresponding

Arria V GT FPGA pin numbers.

Table 2–16. User-Defined LED Schematic Signal Names and Functions

Board Reference

D25

D24

D23

D22

D21

D20

D19

D18

D33

D32

D31

D30

D29

D28

D27

D26

Schematic

Signal Name

USER1_LED_G0

USER1_LED_R0

USER1_LED_G1

USER1_LED_R1

USER1_LED_G2

USER1_LED_R2

USER1_LED_G3

USER1_LED_R3

USER1_LED_G4

USER1_LED_R4

USER1_LED_G5

USER1_LED_R5

USER1_LED_G6

USER1_LED_R6

USER1_LED_G7

USER1_LED_R7

USER2_LED_G0

USER2_LED_R0

USER2_LED_G1

USER2_LED_R1

USER2_LED_G2

USER2_LED_R2

USER2_LED_G3

USER2_LED_R3

USER2_LED_G4

USER2_LED_R4

USER2_LED_G5

USER2_LED_R5

USER2_LED_G6

USER2_LED_R6

USER2_LED_G7

USER2_LED_R7

Arria V GT FPGA

Pin Number

I/O Standard Description

U16.C15 2.5-V

U16.AL15 2.5-V

U16.R18 2.5-V

U16.AC15 2.5-V

U16.F11 2.5-V

U16.AD14 2.5-V

U16.AP11 2.5-V

U16.AN8 2.5-V

U16.AU14 2.5-V

U16.AP8 2.5-V

U16.AE16 2.5-V

U16.AK14 2.5-V

U16.AF15 2.5-V

U16.AG14 2.5-V

U16.AK15 2.5-V

U16.AH15 2.5-V

U13.M19 2.5-V

U13.N20 2.5-V

U13.L19 2.5-V

U13.C15 2.5-V

U13.K19 2.5-V

U13.AL28 2.5-V

U13.J19 2.5-V

U13.F11 2.5-V

U13.K20 2.5-V

U13.AJ31 2.5-V

U13.J20 2.5-V

U13.AN34 2.5-V

U13.T20 2.5-V

U13.AJ34 2.5-V

U13.R20 2.5-V

U13.AK33 2.5-V

User-defined LEDs for FPGA 1.

User-defined LEDs for FPGA 2.

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General User Input/Output

HSMC User-Defined LEDs

Each HSMC port has two LEDs located nearby. There are no board-specific functions for the HSMC LEDs. The LEDs are labeled TX and RX, and are intended to display data flow to and from the connected HSMC daughtercards. The LEDs are driven by the Arria V GT FPGA.

Tab le 2 –1 7 lists the HSMC user-defined LED schematic signal names and their

corresponding Arria V GT FPGA pin numbers.

Table 2–17. HSMC User-Defined LED Schematic Signal Names and Functions

Board

Reference

Schematic

Signal Name

HSMA_TX_LED

HSMA_RX_LED

HSMB_TX_LED

HSMB_RX_LED

Arria V GT FPGA

Pin Number

U16.AH14 2.5-V

U16.AT15 2.5-V

U13.AM28 2.5-V

U13.AG26 2.5-V

I/O Standard Description

LCD

The development board includes a single 14-pin 0.1" pitch dual-row header that interfaces to a 16 character × 2 line Lumex LCD display. The LCD has a 14-pin receptacle that mounts directly to the board's 14-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging or other purposes.

Tab le 2 –1 8 summarizes the LCD pin assignments. The signal names and directions are

relative to the Arria V GT FPGA.

Table 2–18. LCD Pin Assignments, Schematic Signal Names, and Functions

User-defined LEDs. Labeled TX for HSMC port A.

User-defined LEDs. Labeled RX for HSMC port A.

User-defined LEDs. Labeled TX for HSMC port B.

User-defined LEDs. Labeled RX for HSMC port B.

Board

Reference (J30)

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Schematic Signal Name

LCD1_DATA0

LCD1_DATA1

LCD1_DATA2

LCD1_DATA3

LCD1_DATA4

LCD1_DATA5

LCD1_DATA6

LCD1_DATA7

LCD1_D_Cn

LCD1_WEn

LCD1_CSn

Arria V GT FPGA

Pin Number

N20 2.5-V LCD data bus

R20 2.5-V LCD data bus

T20 2.5-V LCD data bus

J20 2.5-V LCD data bus

K20 2.5-V LCD data bus

J19 2.5-V LCD data bus

K19 2.5-V LCD data bus

L19 2.5-V LCD data bus

M19 2.5-V LCD data or command select

M20 2.5-V LCD write enable

E18 2.5-V LCD chip select

I/O Standard Description

Chapter 2: Board Components 2–31

General User Input/Output

Tab le 2 –1 9 lists the LCD pin definitions, and is an excerpt from Lumex data sheet.

Table 2–19. LCD Pin Definitions and Functions

Number

Symbol

Level

—

—GND (0 V)

Power supply

Function

5 V

— For LCD drive

4RS H/L

H: Data input

L: Instruction input

5R/W H/L

H: Data read (module to MPU)

L: Data write (MPU to module)

6 E H, H to L Enable

7–14 DB0–DB7 H/L Data bus—software selectable 4-bit or 8-bit mode

f For more information such as timing, character maps, interface guidelines, and other

related documentation, visit www.lumex.com.

SDI Video Output/Input

The SDI video port consists of a LMH0303SQx cable driver and a LMH0384SQ cable equalizer. The PHY devices from National Semiconductor interface to single-ended 75- SMB connectors.

The cable driver supports operation at 270 Mbit standard definition (SD), 1.5 Gbit high definition (HD), and 3.0 Gbit dual-link HD modes. Control signals are allowed for SD and HD modes selections, as well as device enable. The device can be clocked by the 148.5 MHz voltage-controlled crystal oscillator (VCXO) and matched to incoming signals within 50 ppm using the UP and DN voltage control lines to the VCXO.

Tab le 2 –2 0 lists the supported output standards for the SD and HD input.

Table 2–20. Supported Output Standards for SD and HD Input

SD_HD Input Supported Output Standards Rise TIme

0 SMPTE 424M, SMPTE 292M Faster

1 SMPTE 259M Slower

f For more information about the application circuit of the LMH0303SQx cable driver,

refer to the cable driver data sheet at www.national.com.

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General User Input/Output

Tab le 2 –2 1 summarizes the SDI video output interface pin assignments, signal names,

and functions.

Table 2–21. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (U24)

Schematic

Signal Name

SDI_A_TX_P

SDI_A_TX_N

SDI_A_TX_RSET

SDI_A_TX_EN

SDI_A_TX_SD_HDN

SDI_A_TXDRV_N

SDI_A_TXDRV_P

Arria V GT FPGA

Pin Number

I/O Standard Description

AH3 1.4-V PCML SDI video input P

AH4 1.4-V PCML SDI video input N

— 3.3-V Device reset pull up register

AK31 2.5-V Device enable

M20 2.5-V High definition select

— 3.3-V SDI video output from cable driver N

— 3.3-V SDI video output from cable driver P

The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and 3.0 Gbit dual-link HD modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute signal interface.

Tab le 2 –2 2 lists the cable equalizer lengths.

Table 2–22. SDI Cable Equalizer Lengths

Data Rate (Mbps) Cable Type Maximum Cable Length (m)

270

1485 140

Belden 1694A

400

2970 120

Figure 2–7 is an excerpt from the LMH0384SQ cable equalizer data sheet that shows

the SDI cable equalizer. On this development board, the output is a single-ended output, with the negative channel driving a load local to the board.

Figure 2–7. SDI Cable Equalizer

SDI Adaptive

Cable Equalizer

75 Ω

1.0 μF

37.4 Ω

SDI

MUTE

BYPASS

AEC+

REF

1.0 μF

SDO

AEC–

To FPGA

Coaxial Cable

MUTE

BYPASS

75 Ω

3.9 nH

REF

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Chapter 2: Board Components 2–33

Components and Interfaces

Tab le 2 –2 3 summarizes the SDI video input interface pin assignments, signal names,

and functions.

Table 2–23. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions

Board Reference

(U23)

Schematic

Signal Name

SDI_A_EQIN_P1

SDI_A_EQIN_N1

SDI_A_RX_BYPASS

SDI_A_RX_P

SDI_A_RX_N

SDI_A_RX_EN

SDI_A_RX_CDN

Components and Interfaces

This section describes the development board's communication ports and interface cards relative to the Arria V GT FPGA. The development board supports the following communication ports:

■ PCI Express

■ 10/100/1000 Ethernet

■ HSMC

■ SFP+ modules

Arria V GT FPGA

Pin Number

— 3.3-V SDI video cable equalizer input P

— 3.3-V SDI video cable equalizer input N

P19 2.5-V Equalizer bypass enable

AJ1 1.4-V PCML SDI video output P

AJ2 1.4-V PCML SDI video output N

AK34 2.5-V Device enable

—3.3-V

I/O Standard Description

SDI video cable equalizer input carrier detect output to LED

■ FMC connector

■ Bull’s Eye connector

PCI Express

The Arria V GT FPGA development board is designed to fit entirely into a PC motherboard with a ×8 PCI Express slot that can accommodate a full height long form factor add-in card. This interface uses the Arria V GT FPGA's PCI Express hard IP block, saving logic resources for the user logic application. The PCI express edge connector has a presence detect feature to allow the motherboard to determine if a card is installed.

f For more information on using the PCI Express hard IP block, refer to the PCI Express

Compiler User Guide.

The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 to ×8 by using Altera's PCIe MegaCore IP. You can also configure this board to a ×1, ×4, or ×8 interface through a DIP switch that connects the

The PCI Express edge connector has a connection speed of 2.5 Gbps/lane for a maximum of 20 Gbps full-duplex (Gen1) or 5.0 Gbps/lane for a maximum of 40 Gbps full-duplex (Gen2).

PRSNTn

pins for each bus width.

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MAX

= 1.15 V

CROSS MAX

= 550 mV

CROSS MIN

= 250 mV

MIN

= –0.30 V

REFCLK –

REFCLK +

Components and Interfaces

The power for the board can be sourced entirely from the PCI Express edge connector when installed into a PC motherboard. Although the board can also be powered by a laptop power supply for use on a lab bench, Altera recommends that you do not power up from both supplies at the same time. Ideal diode power sharing devices have been designed into this board to prevent damages or back-current from one supply to the other.

The

PCIE_REFCLK_P

signal is a 100 MHz differential input that is driven from the PC motherboard on to this board through the edge connector. This signal connects directly to a Arria V GT FPGA

REFCLK

input pin pair using DC coupling. This clock is terminated on the motherboard and therefore, no on-board termination is required. This clock can have spread-spectrum properties that change its period between

9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL).

Figure 2–8 shows the PCI Express reference clock levels.

Figure 2–8. PCI Express Reference Clock Levels

The JTAG and SMB are optional signals in the PCI Express specification. Therefore, the JTAG signal loopback from PCI Express TDI to PCI Express TDO and are not used on this board. The SMB signals are wired to the Arria V GT FPGA but are not required for normal operation.

Tab le 2 –2 4 summarizes the PCI Express pin assignments. The signal names and

directions are relative to the Arria V GT FPGA.

Table 2–24. PCI Express Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J4)

A11

B17

B31

B48

A14

A13

B15

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Schematic Signal Name

PCIE_JTAG_TCK

PCIE_JTAG_TDI

PCIE_JTAG_TDO

PCIE_JTAG_TMS

PCIE_PERSTN

PCIE_PRSNT1N

PCIE_PRSNT2N_X1

PCIE_PRSNT2N_X4

PCIE_PRSNT2N_X8

PCIE_REFCLK_N

PCIE_REFCLK_P

PCIE_RX_N0

Arria V GT FPGA

Pin Number

I/O Standard Description

— 1.4-V PCML JTAG chain clock

— 1.4-V PCML JTAG chain data in

— 1.4-V PCML JTAG chain data out

— 1.4-V PCML JTAG chain mode select

N9 1.4-V PCML Presence detect DIP switch

— 1.4-V PCML Presence detect DIP switch

AG33 1.4-V PCML Motherboard reference clock

AG32 1.4-V PCML Motherboard reference clock

AW36 1.4-V PCML Receive bus

Chapter 2: Board Components 2–35

Components and Interfaces

Table 2–24. PCI Express Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J4)

B20

B24

B28

B34

B38

B42

B46

B14

B19

B23

B27

B33

B37

B41

B45

A17

A22

A26

A30

A36

A40

A44

A48

A16

A21

A25

A29

A35

A39

A43

A47

B11

Schematic Signal Name

PCIE_RX_N1

PCIE_RX_N2

PCIE_RX_N3

PCIE_RX_N4

PCIE_RX_N5

PCIE_RX_N6

PCIE_RX_N7

PCIE_RX_P0

PCIE_RX_P1

PCIE_RX_P2

PCIE_RX_P3

PCIE_RX_P4

PCIE_RX_P5

PCIE_RX_P6

PCIE_RX_P7

PCIE_SMBCLK

PCIE_SMBDAT

PCIE_TX_CN0

PCIE_TX_CN1

PCIE_TX_CN2

PCIE_TX_CN3

PCIE_TX_CN4

PCIE_TX_CN5

PCIE_TX_CN6

PCIE_TX_CN7

PCIE_TX_CP0

PCIE_TX_CP1

PCIE_TX_CP2

PCIE_TX_CP3

PCIE_TX_CP4

PCIE_TX_CP5

PCIE_TX_CP6

PCIE_TX_CP7

PCIE_WAKEN_R

Arria V GT FPGA

Pin Number

I/O Standard Description

AT38 1.4-V PCML Receive bus

AP38 1.4-V PCML Receive bus

AM38 1.4-V PCML Receive bus

AH38 1.4-V PCML Receive bus

AF38 1.4-V PCML Receive bus

AD38 1.4-V PCML Receive bus

AB38 1.4-V PCML Receive bus

AW37 1.4-V PCML Receive bus

AT39 1.4-V PCML Receive bus

AP39 1.4-V PCML Receive bus

AM39 1.4-V PCML Receive bus

AH39 1.4-V PCML Receive bus

AF39 1.4-V PCML Receive bus

AD39 1.4-V PCML Receive bus

AB39 1.4-V PCML Receive bus

AV18 1.4-V PCML SMB clock

AM16 1.4-V PCML SMB data

AU36 1.4-V PCML Transmit bus

AR36 1.4-V PCML Transmit bus

AN36 1.4-V PCML Transmit bus

AL36 1.4-V PCML Transmit bus

AG36 1.4-V PCML Transmit bus

AE36 1.4-V PCML Transmit bus

AC36 1.4-V PCML Transmit bus

AA36 1.4-V PCML Transmit bus

AU37 1.4-V PCML Transmit bus

AR37 1.4-V PCML Transmit bus

AN37 1.4-V PCML Transmit bus

AL37 1.4-V PCML Transmit bus

AG37 1.4-V PCML Transmit bus

AE37 1.4-V PCML Transmit bus

AC37 1.4-V PCML Transmit bus

AA37 1.4-V PCML Transmit bus

AL16 1.4-V PCML Wake signal

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10/100/1000 Mbps

Ethernet MAC

Marvell 88E1111

PHY

Device

Transformer

RJ45

RGMII Interface

TXD[3:0]

RXD[3:0]

Components and Interfaces

10/100/1000 Ethernet

This development board supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The PHY-to-MAC interface employs RGMII using the Arria V GT FPGA LVDS pins in Soft-CDR mode at 1.25 Gbps transmit and receive. In 10-Mb or 100-Mb mode, the RGMII interface still runs at 1.25 GHz but the packet data is repeated 10 or 100 times. The MAC function must be provided in the FPGA for typical networking applications.

The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25 MHz reference clock driven from a dedicated oscillator. The PHY interfaces to a HALO HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Figure 2–9 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111

PHY.

Figure 2–9. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY

Tab le 2 –2 5 lists the Ethernet PHY interface pin assignments.

Table 2–25. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference

(U14)

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Schematic Signal

Name

ENET_GTX_CLK

ENET_INTN

ENET_LED_DUPLEX

ENET_LED_LINK10

ENET_LED_LINK100

ENET_LED_LINK1000

ENET_LED_RX

ENET_LED_TX

ENET_MDC

ENET_MDIO

ENET_RESETN

Arria V GT FPGA

Pin Number

I/O Standard Description

AN16 2.5-V CMOS RGMII transmit clock

AP16 2.5-V CMOS Management bus interrupt

— 2.5-V CMOS Duplex link LED

— 2.5-V CMOS 10-Mb link LED

— 2.5-V CMOS 100-Mb link LED

AN17 2.5-V CMOS 1000-Mb link LED

— 2.5-V CMOS RX data active LED

— 2.5-V CMOS TX data active LED

AJ18 2.5-V CMOS Management bus data clock

AL17 2.5-V CMOS Management bus data

AK17 2.5-V CMOS Device reset

Chapter 2: Board Components 2–37

Components and Interfaces

Table 2–25. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board

Reference

(U14)

Schematic Signal

Name

ENET_RSET

ENET_RX_CLK

ENET_RX_D0

ENET_RX_D1

ENET_RX_D2

ENET_RX_D3

ENET_RX_DV

ENET_RX_N

ENET_RX_P

ENET_TX_D0

ENET_TX_D1

ENET_TX_D2

ENET_TX_D3

ENET_TX_EN

ENET_TX_N

ENET_TX_P

ENET_XTAL_25MHZ

MDI_P0

MDI_N0

MDI_P1

MDI_N1

MDI_P2

MDI_N2

MDI_P3

MDI_N3

Arria V GT FPGA

Pin Number

— 2.5-V CMOS

AK7 2.5-V CMOS RGMII receive clock

AU17 2.5-V CMOS RGMII receive data

AT17 2.5-V CMOS RGMII receive data

AW16 2.5-V CMOS RGMII receive data

AH18 2.5-V CMOS RGMII receive data

AW17 2.5-V CMOS RGMII receive data valid

AK19 2.5-V CMOS RGMII receive channel

AL19 2.5-V CMOS RGMII receive channel

AT19 2.5-V CMOS RGMII transmit data

AU18 2.5-V CMOS RGMII transmit data

AH19 2.5-V CMOS RGMII transmit data

AG19 2.5-V CMOS RGMII transmit data

AP19 2.5-V CMOS RGMII transmit enable

AE19 2.5-V CMOS RGMII transmit channel

AF19 2.5-V CMOS RGMII transmit channel

— 2.5-V CMOS 25-MHz clock

— 2.5-V CMOS Media dependent interface 0

— 2.5-V CMOS Media dependent interface 1

— 2.5-V CMOS Media dependent interface 2

— 2.5-V CMOS Media dependent interface 3

I/O Standard Description

Bias voltage for the Ethernet PHY. This pin connects to ground through a 4.99-K resistor.

HSMC

The development board contains two HSMC interfaces—port A on device 1 and port B on device 2. HSMC port A and port B interfaces support both single-ended and differential signaling. This physical interface provides eight channels of

6.5536 Gbps-capable transceivers for the GT version of this board. The HSMC interface also supports a full SPI4.2 interface (17 LVDS channels), three input and output clocks, JTAG and SMB signals, as well as power for compatible HSMC cards. The LVDS channels can be used for CMOS signaling as well as LVDS.

1 The HSMC is an Altera-developed open specification, which allows you to expand

the functionality of the development board through the addition of daughtercards (HSMCs).

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–38 Chapter 2: Board Components

Components and Interfaces

f For more information about the HSMC specification such as signaling standards,

signal integrity, compatible connectors, and mechanical information, refer to the High

Speed Mezzanine Card (HSMC) Specification manual.

The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins, and 13 ground pins. The ground pins are located between the two rows of signal and power pins, acting both as a shield and a reference. The HSMC host connector is based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board connectors from Samtec. There are three banks in this connector. Bank 1 has every third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have all the pins populated as done in the QSH/QTH series.

Figure 2–10 shows the bank arrangement of signals with respect to the Samtec

connector's three banks.

Figure 2–10. HSMC Signal and Bank Diagram

Bank 3

Powe r

D(79.40)

-or-

LVDS

CLKIN2, CLKOUT2

Bank 2

Powe r

D(39:0)

-or-

D[3:0] + LVDS

CLKIN1, CLKOUT1

Bank 1 8 TX Channels CDR 8 RX Channels CDR

JTAG SMB

CLKIN0, CLKOUT0

The HSMC interface has programmable bi-directional I/O pins that can be used as

2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to, LVDS, mini-LVDS, and RSDS with up to 17 full-duplex channels.

1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and

single-ended I/O standards are only guaranteed to function when mixed according to either the generic single-ended pin-out or generic differential pin-out.

Tab le 2 –2 6 lists the HSMC port A interface pin assignments, signal names, and

functions.

Table 2–26. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5)

Board

Reference (J1)

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Schematic Signal Name

HSMA_TX_P7

HSMA_RX_P7

HSMA_TX_N7

Arria V GT

FPGA

I/O Standard Description

Pin Number

D3 1.5-V PCML Transceiver TX bit 7

E1 1.5-V PCML Transceiver RX bit 7

D4 1.5-V PCML Transceiver TX bit 7n

Chapter 2: Board Components 2–39

Components and Interfaces

Table 2–26. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)

Board

Reference (J1)

Schematic Signal Name

HSMA_RX_N7

HSMA_TX_P6

HSMA_RX_P6

HSMA_TX_N6

HSMA_RX_N6

HSMA_TX_P5

HSMA_RX_P5

HSMA_TX_N5

HSMA_RX_N5

HSMA_TX_P4

HSMA_RX_P4

HSMA_TX_N4

HSMA_RX_N4

HSMA_TX_P3

HSMA_RX_P3

HSMA_TX_N3

HSMA_RX_N3

HSMA_TX_P2

HSMA_RX_P2

HSMA_TX_N2

HSMA_RX_N2

HSMA_TX_P1

HSMA_RX_P1

HSMA_TX_N1

HSMA_RX_N1

HSMA_TX_P0

HSMA_RX_P0

HSMA_TX_N0

HSMA_RX_N0

HSMA_SDA

HSMA_SCL

JTAG_TCK

HSMA_JTAG_TMS

HSMA_JTAG_TDO

AVB_JTAG_TDO

HSMA_CLK_OUT0

HSMA_CLK_IN0

HSMA_D0

Arria V GT

FPGA

I/O Standard Description

Pin Number

E2 1.5-V PCML Transceiver RX bit 7n

H3 1.5-V PCML Transceiver TX bit 6

J1 1.5-V PCML Transceiver RX bit 6

H4 1.5-V PCML Transceiver TX bit 6n

J2 1.5-V PCML Transceiver RX bit 6n

K3 1.5-V PCML Transceiver TX bit 5

L1 1.5-V PCML Transceiver RX bit 5

K4 1.5-V PCML Transceiver TX bit 5n

L2 1.5-V PCML Transceiver RX bit 5n

M3 1.5-V PCML Transceiver TX bit 4

N1 1.5-V PCML Transceiver RX bit 4

M4 1.5-V PCML Transceiver TX bit 4n

N2 1.5-V PCML Transceiver RX bit 4n

AH3 1.5-V PCML Transceiver TX bit 3

AJ1 1.5-V PCML Transceiver RX bit 3

AH4 1.5-V PCML Transceiver TX bit 3n

AJ2 1.5-V PCML Transceiver RX bit 3n

V3 1.5-V PCML Transceiver TX bit 2

W1 1.5-V PCML Transceiver RX bit 2

V4 1.5-V PCML Transceiver TX bit 2n

W2 1.5-V PCML Transceiver RX bit 2n

T3 1.5-V PCML Transceiver TX bit 1

U1 1.5-V PCML Transceiver RX bit 1

T4 1.5-V PCML Transceiver TX bit 1n

U2 1.5-V PCML Transceiver RX bit 1n

P3 1.5-V PCML Transceiver TX bit 0

R1 1.5-V PCML Transceiver RX bit 0

P4 1.5-V PCML Transceiver TX bit 0n

R2 1.5-V PCML Transceiver RX bit 0n

AT14 2.5-V CMOS Management serial data

AU15 2.5-V CMOS Management serial clock

AV34 2.5-V CMOS JTAG clock signal

— 2.5-V CMOS JTAG mode select signal

— 2.5-V CMOS JTAG data output

AT34 2.5-V CMOS JTAG data output

AL14 LVDS or 2.5-V Dedicated CMOS clock out

AT7 LVDS or 2.5-V Dedicated CMOS clock in

AG16 2.5-V CMOS Dedicated CMOS I/O bit 0

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–40 Chapter 2: Board Components

Components and Interfaces

Table 2–26. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)

Board

Reference (J1)

Schematic Signal Name

HSMA_D1

HSMA_D2

HSMA_D3

HSMA_TX_D_P0

HSMA_RX_D_P0

HSMA_TX_D_N0

HSMA_RX_D_N0

HSMA_TX_D_P1

HSMA_RX_D_P1

HSMA_TX_D_N1

HSMA_RX_D_N1

HSMA_TX_D_P2

HSMA_RX_D_P2

HSMA_TX_D_N2

HSMA_RX_D_N2

HSMA_TX_D_P3

HSMA_RX_D_P3

HSMA_TX_D_N3

HSMA_RX_D_N3

HSMA_TX_D_P4

HSMA_RX_D_P4

HSMA_TX_D_N4

HSMA_RX_D_N4

HSMA_TX_D_P5

HSMA_RX_D_P5

HSMA_TX_D_N5

HSMA_RX_D_N5

HSMA_TX_D_P6

HSMA_RX_D_P6

HSMA_TX_D_N6

HSMA_RX_D_N6

HSMA_TX_D_P7

HSMA_RX_D_P7

HSMA_TX_D_N7

HSMA_RX_D_N7

HSMA_CLK_OUT_P1

HSMA_CLK_IN_P1

HSMA_CLK_OUT_N1

Arria V GT

FPGA

I/O Standard Description

Pin Number

AH16 2.5-V CMOS Dedicated CMOS I/O bit 1

AV13 2.5-V CMOS Dedicated CMOS I/O bit 2

AW13 2.5-V CMOS Dedicated CMOS I/O bit 3

AV6 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4

AW12 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5

AV7 LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6

AV12 LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7

AU6 LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8

AR18 LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9

AT6 LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10

AP18 LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11

AU9 LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12

AU8 LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13

AT9 LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14

AU7 LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15

AV10 LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16

AW8 LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17

AU10 LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18

AW7 LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19

AU12 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20

AW9 LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21

AT12 LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22

AV9 LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23

AP9 LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24

AU11 LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25

AN9 LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26

AT11 LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27

AP12 LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28

AR9 LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29

AN12 LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30

AT8 LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31

AM9 LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32

AW5 LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33

AL9 LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34

AW6 LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35

AU13 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36

AW4 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37

AT13 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–41

Components and Interfaces

Table 2–26. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)

Board

Reference (J1)

101

102

103

104

107

108

109

110

113

114

115

116

119

120

121

122

125

126

127

128

131

132

133

134

137

138

139

140

143

144

145

146

149

150

151

152

155

Schematic Signal Name

HSMA_CLK_IN_N1

HSMA_TX_D_P8

HSMA_RX_D_P8

HSMA_TX_D_N8

HSMA_RX_D_N8

HSMA_TX_D_P9

HSMA_RX_D_P9

HSMA_TX_D_N9

HSMA_RX_D_N9

HSMA_TX_D_P10

HSMA_RX_D_P10

HSMA_TX_D_N10

HSMA_RX_D_N10

HSMA_TX_D_P11

HSMA_RX_D_P11

HSMA_TX_D_N11

HSMA_RX_D_N11

HSMA_TX_D_P12

HSMA_RX_D_P12

HSMA_TX_D_N12

HSMA_RX_D_N12

HSMA_TX_D_P13

HSMA_RX_D_P13

HSMA_TX_D_N13

HSMA_RX_D_N13

HSMA_TX_D_P14

HSMA_RX_D_P14

HSMA_TX_D_N14

HSMA_RX_D_N14

HSMA_TX_D_P15

HSMA_RX_D_P15

HSMA_TX_D_N15

HSMA_RX_D_N15

HSMA_TX_D_P16

HSMA_RX_D_P16

HSMA_TX_D_N16

HSMA_RX_D_N16

HSMA_CLK_OUT_P2

Arria V GT

FPGA

I/O Standard Description

Pin Number

AV4 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 39

AL8 LVDS or 2.5-V LVDS TX bit 8 or CMOS bit 40

AW11 LVDS or 2.5-V LVDS RX bit 8 or CMOS bit 41

AK8 LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42

AW10 LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43

AK10 LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44

AR10 LVDS or 2.5-V LVDS RX bit 9 or CMOS bit 45

AK9 LVDS or 2.5-V LVDS TX bit 9n or CMOS bit 46

AP10 LVDS or 2.5-V LVDS RX bit 9n or CMOS bit 47

AL11 LVDS or 2.5-V LVDS TX bit 10 or CMOS bit 48

AM10 LVDS or 2.5-V LVDS RX bit 10 or CMOS bit 49

AK11 LVDS or 2.5-V LVDS TX bit 10n or CMOS bit 50

AL10 LVDS or 2.5-V LVDS RX bit 10n or CMOS bit 51

AL12 LVDS or 2.5-V LVDS TX bit 11 or CMOS bit 52

AJ13 LVDS or 2.5-V LVDS RX bit 11 or CMOS bit 53

AK12 LVDS or 2.5-V LVDS TX bit 11n or CMOS bit 54

AH13 LVDS or 2.5-V LVDS RX bit 11n or CMOS bit 55

AM13 LVDS or 2.5-V LVDS TX bit 12 or CMOS bit 56

AH11 LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57

AL13 LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58

AG11 LVDS or 2.5-V LVDS RX bit 12n or CMOS bit 59

AE12 LVDS or 2.5-V LVDS TX bit 13 or CMOS bit 60

AG12 LVDS or 2.5-V LVDS RX bit 13 or CMOS bit 61

AD12 LVDS or 2.5-V LVDS TX bit 13n or CMOS bit 62

AF12 LVDS or 2.5-V LVDS RX bit 13n or CMOS bit 63

AD11 LVDS or 2.5-V LVDS TX bit 14 or CMOS bit 64

AD13 LVDS or 2.5-V LVDS RX bit 14 or CMOS bit 65

AC12 LVDS or 2.5-V LVDS TX bit 14n or CMOS bit 66

AC13 LVDS or 2.5-V LVDS RX bit 14n or CMOS bit 67

AR13 LVDS or 2.5-V LVDS TX bit 15 or CMOS bit 68

AE13 LVDS or 2.5-V LVDS RX bit 15 or CMOS bit 69

AP13 LVDS or 2.5-V LVDS TX bit 15n or CMOS bit 70

AE14 LVDS or 2.5-V LVDS RX bit 15n or CMOS bit 71

AJ12 LVDS or 2.5-V LVDS TX bit 16 or CMOS bit 72

AG13 LVDS or 2.5-V LVDS RX bit 16 or CMOS bit 73

AH12 LVDS or 2.5-V LVDS TX bit 16n or CMOS bit 74

AF13 LVDS or 2.5-V LVDS RX bit 16n or CMOS bit 75

AM7 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 76

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–42 Chapter 2: Board Components

Components and Interfaces

Table 2–26. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)

Board

Reference (J1)

156

157

158

160

Schematic Signal Name

HSMA_CLK_IN_P2

HSMA_CLK_OUT_N2

HSMA_CLK_IN_N2

HSMA_PSNTN

Arria V GT

FPGA

I/O Standard Description

Pin Number

AR6 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77

AL7 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78

AP6 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79

AW15 2.5-V CMOS HSMC port A presence detect

Tab le 2 –2 7 lists the HSMC port B interface pin assignments, signal names, and

functions.

Table 2–27. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference (J2) Schematic Signal Name

HSMB_TX_P3

HSMB_RX_P3

HSMB_TX_N3

HSMB_RX_N3

HSMB_TX_P2

HSMB_RX_P2

HSMB_TX_N2

HSMB_RX_N2

HSMB_TX_P1

HSMB_RX_P1

HSMB_TX_N1

HSMB_RX_N1

HSMB_TX_P0

HSMB_RX_P0

HSMB_TX_N0

HSMB_RX_N0

HSMB_SDA

HSMB_SCL

JTAG_TCK

HSMB_JTAG_TMS

HSMB_JTAG_TDO

HSMB_JTAG_TDI

HSMB_CLK_OUT0

HSMB_CLK_IN0

HSMB_D0

HSMB_D1

HSMB_D2

HSMB_D3

Arria V GT

FPGA

I/O Standard Description

Pin Number

AT3 1.5-V PCML Transceiver TX bit 3

AU1 1.5-V PCML Transceiver RX bit 3

AT4 1.5-V PCML Transceiver TX bit 3n

AU2 1.5-V PCML Transceiver RX bit 3n

AP3 1.5-V PCML Transceiver TX bit 2

AR1 1.5-V PCML Transceiver RX bit 2

AP4 1.5-V PCML Transceiver TX bit 2n

AR2 1.5-V PCML Transceiver RX bit 2n

AM3 1.5-V PCML Transceiver TX bit 1

AN1 1.5-V PCML Transceiver RX bit 1

AM4 1.5-V PCML Transceiver TX bit 1n

AN2 1.5-V PCML Transceiver RX bit 1n

AK3 1.5-V PCML Transceiver TX bit 0

AL1 1.5-V PCML Transceiver RX bit 0

AK4 1.5-V PCML Transceiver TX bit 0n

AL2 1.5-V PCML Transceiver RX bit 0n

AG25 2.5-V CMOS Management serial data

AH26 2.5-V CMOS Management serial clock

AV34 2.5-V CMOS JTAG clock signal

— 2.5-V CMOS JTAG mode select signal

— 2.5-V CMOS JTAG data output

— 2.5-V CMOS JTAG data input

AJ33 LVDS or 2.5-V Dedicated CMOS clock out

AR6 LVDS or 2.5-V Dedicated CMOS clock in

AW25 2.5-V CMOS Dedicated CMOS I/O bit 0

AW26 2.5-V CMOS Dedicated CMOS I/O bit 1

AV25 2.5-V CMOS Dedicated CMOS I/O bit 2

AV24 2.5-V CMOS Dedicated CMOS I/O bit 3

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–43

Components and Interfaces

Table 2–27. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference (J2) Schematic Signal Name

101

102

HSMB_TX_D_P0

HSMB_RX_D_P0

HSMB_TX_D_N0

HSMB_RX_D_N0

HSMB_TX_D_P1

HSMB_RX_D_P1

HSMB_TX_D_N1

HSMB_RX_D_N1

HSMB_TX_D_P2

HSMB_RX_D_P2

HSMB_TX_D_N2

HSMB_RX_D_N2

HSMB_TX_D_P3

HSMB_RX_D_P3

HSMB_TX_D_N3

HSMB_RX_D_N3

HSMB_TX_D_P4

HSMB_RX_D_P4

HSMB_TX_D_N4

HSMB_RX_D_N4

HSMB_TX_D_P5

HSMB_RX_D_P5

HSMB_TX_D_N5

HSMB_RX_D_N5

HSMB_TX_D_P6

HSMB_RX_D_P6

HSMB_TX_D_N6

HSMB_RX_D_N6

HSMB_TX_D_P7

HSMB_RX_D_P7

HSMB_TX_D_N7

HSMB_RX_D_N7

HSMB_CLK_OUT_P1

HSMB_CLK_IN_P1

HSMB_CLK_OUT_N1

HSMB_CLK_IN_N1

HSMB_TX_D_P8

HSMB_RX_D_P8

Arria V GT

FPGA

I/O Standard Description

Pin Number

AC29 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4

AC25 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5

AB29 LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6

AB25 LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7

AE28 LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8

AF25 LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9

AD28 LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10

AE25 LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11

AE29 LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12

AD27 LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13

AD29 LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14

AC27 LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15

AK27 LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16

AB28 LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17

AJ27 LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18

AB27 LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19

AL29 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20

AJ28 LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21

AK29 LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22

AH28 LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23

AL30 LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24

AG28 LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25

AK30 LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26

AF28 LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27

AL32 LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28

AH30 LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29

AK32 LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30

AG30 LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31

AM31 LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32

AP29 LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33

AL31 LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34

AN29 LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35

AM34 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36

AM33 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37

AL34 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38

AL33 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 39

AN27 LVDS or 2.5-V LVDS TX bit 8 or CMOS bit 40

AU29 LVDS or 2.5-V LVDS RX bit 8 or CMOS bit 41

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–44 Chapter 2: Board Components

Components and Interfaces

Table 2–27. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference (J2) Schematic Signal Name

103

104

107

108

109

110

113

114

115

116

119

120

121

122

125

126

127

128

131

132

133

134

137

138

139

140

143

144

145

146

149

150

151

152

155

156

157

HSMB_TX_D_N8

HSMB_RX_D_N8

HSMB_TX_D_P9

HSMB_RX_D_P9

HSMB_TX_D_N9

HSMB_RX_D_N9

HSMB_TX_D_P10

HSMB_RX_D_P10

HSMB_TX_D_N10

HSMB_RX_D_N10

HSMB_TX_D_P11

HSMB_RX_D_P11

HSMB_TX_D_N11

HSMB_RX_D_N11

HSMB_TX_D_P12

HSMB_RX_D_P12

HSMB_TX_D_N12

HSMB_RX_D_N12

HSMB_TX_D_P13

HSMB_RX_D_P13

HSMB_TX_D_N13

HSMB_RX_D_N13

HSMB_TX_D_P14

HSMB_RX_D_P14

HSMB_TX_D_N14

HSMB_RX_D_N14

HSMB_TX_D_P15

HSMB_RX_D_P15

HSMB_TX_D_N15

HSMB_RX_D_N15

HSMB_TX_D_P16

HSMB_RX_D_P16

HSMB_TX_D_N16

HSMB_RX_D_N16

HSMB_CLK_OUT_P2

HSMB_CLK_IN_P2

HSMB_CLK_OUT_N2

Arria V GT

FPGA

I/O Standard Description

Pin Number

AM27 LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42

AT29 LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43

AP30 LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44

AW31 LVDS or 2.5-V LVDS RX bit 9 or CMOS bit 45

AN30 LVDS or 2.5-V LVDS TX bit 9n or CMOS bit 46

AW30 LVDS or 2.5-V LVDS RX bit 9n or CMOS bit 47

AR28 LVDS or 2.5-V LVDS TX bit 10 or CMOS bit 48

AW28 LVDS or 2.5-V LVDS RX bit 10 or CMOS bit 49

AP28 LVDS or 2.5-V LVDS TX bit 10n or CMOS bit 50

AW29 LVDS or 2.5-V LVDS RX bit 10n or CMOS bit 51

AV30 LVDS or 2.5-V LVDS TX bit 11 or CMOS bit 52

AU27 LVDS or 2.5-V LVDS RX bit 11 or CMOS bit 53

AU30 LVDS or 2.5-V LVDS TX bit 11n or CMOS bit 54

AT27 LVDS or 2.5-V LVDS RX bit 11n or CMOS bit 55

AV31 LVDS or 2.5-V LVDS TX bit 12 or CMOS bit 56

AW27 LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57

AU31 LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58

AV27 LVDS or 2.5-V LVDS RX bit 12n or CMOS bit 59

AR27 LVDS or 2.5-V LVDS TX bit 13 or CMOS bit 60

AW32 LVDS or 2.5-V LVDS RX bit 13 or CMOS bit 61

AP27 LVDS or 2.5-V LVDS TX bit 13n or CMOS bit 62

AW33 LVDS or 2.5-V LVDS RX bit 13n or CMOS bit 63

AP31 LVDS or 2.5-V LVDS TX bit 14 or CMOS bit 64

AT31 LVDS or 2.5-V LVDS RX bit 14 or CMOS bit 65

AN31 LVDS or 2.5-V LVDS TX bit 14n or CMOS bit 66

AR31 LVDS or 2.5-V LVDS RX bit 14n or CMOS bit 67

AP32 LVDS or 2.5-V LVDS TX bit 15 or CMOS bit 68

AV28 LVDS or 2.5-V LVDS RX bit 15 or CMOS bit 69

AN32 LVDS or 2.5-V LVDS TX bit 15n or CMOS bit 70

AU28 LVDS or 2.5-V LVDS RX bit 15n or CMOS bit 71

AP33 LVDS or 2.5-V LVDS TX bit 16 or CMOS bit 72

AT30 LVDS or 2.5-V LVDS RX bit 16 or CMOS bit 73

AN33 LVDS or 2.5-V LVDS TX bit 16n or CMOS bit 74

AR30 LVDS or 2.5-V LVDS RX bit 16n or CMOS bit 75

AE26 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 76

AU32 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77

AD26 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–45

Components and Interfaces

Table 2–27. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board

Reference (J2) Schematic Signal Name

158

160

HSMB_CLK_IN_N2

HSMB_PRSNTN

Arria V GT

FPGA

Pin Number

AT32 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79

AT24 2.5-V CMOS HSMC port B presence detect

I/O Standard Description

SFP+ Modules

The development board include two SFP+ modules that use transceiver channels from the FPGA. These modules takes in serial data from the FPGA and transform them into optical signals. Both SFP+ ports are active and include the SFP+ cage assembly only when the Arria V GT FPGA device is installed.

1 The Arria V GX FPGA development board includes only one SFP+ cage assembly for

the SFP+ port used by the device.

Tab le 2 –2 8 list the SFP+ modules interface pin assignments, signal names, and

functions.

Table 2–28. SFP+ Modules Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference

SFP+ Module (J10)

SFP+ Module (J15)

Schematic

Signal Name

SFP_MOD_ABS1

SFP_OP_RX_LOS1

SFP_OP_TX_FLT1

SFP_RX_N1

SFP_RX_P1

SFP_SCL1

SFP_SDA1

SFP_TX_DIS1

SFP_TX_N1

SFP_TX_P1

SFP_TX_RS01

SFP_TX_RS11

SFP_MOD_ABS2

SFP_OP_RX_LOS2

SFP_OP_TX_FLT2

SFP_RX_N2

SFP_RX_P2

SFP_SCL2

SFP_SDA2

SFP_TX_DIS2

Arria V GT FPGA

Pin Number

AK16 3.3-V LVTTL Module present indicator

AN19 3.3-V LVTTL Signal present indicator

AG17 3.3-V LVTTL Transmitter fault indicator

Y38 3.3-V LVTTL Receiver data

Y39 3.3-V LVTTL Receiver data

AL18 3.3-V LVTTL Serial 2-wire clock

AC16 3.3-V LVTTL Serial 2-wire data

AN15 3.3-V LVTTL Drive low to disable transmitter

W36 3.3-V LVTTL Transmitter data

W37 3.3-V LVTTL Transmitter data

AN14 3.3-V LVTTL Reserved

AE15 3.3-V LVTTL Reserved

AT16 3.3-V LVTTL Module present indicator

AH17 3.3-V LVTTL Signal present indicator

AM18 3.3-V LVTTL Transmitter fault indicator

K38 3.3-V LVTTL Receiver data

K39 3.3-V LVTTL Receiver data

AD16 3.3-V LVTTL Serial 2-wire clock

AP15 3.3-V LVTTL Serial 2-wire data

AD15 3.3-V LVTTL Drive low to disable transmitter

I/O Standard Description

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–46 Chapter 2: Board Components

Table 2–28. SFP+ Modules Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Components and Interfaces

Board

Reference

19 SFP_TX_N2 J36 3.3-V LVTTL Transmitter data

18 SFP_TX_P2 J37 3.3-V LVTTL Transmitter data

7 SFP_TX_RS02 AP14 3.3-V LVTTL Reserved

9 SFP_TX_RS12 AN7 3.3-V LVTTL Reserved

Schematic

Signal Name

Arria V GT FPGA

Pin Number

I/O Standard Description

FMC Connector

The development board contains a high pin count (HPC) FPGA mezzanine card (FMC) connector that functions with a quadrature amplitude modulation (QAM) digital-to-analog converter (DAC) FMC module or daughter card. This pinout satisfies a QAM DAC that requires 58 LVDS data output pairs, one LVDS input clock pair, and three low-voltage differential signaling (LVDS) control pairs from the Arria V. These pins also have the option to be used as single-ended I/O pins. The VCCIO supply for the FMC A banks in the low pin count (LPC) and HPC provide a variable voltage of 1.5 V, 1.8 V, 2.5 V (default), or 3.3 V. The VCCIO supply for the FMC B bank in the HPC provides a variable voltage from 1.2 V to 3.3 V, which can be supplied by the FMC module. However, for the sake of device safety concerns, a jumper is available for you to connect this bank to the same VCCIO used for the FMC A banks. This allows the VCCIO pins on the FPGA to be tied to a known power. The VCCIO pins also allows you the option to perform a manual check for the module’s input voltage before connecting to the FPGA. This is to ensure that the module does not exceed the power supply maximum voltage rating.

Tab le 2 –2 9 lists the FMC connector pin assignments, signal names, and functions.

Table 2–29. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 7)

Board

Reference

(J10)

A23

A27

A31

A35

Schematic

Signal Name

FMC_C2M_PG

FMC_CLK_BIDIR_P2

FMC_CLK_BIDIR_N2

FMC_CLK_BIDIR_P3

FMC_CLK_BIDIR_N3

FMC_CLK_DIR

FMC_CLK_M2C_P0

FMC_CLK_M2C_N0

FMC_CLK_M2C_P1

FMC_CLK_M2C_N1

FMC_DP_C2M_N0

FMC_DP_C2M_N1

FMC_DP_C2M_N2

FMC_DP_C2M_N3

FMC_DP_C2M_N4

Arria V GT

FPGA

Pin Number

— 2.5-V CMOS Power good output

AE23 2.5-V CMOS Clock input or output 2

AD22 2.5-V CMOS Clock input or output 2

AU22 2.5-V CMOS Clock input or output 3

AT22 2.5-V CMOS Clock input or output 3

AW21 2.5-V CMOS Clock direction select for

AV19 2.5-V CMOS Clock input 0

AU19 2.5-V CMOS Clock input 0

AF21 2.5-V CMOS Clock input 1

AE21 2.5-V CMOS Clock input 1

AD4 2.5-V CMOS Transmit channel

Y4 2.5-V CMOS Transmit channel

T4 2.5-V CMOS Transmit channel

P4 2.5-V CMOS Transmit channel

H4 2.5-V CMOS Transmit channel

I/O Standard Description

FMC_CLK_BIDIR

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–47

Components and Interfaces

Table 2–29. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 7)

Board

Reference

(J10)

A39

B37

B33

B29

B25

A22

A26

A30

A34

A38

B36

B32

B28

B24

A11

A15

A19

B17

B13

A10

A14

A18

B16

B12

B20

Schematic

Signal Name

FMC_DP_C2M_N5

FMC_DP_C2M_N6

FMC_DP_C2M_N7

FMC_DP_C2M_N8

FMC_DP_C2M_N9

FMC_DP_C2M_P0

FMC_DP_C2M_P1

FMC_DP_C2M_P2

FMC_DP_C2M_P3

FMC_DP_C2M_P4

FMC_DP_C2M_P5

FMC_DP_C2M_P6

FMC_DP_C2M_P7

FMC_DP_C2M_P8

FMC_DP_C2M_P9

FMC_DP_M2C_N0

FMC_DP_M2C_N1

FMC_DP_M2C_N2

FMC_DP_M2C_N3

FMC_DP_M2C_N4

FMC_DP_M2C_N5

FMC_DP_M2C_N6

FMC_DP_M2C_N7

FMC_DP_M2C_N8

FMC_DP_M2C_N9

FMC_DP_M2C_P0

FMC_DP_M2C_P1

FMC_DP_M2C_P2

FMC_DP_M2C_P3

FMC_DP_M2C_P4

FMC_DP_M2C_P5

FMC_DP_M2C_P6

FMC_DP_M2C_P7

FMC_DP_M2C_P8

FMC_DP_M2C_P9

FMC_GBTCLK_M2C_P0

FMC_GBTCLK_M2C_N0

FMC_GBTCLK_M2C_P1

Arria V GT

FPGA

I/O Standard Description

Pin Number

M4 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

K4 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

F4 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

D4 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

B4 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

AD3 2.5-V CMOS Transmit channel

Y3 2.5-V CMOS Transmit channel

T3 2.5-V CMOS Transmit channel

P3 2.5-V CMOS Transmit channel

H3 2.5-V CMOS Transmit channel

M3 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

K3 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

F3 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

D3 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

B3 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

AE2 2.5-V CMOS Transmit channel

AA2 2.5-V CMOS Transmit channel

U2 2.5-V CMOS Transmit channel

R2 2.5-V CMOS Transmit channel

J2 2.5-V CMOS Transmit channel

N2 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

L2 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

G2 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

E2 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

C2 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

AE1 2.5-V CMOS Transmit channel

AA1 2.5-V CMOS Transmit channel

U1 2.5-V CMOS Transmit channel

R1 2.5-V CMOS Transmit channel

J1 2.5-V CMOS Transmit channel

N1 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

L1 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

G1 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

E1 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

C1 2.5-V CMOS Transmit channel (available in Arria V GT FPGA device)

AB9 2.5-V CMOS Transceiver reference clock 0

AB8 2.5-V CMOS Transceiver reference clock 0

— 2.5-V CMOS Transceiver reference clock 1

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–48 Chapter 2: Board Components

Components and Interfaces

Table 2–29. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 7)

Board

Reference

(J10)

B21

K11

J10

F11

E10

K14

J13

F14

E13

J16

F17

E16

K17

J19

F20

E19

K20

J22

K23

K10

F10

K13

J12

F13

Schematic

Signal Name

FMC_GBTCLK_M2C_N1

FMC_HA_N0

FMC_HA_N1

FMC_HA_N2

FMC_HA_N3

FMC_HA_N4

FMC_HA_N5

FMC_HA_N6

FMC_HA_N7

FMC_HA_N8

FMC_HA_N9

FMC_HA_N10

FMC_HA_N11

FMC_HA_N12

FMC_HA_N13

FMC_HA_N14

FMC_HA_N15

FMC_HA_N16

FMC_HA_N17

FMC_HA_N18

FMC_HA_N19

FMC_HA_N20

FMC_HA_N21

FMC_HA_N22

FMC_HA_N23

FMC_HA_P0

FMC_HA_P1

FMC_HA_P2

FMC_HA_P3

FMC_HA_P4

FMC_HA_P5

FMC_HA_P6

FMC_HA_P7

FMC_HA_P8

FMC_HA_P9

FMC_HA_P10

FMC_HA_P11

FMC_HA_P12

Arria V GT

FPGA

I/O Standard Description

Pin Number

— 2.5-V CMOS Transceiver reference clock 1

AG16 2.5-V CMOS FMC data bus HPC bank A

AE17 2.5-V CMOS FMC data bus HPC bank A

AU16 2.5-V CMOS FMC data bus HPC bank A

AN17 2.5-V CMOS FMC data bus HPC bank A

AK9 2.5-V CMOS FMC data bus HPC bank A

AK11 2.5-V CMOS FMC data bus HPC bank A

K8 2.5-V CMOS FMC data bus HPC bank A

AG14 2.5-V CMOS FMC data bus HPC bank A

AC19 2.5-V CMOS FMC data bus HPC bank A

AL7 2.5-V CMOS FMC data bus HPC bank A

G6 2.5-V CMOS FMC data bus HPC bank A

AD17 2.5-V CMOS FMC data bus HPC bank A

AH18 2.5-V CMOS FMC data bus HPC bank A

AE19 2.5-V CMOS FMC data bus HPC bank A

AC15 2.5-V CMOS FMC data bus HPC bank A

AG20 2.5-V CMOS FMC data bus HPC bank A

AK17 2.5-V CMOS FMC data bus HPC bank A

AR25 2.5-V CMOS FMC data bus HPC bank A

AN20 2.5-V CMOS FMC data bus HPC bank A

AN19 2.5-V CMOS FMC data bus HPC bank A

AM21 2.5-V CMOS FMC data bus HPC bank A

AN23 2.5-V CMOS FMC data bus HPC bank A

AN22 2.5-V CMOS FMC data bus HPC bank A

AN24 2.5-V CMOS FMC data bus HPC bank A

AH16 2.5-V CMOS FMC data bus HPC bank A

AF16 2.5-V CMOS FMC data bus HPC bank A

AV16 2.5-V CMOS FMC data bus HPC bank A

AP17 2.5-V CMOS FMC data bus HPC bank A

AK10 2.5-V CMOS FMC data bus HPC bank A

AL11 2.5-V CMOS FMC data bus HPC bank A

J8 2.5-V CMOS FMC data bus HPC bank A

AH14 2.5-V CMOS FMC data bus HPC bank A

AD19 2.5-V CMOS FMC data bus HPC bank A

AM7 2.5-V CMOS FMC data bus HPC bank A

F6 2.5-V CMOS FMC data bus HPC bank A

AC18 2.5-V CMOS FMC data bus HPC bank A

AJ18 2.5-V CMOS FMC data bus HPC bank A

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–49

Components and Interfaces

Table 2–29. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 7)

Board

Reference

(J10)

E12

J15

F16

E15

K16

J18

F19

E18

K19

J21

K22

K26

J25

F23

E22

F26

E25

K29

J28

F29

E28

K32

J31

F32

E31

K35

J34

F35

K38

J37

E34

F38

E37

K25

J24

F22

E21

F25

Schematic

Signal Name

FMC_HA_P13

FMC_HA_P14

FMC_HA_P15

FMC_HA_P16

FMC_HA_P17

FMC_HA_P18

FMC_HA_P19

FMC_HA_P20

FMC_HA_P21

FMC_HA_P22

FMC_HA_P23

FMC_HB_N0

FMC_HB_N1

FMC_HB_N2

FMC_HB_N3

FMC_HB_N4

FMC_HB_N5

FMC_HB_N6

FMC_HB_N7

FMC_HB_N8

FMC_HB_N9

FMC_HB_N10

FMC_HB_N11

FMC_HB_N12

FMC_HB_N13

FMC_HB_N14

FMC_HB_N15

FMC_HB_N16

FMC_HB_N17

FMC_HB_N18

FMC_HB_N19

FMC_HB_N20

FMC_HB_N21

FMC_HB_P0

FMC_HB_P1

FMC_HB_P2

FMC_HB_P3

FMC_HB_P4

Arria V GT

FPGA

I/O Standard Description

Pin Number

AF19 2.5-V CMOS FMC data bus HPC bank A

AD14 2.5-V CMOS FMC data bus HPC bank A

AH20 2.5-V CMOS FMC data bus HPC bank A

AL17 2.5-V CMOS FMC data bus HPC bank A

AT25 2.5-V CMOS FMC data bus HPC bank A

AP20 2.5-V CMOS FMC data bus HPC bank A

AP19 2.5-V CMOS FMC data bus HPC bank A

AN21 2.5-V CMOS FMC data bus HPC bank A

AP23 2.5-V CMOS FMC data bus HPC bank A

AP22 2.5-V CMOS FMC data bus HPC bank A

AP24 2.5-V CMOS FMC data bus HPC bank A

AH13 2.5-V CMOS FMC data bus HPC bank B

AV12 2.5-V CMOS FMC data bus HPC bank B

AT11 2.5-V CMOS FMC data bus HPC bank B

AW10 2.5-V CMOS FMC data bus HPC bank B

AF13 2.5-V CMOS FMC data bus HPC bank B

AE14 2.5-V CMOS FMC data bus HPC bank B

AF12 2.5-V CMOS FMC data bus HPC bank B

AG11 2.5-V CMOS FMC data bus HPC bank B

AP10 2.5-V CMOS FMC data bus HPC bank B

AL10 2.5-V CMOS FMC data bus HPC bank B

AC13 2.5-V CMOS FMC data bus HPC bank B

AV9 2.5-V CMOS FMC data bus HPC bank B

AU10 2.5-V CMOS FMC data bus HPC bank B

AT9 2.5-V CMOS FMC data bus HPC bank B

AP13 2.5-V CMOS FMC data bus HPC bank B

AH12 2.5-V CMOS FMC data bus HPC bank B

AN12 2.5-V CMOS FMC data bus HPC bank B

AC12 2.5-V CMOS FMC data bus HPC bank B

AD12 2.5-V CMOS FMC data bus HPC bank B

AT12 2.5-V CMOS FMC data bus HPC bank B

AK12 2.5-V CMOS FMC data bus HPC bank B

AL13 2.5-V CMOS FMC data bus HPC bank B

AJ13 2.5-V CMOS FMC data bus HPC bank B

AW12 2.5-V CMOS FMC data bus HPC bank B

AU11 2.5-V CMOS FMC data bus HPC bank B

AW11 2.5-V CMOS FMC data bus HPC bank B

AG13 2.5-V CMOS FMC data bus HPC bank B

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–50 Chapter 2: Board Components

Components and Interfaces

Table 2–29. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 7)

Board

Reference

(J10)

E24

K28

J27

F28

E27

K31

J30

F31

E30

K34

J33

F34

K37

J36

E33

F37

E36

D30

D31

D33

G10

H11

D12

C11

H14

G13

D15

C15

H17

G16

D18

C19

H20

G19

D21

Schematic

Signal Name

FMC_HB_P5

FMC_HB_P6

FMC_HB_P7

FMC_HB_P8

FMC_HB_P9

FMC_HB_P10

FMC_HB_P11

FMC_HB_P12

FMC_HB_P13

FMC_HB_P14

FMC_HB_P15

FMC_HB_P16

FMC_HB_P17

FMC_HB_P18

FMC_HB_P19

FMC_HB_P20

FMC_HB_P21

FMC_JTAG_TDI

FMC_JTAG_TDO

FMC_JTAG_TMS

FMC_LA_N0

FMC_LA_N1

FMC_LA_N2

FMC_LA_N3

FMC_LA_N4

FMC_LA_N5

FMC_LA_N6

FMC_LA_N7

FMC_LA_N8

FMC_LA_N9

FMC_LA_N10

FMC_LA_N11

FMC_LA_N12

FMC_LA_N13

FMC_LA_N14

FMC_LA_N15

FMC_LA_N16

FMC_LA_N17

Arria V GT

FPGA

I/O Standard Description

Pin Number

AE13 2.5-V CMOS FMC data bus HPC bank B

AG12 2.5-V CMOS FMC data bus HPC bank B

AH11 2.5-V CMOS FMC data bus HPC bank B

AR10 2.5-V CMOS FMC data bus HPC bank B

AM10 2.5-V CMOS FMC data bus HPC bank B

AD13 2.5-V CMOS FMC data bus HPC bank B

AW9 2.5-V CMOS FMC data bus HPC bank B

AV10 2.5-V CMOS FMC data bus HPC bank B

AU9 2.5-V CMOS FMC data bus HPC bank B

AR13 2.5-V CMOS FMC data bus HPC bank B

AJ12 2.5-V CMOS FMC data bus HPC bank B

AP12 2.5-V CMOS FMC data bus HPC bank B

AD11 2.5-V CMOS FMC data bus HPC bank B

AE12 2.5-V CMOS FMC data bus HPC bank B

AU12 2.5-V CMOS FMC data bus HPC bank B

AL12 2.5-V CMOS FMC data bus HPC bank B

AM13 2.5-V CMOS FMC data bus HPC bank B

— 2.5-V CMOS JTAG data in

— 2.5-V CMOS JTAG data out

— 2.5-V CMOS JTAG mode select

AN16 2.5-V CMOS FMC data bus LPC bank A

AV13 2.5-V CMOS FMC data bus LPC bank A

AT15 2.5-V CMOS FMC data bus LPC bank A

AW14 2.5-V CMOS FMC data bus LPC bank A

AK8 2.5-V CMOS FMC data bus LPC bank A

AN7 2.5-V CMOS FMC data bus LPC bank A

AL9 2.5-V CMOS FMC data bus LPC bank A

AU6 2.5-V CMOS FMC data bus LPC bank A

AN9 2.5-V CMOS FMC data bus LPC bank A

AG17 2.5-V CMOS FMC data bus LPC bank A

AV7 2.5-V CMOS FMC data bus LPC bank A

AK15 2.5-V CMOS FMC data bus LPC bank A

AJ16 2.5-V CMOS FMC data bus LPC bank A

AK14 2.5-V CMOS FMC data bus LPC bank A

AT13 2.5-V CMOS FMC data bus LPC bank A

AL16 2.5-V CMOS FMC data bus LPC bank A

AK24 2.5-V CMOS FMC data bus LPC bank A

AN15 2.5-V CMOS FMC data bus LPC bank A

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–51

Components and Interfaces

Table 2–29. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 7)

Board

Reference

(J10)

C23

H23

G22

H26

G25

D24

H29

G28

D27

C27

H32

G31

H35

G34

H38

G37

H10

D11

C10

H13

G12

D14

C14

H16

G15

D17

C18

H19

G18

D20

C22

H22

G21

H25

Schematic

Signal Name

FMC_LA_N18

FMC_LA_N19

FMC_LA_N20

FMC_LA_N21

FMC_LA_N22

FMC_LA_N23

FMC_LA_N24

FMC_LA_N25

FMC_LA_N26

FMC_LA_N27

FMC_LA_N28

FMC_LA_N29

FMC_LA_N30

FMC_LA_N31

FMC_LA_N32

FMC_LA_N33

FMC_LA_P0

FMC_LA_P1

FMC_LA_P2

FMC_LA_P3

FMC_LA_P4

FMC_LA_P5

FMC_LA_P6

FMC_LA_P7

FMC_LA_P8

FMC_LA_P9

FMC_LA_P10

FMC_LA_P11

FMC_LA_P12

FMC_LA_P13

FMC_LA_P14

FMC_LA_P15

FMC_LA_P16

FMC_LA_P17

FMC_LA_P18

FMC_LA_P19

FMC_LA_P20

FMC_LA_P21

Arria V GT

FPGA

I/O Standard Description

Pin Number

AC16 2.5-V CMOS FMC data bus LPC bank A

AV22 2.5-V CMOS FMC data bus LPC bank A

AR16 2.5-V CMOS FMC data bus LPC bank A

AG22 2.5-V CMOS FMC data bus LPC bank A

AD21 2.5-V CMOS FMC data bus LPC bank A

AV18 2.5-V CMOS FMC data bus LPC bank A

AJ25 2.5-V CMOS FMC data bus LPC bank A

AK23 2.5-V CMOS FMC data bus LPC bank A

AK22 2.5-V CMOS FMC data bus LPC bank A

AG23 2.5-V CMOS FMC data bus LPC bank A

AG24 2.5-V CMOS FMC data bus LPC bank A

AN26 2.5-V CMOS FMC data bus LPC bank A

AE27 2.5-V CMOS FMC data bus LPC bank A

AG27 2.5-V CMOS FMC data bus LPC bank A

AD23 2.5-V CMOS FMC data bus LPC bank A

AC24 2.5-V CMOS FMC data bus LPC bank A

AP16 2.5-V CMOS FMC data bus LPC bank A

AW13 2.5-V CMOS FMC data bus LPC bank A

AU15 2.5-V CMOS FMC data bus LPC bank A

AW15 2.5-V CMOS FMC data bus LPC bank A

AL8 2.5-V CMOS FMC data bus LPC bank A

AP7 2.5-V CMOS FMC data bus LPC bank A

AM9 2.5-V CMOS FMC data bus LPC bank A

AT6 2.5-V CMOS FMC data bus LPC bank A

AP9 2.5-V CMOS FMC data bus LPC bank A

AH17 2.5-V CMOS FMC data bus LPC bank A

AV6 2.5-V CMOS FMC data bus LPC bank A

AL15 2.5-V CMOS FMC data bus LPC bank A

AK16 2.5-V CMOS FMC data bus LPC bank A

AL14 2.5-V CMOS FMC data bus LPC bank A

AU13 2.5-V CMOS FMC data bus LPC bank A

AM16 2.5-V CMOS FMC data bus LPC bank A

AL24 2.5-V CMOS FMC data bus LPC bank A

AP15 2.5-V CMOS FMC data bus LPC bank A

AD16 2.5-V CMOS FMC data bus LPC bank A

AW22 2.5-V CMOS FMC data bus LPC bank A

AT16 2.5-V CMOS FMC data bus LPC bank A

AH22 2.5-V CMOS FMC data bus LPC bank A

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Table 2–29. FMC Connector Pin Assignments, Schematic Signal Names, and Functions (Part 7 of 7)

Components and Interfaces

Board

Reference

(J10)

G24

D23

H28

G27

D26

C26

H31

G30

H34

G33

H37

G36

C30

C31

Schematic

Signal Name

FMC_LA_P22

FMC_LA_P23

FMC_LA_P24

FMC_LA_P25

FMC_LA_P26

FMC_LA_P27

FMC_LA_P28

FMC_LA_P29

FMC_LA_P30

FMC_LA_P31

FMC_LA_P32

FMC_LA_P33

FMC_M2C_PG

FMC_PRSNT

FMC_SCL

FMC_SDA

Arria V GT

FPGA

Pin Number

AC22 2.5-V CMOS FMC data bus LPC bank A

AW18 2.5-V CMOS FMC data bus LPC bank A

AK25 2.5-V CMOS FMC data bus LPC bank A

AL23 2.5-V CMOS FMC data bus LPC bank A

AL22 2.5-V CMOS FMC data bus LPC bank A

AH23 2.5-V CMOS FMC data bus LPC bank A

AH24 2.5-V CMOS FMC data bus LPC bank A

AP26 2.5-V CMOS FMC data bus LPC bank A

AF27 2.5-V CMOS FMC data bus LPC bank A

AH27 2.5-V CMOS FMC data bus LPC bank A

AD24 2.5-V CMOS FMC data bus LPC bank A

AD25 2.5-V CMOS FMC data bus LPC bank A

— 2.5-V CMOS Power good input

— 2.5-V CMOS FMC module present

— 2.5-V CMOS Management serial clock line

— 2.5-V CMOS Management serial data line

I/O Standard Description

Bull's Eye Connector

The development board comes with Samtec's Bull's Eye system, which includes four SMA cables along with the insertion tool to insert the cables into the connector.

The Bull's Eye high-density RF interconnect system allows many channels to be compacted into a small area on a printed circuit board at a comparable performance to SMA connectors. The cables allow you to monitor only two differential signals at a time. You can move the cables from one channel to another using the tool included with this board.

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Chapter 2: Board Components 2–53

Components and Interfaces

Figure 2–11 shows a diagram of the color coded Bull's Eye connections. Follow the

color code to make loopback connections. For example, connect purple to purple (pins 17 to 21) for RX to TX loopback. The only pins not connected are pins 3 and 4.

Figure 2–11. Bull’s Eye Connections

1 You can order more cables from www.samtec.com and these cable systems can be

reused on other boards.

f For specific instructions on how to install the connector to the board and insert the

cables into the connector, refer to Samtec's web page regarding this system.

Tab le 2 –3 0 lists the Bull’s eye connector pin assignments, signal names, and functions.

Table 2–30. Bull’s Eye Connector Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J16)

Schematic Signal Name

BULLSEYE_SMA_CLKN

BULLSEYE_SMA_CLKP

SMA_A_10G_RX_N0

SMA_A_10G_RX_N1

SMA_A_10G_RX_P0

SMA_A_10G_RX_P1

SMA_A_6G_RX_N2

SMA_A_6G_RX_P2

SMA_A_TX_L15_N

SMA_A_TX_L15_P

SMA_A_TX_R16_N

SMA_A_TX_R16_P

SMA_A_TX_R17_N

SMA_A_TX_R17_P

SMA_B_10G_RX_N1

Arria V GT FPGA

Pin Number

I/O Standard Description

— LVDS or 2.5-V Clock buffer

G2 LVDS or 2.5-V Transceiver channel

H38 LVDS or 2.5-V Transceiver channel

G1 LVDS or 2.5-V Transceiver channel

H39 LVDS or 2.5-V Transceiver channel

C2 LVDS or 2.5-V Transceiver channel

C1 LVDS or 2.5-V Transceiver channel

G36 LVDS or 2.5-V Transceiver channel

G37 LVDS or 2.5-V Transceiver channel

F4 LVDS or 2.5-V Transceiver channel

F3 LVDS or 2.5-V Transceiver channel

B4 LVDS or 2.5-V Transceiver channel

B3 LVDS or 2.5-V Transceiver channel

H38 LVDS or 2.5-V Transceiver channel

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Table 2–30. Bull’s Eye Connector Pin Assignments, Schematic Signal Names, and Functions

Memory

Board

Reference (J16)

Memory

Schematic Signal Name

SMA_B_10G_RX_P1

SMA_B_6G_RX_N0

SMA_B_6G_RX_P0

SMA_B_TX_L15_N

SMA_B_TX_L15_P

SMA_B_TX_R6_N

SMA_B_TX_R6_P

Arria V GT FPGA

Pin Number

H39 LVDS or 2.5-V Transceiver channel

AC2 LVDS or 2.5-V Transceiver channel

AC1 LVDS or 2.5-V Transceiver channel

G36 LVDS or 2.5-V Transceiver channel

G37 LVDS or 2.5-V Transceiver channel

AB4 LVDS or 2.5-V Transceiver channel

AB3 LVDS or 2.5-V Transceiver channel

I/O Standard Description

This section describes the development board’s memory interface support and also their signal names, types, and connectivity relative to the Arria V GT FPGA. The development board has the following memory interfaces:

■ DDR3

■ QDRII+

■ Flash

f For more information about the memory interfaces, refer to the following documents:

DDR3

■ Timing Analysis section in volume 4 of the External Memory Interface Handbook.

■ DDR, DDR2, and DDR3 SDRAM Design Tutorials section in volume 6 of the

External Memory Interface Handbook.

DDR3A for FPGA 1

The development board supports a 16Mx72x8 bank DDR3 SDRAM interface on FPGA 1 for very high-speed sequential memory access. The 72-bit data bus consists of four x16 devices and one x8 device with a single address or command bus. This interface connects to the vertical I/O banks on the top edge of the FPGA and utilizes the memory soft controller.

This memory interface is designed to run at a target frequency of 667 MHz for a maximum theoretical bandwidth of over 115.2 Gbps. The minimum frequency for this device is 667 MHz. The target Micron device is rated at 800 MHz with a CAS latency of 11.

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Memory

Tab le 2 –3 1 lists the DDR3A (x72 soft controller) pin assignments, signal names, and

functions. The signal names and types are relative to the Arria V GT FPGA in terms of I/O setting and direction.

Table 2–31. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5)

Board Reference

Schematic

Signal Name

DDR3A (U11, U18, U21, U28)

DDR3A_A0

DDR3A_A1

DDR3A_A2

DDR3A_A3

DDR3A_A4

DDR3A_A5

DDR3A_A6

DDR3A_A7

DDR3A_A8

DDR3A_A9

DDR3A_A10

DDR3A_A11

DDR3A_A12

DDR3A_A13

DDR3A_BA0

DDR3A_BA1

DDR3A_BA2

DDR3A_CASN

DDR3A_CKE

DDR3A_CLK_N

DDR3A_CLK_P

DDR3A_CSN

DDR3A_ODT

DDR3A_RASN

DDR3A_RESETN

DDR3A_WEN

DDR3A (U7)

DDR3A_A0

DDR3A_A1

DDR3A_A2

DDR3A_A3

DDR3A_A4

DDR3A_A5

DDR3A_A6

Arria V GT FPGA

Pin Number

I/O Standard Description

M34 1.5-V SSTL Class I Address bus

H25 1.5-V SSTL Class I Address bus

F32 1.5-V SSTL Class I Address bus

P28 1.5-V SSTL Class I Address bus

L24 1.5-V SSTL Class I Address bus

G32 1.5-V SSTL Class I Address bus

R21 1.5-V SSTL Class I Address bus

K30 1.5-V SSTL Class I Address bus

D21 1.5-V SSTL Class I Address bus

M30 1.5-V SSTL Class I Address bus

J28 1.5-V SSTL Class I Address bus

M21 1.5-V SSTL Class I Address bus

G28 1.5-V SSTL Class I Address bus

M31 1.5-V SSTL Class I Address bus

G30 1.5-V SSTL Class I Bank address bus

T24 1.5-V SSTL Class I Bank address bus

K34 1.5-V SSTL Class I Bank address bus

D32 1.5-V SSTL Class I Row address select

K29 1.5-V SSTL Class I Column address select

F34 1.5-V SSTL Class I Differential output clock

E34 1.5-V SSTL Class I Differential output clock

F31 1.5-V SSTL Class I Chip select

E33 1.5-V SSTL Class I On-die termination enable

A32 1.5-V SSTL Class I Row address select

J31 1.5-V SSTL Class I Reset

G29 1.5-V SSTL Class I Write enable

M34 1.5-V SSTL Class I Address bus

H25 1.5-V SSTL Class I Address bus

F32 1.5-V SSTL Class I Address bus

P28 1.5-V SSTL Class I Address bus

L24 1.5-V SSTL Class I Address bus

G32 1.5-V SSTL Class I Address bus

R21 1.5-V SSTL Class I Address bus

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Memory

Table 2–31. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)

Board Reference

DDR3A (U11)

Schematic

Signal Name

DDR3A_A7

DDR3A_A8

DDR3A_A9

DDR3A_A10

DDR3A_A11

DDR3A_A12

DDR3A_A13

DDR3A_BA0

DDR3A_BA1

DDR3A_BA2

DDR3A_CASN

DDR3A_CKE

DDR3A_CLK_N

DDR3A_CLK_P

DDR3A_CSN

DDR3A_DM8

DDR3A_DQ64

DDR3A_DQ65

DDR3A_DQ66

DDR3A_DQ67

DDR3A_DQ68

DDR3A_DQ69

DDR3A_DQ70

DDR3A_DQ71

DDR3A_DQS_N8

DDR3A_DQS_P8

DDR3A_ODT

DDR3A_RASN

DDR3A_RESETN

DDR3A_WEN

DDR3A_ZQ05

DDR3A_DM6

DDR3A_DM7

DDR3A_DQ48

DDR3A_DQ49

DDR3A_DQ50

DDR3A_DQ51

DDR3A_DQ52

Arria V GT FPGA

Pin Number

I/O Standard Description

K30 1.5-V SSTL Class I Address bus

D21 1.5-V SSTL Class I Address bus

M30 1.5-V SSTL Class I Address bus

J28 1.5-V SSTL Class I Address bus

M21 1.5-V SSTL Class I Address bus

G28 1.5-V SSTL Class I Address bus

M31 1.5-V SSTL Class I Address bus

G30 1.5-V SSTL Class I Bank address bus

T24 1.5-V SSTL Class I Bank address bus

K34 1.5-V SSTL Class I Bank address bus

D32 1.5-V SSTL Class I Row address select

K29 1.5-V SSTL Class I Column address select

F34 1.5-V SSTL Class I Differential output clock

E34 1.5-V SSTL Class I Differential output clock

F31 1.5-V SSTL Class I Chip select

P22 1.5-V SSTL Class I Write mask byte lane

B22 1.5-V SSTL Class I Data bus byte lane

L22 1.5-V SSTL Class I Data bus byte lane

C22 1.5-V SSTL Class I Data bus byte lane

N22 1.5-V SSTL Class I Data bus byte lane

E22 1.5-V SSTL Class I Data bus byte lane

J22 1.5-V SSTL Class I Data bus byte lane

A23 1.5-V SSTL Class I Data bus byte lane

F22 1.5-V SSTL Class I Data bus byte lane

D23 1.5-V SSTL Class I Data strobe N byte lane

C23 1.5-V SSTL Class I Data strobe P byte lane

E33 1.5-V SSTL Class I On-die termination enable

A32 1.5-V SSTL Class I Row address select

J31 1.5-V SSTL Class I Reset

G29 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

M32 1.5-V SSTL Class I Write mask byte lane

D31 1.5-V SSTL Class I Write mask byte lane

T26 1.5-V SSTL Class I Data bus byte lane

R24 1.5-V SSTL Class I Data bus byte lane

D25 1.5-V SSTL Class I Data bus byte lane

T25 1.5-V SSTL Class I Data bus byte lane

E25 1.5-V SSTL Class I Data bus byte lane

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Memory

Table 2–31. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)

Board Reference

DDR3A (U18)

Schematic

Signal Name

DDR3A_DQ53

DDR3A_DQ54

DDR3A_DQ55

DDR3A_DQ56

DDR3A_DQ57

DDR3A_DQ58

DDR3A_DQ59

DDR3A_DQ60

DDR3A_DQ61

DDR3A_DQ62

DDR3A_DQ63

DDR3A_DQS_N6

DDR3A_DQS_N7

DDR3A_DQS_P6

DDR3A_DQS_P7

DDR3A_ZQ04

DDR3A_DM4

DDR3A_DM5

DDR3A_DQ32

DDR3A_DQ33

DDR3A_DQ34

DDR3A_DQ35

DDR3A_DQ36

DDR3A_DQ37

DDR3A_DQ38

DDR3A_DQ39

DDR3A_DQ40

DDR3A_DQ41

DDR3A_DQ42

DDR3A_DQ43

DDR3A_DQ44

DDR3A_DQ45

DDR3A_DQ46

DDR3A_DQ47

DDR3A_DQS_N4

DDR3A_DQS_N5

DDR3A_DQS_P4

DDR3A_DQS_P5

Arria V GT FPGA

Pin Number

I/O Standard Description

N24 1.5-V SSTL Class I Data bus byte lane

G25 1.5-V SSTL Class I Data bus byte lane

K24 1.5-V SSTL Class I Data bus byte lane

F23 1.5-V SSTL Class I Data bus byte lane

J23 1.5-V SSTL Class I Data bus byte lane

G23 1.5-V SSTL Class I Data bus byte lane

C24 1.5-V SSTL Class I Data bus byte lane

F24 1.5-V SSTL Class I Data bus byte lane

R23 1.5-V SSTL Class I Data bus byte lane

G24 1.5-V SSTL Class I Data bus byte lane

M23 1.5-V SSTL Class I Data bus byte lane

B25 1.5-V SSTL Class I Data strobe N byte lane

E24 1.5-V SSTL Class I Data strobe N byte lane

A25 1.5-V SSTL Class I Data strobe P byte lane

D24 1.5-V SSTL Class I Data strobe P byte lane

— 1.5-V SSTL Class I ZQ impedance calibration

E27 1.5-V SSTL Class I Write mask byte lane

A26 1.5-V SSTL Class I Write mask byte lane

P27 1.5-V SSTL Class I Data bus byte lane

B27 1.5-V SSTL Class I Data bus byte lane

R27 1.5-V SSTL Class I Data bus byte lane

C27 1.5-V SSTL Class I Data bus byte lane

M27 1.5-V SSTL Class I Data bus byte lane

H27 1.5-V SSTL Class I Data bus byte lane

N27 1.5-V SSTL Class I Data bus byte lane

K27 1.5-V SSTL Class I Data bus byte lane

J26 1.5-V SSTL Class I Data bus byte lane

D26 1.5-V SSTL Class I Data bus byte lane

K25 1.5-V SSTL Class I Data bus byte lane

G26 1.5-V SSTL Class I Data bus byte lane

T27 1.5-V SSTL Class I Data bus byte lane

F26 1.5-V SSTL Class I Data bus byte lane

R26 1.5-V SSTL Class I Data bus byte lane

C26 1.5-V SSTL Class I Data bus byte lane

T28 1.5-V SSTL Class I Data strobe N byte lane

N26 1.5-V SSTL Class I Data strobe N byte lane

R28 1.5-V SSTL Class I Data strobe P byte lane

M26 1.5-V SSTL Class I Data strobe P byte lane

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Memory

Table 2–31. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)

Board Reference

DDR3A (U21)

DDR3A (U28)

Schematic

Signal Name

DDR3A_ZQ03

DDR3A_DM2

DDR3A_DM3

DDR3A_DQ16

DDR3A_DQ17

DDR3A_DQ18

DDR3A_DQ19

DDR3A_DQ20

DDR3A_DQ21

DDR3A_DQ22

DDR3A_DQ23

DDR3A_DQ24

DDR3A_DQ25

DDR3A_DQ26

DDR3A_DQ27

DDR3A_DQ28

DDR3A_DQ29

DDR3A_DQ30

DDR3A_DQ31

DDR3A_DQS_N2

DDR3A_DQS_N3

DDR3A_DQS_P2

DDR3A_DQS_P3

DDR3A_ZQ01

DDR3A_DM0

DDR3A_DM1

DDR3A_DQ0

DDR3A_DQ1

DDR3A_DQ2

DDR3A_DQ3

DDR3A_DQ4

DDR3A_DQ5

DDR3A_DQ6

DDR3A_DQ7

DDR3A_DQ8

DDR3A_DQ9

DDR3A_DQ10

Arria V GT FPGA

Pin Number

I/O Standard Description

— 1.5-V SSTL Class I ZQ impedance calibration

M32 1.5-V SSTL Class I Write mask byte lane

D31 1.5-V SSTL Class I Write mask byte lane

D30 1.5-V SSTL Class I Data bus byte lane

C29 1.5-V SSTL Class I Data bus byte lane

R30 1.5-V SSTL Class I Data bus byte lane

A29 1.5-V SSTL Class I Data bus byte lane

L30 1.5-V SSTL Class I Data bus byte lane

A28 1.5-V SSTL Class I Data bus byte lane

J30 1.5-V SSTL Class I Data bus byte lane

B28 1.5-V SSTL Class I Data bus byte lane

J29 1.5-V SSTL Class I Data bus byte lane

C28 1.5-V SSTL Class I Data bus byte lane

L28 1.5-V SSTL Class I Data bus byte lane

F28 1.5-V SSTL Class I Data bus byte lane

N29 1.5-V SSTL Class I Data bus byte lane

D28 1.5-V SSTL Class I Data bus byte lane

M29 1.5-V SSTL Class I Data bus byte lane

M28 1.5-V SSTL Class I Data bus byte lane

P30 1.5-V SSTL Class I Data strobe N byte lane

T29 1.5-V SSTL Class I Data strobe N byte lane

N30 1.5-V SSTL Class I Data strobe P byte lane

R29 1.5-V SSTL Class I Data strobe P byte lane

— 1.5-V SSTL Class I ZQ impedance calibration

M32 1.5-V SSTL Class I Write mask byte lane

D31 1.5-V SSTL Class I Write mask byte lane

N33 1.5-V SSTL Class I Data bus byte lane

N31 1.5-V SSTL Class I Data bus byte lane

N34 1.5-V SSTL Class I Data bus byte lane

L31 1.5-V SSTL Class I Data bus byte lane

N32 1.5-V SSTL Class I Data bus byte lane

J34 1.5-V SSTL Class I Data bus byte lane

P31 1.5-V SSTL Class I Data bus byte lane

J32 1.5-V SSTL Class I Data bus byte lane

A30 1.5-V SSTL Class I Data bus byte lane

C30 1.5-V SSTL Class I Data bus byte lane

B30 1.5-V SSTL Class I Data bus byte lane

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Memory

Table 2–31. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)

Board Reference

Schematic

Signal Name

DDR3A_DQ11

DDR3A_DQ12

DDR3A_DQ13

DDR3A_DQ14

DDR3A_DQ15

DDR3A_DQS_N0

DDR3A_DQS_N1

DDR3A_DQS_P0

DDR3A_DQS_P1

DDR3A_ZQ01

Arria V GT FPGA

Pin Number

H31 1.5-V SSTL Class I Data bus byte lane

B31 1.5-V SSTL Class I Data bus byte lane

E31 1.5-V SSTL Class I Data bus byte lane

A31 1.5-V SSTL Class I Data bus byte lane

C31 1.5-V SSTL Class I Data bus byte lane

M33 1.5-V SSTL Class I Data strobe N byte lane

B33 1.5-V SSTL Class I Data strobe N byte lane

L33 1.5-V SSTL Class I Data strobe P byte lane

N30 1.5-V SSTL Class I Data strobe P byte lane

— 1.5-V SSTL Class I ZQ impedance calibration

I/O Standard Description

DDR3B/C for FPGA 2

The development board supports a 16Mx64x8 bank DDR3 SDRAM interface on FPGA 2 for very high-speed sequential memory access. The 64-bit data bus consists of four x16 devices with a single address or command bus. This interface connects to the vertical I/O banks on the top edge of the FPGA.

This DDR3 SDRAM has two interface options. The first option is a x32 interface using a memory hard controller. The second option is a x64 interface using a memory soft controller.

Tab le 2 –3 2 lists the DDR3B (x32 hard controller) pin assignments, signal names, and

functions. The signal names and types are relative to the Arria V GT FPGA in terms of I/O setting and direction.

Table 2–32. DDR3 x32 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)

Board Reference

DDR3B (U6, U12)

Schematic

Signal Name

DDR3B_A0

DDR3B_A1

DDR3B_A2

DDR3B_A3

DDR3B_A4

DDR3B_A5

DDR3B_A6

DDR3B_A7

DDR3B_A8

DDR3B_A9

DDR3B_A10

DDR3B_A11

DDR3B_A12

Arria V GT FPGA

Pin Number

B31 1.5-V SSTL Class I Address bus

A30 1.5-V SSTL Class I Address bus

A31 1.5-V SSTL Class I Address bus

A32 1.5-V SSTL Class I Address bus

A33 1.5-V SSTL Class I Address bus

B33 1.5-V SSTL Class I Address bus

H31 1.5-V SSTL Class I Address bus

J31 1.5-V SSTL Class I Address bus

C31 1.5-V SSTL Class I Address bus

D31 1.5-V SSTL Class I Address bus

C32 1.5-V SSTL Class I Address bus

D32 1.5-V SSTL Class I Address bus

N31 1.5-V SSTL Class I Address bus

I/O Standard Description

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Reference Manual

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Memory

Table 2–32. DDR3 x32 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board Reference

DDR3B (U6)

DDR3B (U12)

Schematic

Signal Name

DDR3B_A13

DDR3B_BA0

DDR3B_BA1

DDR3B_BA2

DDR3B_CASN

DDR3B_CKE

DDR3B_CLK_N

DDR3B_CLK_P

DDR3B_CSN

DDR3B_ODT

DDR3B_RASN

DDR3B_RESETN

DDR3B_WEN

DDR3B_ZQ2

DDR3B_DM0

DDR3B_DM1

DDR3B_DQ0

DDR3B_DQ1

DDR3B_DQ2

DDR3B_DQ3

DDR3B_DQ4

DDR3B_DQ5

DDR3B_DQ6

DDR3B_DQ7

DDR3B_DQ8

DDR3B_DQ9

DDR3B_DQ10

DDR3B_DQ11

DDR3B_DQ12

DDR3B_DQ13

DDR3B_DQ14

DDR3B_DQ15

DDR3B_DQS_N0

DDR3B_DQS_N1

DDR3B_DQS_P0

DDR3B_DQS_P1

DDR3B_DM2

Arria V GT FPGA

Pin Number

I/O Standard Description

P31 1.5-V SSTL Class I Address bus

M32 1.5-V SSTL Class I Bank address bus

N32 1.5-V SSTL Class I Bank address bus

J34 1.5-V SSTL Class I Bank address bus

L33 1.5-V SSTL Class I Row address select

E31 1.5-V SSTL Class I Column address select

C30 1.5-V SSTL Class I Differential output clock

B30 1.5-V SSTL Class I Differential output clock

L34 1.5-V SSTL Class I Chip select

L31 1.5-V SSTL Class I On-die termination enable

K34 1.5-V SSTL Class I Row address select

G30 1.5-V SSTL Class I Reset

M33 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

J30 1.5-V SSTL Class I Write mask byte lane

J29 1.5-V SSTL Class I Write mask byte lane

B28 1.5-V SSTL Class I Data bus byte lane

C29 1.5-V SSTL Class I Data bus byte lane

R30 1.5-V SSTL Class I Data bus byte lane

A29 1.5-V SSTL Class I Data bus byte lane

A28 1.5-V SSTL Class I Data bus byte lane

L30 1.5-V SSTL Class I Data bus byte lane

D30 1.5-V SSTL Class I Data bus byte lane

D29 1.5-V SSTL Class I Data bus byte lane

L28 1.5-V SSTL Class I Data bus byte lane

M28 1.5-V SSTL Class I Data bus byte lane

H28 1.5-V SSTL Class I Data bus byte lane

C28 1.5-V SSTL Class I Data bus byte lane

D28 1.5-V SSTL Class I Data bus byte lane

F28 1.5-V SSTL Class I Data bus byte lane

M29 1.5-V SSTL Class I Data bus byte lane

N29 1.5-V SSTL Class I Data bus byte lane

P30 1.5-V SSTL Class I Data strobe N byte lane

T29 1.5-V SSTL Class I Data strobe N byte lane

N30 1.5-V SSTL Class I Data strobe P byte lane

R29 1.5-V SSTL Class I Data strobe P byte lane

J30 1.5-V SSTL Class I Write mask byte lane

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–61

Memory

Table 2–32. DDR3 x32 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)

Board Reference

Schematic

Signal Name

DDR3B_DM3

DDR3B_DQ16

DDR3B_DQ17

DDR3B_DQ18

DDR3B_DQ19

DDR3B_DQ20

DDR3B_DQ21

DDR3B_DQ22

DDR3B_DQ23

DDR3B_DQ24

DDR3B_DQ25

DDR3B_DQ26

DDR3B_DQ27

DDR3B_DQ28

DDR3B_DQ29

DDR3B_DQ30

DDR3B_DQ31

DDR3B_DQS_N2

DDR3B_DQS_N3

DDR3B_DQS_P2

DDR3B_DQS_P3

Arria V GT FPGA

Pin Number

I/O Standard Description

J29 1.5-V SSTL Class I Write mask byte lane

P27 1.5-V SSTL Class I Data bus byte lane

R27 1.5-V SSTL Class I Data bus byte lane

H27 1.5-V SSTL Class I Data bus byte lane

B27 1.5-V SSTL Class I Data bus byte lane

C27 1.5-V SSTL Class I Data bus byte lane

E27 1.5-V SSTL Class I Data bus byte lane

M27 1.5-V SSTL Class I Data bus byte lane

N27 1.5-V SSTL Class I Data bus byte lane

C26 1.5-V SSTL Class I Data bus byte lane

D26 1.5-V SSTL Class I Data bus byte lane

K25 1.5-V SSTL Class I Data bus byte lane

R26 1.5-V SSTL Class I Data bus byte lane

T27 1.5-V SSTL Class I Data bus byte lane

A26 1.5-V SSTL Class I Data bus byte lane

F26 1.5-V SSTL Class I Data bus byte lane

G26 1.5-V SSTL Class I Data bus byte lane

T28 1.5-V SSTL Class I Data strobe N byte lane

N26 1.5-V SSTL Class I Data strobe N byte lane

R28 1.5-V SSTL Class I Data strobe P byte lane

M26 1.5-V SSTL Class I Data strobe P byte lane

Tab le 2 –3 3 lists the DDR3C (x64 soft controller) pin assignments, signal names, and

functions. The signal names and types are relative to the Arria V GT FPGA in terms of I/O setting and direction.

Table 2–33. DDR3 x64 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)

Board Reference

Schematic

Signal Name

Arria V GT FPGA

Pin Number

I/O Standard Description

DDR3C (U19, U22)

DDR3B_A0

DDR3B_A1

DDR3B_A2

DDR3B_A3

DDR3B_A4

DDR3B_A5

DDR3B_A6

DDR3B_A7

DDR3B_A8

DDR3B_A9

B31 1.5-V SSTL Class I Address bus

A30 1.5-V SSTL Class I Address bus

A31 1.5-V SSTL Class I Address bus

A32 1.5-V SSTL Class I Address bus

A33 1.5-V SSTL Class I Address bus

B33 1.5-V SSTL Class I Address bus

H31 1.5-V SSTL Class I Address bus

J31 1.5-V SSTL Class I Address bus

C31 1.5-V SSTL Class I Address bus

D31 1.5-V SSTL Class I Address bus

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Memory

Table 2–33. DDR3 x64 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board Reference

DDR3C (U19)

Schematic

Signal Name

DDR3B_A10

DDR3B_A11

DDR3B_A12

DDR3B_A13

DDR3B_BA0

DDR3B_BA1

DDR3B_BA2

DDR3B_CASN

DDR3B_CKE

DDR3B_CLK_N

DDR3B_CLK_P

DDR3B_CSN

DDR3B_ODT

DDR3B_RASN

DDR3B_RESETN

DDR3B_WEN

DDR3C_DM0

DDR3C_DM1

DDR3C_DQ0

DDR3C_DQ1

DDR3C_DQ2

DDR3C_DQ3

DDR3C_DQ4

DDR3C_DQ5

DDR3C_DQ6

DDR3C_DQ7

DDR3C_DQ8

DDR3C_DQ9

DDR3C_DQ10

DDR3C_DQ11

DDR3C_DQ12

DDR3C_DQ13

DDR3C_DQ14

DDR3C_DQ15

DDR3C_DQS_N0

DDR3C_DQS_N1

DDR3C_DQS_P0

DDR3C_DQS_P1

Arria V GT FPGA

Pin Number

I/O Standard Description

C32 1.5-V SSTL Class I Address bus

D32 1.5-V SSTL Class I Address bus

N31 1.5-V SSTL Class I Address bus

P31 1.5-V SSTL Class I Address bus

M32 1.5-V SSTL Class I Bank address bus

N32 1.5-V SSTL Class I Bank address bus

J34 1.5-V SSTL Class I Bank address bus

L33 1.5-V SSTL Class I Row address select

E31 1.5-V SSTL Class I Column address select

C30 1.5-V SSTL Class I Differential output clock

B30 1.5-V SSTL Class I Differential output clock

L34 1.5-V SSTL Class I Chip select

L31 1.5-V SSTL Class I On-die termination enable

K34 1.5-V SSTL Class I Row address select

G30 1.5-V SSTL Class I Reset

M33 1.5-V SSTL Class I Write enable

M21 1.5-V SSTL Class I Write mask byte lane

B22 1.5-V SSTL Class I Write mask byte lane

D20 1.5-V SSTL Class I Data bus byte lane

H21 1.5-V SSTL Class I Data bus byte lane

D21 1.5-V SSTL Class I Data bus byte lane

J21 1.5-V SSTL Class I Data bus byte lane

A21 1.5-V SSTL Class I Data bus byte lane

G21 1.5-V SSTL Class I Data bus byte lane

A22 1.5-V SSTL Class I Data bus byte lane

C20 1.5-V SSTL Class I Data bus byte lane

A23 1.5-V SSTL Class I Data bus byte lane

E22 1.5-V SSTL Class I Data bus byte lane

L22 1.5-V SSTL Class I Data bus byte lane

C22 1.5-V SSTL Class I Data bus byte lane

N22 1.5-V SSTL Class I Data bus byte lane

F22 1.5-V SSTL Class I Data bus byte lane

P22 1.5-V SSTL Class I Data bus byte lane

J22 1.5-V SSTL Class I Data bus byte lane

B21 1.5-V SSTL Class I Data strobe N byte lane

D23 1.5-V SSTL Class I Data strobe N byte lane

A20 1.5-V SSTL Class I Data strobe P byte lane

C23 1.5-V SSTL Class I Data strobe P byte lane

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Chapter 2: Board Components 2–63

Memory

Table 2–33. DDR3 x64 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)

Board Reference

DDR3C (U22)

Schematic

Signal Name

DDR3B_ZQ4

DDR3C_DM2

DDR3C_DM3

DDR3C_DQ16

DDR3C_DQ17

DDR3C_DQ18

DDR3C_DQ19

DDR3C_DQ20

DDR3C_DQ21

DDR3C_DQ22

DDR3C_DQ23

DDR3C_DQ24

DDR3C_DQ25

DDR3C_DQ26

DDR3C_DQ27

DDR3C_DQ28

DDR3C_DQ29

DDR3C_DQ30

DDR3C_DQ31

DDR3C_DQS_N2

DDR3C_DQS_N3

DDR3C_DQS_P2

DDR3C_DQS_P3

DDR3B_ZQ3

Arria V GT FPGA

Pin Number

I/O Standard Description

— 1.5-V SSTL Class I ZQ impedance calibration

J23 1.5-V SSTL Class I Write mask byte lane

D25 1.5-V SSTL Class I Write mask byte lane

C24 1.5-V SSTL Class I Data bus byte lane

M23 1.5-V SSTL Class I Data bus byte lane

B24 1.5-V SSTL Class I Data bus byte lane

R23 1.5-V SSTL Class I Data bus byte lane

G24 1.5-V SSTL Class I Data bus byte lane

G23 1.5-V SSTL Class I Data bus byte lane

F24 1.5-V SSTL Class I Data bus byte lane

F23 1.5-V SSTL Class I Data bus byte lane

R24 1.5-V SSTL Class I Data bus byte lane

G25 1.5-V SSTL Class I Data bus byte lane

T26 1.5-V SSTL Class I Data bus byte lane

E25 1.5-V SSTL Class I Data bus byte lane

N24 1.5-V SSTL Class I Data bus byte lane

K24 1.5-V SSTL Class I Data bus byte lane

T25 1.5-V SSTL Class I Data bus byte lane

P24 1.5-V SSTL Class I Data bus byte lane

E24 1.5-V SSTL Class I Data strobe N byte lane

B25 1.5-V SSTL Class I Data strobe N byte lane

D24 1.5-V SSTL Class I Data strobe P byte lane

A25 1.5-V SSTL Class I Data strobe P byte lane

— 1.5-V SSTL Class I ZQ impedance calibration

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2–64 Chapter 2: Board Components

Memory

QDRII+

The development board supports a burst-of-4 QDRII+ SRAM memory device for very-high-speed, low-latency memory access. The QDRII+ has a x36 interface, providing device addressing of up to a 36 Mb.

The QDRII+ has separate read and write data ports with DDR signaling at up to 550 MHz. The pinout and footprint is compatible with a burst-of-2 QDRII SSRAM memory device. The FPGA can support up to 400 MHz QDRII data.

Tab le 2 –3 4 lists the QDRII+ pin assignments, signal names, and functions.

Table 2–34. QDRII+ Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)

Board

Reference (U8)

A10

A11

P10

Schematic

Signal Name

QDRII_A0

QDRII_A1

QDRII_A2

QDRII_A3

QDRII_A4

QDRII_A5

QDRII_A6

QDRII_A7

QDRII_A8

QDRII_A9

QDRII_A10

QDRII_A11

QDRII_A12

QDRII_A13

QDRII_A14

QDRII_A15

QDRII_A16

QDRII_A17

QDRII_A18

QDRII_A19

QDRII_A20

QDRII_BWSN0

QDRII_BWSN1

QDRII_BWSN2

QDRII_BWSN3

QDRII_C_N

QDRII_C_P

QDRII_CQ_N

QDRII_CQ_P

QDRII_D0

Arria V GT FPGA

Pin Number

AB29 1.8-V HSTL Address bus

AC29 1.8-V HSTL Address bus

AF28 1.8-V HSTL Address bus

AG28 1.8-V HSTL Address bus

AK29 1.8-V HSTL Address bus

AL29 1.8-V HSTL Address bus

AH28 1.8-V HSTL Address bus

AJ28 1.8-V HSTL Address bus

AD28 1.8-V HSTL Address bus

AP28 1.8-V HSTL Address bus

AJ27 1.8-V HSTL Address bus

AP27 1.8-V HSTL Address bus

AM27 1.8-V HSTL Address bus

AG27 1.8-V HSTL Address bus

AE27 1.8-V HSTL Address bus

AC24 1.8-V HSTL Address bus

AD26 1.8-V HSTL Address bus

AN26 1.8-V HSTL Address bus

AJ25 1.8-V HSTL Address bus

AT32 1.8-V HSTL Address bus

AU32 1.8-V HSTL Address bus

AK27 1.8-V HSTL Write byte write select 0

AB25 1.8-V HSTL Write byte write select 1

AM25 1.8-V HSTL Write byte write select 2

AV24 1.8-V HSTL Write byte write select 3

AG24 1.8-V HSTL Clock N

AD23 1.8-V HSTL Clock P

AR21 1.8-V HSTL Echo clock N

AT21 1.8-V HSTL Echo clock P

AE28 1.8-V HSTL Write data bus

I/O Standard Description

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–65

Memory

Table 2–34. QDRII+ Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board

Reference (U8)

N11

M11

K10

J11

G11

E10

D11

C11

N10

G10

D10

P11

Schematic

Signal Name

QDRII_D1

QDRII_D2

QDRII_D3

QDRII_D4

QDRII_D5

QDRII_D6

QDRII_D7

QDRII_D8

QDRII_D9

QDRII_D10

QDRII_D11

QDRII_D12

QDRII_D13

QDRII_D14

QDRII_D15

QDRII_D16

QDRII_D17

QDRII_D18

QDRII_D19

QDRII_D20

QDRII_D21

QDRII_D22

QDRII_D23

QDRII_D24

QDRII_D25

QDRII_D26

QDRII_D27

QDRII_D28

QDRII_D29

QDRII_D30

QDRII_D31

QDRII_D32

QDRII_D33

QDRII_D34

QDRII_D35

QDRII_DOFFN

QDRII_K_N

QDRII_K_P

QDRII_Q0

Arria V GT FPGA

Pin Number

I/O Standard Description

AB27 1.8-V HSTL Write data bus

AB28 1.8-V HSTL Write data bus

AM28 1.8-V HSTL Write data bus

AC27 1.8-V HSTL Write data bus

AD27 1.8-V HSTL Write data bus

AR28 1.8-V HSTL Write data bus

AU28 1.8-V HSTL Write data bus

AV28 1.8-V HSTL Write data bus

AW29 1.8-V HSTL Write data bus

AW28 1.8-V HSTL Write data bus

AR27 1.8-V HSTL Write data bus

AT27 1.8-V HSTL Write data bus

AU27 1.8-V HSTL Write data bus

AN27 1.8-V HSTL Write data bus

AV27 1.8-V HSTL Write data bus

AW27 1.8-V HSTL Write data bus

AH27 1.8-V HSTL Write data bus

AC25 1.8-V HSTL Write data bus

AF27 1.8-V HSTL Write data bus

AD25 1.8-V HSTL Write data bus

AG26 1.8-V HSTL Write data bus

AH26 1.8-V HSTL Write data bus

AE26 1.8-V HSTL Write data bus

AG25 1.8-V HSTL Write data bus

AH25 1.8-V HSTL Write data bus

AP26 1.8-V HSTL Write data bus

AN25 1.8-V HSTL Write data bus

AK25 1.8-V HSTL Write data bus

AT26 1.8-V HSTL Write data bus

AU26 1.8-V HSTL Write data bus

AT25 1.8-V HSTL Write data bus

AW25 1.8-V HSTL Write data bus

AW26 1.8-V HSTL Write data bus

AL26 1.8-V HSTL Write data bus

AV25 1.8-V HSTL Write data bus

AN24 1.8-V HSTL DLL enable

AE25 1.8-V HSTL Write clock N

AF25 1.8-V HSTL Write clock P

AD24 1.8-V HSTL Read data bus

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Reference Manual

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Memory

Table 2–34. QDRII+ Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)

Board

Reference (U8)

M10

L11

K11

J10

F11

E11

C10

B11

L10

F10

B10

Schematic

Signal Name

QDRII_Q1

QDRII_Q2

QDRII_Q3

QDRII_Q4

QDRII_Q5

QDRII_Q6

QDRII_Q7

QDRII_Q8

QDRII_Q9

QDRII_Q10

QDRII_Q11

QDRII_Q12

QDRII_Q13

QDRII_Q14

QDRII_Q15

QDRII_Q16

QDRII_Q17

QDRII_Q18

QDRII_Q19

QDRII_Q20

QDRII_Q21

QDRII_Q22

QDRII_Q23

QDRII_Q24

QDRII_Q25

QDRII_Q26

QDRII_Q27

QDRII_Q28

QDRII_Q29

QDRII_Q30

QDRII_Q31

QDRII_Q32

QDRII_Q33

QDRII_Q34

QDRII_Q35

QDRII_RPSN

QDRII_WPSN

Arria V GT FPGA

Pin Number

I/O Standard Description

AT24 1.8-V HSTL Read data bus

AU24 1.8-V HSTL Read data bus

AL24 1.8-V HSTL Read data bus

AE24 1.8-V HSTL Read data bus

AF24 1.8-V HSTL Read data bus

AH24 1.8-V HSTL Read data bus

AW23 1.8-V HSTL Read data bus

AW24 1.8-V HSTL Read data bus

AP24 1.8-V HSTL Read data bus

AT23 1.8-V HSTL Read data bus

AU23 1.8-V HSTL Read data bus

AP23 1.8-V HSTL Read data bus

AD22 1.8-V HSTL Read data bus

AE23 1.8-V HSTL Read data bus

AL23 1.8-V HSTL Read data bus

AT22 1.8-V HSTL Read data bus

AU22 1.8-V HSTL Read data bus

AW22 1.8-V HSTL Read data bus

AV21 1.8-V HSTL Read data bus

AW21 1.8-V HSTL Read data bus

AH23 1.8-V HSTL Read data bus

AE22 1.8-V HSTL Read data bus

AF22 1.8-V HSTL Read data bus

AP22 1.8-V HSTL Read data bus

AW19 1.8-V HSTL Read data bus

AW20 1.8-V HSTL Read data bus

AH22 1.8-V HSTL Read data bus

AT20 1.8-V HSTL Read data bus

AU20 1.8-V HSTL Read data bus

AK21 1.8-V HSTL Read data bus

AU19 1.8-V HSTL Read data bus

AV19 1.8-V HSTL Read data bus

AN21 1.8-V HSTL Read data bus

AE21 1.8-V HSTL Read data bus

AG21 1.8-V HSTL Read data bus

AR25 1.8-V HSTL Read port select

AK24 1.8-V HSTL Write port select

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Chapter 2: Board Components 2–67

Memory

Flash

The development board supports a 1 Gb CFI-compatible synchronous flash device for non-volatile storage of FPGA configuration data, board information, test application data, and user code space. This device is part of the shared FM bus that connects to the flash memory and MAX II CPLD EPM2210 System Controller.

This 16-bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps. The write performance is 270 µs for a single word while the erase time is 800 ms for a 128 K main block.

Tab le 2 –3 5 lists the flash pin assignments, signal names, and functions. The signal

names and types are relative to the Arria V GT FPGA in terms of I/O setting and direction.

Table 2–35. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference (U4)

Schematic

Signal Name

FLASH_ADVN

FLASH_CEN

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FLASH_WPN

FM_A1

FM_A2

FM_A3

FM_A4

FM_A5

FM_A6

FM_A7

FM_A8

FM_A9

FM_A10

FM_A11

FM_A12

FM_A13

FM_A14

FM_A15

FM_A16

FM_A17

FM_A18

FM_A19

FM_A20

Arria V GT FPGA

Pin Number

AK30 1.8-V Address valid

AU30 1.8-V Chip enable

AL31 1.8-V Clock

AN30 1.8-V Output enable

AK32 1.8-V Ready

AL34 1.8-V Reset

AN32 1.8-V Write enable

— 1.8-V Write protect

AT30 1.8-V Address bus

AL30 1.8-V Address bus

AP32 1.8-V Address bus

AM34 1.8-V Address bus

AJ33 1.8-V Address bus

AK33 1.8-V Address bus

AW33 1.8-V Address bus

AH30 1.8-V Address bus

AR30 1.8-V Address bus

AP33 1.8-V Address bus

AM31 1.8-V Address bus

AP31 1.8-V Address bus

AR31 1.8-V Address bus

AT31 1.8-V Address bus

AE29 1.8-V Address bus

AG30 1.8-V Address bus

AV31 1.8-V Address bus

AW30 1.8-V Address bus

AW31 1.8-V Address bus

AV30 1.8-V Address bus

I/O Standard Description

December 2014 Altera Corporation Arria V GT FPGA Development Board

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Table 2–35. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Power Supply

Board

Reference (U4)

FM_A21

FM_A22

FM_A23

FM_A24

FM_A25

FM_A26

FM_D0

FM_D1

FM_D2

FM_D3

FM_D4

FM_D5

FM_D6

FM_D7

FM_D8

FM_D9

FM_D10

FM_D11

FM_D12

FM_D13

FM_D14

FM_D15

Schematic

Signal Name

Arria V GT FPGA

Pin Number

AT29 1.8-V Address bus

AU29 1.8-V Address bus

AP30 1.8-V Address bus

AN29 1.8-V Address bus

AL32 1.8-V Address bus

AK31 1.8-V Address bus

AC22 1.8-V Data bus

AH20 1.8-V Data bus

AG22 1.8-V Data bus

AN20 1.8-V Data bus

AP20 1.8-V Data bus

AV22 1.8-V Data bus

AG23 1.8-V Data bus

AN22 1.8-V Data bus

AH21 1.8-V Data bus

AD21 1.8-V Data bus

AN23 1.8-V Data bus

AM21 1.8-V Data bus

AL22 1.8-V Data bus

AG20 1.8-V Data bus

AK22 1.8-V Data bus

AK23 1.8-V Data bus

I/O Standard Description

Power Supply

A laptop style DC power input provides power to the development board. The input voltage must be in the range of 14 V to 20 V. The DC voltage is then stepped down to various power rails used by the board components and installed into the HSMC connectors.

An on-board multi-channel analog-to-digital converter (ADC) measures both the voltage and current for several specific board rails. The power utilization is displayed on a graphical user interface (GUI) that can graph power consumption versus time.

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–69

2.5 V

Flash VDDQ, ENET VDD,

EPM2210 VCCIO2, NB6L11S,

6 Oscillators

A5_VCCD_PLL

VCCD_FPLL, VCCH_GXB,

VCCBAT

1.5 V, 1.133 A

A5_VCCIO_1.8V

FPGA VCCIO 1.8-V Banks

1.8 V, 1.688 A

A5_VCCR_GXB

VCCR_GXB, VCCL_GXB

A5_VCCT_GXB

VCCR_GXB

2.5 V, 0.141 A

2.5 V, 0.704 A

A5_VCCA

VCCA_FPLL, VCCAUX

2.5 V, 2.542 A

2.5 V, 1.226 A

A5_VCCPD_PGM_IO

VCCPD, VCCPGM

1.2 V, 4.512 A

1.2 V, 2.070 A

A5_VCCPD_PGM_IO

FPGA VCCIO 2.5-V Banks

A5_VCCA

VCCA_GXB

SENSE

BEAD

TPS51200

SENSE

1.8 V

Flash, QDR_VDD,

EPM2210, EPCQ

1.8 V, 0.693 A

SENSE

A5_VCCIO_1.5V

FPGA VCCIO 1.5-V Bank 8

1.5 V, 4.734 A

1.5 V

DDR3 VDD, EZ_USB

1.5 V, 1.080 A

SENSE

0.75 V, 0.050 A

VTT_DDR3A

VTT_DDR3B

TPS51200

VREF_DDR3B

0.75 V, 0.050 A

A5_VCCIO_FMC

VCCIO_FMC

1.8 - 3.3 V, 4.500 A

SENSE

A5_VCCINT

FPGA VCC

A5_VCCP

FPGA VCCP

1.15 V, 29.902 A

SENSE

BEAD

5.0 V, 0.018 A

5.0 V

Character LCD, MAX3378,

Regulator Bias

5.37 V, 0.220 A

ADC_MONITOR

LT2418 x 2

3.3 V, 2.198 A

3.3 V

ICS8543 CLK Buffer, EZ-USB,

SDI, OSC, Display Port

1.0 V, 0.253 A

1.0 V

ENET_DVDD

12 V, 3.0 A

12V_ATX

HSMA, HSMB, FMC

3.3 V, 9.4 A

3.3V_ATX

HSMA. HSMB, SFP+, FMC

LTM4628 Dual 8A

Switching Regulator

(+/- 3%)

BEAD

2.5 V, 5.861 A

1.2 V, 6.582 A

LT3026

1.5 A LDO (+/- 3%)

LTM4628 Dual 8A

Switching Regulator

(+/- 3%)

1.8 V, 3.614 A

1.5 V, 5.864 A

VREF_DDR3A

LTM4618

Switching Regulator

LTC3880 Switching

Regulator (+/- 3%)

LT3029

Channel 1 LDO

LT3029

Channel 2 LDO

LTM4601

Switching Regulator

LTC3025-1 0.5 A

Linear Regulator

12 V, 2.093 A

12 V, 1.466 A

1.345 A

3.426 A

Ideal Diode Multiplexer

Ideal Diode

Multiplexer

Ideal Diode

Multiplexer

12V_ATX

12V_ATX, 5.971 A

12 V, 8.651 A

3.3 V, 2.451 A

12 V, 5.5 A Maximum

PCIe Motherboard

3.3 V, 3.0 A Maximum

PCIe Motherboard

2.5 V, 1.249 A

12 V, 2.971 A

0.018 A

0.220 A

LTC3855 Dual

Channel Controller

DC INPUT 19 V

VCC/VCCP/VCCR_GXB/VCCT_GXB/VCCL_GXB

VCCPD/VCCPGM/VCCAUX/VCCA_FPLL, VCCA_GXB

VCCH_GXB/VCCD_FPLL

Power Sequencing

Power Supply

Power Distribution System

Figure 2–12 shows the power distribution system on the development board.

Regulator efficiencies and sharing are reflected in the currents shown, which are conservative absolute maximum levels.

Figure 2–12. Power Distribution System

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–70 Chapter 2: Board Components

SCK

DSI

DSO

CSn

8 Ch.

Power Supply Load #0-14

SENSE

SCK

DSI

DSO

CSn

8 Ch.

EPM2210

Arria V

FPGA

LTC2418

To User PC

Power GUI

JTAG Chain

Feedback

14-pin

2x16 LCD

E RW RS D(0:7)

Supply

#0-14

EPM570

USB PHY

Embedded

USB-Blaster

Power Supply

Power Measurement

There are 16 power supply rails that have on-board voltage, current, and wattage sense capabilities using 24-bit differential ADC devices. Precision sense resistors split the ADC devices and rails from the primary supply plane for the ADC to measure voltage and current. A SPI bus connects these ADC devices to the MAX II CPLD EPM2210 System Controller as well as the Arria V GT FPGA.

Figure 2–13 shows the block diagram for the power measurement circuitry.

Figure 2–13. Power Measurement Circuit

Tab le 2 –3 6 lists the targeted rails. The schematic signal name column specifies the

name of the rail being measured while the device pin column specifies the devices attached to the rail. If no subnet is named, the power is the total output power for that voltage.

Table 2–36. Power Measurement Rails (Part 1 of 3)

Switch Schematic Signal Name GUI Name Voltage Device Pin Description

A5A_VCCR_VCCL_GXB

A5A_XCVR_GXB

1.2V

VCCR_GXB, VCCL_GXB

XCVR analog receive and clock network

A5A_VCCT_GXB 1.2V VCCT_GXB XCVR transmitter power

2.5V VCCA_FPLL PLL analog power

2 A5A_VCCA_2.5V A5A_VCCA

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

2.5V

VCC_AUX, VCCA_GXB

Auxiliary

Chapter 2: Board Components 2–71

Power Supply

Table 2–36. Power Measurement Rails (Part 2 of 3)

Switch Schematic Signal Name GUI Name Voltage Device Pin Description

2.5 V VCCPD I/O pre-drivers

2.5 V VCCPGM Configuration I/O

VCCIO_4A, VCCIO_4B,

3 A5A_VCCPD_PGM_IO_2.5V A5A_VCCPD/PGM

2.5 V

VCCIO_4C, VCCIO_4D, VCCIO_7A,

VCC I/O banks 4 and 7

VCCIO_7B, VCCIO_7C, VCCIO_7D

4 A5A_VCCINT A5A_VCCINT 1.15 V VCC, VCCP FPGA core and periphery power

VCCIO_8A,

5 A5A_VCCIO_1.5V A5A_VCCIO_1.5V 1.5 V

VCCIO_8B, VCCIO_8C,

VCCIO bank 8 (DDR3A)

VCCIO_8D

1.5 V VCCD_FPLL PLL digital power

6 A5A_VCCD_PLL_1.5V A5A_VCCD_PLL

1.5 V VCCH_GXB

XCVR block level transmit buffers

VCCIO_3A,

7 A5A_VCCIO_1.8V A5A_VCCIO_1.8V 1.8 V

VCCIO_3B, VCCIO_3C,

VCC I/O bank 3 (QDRII+)

VCCIO_3D

A5B_VCCR_VCCL_GXB

A5B_XCVR_GXB

1.2 V

VCCR_GXB, VCCL_GXB

XCVR analog receive and clock network

A5B_VCCT_GXB 1.2 V VCCT_GXB XCVR transmitter power

9 A5B_VCCA_2.5V A5B_VCCA

2.5 V VCCA_FPLL PLL analog power

2.5 V VCC_AUX Auxiliary

2.5 V VCCPD I/O pre-drivers

2.5 V VCCPGM Configuration I/O

VCCIO_3A,

10 A5B_VCCPD_PGM_IO_2.5V A5B_VCCPD/PGM

2.5 V

VCCIO_3B, VCCIO_7A, VCCIO_7B,

VCC I/O banks 3A, 3B and 7

VCCIO_7C, VCCIO_7D

11 A5B_VCCINT A5B_VCCINT 1.15 V VCC, VCCP FPGA core and periphery power

VCCIO_8A,

12 A5B_VCCIO_1.5V A5B_VCCIO_1.5V 1.5 V

VCCIO_8B, VCCIO_8C,

VCCIO bank 8 (DDR3A)

VCCIO_8D

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

2–72 Chapter 2: Board Components

Statement of China-RoHS Compliance

Table 2–36. Power Measurement Rails (Part 3 of 3)

Switch Schematic Signal Name GUI Name Voltage Device Pin Description

1.5 V VCCD_FPLL PLL digital power

13 A5B_VCCD_PLL_1.5V A5B_VCCD_PLL

14 A5_VCCIO_FMC A5_VCCIO_FMC

1.5 V VCCH_GXB

1.5 V/

1.8 V/

2.5 V/

3.3 V

VCCIO_3C, VCCIO_3D, VCCIO_4A, VCCIO_4C, VCCIO_4D

XCVR block level transmit buffers

I/O supply bank (FMC port)

Statement of China-RoHS Compliance

Tab le 2 –3 7 lists hazardous substances included with the kit.

(Hg)

(1), (2)

Polybrominated biphenyls (PBB)

Polybrominated diphenyl Ethers

(PBDE)

Table 2–37. Table of Hazardous Substances’ Name and Concentration Notes

Part Name

Lead

(Pb)

Cadmium

(Cd)

Hexavalent

Chromium

(Cr6+)

Mercury

Arria V development board X* 0 0 0 0 0

12 V power supply 0 0 0 0 0 0

Type A-B USB cable 0 0 0 0 0 0

User guide 0 0 0 0 0 0

Notes to Table 2–37:

(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the

SJ/T11363-2006 standard.

(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant

threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

3. Board Components Reference

This chapter lists the component reference and manufacturing information of all the components on the Arria V GT FPGA FPGA development board.

Table 3–1. Component Reference and Manufacturing Information (Part 1 of 2)

Board

Reference

U13, U16

Component Manufacturer

FPGAs, Arria V GT F1517, 504K LEs, lead free

IC - MAX II CPLD EPM2210 324FBGA -3 LF 1.8V VCCINT

Corporation 5AGTFD7K3F40I3N www.altera.com

Altera

Corporation EPM2210GF324 www.altera.com

Altera

Manufacturing

Part Number

Manufacturer

Website

D2–D12, D14–D17, D34–D40,

Green LEDs Lumex Inc. SML-LXT0805GW-TR www.lumex.com

D45

D42, D43,

D44

Yellow LEDs Lumex Inc. SML-LXT0805YW-TR www.lumex.com

D18–D33 Bi color Red/Green LEDs Lite-On LTST-C195KGJRKT www.lite-on.com

D13 Red LED Lumex Inc. SML-LXT0805IW-TR www.lumex.com

D1 Blue LED Lumex Inc. SML-LX0805USBC-TR www.lumex.com

SW5–SW7 Four-position DIP switches

S1, S4, S8 Reset push buttons

S3 Configuration push button

S2 Image select push button

X1, X4

125.000-MHz LVDS saw clock oscillator

X5 25-MHz oscillator Epson

C&K Components/

ITT Industries

Dawning Precision

Co.

Dawning Precision

Co.

Dawning Precision

Co.

Epson

TDA04H0SB1 www.ittcannon.com

TS-A02SA-2-S100 www.dawning2.com.tw

EG-2121CA 125.0000M-

LGPNL3

SG-310SDF 25.0000M-

www.eea.epson.com

Y3 24-MHz crystal oscillator Epson FA-128 24.0000MB-W www.eea.epson.com

Y1, Y2,

Y4, Y5

25-MHz crystal oscillator Epson FA-128 25.0000MB-C www.eea.epson.com

X6 50-MHz oscillator ECS Inc. ECS-3518-500-B-xx www.ecsxtal.com

Si5338A-A01316-GM,

U34, U48,

U53, U52

Quad output programmable clock generator

Silicon Labs Inc.

Si5338A-A01317-GM, Si5338A-A01318-GM,

www.silabs.com

Si5338A-A01319-GM

100-MHz single output programmable oscillator

148.5-MHz single output programmable VCXO

Silicon Labs Inc. 570FAB000433DG www.silabs.com

Silicon Labs Inc. 571FDB000159DG www.silabs.com

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

3–2 Chapter 3: Board Components Reference

Table 3–1. Component Reference and Manufacturing Information (Part 2 of 2)

Board

Reference

Component Manufacturer

Manufacturing

Part Number

Manufacturer

Website

X7 100 MHz crystal oscillator ECS Inc. ECS-3525-1000-B-TR www.ecsxtal.com

S4–S6,

S9–S11

SW2, SW3

D18–D25,

D26–D33

D4, D5, D7, D8

J30

U24

U23

User-defined push button

User-defined eight-position DIP switch

User-defined bi-color red and green LEDs

HSMC Green LEDs Lumex Inc. SML-LXT0805GW-TR www.lumex.com

2×7 pin, 100 mil, vertical header LCD socket strip

2×16 character display, 5×8 dot matrix

3-Gbps HD/SD SDI cable driver with cable detect

3-Gbps HD/SD SDI adaptive cable equalizer

Dawning Precision

Co.

C&K Components/

ITT Industries

Lite-On LTST-C195GEKT

TS-A02SA-2-S100 www.dawning2.com.tw

TDA08H0SB1 www.ittcannon.com

www.us.liteon.com/opto

.index.html

Samtec TSM-107-01-G-DV www.samtec.com

Lumex Inc. LCM-S01602DSR/C www.lumex.com

National

Semiconductor

National

Semiconductor

LMH0303SQx www.national.com

LMH0384SQ www.national.com

PCI Express 4.20-mm pitch header,

13 A per pin, dual row, right angle,

Molex 50-34-8571 www.molex.com

with PCB mounting flanges.

U14 Ethernet PHY BASE-T device

J1, J2

RJ-45 connector, 10/100/1000 Mbps

HSMC, custom version of QSH-DP family high-speed socket.

Marvell

Semiconductor

88E1111-B2-CAA1C000 www.marvell.com

Wurth Elektronik 7499111001A www.we-online.com

Samtec ASP-122953-01 www.samtec.com

B2 SFP+ right-angle, press-fit cage Molex 74754-0101 www.molex.com

J10, J15

J10

J16

SFP+ right-angle, 20-pin SMT connector

FMC pitch socket array assembly connector

Bull's Eye test point receptacle

Samtec MECT-110-01-M-D-RA1 www.samtec.com

Samtec ASP-134486-01 www.samtec.com

BAR-J-22

Samtec

BE25S-01SP1-01.0-02-

0152

www.samtec.comFour CCA-25M cable assemblies

Insertion/Extraction tool CAT-EX-SCC-01

U6, U11, U12, U18, U19, U21,

32M×16×8, 2 Gb, DDR3 memory Micron

MT41J128M16HA-

125:D

www.micron.com

U22, U28

U7 16M×8×8, 1 Gb, DDR3 memory Micron MT41J128M8JP-125:G www.micron.com

QDRII+ SRAM 72-Mb 4-word burst 2M×36, 533 MHz

Renesas

Technology Corp.

R1QDA7236ABG_19IB0 www.am.renesas.com

U4 1-Gb synchronous flash Numonyx PC28F512P30BF www.numonyx.com

U29, U31 8-channel differential 24-bit ADC Linear Technology LTC2418CGN#PBF www.linear.com

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Additional Information

This chapter provides additional information about the document and Altera.

Document Revision History

The following table lists the revision history for this document.

Date Version Changes

December 2014 1.2 Corrected FPGA pin numbers for user-defined LEDs for FPGA 1. Table 2–16.

May 2013 1.1 Revised the FPGA core voltage to 1.15 V in Figure 2–12 and Table 2–36.

November 2012 1.0 Initial release.

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the following table.

Contact

Technical support Website www.altera.com/support

Technical training

Product literature Website www.altera.com/literature

Nontechnical support (general) Email nacomp@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

(1)

(software licensing) Email authorization@altera.com

Contact Method Address

Website www.altera.com/training

Email custrain@altera.com

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

italic type

Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

Indicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

Info–2 Additional InformationAdditional Information

Typographic Conventions

Visual Cue Meaning

Initial Capital Letters

“Subheading Title”

Indicate keyboard keys and menu names. For example, the Delete key and the Options menu.

Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example,

tdi

, and

input

. The suffix n denotes an active-low signal. For example,

resetn

data1

Indicates command line commands and anything that must be typed exactly as it

Courier type

appears. For example,

c:\qdesigns\tutorial\chiptrip.gdf

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword

TRI

example,

SUBDESIGN

), and logic function names (for

r An angled arrow instructs you to press the Enter key.

1., 2., 3., and a., b., c., and so on

■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

1 The hand points to information that requires special attention. h The question mark directs you to a software help system with related information. f The feet direct you to another document or website with related information. m The multimedia icon directs you to a related multimedia presentation.

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.

Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual

Altera Arria V GT FPGA Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Dual FPGA

FPGA 1

FPGA 2

Development Board Block Diagram

Handling the Board

Introduction

2. Board Components

Board Overview

Featured Device: Arria V GT FPGA

I/O Resources

MAX II CPLD EPM2210 System Controller

Configuration, Status, and Setup Elements

Configuration

FPGA Programming over On-Board USB-Blaster II

FPGA Programming from Flash Memory

FPGA Programming over External USB-Blaster

Status Elements

Setup Elements

Board Settings DIP Switch

JTAG Settings DIP Switch

PCI Express Control DIP Switch

CPU Reset Push Button

MAX II Reset Push Button

Configuration Push Button

Clock Circuitry

Image Select Push Button

On-Board Oscillators

Off-Board Clock Input/Output

General User Input/Output

User-Defined Push Buttons

User-Defined DIP Switches

User-Defined LEDs

General User-Defined LEDs

HSMC User-Defined LEDs

SDI Video Output/Input

Components and Interfaces

PCI Express

10/100/1000 Ethernet

HSMC

SFP+ Modules

FMC Connector

Bull's Eye Connector

Memory

DDR3

DDR3A for FPGA 1

DDR3B/C for FPGA 2

QDRII+

Flash

Power Supply

Power Distribution System

Power Measurement

Statement of China-RoHS Compliance

3. Board Components Reference

Additional Information

Document Revision History

How to Contact Altera

Typographic Conventions