Altera Arria V GT FPGA User Manual
Arria V GT FPGA Development Kit User Guide
Arria V GT FPGA Development Kit
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-01124-1.0
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Registered
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
Contents
Chapter 1. About This Kit
Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Arria V GT FPGA Development Kit Installer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Chapter 2. Getting Started
Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Inspect the Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Chapter 3. Software Installation
Installing the Quartus II Subscription Edition Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Licensing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Installing the Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Installing the USB-Blaster II Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Chapter 4. Development Board Setup
Setting Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Factory Default Switch and Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Chapter 5. Board Update Portal
Connecting to the Board Update Portal Web Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Using the Board Update Portal to Update User Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Chapter 6. Board Test System
Preparing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Running the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Using the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
The Configure Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
The System Info Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
MAX II Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
The GPIO FPGA 1 Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
The Flash Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Random Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
CFI Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Increment Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
iv Contents
Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
The HSMA Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Port (FPGA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
PMA Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
The SFP/SMA/C2C Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
Port (FPGA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
PMA Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
The HSMB/FMC Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
Port (FPGA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
PMA Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
The SDI/Bull’s Eye Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
Port (FPGA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
PMA Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
The SMA Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
Port (FPGA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
PMA Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
The Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24
Power Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25
Power Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25
Graph Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 6–25
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25
Calculating Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25
The Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
Contents v
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27
Frequency (MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27
Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27
Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27
Set New Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27
Configuring the FPGA Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27
Samtec High-speed Bull’s Eye Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–28
Appendix A. Programming the Flash Memory Device
CFI Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Preparing Design Files for Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Creating Flash Files Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Programming Flash Memory Using the Board Update Portal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Programming Flash Memory Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
Restoring the Flash Device to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
Restoring the MAX II CPLD to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
vi Contents
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
Kit Features
Hardware
1. About This Kit
The Altera® Arria®V GT FPGA Development Kit is a complete design environment
that includes both the hardware and software you need to develop Arria V GT FPGA
designs.
This section briefly describes the Arria V GT FPGA Development Kit contents.
The Arria V GT FPGA Development Kit includes the following hardware:
■ Arria V GT FPGA development board—A development platform that allows you
to develop and prototype hardware designs running on the Arria V GT
5AGTFD7K3F40N FPGA.
Software
f For detailed information about the board components and interfaces, refer
to the Arria V GT FPGA Development Board Reference Manual.
■ HSMC loopback daughtercard
■ HSMC debug daughtercard
■ Power supply and cables—The kit includes the following items:
■ Power supply and AC adapters for North America/Japan, Europe, and the
United Kingdom
■ USB cable
■ Ethernet cable
■ Samtec high-speed Bull’s Eye kit with 22-position connector, four SMA cables
and tool
The software for this kit, described in the following sections, is available on the Altera
website for immediate downloading. You can also request to have Altera mail the
software to you on DVDs.
Quartus II Software
Your kit includes a license for the Development Kit Edition (DKE) of the Quartus II
software (Windows platform only). For one year, this license entitles you to most of
the features of the Subscription Edition (excluding the IP Base Suite).
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
1–2 Chapter 1: About This Kit
Kit Features
1 After the year, your DKE license will no longer be valid and you will not be permitted
to use this version of the Quartus II software. To continue using the Quartus II
software, you should download the free Quartus II Web edition or purchase a
subscription to Quartus II software. For more information, refer to the Design
Software page of the Altera website.
The Quartus II Development Kit Edition (DKE) software includes the following items:
■ Quartus II Software—The Quartus II software, including the Qsys system
integration tool, provides a comprehensive environment for network on a chip
(NoC) design. The Quartus II software integrates into nearly any design
environment and provides interfaces to industry-standard EDA tools.
■ MegaCore
®
IP Library—A library that contains Altera IP MegaCore functions. You
can evaluate MegaCore functions by using the OpenCore Plus feature to do the
following:
■ Simulate behavior of a MegaCore function within your system.
■ Verify functionality of your design, and quickly and easily evaluate its size and
speed.
■ Generate time-limited device programming files for designs that include
MegaCore functions.
■ Program a device and verify your design in hardware.
1 The OpenCore Plus hardware evaluation feature is an evaluation tool for
prototyping only. You must purchase a license to use a MegaCore function
in production.
f For more information about OpenCore Plus, refer to AN 320: OpenCore Plus
Evaluation of Megafunctions.
■ Nios
®
II Embedded Design Suite (EDS)—A full-featured set of tools that allows
you to develop embedded software for the Nios II processor, which you can
include in your Altera FPGA designs.
Arria V GT FPGA Development Kit Installer
The license-free Arria V GT FPGA Development Kit installer includes all the
documentation and design examples for the kit.
For information on installing the Development Kit Installer, refer to “Software
Installation” on page 3–1.
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
The remaining chapters in this user guide lead you through the following Arria V GT
FPGA development board setup steps:
■ Inspecting the contents of the kit
■ Installing the design and kit software
■ Setting up, powering up, and verifying correct operation of the FPGA
■ Configuring the Arria V GT FPGAs
■ Running the Board Test System designs
f For complete information about the FPGA development board, refer to the
Arria V GT FPGA Development Board Reference Manual.
Before You Begin
2. Getting Started
development board
Before using the kit or installing the software, check the kit contents and inspect the
boards to verify that you received all of the items listed in “Kit Features” on page 1–1.
If any of the items are missing, contact Altera before you proceed.
Inspect the Boards
To inspect each board, perform the following steps:
1. Place the board on an anti-static surface and inspect it to ensure that it has not been
damaged during shipment.
c Without proper anti-static handling, you can damage the board.
2. Verify that all components on the board appear in place and intact.
1 In typical applications with the Arria V GT FPGA development board, a heat sink is
not necessary. However, under extreme conditions or for engineering sample silicon
the board might require additional cooling to stay within operating temperature
guidelines. The board has two holes near the FPGAs that accommodate many
different heat sinks, including the Dynatron CHR-152. You can perform power
consumption and thermal modeling to determine whether your application requires
additional cooling. For information about measuring board and FPGA power in real
time, refer to “The Power Monitor” on page 6–23.
f For more information about power consumption and thermal modeling, refer to
AN 358: Thermal Management for FPGAs.
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
2–2 Chapter 2: Getting Started
References
References
Use the following links to check the Altera website for other related information:
■ For the latest board design files and reference designs, refer to the Arria V GT
FPGA Development Kit page.
■ For additional daughter cards available for purchase, refer to the Development
Board Daughtercards page.
■ For the Arria V GT device documentation, refer to the Documentation: Arria V
Devices page.
■ To purchase devices from the eStore, refer to the Devices page.
■ For Arria V GT OrCAD symbols, refer to the Capture CIS Symbols page.
■ For Nios II 32-bit embedded processor solutions, refer to the Embedded
Processing page.
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
3. Software Installation
This chapter explains how to install the following software:
■ Quartus II Subscription Edition Software
■ Arria V GT FPGA Development Kit
■ USB-Blaster™ II driver
Installing the Quartus II Subscription Edition Software
The Quartus II Subscription Edition Software provides the necessary tools used for
developing hardware and software for Altera devices. Included in the Quartus II
Subscription Edition Software are the Quartus II software, the Nios II EDS, and the
MegaCore IP Library. The Quartus II software (including SOPC Builder) and the
Nios II EDS are the primary FPGA development tools used to create the reference
designs in this kit. To install the Altera development tools, perform the following
steps:
1. Download the Quartus II Subscription Edition Software from the Quartus II
Subscription Edition Software page of the Altera website. Alternatively, you can
request a DVD from the Altera IP and Software DVD Request Form page of the
Altera website.
2. Choosing an installation directory that is relative to the Quartus II software
installation directory, follow the on-screen instructions to complete the installation
process.
f If you have difficulty installing the Quartus II software, refer to Altera Software
Installation and Licensing Manual.
Licensing Considerations
Purchasing this kit entitles you to a one-year license for the Development Kit Edition
(DKE) of the Quartus II software.
After the year, your DKE license will no longer be valid and you will not be permitted
to use this version of the Quartus II software. To continue using the Quartus II
software, you should download the free Quartus II Web edition or purchase a
subscription to Quartus II software.
Before using the Quartus II software, you must activate your license, identify specific
users and computers, and obtain and install a license file.
If you already have a licensed version of the subscription edition, you can use that
license file with this kit. If not, you need to obtain and install a license file. To begin,
go to the Self Service Licensing Center page of the Altera website, log into or create
your myAltera account, and take the following actions:
1. On the Activate Products page, enter the serial number provided with your
development kit in the License Activation Code box.
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
3–2 Chapter 3: Software Installation
Installing the Quartus II Subscription Edition Software
1 Your serial number is printed on the development kit box below the bottom
bar code. The number is 10 or 11 alphanumeric characters and does not
contain hyphens. Figure 3–1 shows 3S150SPXXXX as an example serial
number.
Figure 3–1. Locating Your Serial Number
2. Consult the Activate Products table, to determine how to proceed.
a. If the administrator listed for your product is someone other than you, skip the
remaining steps and contact your administrator to become a licensed user.
b. If the administrator listed for your product is you, proceed to step 3.
c. If the administrator listed for your product is Stocking, activate the product,
making you the administrator, and proceed to step 3.
3. Use the Create New License page to license your product for a specific user (you)
on specific computers. The Manage Computers and Manage Users pages allow
you to add users and computers not already present in the licensing system.
1 To license the Quartus II software, you need your computer’s network
interface card (NIC) ID, a number that uniquely identifies your computer.
On the computer you use to run the Quartus II software, type
/all
at a command prompt to determine the NIC ID. Your NIC ID is the 12-
ipconfig
digit hexadecimal number on the Physical Address line.
4. When licensing is complete, Altera emails a license.dat file to you. Store the file on
your computer and use the License Setup page of the Options dialog box in the
Quartus_II software to enable the software.
f For complete licensing details, refer to Altera Software Installation and Licensing Manual.
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
Chapter 3: Software Installation 3–3
<install dir>
documents
board_design_files
The default Windows installation directory is C:\altera\
<version>
\.
examples
factory_recovery
demos
kits
arriaVGT_5agtfd7kf40_fpga
Installing the Development Kit
Installing the Development Kit
To install the Arria V GT FPGA Development Kit, perform the following steps:
1. Download the Arria V GT FPGA Development Kit installer from the Arria V GT
FPGA Development Kit page of the Altera website. Alternatively, you can request
a development kit DVD from the Altera Kit Installations DVD Request Form page
of the Altera website.
2. Run the Arria V GT FPGA Development Kit installer.
3. Follow the on-screen instructions to complete the installation process. Be sure that
the installation directory you choose is in the same relative location to the
Quartus II software installation.
The installation program creates the Arria V GT FPGA Development Kit directory
structure shown in Figure 3–2.
Figure 3–2. Arria V GT FPGA Development Kit Installed Directory Structure
Note to Figure 3–2:
(1) Early-release versions might have slightly different directory names.
Tab le 3 –1 lists the file directory names and a description of their contents.
Table 3–1. Installed Directory Contents
Directory Name Description of Contents
board_design_files
Contains schematic, layout, assembly, and bill of material board design files. Use these files as a
starting point for a new prototype board design.
demos Contains demonstration applications, if present.
documents Contains the kit documentation.
examples Contains the sample design files for the Arria V GT FPGA Development Kit.
factory_recovery
Contains the original data programmed onto the board before shipment. Use this data to restore
the board with its original factory contents.
(1)
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
3–4 Chapter 3: Software Installation
Installing the USB-Blaster II Driver
Installing the USB-Blaster II Driver
The Arria V GT FPGA development board includes integrated On-Board USB-Blaster
II circuitry for FPGA programming. However, for the host computer and board to
communicate, you must install the USB-Blaster II driver on the host computer.
f Installation instructions for the USB-Blaster II driver for your operating system are
available on the Altera website. On the Altera Programming Cable Driver Information
page of the Altera website, locate the table entry for your configuration and click the
link to access the instructions.
f For USB-Blaster II configuration details, refer to the On-Board USB-Blaster II page.
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
The instructions in this chapter explain how to set up the Arria V GT FPGA
development board.
Setting Up the Board
To prepare and apply power to the board, perform the following steps:
1. The Arria V GT FPGA development board ships with its board switches
preconfigured to support the design examples in the kit. If you suspect your board
might not be currently configured with the default settings, follow the instructions
in “Factory Default Switch and Jumper Settings” on page 4–2 to return the board
to its factory settings before proceeding.
2. The development board ships with design examples stored in the flash memory
device. Verify the Load Selector (SW5.3) is in the on (factory) position to load the
design stored in the factory portion of flash memory. Figure 4–1/Figure 4–2 shows
the switch locations on the Arria V GT FPGA development board.
4. Development Board Setup
3. Connect the +19 V, 6.32 A to the DC Power Jack (J6) on the FPGA board and plug
the cord into a power outlet.
c Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage, and a
lower-rated power supply may not be able to provide enough power for the
board.
4. Set the POWER switch (SW1) to the on position. When power is supplied to the
board, blue LED (D1) illuminates indicating that the board has power.
The MAX II device on the board contains (among other things) a parallel flash loader
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. The Load Selector (SW5.3) controls which design
to load. When the switch is in the on (factory) position, the PFL loads the design from
the factory portion of flash memory.
1 The kit includes a MAX II design which contains the MAX II PFL megafunction. The
design resides in the <install
dir>\kits\arriaVGT_5agtfd7kf40_fpga\examples\max2 directory.
When configuration is complete, the Config Done LED (D16) illuminates, signaling
that the Arria V GT device configured successfully.
f For more information about the PFL megafunction, refer to Parallel Flash Loader
Megafunction User Guide.
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
4–2 Chapter 4: Development Board Setup
J23
J28
SW3
(installed)
FAN 1
J14
(installed)
FAN2
J5
7
2.5V
FMC_VCCPD
3.3V
6543210
SW2
76543210
USER_DIP1
USER_DIP2
ON
ON
J11
1.8V
2.5V
3.3V
Factory Default Switch and Jumper Settings
Factory Default Switch and Jumper Settings
This section shows the factory switch and jumper settings for the Arria V GT FPGA
development board. Figure 4–1 shows the switch and jumper locations and the
default position of each switch and jumper on the top side of the board.
Figure 4–1. Switch Locations and Default Settings on the Board Top
Figure 4–2 shows the switch locations and the default position of each switch on the
bottom side of the board.
Figure 4–2. Switch Locations and Default Settings on the Board Bottom
MSEL2
421
ON
SW4
1 2 3 4
SW5
PCIe Width
SW7
Factory2
ON
1 2 3 4
Factory1
CLK_EN
CLK_SEL
1 2 3 4
ON
SW6
HSMA
HSMB
ON
1 2 3 4
MSEL 1
421
ON
1 2 3 4
SW8
FMC
JTAG_CHAIN
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
Chapter 4: Development Board Setup 4–3
Factory Default Switch and Jumper Settings
To restore the switches to their factory default settings, perform the following steps:
1. Set DIP switch bank (SW4) to match Tab le 4 –1 and Figure 4–2.
Table 4–1. SW4 FPGA2 MSEL Dip Switch Settings
Switch
Board
Label
(1)
Function
Default
Position
Switch 1 has the following options:
1 FPGA2_MSEL[1]
■ When ON, a logic 0 is selected.
■ When OFF, a logic 1 is selected.
ON
Switch 2 has the following options:
2 FPGA2_MSEL[2]
■ When ON, a logic 0 is selected.
■ When OFF, a logic 1 is selected.
OFF
3— — ON
Switch 4 has the following options:
4 FPGA2_MSEL[4]
Note to: Table 4–1
(1) Ensure that all MSEL setting are in a defined configuration scheme as shown in Volume 2: Device Interfaces and
Integration of the Arria V Device Handbook.
■ When ON, a logic 0 is selected.
■ When OFF, a logic 1 is selected.
OFF
2. Set DIP switch bank (SW5) to match Tab le 4 –2 and Figure 4–2.
Table 4–2. SW5 Board Settings Dip Switch
Switch
Board
Label
Function
Default
Position
Switch 1 has the following options:
1 CLK_SEL
■ ON, (logical 0) = SMA input clock select.
■ OFF, (logical 1) = programmable oscillator clock select.
OFF
Switch 2 has the following options:
2 CLK_EN
■ ON, (logical 0) = on-board oscillator disable.
■ OFF, (logical 1) = on-board oscillator enable.
ON
Switch 3 has the following options:
■ ON, (logical 0) = load the factory design for Arria V
3Factory1
FPGA 1 from flash at power up.
■ OFF, (logical 1) = load the user design for Arria V FPGA
ON
1 from flash at power up.
4 Factory2 Switch 4 is for factory test only. OFF
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
4–4 Chapter 4: Development Board Setup
Factory Default Switch and Jumper Settings
3. Set DIP switch bank (SW6) to match Tab le 4 –3 and Figure 4–2.
Table 4–3. SW6 JTAG Dip Switch Settings
Switch
Board
Label
Function
Default
Position
1— — OFF
Switch 2 has the following options:
2 HSMA_JTAG_EN
■ ON, (logical 0) = HCMC Port A not in JTAG chain.
■ OFF, (logical 1) = Include HCMC Port A in the
ON
JTAG chain.
Switch 3 has the following options:
3 HSMB_JTAG_EN
■ ON, (logical 0) = HCMC Port B not in JTAG chain.
■ OFF, (logical 1) = Include HCMC Port B in the
ON
JTAG chain.
Switch 4 has the following options:
■ ON, (logical 0) = FMC connector not in JTAG
4FMC_JTAG_EN
chain.
■ OFF, (logical 1) = Include FMC connector in the
ON
JTAG chain.
4. Set DIP switch bank (SW7) to match Tab le 4 –4 and Figure 4–2.
Table 4–4. SW7 PCIe DIP Switch Settings
Switch
Board
Label
Function
Default
Position
Switch 1 has the following options:
1 PCIE_PRSNT2n_x1
■ ON (0) = x1 presence detect is enabled.
■ OFF (1) = x1 presence detect is disabled.
ON
Switch 2 has the following options:
2 PCIE_PRSNT2n_x4
■ ON (0) = x4 presence detect is enabled.
■ OFF (1) = x4 presence detect is disabled.
ON
Switch 3 has the following options:
3 PCIE_PRSNT2n_x8
■ ON (0) = x8 presence detect is enabled.
■ OFF (1) = x8 presence detect is disabled.
ON
4— — OFF
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
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