Altera Arria V Avalon-ST User Manual

Arria V Avalon-ST Interface for PCIe Solutions

User Guide

Last updated for Altera Complete Design Suite: 14.1

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Application

Layer

(User Logic)

Avalon-ST

Interface

PCIe Hard IP

Block

PIPE

Interface

PHY IP Core

for PCIe

(PCS/PMA)

Serial Data

Transmission

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Datasheet

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Arria V Avalon-ST Interface for PCIe Datasheet

Altera® Arria® V FPGAs include a configurable, hardened protocol stack for PCI Express compliant with PCI Express Base Specification 2.1 or 3.0. The Hard IP for PCI Express using the Avalon Streaming (Avalon-ST) interface is the most flexible variant. However, this variant requires a thorough understanding of the PCIe interfaces for this variant.

Figure 1-1: Arria V PCIe Variant with Avalon-ST Interface

Table 1-1: PCI Express Data Throughput

Protocol. The following figure shows the high-level modules and connecting

that is

The following table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead.

PCI Express Gen1 (2.5 Gbps)

PCI Express Gen2 (5.0 Gbps)

Refer to the PCI Express High Performance Reference Design for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs.

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Link Width

×1 ×2 ×4 ×8

2 4 8 16

4 8 16

N/A

ISO 9001:2008 Registered

1-2

Features

Related Information

• PCI Express Base Specification 2.1 or 3.0

• PCI Express High Performance Reference Design

• Creating a System with Qsys

Features

New features in the Quartus® II 14.1 software release:

• Reduced Quartus II compilation warnings by 50%. The Arria V Hard IP for PCI Express supports the following features:

• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as

• Support for ×1, ×2, ×4, and ×8 configurations with Gen1 and Gen2 lane rates for Root Ports and

• Dedicated 16 KByte receive buffer.

• Optional hard reset controller for Gen2.

• Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core

• Qsys example designs demonstrating parameterization, design modules, and connectivity.

• Extended credit allocation settings to better optimize the RX buffer space based on application type.

• Multi-function support for up to eight Endpoint functions.

• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error

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hard IP.

Endpoints.

bitstreams to be stored separately.

reporting (AER) for high reliability applications. Easy to use:

• Flexible configuration.

• Substantial on-chip resource savings and guaranteed timing closure.

• No license requirement.

• Example designs to get started.

Table 1-2: Feature Comparison for all Hard IP for PCI Express IP Cores

The table compares the features of the four Hard IP for PCI Express IP Cores.

Feature Avalon‑ST Interface Avalon‑MM Interface Avalon‑MM DMA

IP Core License Free Free Free

Native Endpoint Supported Supported Supported

Legacy Endpoint

(1)

Supported Not Supported Not Supported

Root port Supported Supported Not Supported

(1)

Not recommended for new designs.

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Feature Avalon‑ST Interface Avalon‑MM Interface Avalon‑MM DMA

Gen1 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 x8

Gen2 ×1, ×2, ×4 ×1, ×2, ×4 ×4

Features

1-3

64-bit Application Layer interface

128-bit Application Layer interface

Transaction Layer Packet type (TLP)

Supported Supported Not supported

Supported Supported Supported

• Memory Read Request

• Memory Read RequestLocked

• Memory Write Request

• I/O Read Request

• I/O Write Request

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Message Request

• Message Request with Data Payload

• Completion Message

• Completion with Data

• Completion for Locked

• Memory Read Request

• Memory Write Request

• I/O Read Request— Root Port only

• I/O Write Request— Root Port only

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Completion Message

• Completion with Data

• Memory Read Request (single dword)

• Memory Write Request (single dword)

• Memory Read Request

• Memory Write Request

• Completion Message

• Completion with Data

Read without Data

Datasheet

Payload size 128–512 bytes 128 or 256 bytes 128 or 256 bytes

Number of tags

32 or 64 16 16 supported for nonposted requests

62.5 MHz clock Supported Supported Not Supported

Multi-function

Out-of-order

Supports up to 8 functions Supports single function

only

Supports single function only

Not supported Supported Supported completions (transparent to the Application Layer)

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Release Information

Feature Avalon‑ST Interface Avalon‑MM Interface Avalon‑MM DMA

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Requests that cross 4

Not supported Supported Supported KByte address boundary (transparent to the Application Layer)

Polarity Inversion of

Supported Supported Supported PIPE interface signals

ECRC forwarding on

Supported Not supported Not supported RX and TX

Number of MSI

1, 2, 4, 8, or 16 1, 2, 4, 8, or 16 1, 2, 4, 8, or 16 requests

MSI-X Supported Supported Supported

Legacy interrupts Supported Supported Supported

Expansion ROM Supported Not supported Not supported

The purpose of the Arria V Avalon-ST Interface for PCI e Solutions User Guide is to explain how to use this and not to explain the PCI Express protocol. Although there is inevitable overlap between these two purposes, this document should be used in conjunction with an understanding of the PCI Express Base Specification.

Note:

This release provides separate user guides for the different variants. The Related Information provides links to all versions.

Related Information

• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

• Arria V Avalon-MM Interface for PCIe Solutions User Guide

• Arria V Avalon-ST Interface for PCIe Solutions User Guide

Release Information

Table 1-3: Hard IP for PCI Express Release Information

Item Description

Version 14.1

Release Date December 2014

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Ordering Codes No ordering code is required

Product IDs There are no encrypted files for the Arria V Hard IP

Vendor ID

Device Family Support

Table 1-4: Device Family Support

Device Family Support

Arria V Final. The IP core is verified with final timing

Device Family Support

Item Description

for PCI Express. The Product ID and Vendor ID are not required because this IP core does not require a license.

models. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

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Other device families Refer to the Related Information below for other

device families:

Related Information

• Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide

• Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide

• Arria 10 Avalon-ST Interface for PCIe Solutions User Guide

• Cyclone V Avalon-MM Interface for PCIe Solutions User Guide

• Cyclone V Avalon-ST Interface for PCIe Solutions User Guide

• IP Compiler for PCI Express User Guide

• Stratix V Avalon-MM Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface with SR-IOV for PCIe Solutions User Guide

Datasheet

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Altera FPGA

User Application

Logic

PCIe

Hard IP

PCIe

Hard IP

User Application

Logic

PCI Express Link

Altera FPGA

1-6

Configurations

The Arria V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack comprising the following layers:

• Physical (PHY), including:

• Physical Media Attachment (PMA)

• Physical Coding Sublayer (PCS)

• Media Access Control (MAC)

• Data Link Layer (DL)

• Transaction Layer (TL) The Hard IP supports all memory, I/O, configuration, and message transactions. It is optimized for Altera

devices. The Application Layer interface is also optimized to achieve maximum effective throughput. You can customize the Hard IP to meet your design requirements.

Figure 1-2: PCI Express Application with a Single Root Port and Endpoint

The following figure shows a PCI Express link between two Arria V FPGAs. One is configured as a Root Port and the other as an Endpoint.

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Arria V or Cyclone V FPGA

PCIe Hard

IP Multi-

Function

CAN GbE ATA PCI

Altera FPGA

PCIe

Hard IP

Host

CPU

Memory

Controller

Peripheral Controller

USB

SPI GPIO

I2C

PCI Express Link

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Configurations

Figure 1-3: PCI Express Application with an Endpoint Using the Multi-Function Capability

The following figure shows a PCI Express link between two Altera FPGAs. One is configured as a Root Port and the other as a multi-function Endpoint. The FPGA serves as a custom I/O hub for the host CPU. In the Arria V FPGA, each peripheral is treated as a function with its own set of Configuration Space registers. Eight multiplexed functions operate using a single PCI Express link.

Figure 1-4: PCI Express Application Using Configuration via Protocol

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The Arria V design below includes the following components:

• A Root Port that connects directly to a second FPGA that includes an Endpoint.

• Two Endpoints that connect to a PCIe switch.

• A host CPU that implements CvP using the PCI Express link connects through the switch. For more information about configuration over a PCI Express link below.

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PCIe Link

PCIe Hard IP

Switch

PCIe

Hard IP

User Application

Logic

PCIe Hard IP

PCIe Link

User Application

Logic

Altera FPGA with Hard IP for PCI Express

Active Serial or

Active Quad

Device Configuration

Configuration via Protocol (CvP)

using the PCI Express Link

Serial or

Quad Flash

USB

Download

cable

PCIe

Hard IP

User

Application

Logic

Altera FPGA with Hard IP for PCI Express

Config Control

CvP

USB

Host CPU

PCIe

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Example Designs

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Related Information

• Configuration via Protocol (CvP) on page 13-1

• Configuration via Protocol (CvP)Implementation in Altera FPGAs User Guide

Example Designs

Altera provides example designs to familiarize you with the available functionality. Each design connects the device under test (DUT) to an application (APPS) as the figure below illustrates. Certain critical parameters of the APPs component are set to match the values of DUT. If you change these parameters, you must change the APPs component to match. You can change the values for all other parameters of the DUT without editing the APPs component.

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Figure 1-5: Example Design Preset Parameters

Debug Features

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• Targeted Device Family

• Lanes

• Lane Rate

• Application Clock Rate

• Port type

• Application Interface

• Tags supported

• Maximum payload size

• Number of functions

The following example designs are available for the Arria V Hard IP for PCI Express. You can download them from the <install_dir>/ ip/altera/altera_pcie/altera_pcie_hip_ast_ec/example_design/<dev> directory:

• pcie_de_gen1_x2_ast64.qsys

• pcie_de_gen1_x4_ast64.qsys

• pcie_de_gen1_x8_ast128.qsys

• pcie_de_rp_gen1_x4_ast64.qsys

• pcie_de_rp_gen1_x8_ast128.qsys

Click on the link below to get started with the example design provided in this user guide.

Related Information

Getting Started with the Arria V Hard IP for PCI Express on page 2-1

Debug Features

Debug features allow observation and control of the Hard IP for faster debugging of system-level problems.

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IP Core Verification

Related Information

Debugging on page 17-1

IP Core Verification

To ensure compliance with the PCI Express specification, Altera performs extensive verification. The simulation environment uses multiple testbenches that consist of industry-standard bus functional models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the simulation environment:

• Directed and pseudorandom stimuli are applied to test the Application Layer interface, Configuration Space, and all types and sizes of TLPs

• Error injection tests that inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and check for the proper responses

• PCI-SIG® Compliance Checklist tests that specifically test the items in the checklist

• Random tests that test a wide range of traffic patterns

Altera provides the following two example designs that you can leverage to test your PCBs and complete compliance base board testing (CBB testing) at PCI-SIG.

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Related Information

• PCI SIG Gen3 x8 Merged Design - Stratix V

• PCI SIG Gen2 x8 Merged Design - Stratix V

Compatibility Testing Environment

Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera internally tests every release with motherboards and PCI Express switches from a variety of manufac‐ turers. All PCI-SIG compliance tests are run with each IP core release.

Performance and Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device resources.

Note:

Related Information

Fitter Resources Reports

Soft calibration of the transceiver module requires additional logic. The amount of logic required depends on the configuration.

Recommended Speed Grades

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Steps in Creating a Design for PCI Express

Table 1-5: Arria V Recommended Speed Grades for Link Widths and Application Layer Clock Frequencies

Altera recommends setting the Quartus II Analysis & Synthesis Settings Optimization Technique to Speed when the Application Layer clock frequency is 250 MHz. For information about optimizing synthesis, refer to Setting Up and Running Analysis and Synthesis in Quartus II Help. For more information about how to effect the

Optimization Technique settings, refer to Area and Timing Optimization in volume 2 of the Quartus II Handbook. .

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Link Rate Link Width Interface

Width

Application Clock

Frequency (MHz)

×1 64 bits 62.5

×2 64 bits 125 –4,–5,–6

Gen1

×4 64 bits 125 –4,–5,–6

×8 128 bits 125 –4,–5,–6

×1 64 bits

Gen2

×2 64 bits 125 –4,–5

×4 128 bits 125 –4,–5

Related Information

• Area and Timing Optimization

• Altera Software Installation and Licensing Manual

• Setting up and Running Analysis and Synthesis

Recommended Speed Grades

(2)

,125 –4,–5,–6

125

–4,–5

Steps in Creating a Design for PCI Express

Before you begin

Select the PCIe variant that best meets your design requirements.

• Is your design an Endpoint or Root Port?

• What Generation do you intend to implement?

• What link width do you intend to implement?

• What bandwidth does your application require?

• Does your design require CvP?

1. Select parameters for that variant.

2. Simulate using an Altera-provided example design. All of Altera's PCI Express example designs are

available under <install_dir>/ip/altera/altera_pcie/. Alternatively, create a simulation model and use your own custom or third-party BFM. The Qsys Generate menu generates simulation models. Altera

(2)

This is a power-saving mode of operation

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Steps in Creating a Design for PCI Express

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supports ModelSim®-Altera for all IP. The PCIe cores support the Aldec RivieraPro, Cadence NCsim, Mentor Graphics ModelSim, and Synopsys VCS and VCS-MX simulators.

3. Compile your design using the Quartus II software. If the versions of your design and the Quartus II software you are running do not match, regenerate your PCIe design.

4. Download your design to an Altera development board or your own PCB. Click on the All Develop‐ ment Kits link below for a list of Altera's development boards.

5. Test the hardware. You can use Altera's SignalTap® II Logic Analyzer or a third-party protocol analyzer to observe behavior.

6. Substitute your Application Layer logic for the Application Layer logic in Altera's testbench. Then repeat Steps 3–6. In Altera's testbenches, the PCIe core is typically called the DUT (device under test). The Application Layer logic is typically called APPS.

Related Information

• Parameter Settings on page 3-1

• Getting Started with the Arria V Hard IP for PCI Express on page 2-1

• All Development Kits

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Getting Started with the Arria V Hard IP for PCI

APPS altpcied_<dev>_hwtcl.v

Hard IP for PCI Express Testbench for Endpoints

Avalon-ST TX Avalon-ST RX

reset

status

Avalon-ST TX Avalon-ST RX reset status

DUT altpcie_<dev>_hip_ast_hwtcl.v

Root Port Model altpcie_tbed_<dev>_hwtcl.v

PIPE or

Serial

Interface

Root Port BFM altpcietb_bfm_rpvar_64b_x8_pipen1b

Root Port Driver and Monitor altpcietb_bfm_vc_intf

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Express

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This section provides instructions to help you quickly customize, simulate, and compile the Arria V Hard IP for PCI Express IP Core. When you install the Quartus II software you also install the IP Library. This installation includes design examples for Hard IP for PCI Express under the <install_dir>/ip/altera/altera_

pcie/ directory.

After you install the Quartus II software for 14.0, you can copy the design examples from the <install_dir>/

ip/altera/altera_pcie/altera_pcie/altera_pcie_hip_ast_ed/example_designs/<dev> directory. This walkthrough

uses the Gen1 ×4 Endpoint, pcie_de_gen1_x4_ast64.qsys. The following figure illustrates the top-level modules of the testbench in which the DUT, a Gen1 Endpoint, connects to a chaining DMA engine, labeled APPS in the following figure, and a Root Port model. The simulation can use the parallel PHY Interface for PCI Express (PIPE) or serial interface.

Figure 2-1: Testbench for an Endpoint

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Altera provides example designs to help you get started with the Arria V Hard IP for PCI Express IP Core. You can use example designs as a starting point for your own design. The example designs include scripts to compile and simulate the Arria V Hard IP for PCI Express IP Core. This example design provides a simple method to perform basic testing of the Application Layer logic that interfaces to the Hard IP for PCI Express.

ISO 9001:2008 Registered

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Qsys Design Flow

For a detailed explanation of this example design, refer to the Testbench and Design Example chapter. If you choose the parameters specified in this chapter, you can run all of the tests included in Testbench and Design Example chapter.

For more information about Qsys, refer to System Design with Qsys in the Quartus II Handbook. For more information about the Qsys GUI, refer to About Qsys in Quartus II Help.

Related Information

• System Design with Qsys

• About Qsys

Qsys Design Flow

Copy the pcie_de_gen1_x4_ast64.qsys design example from the <install_dir>/ip/altera/altera_pcie/altera_

pcie/altera_pcie_hip_ast_ed/example_designs/<dev> to your working directory. The following figure

illustrates this Qsys system.

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Qsys Design Flow

Figure 2-2: Complete Gen1 ×4 Endpoint (DUT) Connected to Example Design (APPS)

2-3

The example design includes the following components:

• DUT—This is Gen1 ×4 Endpoint. For your own design, you can select the data rate, number of lanes, and either Endpoint or Root Port mode.

• APPS—This DMA driver configures the DUT and drives read and write TLPs to test DUT function‐ ality.

• pcie_reconfig_driver_0—This Avalon-MM master drives the Transceiver Reconfiguration Controller. The pcie_reconfig_driver_0 is implemented in clear text that you can modify if your design requires different reconfiguration functions. After you generate your Qsys system, the Verilog HDL for this component is available as: <working_dir>/<variant_name>/testbench/<variant_name>_tb/simulation/

submodules/altpcie_reconfig_driver.sv.

• Transceiver Reconfiguration Controller—The Transceiver Reconfiguration Controller dynamically reconfigures analog settings to improve signal quality. For Gen1 and Gen2 data rates, the Transceiver Reconfiguration Controller must perform offset cancellation and PLL calibration.

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Generating the Testbench

Follow these steps to generate the chaining DMA testbench:

1. On the Generate menu, select Generate Testbench System. Specify the parameters listed in the following table.

Table 2-1: Parameters to Specify on the Generation Tab in Qsys

Parameter Value

Create testbench Qsys system Standard, BFMs for standard Qsys interfaces

Create testbench simulation model Verilog

Allow mixed-language simulation Turn this option off

Output Directory

Path <working_dir>/pcie_de_gen1_x4_ast64

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Testbench <working_dir>/pcie_de_gen1_x4_ast64/testbench

2. Click the Generate button at the bottom of the Generation tab to create the testbench.

Simulating the Example Design

1. Start your simulation tool. This example uses the ModelSim® software.

2. From the ModelSim transcript window, in the testbench directory type the following commands: a. do msim_setup.tcl

b. ld_debug (This command compiles all design files and elaborates the top-level design without any

optimization.)

c. run -all

The simulation includes the following stages:

• Link training

• Configuration

• DMA reads and writes

• Root Port to Endpoint memory reads and writes

Disabling Scrambling to Interpret TLPs at the PIPE Interface

1. Go to <project_directory/<variant>/testbench/<variant>_tb/simulation/submodules/.

2. Open altpcietb_bfm_top_rp.v.

3. Locate the declaration of test_in[2:1]. Set test_in[2] = 1 and test_in[1] = 0. Changing

test_in[2] = 1 disables data scrambling on the PIPE interface.

4. Save altpcietb_bfm_top_rp.v.

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Generating Quartus II Synthesis Files

1. On the Generate menu, select Generate HDL.

2. For Create HDL design files for synthesis, select Verilog.

You can leave the default settings for all other items.

3. Click Generate to generate files for Quartus II synthesis.

4. Click Finish when the generation completes.

Understanding the Files Generated

Table 2-2: Overview of Qsys Generation Output Files

Directory Description

<testbench_dir>/<variant_name>/synthesis Includes the top-level HDL file for the Hard IP for

Generating Quartus II Synthesis Files

PCI Express and the .qip file that lists all of the necessary assignments and information required to process the IP core in the Quartus II compiler. Generally, a single .qip file is generated for each IP core.

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<testbench_dir>/<variant_name>/synthesis/submodules

Includes the HDL files necessary for Quartus II synthesis.

<testbench_dir>/<variant_name>/testbench

Includes testbench subdirectories for the Aldec, Cadence, Synopsys, and Mentor simulation tools with the required libraries and simulation scripts.

<testbench_dir>/<variant_name>/testbench<cad_ vendor>

Includes the HDL source files and scripts for the simulation testbench.

For a more detailed listing of the directories and files the Quartus II software generates, refer to Files Generated for Altera IP Cores in Compiling the Design in the Qsys Design Flow.

Understanding Physical Placement of the PCIe IP Core

For more information about physical placement of the PCIe blocks, refer to the links below. Contact your Altera sales representative for detailed information about channel and PLL usage.

Related Information

• Physical Layout of Hard IP in Arria V Devices on page 4-49

• Channel Placement in Arria V Devices on page 4-52

Compiling the Design in the Quartus II Software

To compile the Qsys design example in the Quartus II software, you must create a Quartus II project and add your Qsys files to that project.

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Compiling the Design in the Quartus II Software

Complete the following steps to create your Quartus II project:

1. Click the New Project Wizard icon.

2. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you

previously turned it off)

3. On the Directory, Name, Top-Level Entity page, enter the following information: a. The working directory shown is correct. You do not have to change it.

b. For the project name, browse to the synthesis directory that includes your Qsys project,

<working_dir>/pcie_de_gen1_x4_ast64/synthesis. Select your variant name, pcie_de_gen1_x4_ast64.v .

Then, click Open.

c. If the top-level design entity and Qsys system names are identical, the Quartus II software treats the

Qsys system as the top-level design entity.

4. Click Next to display the Add Files page.

5. Complete the following steps to add the Quartus II IP File (.qip)to the project: a. Click the browse button. The Select File dialog box appears.

b. In the Files of type list, select IP Variation Files (*.qip). c. Browse to the <working_dir>/pcie_de_gen1_x4_ast64/synthesis directory. d. Click pcie_de_gen1_x4_ast64.qip and then click Open. e. On the Add Files page, click Add, then click OK.

6. Click Next to display the Device page.

7. On the Family & Device Settings page, choose the following target device family and options:

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a. In the Family list, select Arria V (GT/GX/ST/SX). b. In the Devices list, select Arria V GX Extended Features.. c. In the Available Devices list, select 5AGXFB3H6F35C6.

8. Click Next to close this page and display the EDA Tool Settings page.

9. From the Simulation list, select ModelSim®. From the Format list, select the HDL language you

intend to use for simulation.

10.Click Next to display the Summary page.

11.Check the Summary page to ensure that you have entered all the information correctly.

12.Click Finish to create the Quartus II project.

13.Add the Synopsys Design Constraint (SDC) commands shown in the following example to the

top-level design file for your Quartus II project.

14.To compile your design using the Quartus II software, on the Processing menu, click Start Compila‐ tion. The Quartus II software then performs all the steps necessary to compile your design.

15.After compilation, expand the TimeQuest Timing Analyzer folder in the Compilation Report. Note

whether the timing constraints are achieved in the Compilation Report.

16.If your design does not initially meet the timing constraints, you can find the optimal Fitter settings for your design by using the Design Space Explorer. To use the Design Space Explorer, click Launch Design Space Explorer on the tools menu.

Example 2-1: Synopsys Design Constraints

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create_clock -period “100 MHz” -name {refclk_pci_express}{*refclk_*} derive_pll_clocks derive_clock_uncertainty

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Compiling the Design in the Quartus II Software

# PHY IP reconfig controller constraints # Set reconfig_xcvr clock # Modify to match the actual clock pin name # used for this clock, and also changed to have the correct period set create_clock -period "125 MHz" -name {reconfig_xcvr_clk}{*reconfig_xcvr_clk*}

# HIP Soft reset controller SDC constraints set_false_path -to [get_registers* altpcie_rs_serdes|fifo_err_sync_r[0]] set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to[get_registers *altpcie_rs_serdes|*]

# Hard IP testin pins SDC constraints set_false_path -from [get_pins -compatibilitly_mode *hip_ctrl*]

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Notes:

1. If supported and enabled for your IP variation

2. If functional simulation models are generated

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file <your_ip>_inst.v or .vhd - Sample instantiation template

synthesis - IP synthesis files

<your_ip>.qip - Lists files for synthesis

testbench - Simulation testbench files

<testbench_hdl_files>

<simulator_vendor> - Testbench for supported simulators

<simulation_testbench_files>

<your_ip>.v or .vhd - Top-level IP variation synthesis file

simulation - IP simulation files

<your_ip>.sip - NativeLink simulation integration file

<simulator vendor> - Simulator setup scripts

<simulator_setup_scripts>

<your_ip> - IP core variation files

<your_ip>.qip or .qsys - System or IP integration file

<your_ip>_generation.rpt - IP generation report <your_ip>.bsf - Block symbol schematic file

<your_ip>.ppf - XML I/O pin information file <your_ip>.spd - Combines individual simulation startup scripts

<your_ip>.html - Contains memory map

<your_ip>.sopcinfo - Software tool-chain integration file

<your_ip>_syn.v or .vhd - Timing & resource estimation netlist

<your_ip>.debuginfo - Lists files for synthesis

<your_ip>.v, .vhd, .vo, .vho - HDL or IPFS models

<your_ip>_tb - Testbench for supported simulators

<your_ip>_tb.v or .vhd - Top-level HDL testbench file

2-8

Modifying the Example Design

Files Generated for Altera IP Cores Figure 2-3: IP Core Generated Files

The Quartus II software generates the following output for your IP core.

2014.12.15

Modifying the Example Design

To use this example design as the basis of your own design, replace the Chaining DMA Example shown in the following figure with your own Application Layer design. Then modify the Root Port BFM driver to generate the transactions needed to test your Application Layer.

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Getting Started with the Arria V Hard IP for PCI Express

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PCB

Avalon-MM slave

Reset

Hard IP for PCI Express

Altera FPGA

PCB

Transaction Layer

Data Link Layer

PHY MAC Layer

x4 PCIe Link

(Physical Layer)

PHY IP Core for PCI Express

Lane 2

Lane 3

Lane 4

Lane 1

Lane 0

TX PLL

Transceiver Bank

Reconfig to and from Transceiver

to and from

Embedded

Controller

(Avalon-MM

slave interface)

Transceiver

Reconfiguration

Controller

Root

Port BFM

npor

Reset

APPS DUT

Chaining DMA

(User Application)

2014.12.15

Using the IP Catalog To Generate Your Arria V Hard IP for PCI Express as a Separate

Figure 2-4: Testbench for PCI Express

2-9

Component

Using the IP Catalog To Generate Your Arria V Hard IP for PCI Express as a Separate Component

You can also instantiate the Arria V Hard IP for PCI Express IP Core as a separate component for integration into your project.

Getting Started with the Arria V Hard IP for PCI Express

You can use the Quartus II IP Catalog and IP Parameter Editor to select, customize, and generate files representing your custom IP variation. The IP Catalog (Tools > IP Catalog) automatically displays IP cores available for your target device. Double-click any IP core name to launch the parameter editor and generate files representing your IP variation.

For more information about the customizing and generating IP Cores refer to Specifying IP Core Parameters and Options in Introduction to Altera IP Cores. For more information about upgrading older IP cores to the current release, refer to Upgrading Outdated IP Cores in Introduction to Altera IP Cores.

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2-10

Using the IP Catalog To Generate Your Arria V Hard IP for PCI Express as a Separate Component

2014.12.15

Note: Your design must include the Transceiver Reconfiguration Controller IP Core and the Altera PCIe

Reconfig Driver. Refer to the figure in the Qsys Design Flow section to learn how to connect this components.

Related Information

• Introduction to Altera IP Cores

• Managing Quartus II Projects

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Parameter Settings

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Avalon-ST System Settings

Table 3-1: System Settings for PCI Express

Parameter Value Description

Number of Lanes ×1, ×2, ×4, ×8 Specifies the maximum number of lanes supported.

Lane Rate Gen1 (2.5 Gbps)

Gen2 (2.5/5.0 Gbps)

Port type Root Port

Native Endpoint

Legacy Endpoint

Specifies the maximum data rate at which the link can operate.

Specifies the port type. Altera recommends Native Endpoint for all new Endpoint designs. Select Legacy Endpoint only when you require I/O transaction support for compatibility. The Legacy Endpoint is not available for the Avalon-MM Arria V Hard IP for PCI Express.

The Endpoint stores parameters in the Type 0 Configuration Space. The Root Port stores parameters in the Type 1 Configu‐ ration Space.

ISO 9001:2008 Registered

3-2

Avalon-ST System Settings

Parameter Value Description

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Application Interface

RX Buffer credit allocation performance for received requests

Avalon-ST 64-bit

Avalon-ST 128-bit

Minimum

Low

Balanced

High

Maximum

Specifies the width of the Avalon-ST interface between the Application and Transaction Layers. The following widths are required:

Data Rate Link Width Interface Width

×1 64 bits

×2 64 bits

Gen1

×4 64 bits

×8 128 bits

×1 64 bits

Gen2

×2 64 bits

×4 128 bits

Determines the allocation of posted header credits, posted data credits, non-posted header credits, completion header credits, and completion data credits in the 16 KByte RX buffer. The 5 settings allow you to adjust the credit allocation to optimize your system. The credit allocation for the selected setting displays in the message pane.

Refer to the Throughput Optimization chapter for more information about optimizing performance. The Flow Control chapter explains how the RX credit allocation and the

Maximum payload RX Buffer credit allocation and the Maximum payload size that you choose affect the allocation of flow control credits. You can set the Maximum payload size parameter on the Device tab.

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The Message window of the GUI dynamically updates the number of credits for Posted, Non-Posted Headers and Data, and Completion Headers and Data as you change this selection.

Parameter Settings

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Avalon-ST System Settings

Parameter Value Description

• Minimum RX Buffer credit allocation -performance for received requests–This setting configures the minimum

PCIe specification allowed for non-posted and posted request credits, leaving most of the RX Buffer space for received completion header and data. Select this option for variations where application logic generates many read requests and only infrequently receives single requests from the PCIe link.

• Low–This setting configures a slightly larger amount of RX Buffer space for non-posted and posted request credits, but still dedicates most of the space for received completion header and data. Select this option for variations where application logic generates many read requests and infrequently receives small bursts of requests from the PCIe link. This option is recommended for typical endpoint applications where most of the PCIe traffic is generated by a DMA engine that is located in the endpoint application layer logic.

• Balanced–This setting allocates approximately half the RX Buffer space to received requests and the other half of the RX Buffer space to received completions. Select this option for variations where the received requests and received completions are roughly equal.

• High–This setting configures most of the RX Buffer space for received requests and allocates a slightly larger than minimum amount of space for received completions. Select this option where most of the PCIe requests are generated by the other end of the PCIe link and the local application layer logic only infrequently generates a small burst of read requests. This option is recommended for typical root port applications where most of the PCIe traffic is generated by DMA engines located in the endpoints.

• Maximum–This setting configures the minimum PCIe specification allowed amount of completion space, leaving most of the RX Buffer space for received requests. Select this option when most of the PCIe requests are generated by the other end of the PCIe link and the local application layer logic never or only infrequently generates single read requests. This option is recommended for control and status endpoint applications that don't generate any PCIe requests of their own and only are the target of write and read requests from the root complex.

3-3

Parameter Settings

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3-4

Link Capabilities

Parameter Value Description

2014.12.15

Reference clock frequency

Use 62.5 MHz application clock

Use deprecated RX Avalon-ST data byte enable port (rx_st_be)

Enable configu‐ ration via PCIe link

Enable Hard IP Reconfiguration

100 MHz 125 MHz

The PCI Express Base Specification requires a 100 MHz ±300 ppm reference clock. The 125 MHz reference clock is provided as a convenience for systems that include a 125 MHz clock source.

On/Off This mode is only available only for Gen1 ×1.

On/Off This parameter is only available for the Avalon-ST Arria V

Hard IP for PCI Express.

On/Off When On, the Quartus II software places the Endpoint in the

location required for configuration via protocol (CvP). For more information about CvP, click the Configuration via Protocol (CvP) link below.

On/Off When On, you can use the Hard IP reconfiguration bus to

dynamically reconfigure Hard IP read-only registers. For more information refer to Hard IP Reconfiguration Interface. This parameter is not available for the Avalon-MM IP Cores.

Number of

1–8 Specifies the number of functions that share the same link.

Functions

Related Information

• Configuration via Protocol (CvP) on page 13-1

• Throughput Optimization on page 11-1

• PCI Express Base Specification 2.1 or 3.0

Link Capabilities

Table 3-2: Link Capabilities

Parameter Value Description

Link port number

0x01 Sets the read-only value of the port number field in the Link

Capabilities Register.

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Parameter Settings

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Port Function Parameters Shared Across All Port Functions

Parameter Value Description

3-5

Slot clock configuration

On/Off When On, indicates that the Endpoint or Root Port uses the

same physical reference clock that the system provides on the connector. When Off, the IP core uses an independent clock regardless of the presence of a reference clock on the connector.

Port Function Parameters Shared Across All Port Functions

Device Capabilities

Table 3-3: Capabilities Registers

Parameter Possible Values Default Value Description

Maximum payload size

Number of tags supported per function

128 bytes 256 bytes 512 bytes

32 64

128 bytes Specifies the maximum payload size supported. This

parameter sets the read-only value of the max payload size supported field of the Device Capabilities register (0x084[2:0]). Address: 0x084.

32 - Avalon-ST Indicates the number of tags supported for non-posted

requests transmitted by the Application Layer. This parameter sets the values in the Device Control register (0x088) of the PCI Express capability structure described in Table 9–9 on page 9–5.

Completion timeout range

Parameter Settings

ABCD

BCD ABC

The Transaction Layer tracks all outstanding completions for non-posted requests made by the Application Layer. This parameter configureTags supportedes the Transaction Layer for the maximum number to track. The Application Layer must set the tag values in all non-posted PCI Express headers to be less than this value. Values greater than 32 also set the extended tag field supported bit in the Configuration Space Device Capabilities register. The Application Layer can only use tag numbers greater than 31 if configuration software sets the Extended Tag Field Enable bit of the Device Control register. This bit is available to the Application Layer on the tl_cfg_ctl output signal as cfg_devcsr[8].

ABCD Indicates device function support for the optional

completion timeout programmability mechanism. This mechanism allows system software to modify the completion timeout value. This field is applicable only to

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Device Capabilities

Parameter Possible Values Default Value Description

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B A

None

Root Ports and Endpoints that issue requests on their own behalf. Completion timeouts are specified and enabled in the Device Control 2 register (0x0A8) of the PCI Express Capability Structure Version. For all other functions this field is reserved and must be hardwired to 0x0000b. Four time value ranges are defined:

• Range A: 50 us to 10 ms

• Range B: 10 ms to 250 ms

• Range C: 250 ms to 4 s

• Range D: 4 s to 64 s Bits are set to show timeout value ranges supported. The

function must implement a timeout value in the range 50 s to 50 ms. The following values specify the range:

• None – Completion timeout programming is not supported

• 0001 Range A

• 0010 Range B

• 0011 Ranges A and B

• 0110 Ranges B and C

• 0111 Ranges A, B, and C

• 1110 Ranges B, C and D

• 1111 Ranges A, B, C, and D

Implement completion timeout disable

All other values are reserved. Altera recommends that the completion timeout mechanism expire in no less than 10 ms.

On/Off On For Endpoints using PCI Express version 2.1 or 3.0, this

option must be On. The timeout range is selectable. When On, the core supports the completion timeout disable mechanism via the PCI Express Device

Control Register 2. The Application Layer logic must

implement the actual completion timeout mechanism for the required ranges.

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Parameter Settings

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Error Reporting

Table 3-4: Error Reporting

Parameter Value Default Value Description

Error Reporting

3-7

Advanced error reporting (AER)

ECRC checking

ECRC generation

ECRC forwarding

On/Off Off When On, enables the Advanced Error Reporting (AER)

capability.

On/Off Off When On, enables ECRC checking. Sets the read-only

value of the ECRC check capable bit in the Advanced

Error Capabilities and Control Register. This

parameter requires you to enable the AER capability.

On/Off Off When On, enables ECRC generation capability. Sets the

read-only value of the ECRC generation capable bit in the Advanced Error Capabilities and Control

AER capability. Not applicable for Avalon-MM DMA.

On/Off Off When On, enables ECRC forwarding to the Application

Layer. On the Avalon-ST RX path, the incoming TLP contains the ECRC dword

(3)

and the TD bit is set if an ECRC exists. On the transmit the TLP from the Applica‐ tion Layer must contain the ECRC dword and have the

TD bit set.

Link Capabilities

Table 3-5: Link Capabilities

Parameter Value Description

Link port number

(3)

Throughout this user guide, the terms word, dword and qword have the same meaning that they have in the PCI Express Base Specification. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

Parameter Settings

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Not applicable for Avalon-MM DMA.

0x01 Sets the read-only value of the port number field in the Link

Capabilities Register.

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+ 218 hidden pages

Altera Arria V Avalon-ST User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Datasheet

Arria V Avalon-ST Interface for PCIe Datasheet

Features

Release Information

Device Family Support

Configurations

Example Designs

Debug Features

IP Core Verification

Compatibility Testing Environment

Performance and Resource Utilization

Recommended Speed Grades

Steps in Creating a Design for PCI Express

Qsys Design Flow

Generating the Testbench

Simulating the Example Design

Generating Quartus II Synthesis Files

Understanding the Files Generated

Understanding Physical Placement of the PCIe IP Core

Compiling the Design in the Quartus II Software

Modifying the Example Design

Using the IP Catalog To Generate Your Arria V Hard IP for PCI Express as a Separate Component

Parameter Settings

Avalon-ST System Settings

Link Capabilities

Port Function Parameters Shared Across All Port Functions

Device Capabilities

Error Reporting

Link Capabilities